CN118335683B - Semiconductor base, preparation method of semiconductor base and application of semiconductor base - Google Patents
Semiconductor base, preparation method of semiconductor base and application of semiconductor base Download PDFInfo
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- CN118335683B CN118335683B CN202410756756.2A CN202410756756A CN118335683B CN 118335683 B CN118335683 B CN 118335683B CN 202410756756 A CN202410756756 A CN 202410756756A CN 118335683 B CN118335683 B CN 118335683B
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/32—Carbides
- C23C16/325—Silicon carbide
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/458—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
- C23C16/4581—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber characterised by material of construction or surface finish of the means for supporting the substrate
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Abstract
本发明涉及半导体制造的技术领域，提供了一种半导体基座、半导体基座的制备方法及半导体基座的应用。所述半导体基座包括基座，设置于基座上表面的第一碳化硅涂层和设置于基座下表面的第二碳化硅涂层；所述第一碳化硅涂层上表面的发射率小于所述第二碳化硅涂层下表面的发射率且所述第一碳化硅涂层上表面的发射率与所述第二碳化硅涂层下表面的发射率的比值为1:（1‑1.2）。本发明通过优化设置于基座上表面和下表面的碳化硅涂层的粗糙度和碳化硅涂层厚度，使半导体基座下表面的热发射率较大，半导体基座上表面的热发射率较小，有利于提高半导体基座整体蓄热能力，使半导体基座形成均匀的温场，最终提高晶圆上的薄膜成膜质量。
The present invention relates to the technical field of semiconductor manufacturing, and provides a semiconductor base, a method for preparing the semiconductor base, and an application of the semiconductor base. The semiconductor base includes a base, a first silicon carbide coating disposed on the upper surface of the base, and a second silicon carbide coating disposed on the lower surface of the base; the emissivity of the upper surface of the first silicon carbide coating is less than the emissivity of the lower surface of the second silicon carbide coating, and the ratio of the emissivity of the upper surface of the first silicon carbide coating to the emissivity of the lower surface of the second silicon carbide coating is 1:(1-1.2). The present invention optimizes the roughness and thickness of the silicon carbide coating disposed on the upper and lower surfaces of the base, so that the thermal emissivity of the lower surface of the semiconductor base is larger and the thermal emissivity of the upper surface of the semiconductor base is smaller, which is beneficial to improving the overall heat storage capacity of the semiconductor base, so that the semiconductor base forms a uniform temperature field, and finally improves the film formation quality of the thin film on the wafer.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor base, a preparation method of the semiconductor base and application of the semiconductor base.
Background
Graphite susceptors are commonly used in Metal Organic Chemical Vapor Deposition (MOCVD) equipment to support and heat components of single crystal substrates. The thermal stability, thermal uniformity and other performance parameters of the graphite base play a decisive role in the growth quality of the epitaxial material, so the graphite base is a core key component of MOCVD equipment. The graphite base is used as one of core components in MOCVD equipment, is a supporting body and a heating body of a substrate, and directly determines the uniformity and purity of a film material, so that the thermal stability and the thermal uniformity of the base directly influence the preparation of an epitaxial wafer, and meanwhile, the graphite base is extremely easy to wear along with the increase of the use times and the change of working condition links, and belongs to consumable materials.
Accordingly, there is a need to develop a susceptor having thermal stability and thermal uniformity.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned problems of the prior art and providing a semiconductor substrate, a method for manufacturing a semiconductor substrate and an application of a semiconductor substrate.
According to the invention, by optimizing the roughness and the thickness of the silicon carbide coating deposited on the upper surface and the lower surface of the base, the thermal emissivity of the lower surface of the semiconductor base is increased, the thermal emissivity of the upper surface of the semiconductor base is reduced, the integral heat storage capacity of the semiconductor base is improved, the semiconductor base forms a uniform temperature field, and finally the film forming quality of the film on the wafer is improved.
In order to achieve the above object, a first aspect of the present invention provides a semiconductor susceptor, comprising a susceptor, a first silicon carbide coating layer disposed on an upper surface of the susceptor, and a second silicon carbide coating layer disposed on a lower surface of the susceptor; the emissivity of the upper surface of the first silicon carbide coating is smaller than the emissivity of the lower surface of the second silicon carbide coating, and the ratio of the emissivity of the upper surface of the first silicon carbide coating to the emissivity of the lower surface of the second silicon carbide coating is 1 (1-1.2).
Optionally, the emissivity of the upper surface of the first silicon carbide coating is 0.88-0.995.
Optionally, the thickness of the first silicon carbide coating is less than the thickness of the second silicon carbide coating.
Optionally, the roughness of the upper surface of the first silicon carbide coating is less than the roughness of the lower surface of the second silicon carbide coating.
Optionally, the ratio of the thickness of the first silicon carbide coating to the thickness of the second silicon carbide coating is 1 (2-30).
Optionally, the ratio of the roughness of the upper surface of the first silicon carbide coating to the roughness of the lower surface of the second silicon carbide coating is 1 (2-60).
A second aspect of the present invention provides a method of preparing the semiconductor pedestal of the first aspect, the method comprising: taking a base with equal surface roughness of the upper surface and the lower surface, and placing the base in a deposition chamber; depositing a first silicon carbide coating on an upper surface of the susceptor; and depositing a second silicon carbide coating on the lower surface of the base, and polishing the upper surface of the first silicon carbide coating and the lower surface of the second silicon carbide coating to obtain the semiconductor base.
The third aspect of the invention provides a metal organic chemical vapor deposition device, comprising the semiconductor base of the first aspect and/or the semiconductor base prepared by the method of the second aspect.
The technical scheme adopted by the invention has the following beneficial effects:
according to the invention, the roughness and the thickness of the silicon carbide coating deposited on the upper surface and the lower surface of the base are optimized, and the roughness of the upper surface of the first silicon carbide coating on the upper surface of the semiconductor base is smaller than that of the lower surface of the second silicon carbide coating on the lower surface of the base, so that the thickness of the first silicon carbide coating is smaller than that of the second silicon carbide coating, the thermal emissivity of the lower surface of the semiconductor base is increased, the thermal emissivity of the upper surface of the semiconductor base is reduced, the integral heat storage capacity of the semiconductor base is improved, the semiconductor base forms a uniform temperature field, and finally the film forming quality of a film on a wafer is improved.
The endpoints and any values of the ranges disclosed herein are not limited to the precise range or value, and are understood to encompass values approaching those ranges or values. For numerical ranges, one or more new numerical ranges may be found between the endpoints of each range, between the endpoint of each range and the individual point value, and between the individual point value, in combination with each other, and are to be considered as specifically disclosed herein. Herein, unless otherwise specified, data ranges all include endpoints.
Drawings
FIG. 1 shows the temperature field profile of a physical photovoltaic panel made from the semiconductor pedestal of comparative example 2.
Fig. 2 shows a temperature field distribution diagram of a physical photovoltaic panel fabricated from the semiconductor pedestal of example 1.
Detailed Description
The following describes specific embodiments of the present invention in detail. It should be understood that the detailed description and specific examples, while indicating and illustrating the invention, are not intended to limit the invention.
Unless defined otherwise, all scientific and technical terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention relates.
The first aspect of the invention provides a semiconductor substrate, comprising a substrate, a first silicon carbide coating arranged on the upper surface of the substrate and a second silicon carbide coating arranged on the lower surface of the substrate; the emissivity of the upper surface of the first silicon carbide coating is smaller than the emissivity of the lower surface of the second silicon carbide coating, and the ratio of the emissivity of the upper surface of the first silicon carbide coating to the emissivity of the lower surface of the second silicon carbide coating is 1 (1-1.2). The upper surface of the first silicon carbide coating is arranged on one side of the upper surface of the base away from the base. The lower surface of the second silicon carbide coating is the side, far away from the base, of the silicon carbide coating arranged on the lower surface of the base.
In the present invention, the ratio of the emissivity of the upper surface of the first silicon carbide coating to the emissivity of the lower surface of the second silicon carbide coating is 1 (1-1.2), for example, may be 1:1.11, 1:1.12, 1:1.13, 1:1.14, 1:1.15, 1:1.16, 1:1.17, 1:1.18, 1:1.19, and 1:1.2. The emissivity test method comprises the steps of placing a silicon carbide sample block with the diameter of more than or equal to 60 mm on a test bench, using an emissivity tester to test, wherein the test range is set to be 6-14 mu m, the equipment registration error is +/-0.02, and the test precision is less than or equal to 0.1 FS.
In some embodiments, the ratio of the emissivity of the upper surface of the first silicon carbide coating to the emissivity of the lower surface of the second silicon carbide coating is 1 (1.02-1.11), which may be, for example, 1:1.02, 1:1.04, 1:1.06, 1:1.08, 1:1.1, and 1:1.11.
In some embodiments, the emissivity of the upper surface of the first silicon carbide coating is 0.88-0.995, which may be, for example, 0.88, 0.89, 0.9, 0.91, 0.92, 0.93, 0.94, 0.95, 0.96, 0.97, 0.98, and 0.995.
In some embodiments, the thickness of the first silicon carbide coating is less than the thickness of the second silicon carbide coating. The thickness is measured by using a micrometer. The thickness of the first silicon carbide coating is smaller than that of the second silicon carbide coating, so that the emissivity of the upper surface of the first silicon carbide coating is smaller than that of the lower surface of the second silicon carbide coating, and the thermal uniformity of the semiconductor substrate is improved.
In some embodiments, the ratio of the thickness of the first silicon carbide coating to the thickness of the second silicon carbide coating is 1 (2-30), which may be, for example, 1:2, 1:5, 1:10, 1:15, 1:20, 1:25, and 1:30.
In some embodiments, the first silicon carbide coating has a thickness of 0.2 mm-5 mm, which may be, for example, 0.2 mm, 0.5mm, 1mm, 2mm, 3 mm, 4 mm, and 5 mm.
In some embodiments, the roughness of the upper surface of the first silicon carbide coating is less than the roughness of the lower surface of the second silicon carbide coating.
In some embodiments, the ratio of the roughness of the upper surface of the first silicon carbide coating to the roughness of the lower surface of the second silicon carbide coating is 1 (2-60), which may be, for example, 1:2, 1:5, 1:10, 1:20, 1:30, 1:40, 1:50, and 1:60. The roughness test method of the invention is to detect the roughness value of the surface by a roughness measuring instrument. The roughness of the upper surface of the first silicon carbide coating is smaller than that of the lower surface of the second silicon carbide coating, so that the emissivity of the upper surface of the first silicon carbide coating is smaller than that of the lower surface of the second silicon carbide coating, the heat storage capacity of the semiconductor base is higher, and the thermal field of the semiconductor base is more uniform.
In some embodiments, the roughness of the first silicon carbide coating upper surface is 0.5 [ mu ] m-15 [ mu ] m, for example, may be 0.5 [ mu ] m, 1[ mu ] m, 2 [ mu ] m, 4 [ mu ] m, 6 [ mu ] m, 8 [ mu ] m, 10 [ mu ] m and 15 [ mu ] m.
In some embodiments, the base is a graphite base and/or a glassy carbon base.
In some embodiments, the base has a coefficient of thermal expansion of 4.5-5×10 -6/DEG C, as may be 4.5×10-6/℃、4.6-5×10-6/℃、4.7-5×10-6/℃、4.8-5×10-6/℃、4.9-5×10-6/℃、5×10-6/℃.
In some embodiments, the roughness of the upper surface and the lower surface of the base are each independently less than 0.1 mm.
In some embodiments, the roughness of the upper surface of the base is equal to and less than 0.1 mm of the lower surface roughness.
In some embodiments, the diameter error of the base is controlled to within 0.02 mm.
In some embodiments, the flatness of the base is less than 0.1 mm. The flatness testing method is to measure the flatness error of the graphite surface through a feeler gauge.
In some embodiments, the base has a thickness of 5 mm-16: 16 mm, such as may be 5 mm, 6 mm, 8: 8 mm, 10: 10 mm, 12: 12 mm, 14: 14 mm, and 16: 16 mm.
A second aspect of the present invention provides a method of preparing the semiconductor pedestal of the first aspect, the method comprising:
taking a base with equal surface roughness of the upper surface and the lower surface, and placing the base in a deposition chamber;
Depositing a first silicon carbide coating on an upper surface of the susceptor;
Depositing a second silicon carbide coating on the lower surface of the base;
And polishing the upper surface of the first silicon carbide coating and the lower surface of the second silicon carbide coating to obtain the semiconductor base.
In some embodiments, the deposition conditions of the first silicon carbide coating and the second silicon carbide coating each independently comprise: introducing silane and hydrogen into the deposition chamber, wherein the flow ratio of the silane to the reducing gas is 1 (8-16), such as 1:8, 1:10, 1:12, 1:14 and 1:16; the deposition temperature is 1350-1450 ℃, such as 1350 ℃, 1370 ℃, 1390 ℃, 1400 ℃, 1420 ℃, 1440 ℃ and 1450 ℃; the deposition pressure is 5 kPa-20 kPa, such as 5 kPa, 8 kPa, 10 kPa, 12 kPa, 14 kPa, 16 kPa, 18 kPa, and 20 kPa.
In some embodiments, the silane includes a carbon silicon source and/or a chlorine silicon source having a carbon number of C1-C4; preferably, the carbon silicon gas source comprises at least one of monosilane, disilane, trisilane, and Polymethylsilane (PMS); preferably, the source of the silicon chloride gas comprises at least one of methylchlorosilane, dimethylchlorosilane, and trichloromethylsilane (MTS).
In some embodiments, the silane flow rate is 10L/min-40L/min, such as 10L/min, 20L/min, 25L/min, 30L/min, 35L/min, and 40L/min.
In some embodiments, the reducing gas is hydrogen.
In some embodiments, the reducing gas has a flow rate of 160L/min-320L/min, such as 160L/min, 200L/min, 240L/min, 280L/min, and 320L/min.
In some embodiments, the deposition conditions further comprise: inert gases including argon, helium and nitrogen are introduced as carrier gases.
In some embodiments, the argon flow is 2L/min-30L/min, such as 2L/min, 10L/min, 15L/min, 20L/min, 25L/min, and 30L/min.
In some embodiments, silicon carbide coatings with the same thickness are deposited on the upper surface and the lower surface of the base, and then the upper surface of the first silicon carbide coating and the lower surface of the second silicon carbide coating are polished, so that the first silicon carbide coating and the second silicon carbide coating reach respective preset thicknesses, thereby obtaining the semiconductor base. The polishing mode is not limited, and can be flat polishing or finish machining.
In some embodiments, the deposition time is 30h-600h, such as may be 30h, 50h, 100h, 200h, 300h, 400h, 500h, and 600h, and the thickness of the deposited first silicon carbide coating layer and the thickness of the second silicon carbide coating layer are the same.
In some embodiments, silicon carbide may be deposited on the upper and lower surfaces of the susceptor for different times to provide silicon carbide coatings of different thicknesses. In some embodiments, a first silicon carbide coating of a predetermined thickness is deposited directly on the upper surface of the susceptor and a second silicon carbide coating of a predetermined thickness is deposited on the lower surface of the susceptor. In some embodiments, silicon carbide coatings of different thicknesses are deposited on the upper and lower surfaces of the susceptor, and then the first and second silicon carbide coatings are each independently brought to a predetermined thickness by polishing.
In some embodiments, a first silicon carbide coating is deposited on the upper surface of the susceptor for a time period of 30 h-500 a h a, such as 30 a h a 50 a h a 100 a h a 150 a h a 200 a h a 250 a h a 300 a h a.
In some embodiments, a second silicon carbide coating is deposited on the lower surface of the susceptor for a time period of 100 h-600: 600 h, such as 100 h, 200h, 300 h, 400 h, 500 h, and 600: 600 h.
The third aspect of the invention provides a metal organic chemical vapor deposition device, which comprises the semiconductor base in the first aspect and/or the semiconductor base prepared by the method in the second aspect.
The semiconductor base has better temperature field uniformity, and is beneficial to improving the integral heat storage capacity of the semiconductor base.
The technical solutions in the embodiments of the present invention will be clearly and completely described in the following in conjunction with the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Materials, reagents and the like used in the examples described below are commercially available unless otherwise specified.
The invention is described in detail below in connection with specific embodiments, which are intended to be illustrative rather than limiting.
Example 1
The embodiment is used for explaining the preparation method of the semiconductor base.
(1) Placing a graphite base in a chemical vapor deposition furnace (CVD deposition furnace), introducing CH 3SiCl3 gas and H 2 into the CVD deposition furnace by using protective gas Ar, wherein the flow rate of the CH 3SiCl3 gas is 20L/min, the flow rate of the H 2 gas is 240L/min, the flow rate of the protective gas Ar is 10L/min, and setting deposition process parameters: the deposition temperature is 1400 ℃, the deposition pressure is 10 kPa, the deposition time is 300 h, after chemical vapor deposition is completed, the introduction of reaction gas is stopped, and the argon protection gas is continuously introduced for cooling treatment, so that a first silicon carbide coating deposited on the upper surface of the graphite base and a second silicon carbide coating deposited on the lower surface of the graphite base are obtained.
(2) Polishing the first silicon carbide coating and the second silicon carbide coating to enable the thickness of the first silicon carbide coating to be about 0.5mm, the roughness of the upper surface of the first silicon carbide coating to be 1 mu m, the thickness of the second silicon carbide coating to be about 10mm, and the roughness of the lower surface of the second silicon carbide coating to be about 50 mu m.
Example 2
This example is presented to illustrate the preparation of a graphite susceptor when the ratio of the thickness of the first silicon carbide coating to the thickness of the second silicon carbide coating is different.
Example 2-1
The process of example 1 was followed, except that the first silicon carbide coating had a thickness of 0.4 mm a and the second silicon carbide coating had a thickness of 10 a mm a.
Example 2-2
The process of example 1 was followed, except that the first silicon carbide coating had a thickness of 2mm a and the second silicon carbide coating had a thickness of 10a mm a.
Examples 2 to 3
The process of example 1 was followed, except that the first silicon carbide coating had a thickness of 5 mm a and the second silicon carbide coating had a thickness of 10 a mm a.
Example 3
This example is used to illustrate the preparation of a graphite susceptor when the ratio of the roughness of the upper surface of the first silicon carbide coating to the roughness of the lower surface of the second silicon carbide coating is different.
Example 3-1
The operation was performed according to the method of example 1, except that the roughness of the upper surface of the first silicon carbide coating was 5 μm and the roughness of the lower surface of the second silicon carbide coating was 50 μm.
Example 3-2
The operation was performed according to the method of example 1, except that the roughness of the upper surface of the first silicon carbide coating was 10 μm and the roughness of the lower surface of the second silicon carbide coating was 50 μm.
Comparative example 1
This comparative example is used to illustrate the preparation of a graphite susceptor when the relationship between roughness and thickness of the lower surfaces of the first and second silicon carbide coatings is not applicable.
The process of example 1 was followed, except that the thickness of the first silicon carbide coating was greater than the thickness of the second silicon carbide coating, and the roughness of the upper surface of the first silicon carbide coating was greater than the roughness of the lower surface of the second silicon carbide coating. The first silicon carbide coating had a thickness of 15 mm a and the second silicon carbide coating had a thickness of 10a mm a. The roughness of the upper surface of the first silicon carbide coating is 60 mu m, and the roughness of the lower surface of the second silicon carbide coating is 50 mu m.
Comparative example 2
This comparative example is used to illustrate the preparation of a graphite susceptor when the relationship between roughness and thickness of the lower surfaces of the first and second silicon carbide coatings is not applicable.
The process of example 1 was followed, except that the thickness of the first silicon carbide coating was equal to the thickness of the second silicon carbide coating, and the roughness of the upper surface of the first silicon carbide coating was equal to the roughness of the lower surface of the second silicon carbide coating. The first silicon carbide coating has a thickness of 10 mm a and the second silicon carbide coating has a thickness of 10 a mm a. The roughness of the upper surface of the first silicon carbide coating is 50 mu m, and the roughness of the second silicon carbide coating is 50 mu m.
Comparative example 3
This comparative example is used to illustrate the preparation of a graphite susceptor when the relationship of the thicknesses of the first silicon carbide coating and the second silicon carbide coating is not applicable.
The process of example 1 was followed, except that the thickness of the first silicon carbide coating was greater than the thickness of the second silicon carbide coating. The first silicon carbide coating had a thickness of 15 mm a and the second silicon carbide coating had a thickness of 10 a mm a.
Comparative example 4
This comparative example is used to illustrate the preparation of a graphite susceptor when the relationship of roughness of the lower surface of the first silicon carbide coating to that of the second silicon carbide coating is not applicable.
The procedure of example 1 was followed, except that the roughness of the upper surface of the first silicon carbide coating was greater than the roughness of the lower surface of the second silicon carbide coating. The roughness of the upper surface of the first silicon carbide coating is 60 mu m, and the roughness of the lower surface of the second silicon carbide coating is 50 mu m.
Test example:
The examples and comparative examples were tested as follows. The experimental results are shown in Table 1.
(1) Emissivity: the surface emissivity of the examples and the comparative examples are respectively tested by an emissivity tester, the testing range is set at 6-14 mu m, the equipment registration error is +/-0.02, and the testing precision is less than or equal to 0.1FS.
(2) Emissivity difference: emissivity of the lower surface of the second silicon carbide coating-emissivity of the upper surface of the first silicon carbide coating.
TABLE 1
Fig. 1 is a temperature field pattern of a physical photovoltaic panel made of a semiconductor base of comparative example 2, fig. 2 is a temperature field pattern of a physical photovoltaic panel made of a semiconductor base of example 1, and the green area represents a temperature range required for production. Shown in fig. 1 is a temperature field profile of a semiconductor substrate where the roughness of the upper surface of the first silicon carbide coating is equal to the roughness of the lower surface of the second silicon carbide coating and the thickness of the first silicon carbide coating is equal to the thickness of the second silicon carbide coating. Shown in fig. 2 is a temperature field profile of a semiconductor substrate having a first silicon carbide coating with an upper surface having a roughness that is less than a roughness of a lower surface of a second silicon carbide coating, and a thickness of the first silicon carbide coating is less than a thickness of the second silicon carbide coating. Compared with fig. 1, the temperature field of fig. 2 is more uniform than the temperature field of fig. 1, i.e. the thermal field uniformity is better, i.e. reducing the thickness of the upper surface of the first silicon carbide coating and reducing the roughness helps to improve the heat storage capacity of the photovoltaic panel, thereby improving the thermal field uniformity.
According to the embodiment and the comparative example, the roughness of the upper surface of the first silicon carbide coating on the upper surface of the semiconductor base is smaller than that of the lower surface of the second silicon carbide coating on the lower surface of the base, so that the thickness of the first silicon carbide coating is smaller than that of the second silicon carbide coating, the thermal emissivity of the lower surface of the semiconductor base can be large, the thermal emissivity of the upper surface of the semiconductor base is small, the whole heat storage capacity of the semiconductor base is improved, the semiconductor base forms a uniform temperature field, and finally the film forming quality of the thin film on the wafer is improved.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is to be construed as including any modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (8)
1. The semiconductor substrate is characterized by comprising a substrate, a first silicon carbide coating arranged on the upper surface of the substrate and a second silicon carbide coating arranged on the lower surface of the substrate; the thickness of the first silicon carbide coating is smaller than that of the second silicon carbide coating, the roughness of the upper surface of the first silicon carbide coating is smaller than that of the lower surface of the second silicon carbide coating, the emissivity of the upper surface of the first silicon carbide coating is smaller than that of the lower surface of the second silicon carbide coating, and the ratio of the emissivity of the upper surface of the first silicon carbide coating to the emissivity of the lower surface of the second silicon carbide coating is1 (1.02-1.2).
2. The semiconductor pedestal of claim 1, wherein the ratio of the emissivity of the upper surface of the first silicon carbide coating to the emissivity of the lower surface of the second silicon carbide coating is 1 (1.02-1.11); and/or the number of the groups of groups,
The emissivity of the upper surface of the first silicon carbide coating is 0.88-0.995.
3. The semiconductor pedestal of claim 1, wherein the ratio of the thickness of the first silicon carbide coating to the thickness of the second silicon carbide coating is 1 (2-30); and/or the number of the groups of groups,
The first silicon carbide coating has a thickness of 0.2 mm to 5a mm a.
4. The semiconductor pedestal of claim 1, wherein the ratio of the roughness of the upper surface of the first silicon carbide coating to the roughness of the lower surface of the second silicon carbide coating is 1 (2-60); and/or the number of the groups of groups,
The roughness of the upper surface of the first silicon carbide coating is 0.5-15 mu m.
5. The semiconductor pedestal according to claim 1, wherein the pedestal is a graphite pedestal and/or a glassy carbon pedestal; and/or the number of the groups of groups,
The thermal expansion coefficient of the base is 4.5-5 multiplied by 10 -6/DEG C; and/or the number of the groups of groups,
The thickness of the base is 5 mm-16 mm.
6. A method of making the semiconductor pedestal of any one of claims 1-5, the method comprising:
taking a base with equal surface roughness of the upper surface and the lower surface, and placing the base in a deposition chamber;
Depositing a first silicon carbide coating on an upper surface of the susceptor;
Depositing a second silicon carbide coating on the lower surface of the base;
And polishing the upper surface of the first silicon carbide coating and the lower surface of the second silicon carbide coating to obtain the semiconductor base.
7. The method of claim 6, wherein the deposition conditions of the first silicon carbide coating and the second silicon carbide coating each independently comprise: the silane and hydrogen are introduced into the deposition chamber, the flow ratio of the silane to the reducing gas is 1 (8-16), the deposition temperature is 1350-1450 ℃, and the deposition pressure is 5 kPa-20 kPa.
8. A metal organic chemical vapor deposition apparatus comprising the semiconductor substrate according to any one of claims 1 to 5 and/or the semiconductor substrate prepared by the method according to claim 6 or 7.
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