CN118335609A - A three-dimensional semiconductor substrate wafer for IGBT device manufacturing and preparation method thereof - Google Patents

Abstract

The present invention discloses a three-dimensional semiconductor substrate wafer for manufacturing IGBT devices and a preparation method thereof. The three-dimensional semiconductor substrate wafer comprises a semiconductor substrate wafer, a first conductive layer, a second conductive layer and a field base layer, a collector layer and a protective layer, the back of the semiconductor substrate wafer is provided with a plurality of array-distributed grooves; the first conductive layer is provided on the surface of each groove; the second conductive layer and the field base layer are provided on the back surface of the semiconductor substrate wafer without a groove, and the second conductive layer and the field base layer are connected to the first conductive layer; the collector layer is provided on the surface of the first conductive layer and the second conductive layer and the field base layer; the protective layer is provided on the surface of the collector layer; wherein the groove is composed of a plurality of array-distributed doping bodies deep inside the semiconductor substrate wafer, and the first conductive layer, the collector layer and the protective layer are deep inside the semiconductor substrate wafer. The preparation method is used to prepare the three-dimensional semiconductor substrate wafer.

Description

A three-dimensional semiconductor substrate wafer for IGBT device manufacturing and preparation method thereof

Technical Field

The present invention relates to the technical field of semiconductor devices, and in particular to a three-dimensional semiconductor substrate wafer for manufacturing IGBT devices and a preparation method thereof.

Background technique

At present, China has begun to use diffusion polishing substrates as raw materials for IGBT chip production. According to the design requirements of IGBT chips, the chip factory needs to diffuse polishing substrates with the following structures: N-semiconductor wafers, N+ high-concentration impurities are diffused from the back of the semiconductor wafer into the wafer, and the diffusion depth is generally above 150um. The ideal impurity concentration gradient curve is that the same high-concentration impurity level is maintained close to the surface of the silicon wafer, while the diffusion end 10-30um deep into the silicon wafer presents a large impurity concentration gradient.

In the diffusion polishing substrate material manufacturing stage, the production of semiconductor wafer diffusion polishing substrate sheets needs to go through pre-expansion, oxidation, and advancement processes to ensure the ultra-deep diffusion thickness and diffusion concentration gradient required for IGBT chip manufacturing. In the IGBT chip manufacturing process, after completing the chip front process manufacturing, the N-region thickness of non-ultra-high voltage IGBT products is required to be thinner, and the wafer needs to be thinned from the back of the wafer to the designed thickness and morphology (taking 600V IGBT as an example, the wafer needs to be thinned to about 80um), and surface defects are removed by chemical polishing, and then the back of the wafer is N-type doped, P+ type doped, and metal evaporated.

In the IGBT diffusion polishing substrate material and chip manufacturing backside process, there are several contradictions and pain points:

1. The purpose of the ultra-deep diffusion depth requirement for the back of the IGBT diffusion polishing substrate material is to increase the thickness of the silicon wafer to ensure that the silicon wafer is not easily broken during IGBT production. However, the ultra-deep diffusion depth means a more complicated process flow for the manufacture of substrate materials, and the high temperature upper limit and long-term high temperature requirements for the diffusion equipment. At the same time, the large diffusion depth makes it difficult to obtain an ideal concentration gradient for the vertical distribution of N+ diffusion impurities in the silicon wafer. This increases the process difficulty, equipment requirements, more time and energy waste, and it is difficult to obtain excellent substrate material performance.

2. High-precision thinning equipment is required to thin the wafer from the back to a specified thickness, with a surface flatness of less than 3um, while retaining the original thickness of about 5mm at the edge of the silicon wafer. After mechanical thinning, the surface needs to be chemically polished to remove surface defects. The process has extremely high requirements for equipment, and the equipment is expensive. The cost of one piece of equipment often costs several million dollars;

3. It is necessary to use high-energy ion implantation plus laser rapid annealing to dope the back of the thinned wafer. Because the wafer front process has been completed, the depth of the formed N/P+ layer is limited, which limits the current density. During the process, the ultra-thin wafer is prone to breakage under doping and annealing stress;

4. Before metal evaporation, particles need to be bombarded to remove the oxide layer on the back surface of the wafer, which will reduce the thickness of the P+ layer;

5. The cleaning before metal evaporation on the back of the ultra-thin wafer and the stress between the metal and the silicon wafer during the evaporation process can also easily cause the wafer to break.

Summary of the invention

In order to solve at least one of the problems mentioned in the above background technology, an object of the present invention is to provide a three-dimensional semiconductor substrate wafer for IGBT device manufacturing and a preparation method thereof.

The present invention is achieved through the following technical solutions:

A three-dimensional semiconductor substrate wafer for manufacturing an IGBT device, comprising:

A semiconductor substrate wafer, wherein a plurality of grooves distributed in an array are provided on the back side of the semiconductor substrate wafer;

A first conductive layer, wherein the first conductive layer is disposed on a surface of each of the grooves;

A second conductive layer and a field base layer, wherein the second conductive layer and the field base layer are disposed on a back surface of the semiconductor substrate wafer where the groove is not disposed, and the second conductive layer and the field base layer are connected to the first conductive layer;

A collector layer, the collector layer being disposed on the surfaces of the first conductive layer, the second conductive layer and the field base layer;

A protective layer, the protective layer being disposed on the surface of the current collecting layer;

The grooves are composed of a plurality of doped bodies distributed in an array and extending deep into the interior of the semiconductor substrate wafer, and the first conductive layer, the collector layer and the protective layer extend deep into the interior of the semiconductor substrate wafer.

Optionally, the semiconductor substrate wafer is an N-type semiconductor substrate wafer, the first conductive layer is an N+ type conductive layer, the second conductive layer and the field base layer are N type conductive layer and the field base layer, and the collector layer is a P+ type collector layer.

Optionally, the semiconductor substrate wafer is a P-type semiconductor substrate wafer, the first conductive layer is a P+ type conductive layer, the second conductive layer and the field base layer are P type conductive layer and the field base layer, and the collector layer is an N+ type collector layer.

Optionally, the back side of the semiconductor substrate wafer is a collector, which is compatible with a through structure and a cut-off structure.

Optionally, the protective layer is a SiO2 layer or a polysilicon layer or a combination of a SiO2 layer and a polysilicon layer.

Optionally, the semiconductor substrate wafer is in the shape of a circular thin sheet.

Optionally, the dopant is conical or columnar, and the dopant presents a high concentration gradient distribution in the vertical depth.

Optionally, the groove is conical, columnar or prism-shaped.

A preparation method for preparing a three-dimensional semiconductor substrate wafer for IGBT device manufacturing as provided in any of the above embodiments, comprising:

S1: forming the semiconductor substrate wafer;

S2: making a plurality of grooves distributed in an array on the back side of the semiconductor substrate wafer;

S3: forming the first conductive layer by high-temperature diffusion doping on the surface of the groove;

S4: forming the second conductive layer and the field base layer by diffusion doping on the back side of the semiconductor substrate wafer;

S5: Diffusion forming the collector layer on the back side of the semiconductor substrate wafer;

S6: growing or depositing the protective layer on the back side of the semiconductor substrate wafer.

The beneficial effects of the present invention are as follows: the three-dimensional semiconductor substrate wafer for IGBT device manufacturing and the preparation method thereof solve the technical problems in the prior art that it is difficult to obtain an ideal concentration gradient for the vertical distribution of diffused impurities in a silicon wafer, the equipment is expensive, and the ultra-thin wafer is easy to break under doping and annealing stress, and achieve the beneficial effects: the three-dimensional semiconductor substrate wafer for IGBT device manufacturing completes the production of the back N/P+ of the IGBT in the substrate material manufacturing stage, and is also suitable for IGCT chip production. The chip thickness is increased by the first conductive layer, and the high concentration gradients of the second conductive layer, the field base layer and the semiconductor substrate wafer are controlled by controlling the first conductive layer to present different high concentration gradients in the longitudinal depth, forming an impurity absorption center with irreversibility, which can greatly reduce the defect density inside the chip and improve the chip's anti-burning ability. At the same time, a common collector structure is adopted, which is compatible with the design concepts of a through structure and a cut-off structure, so that the chip has a better volt-ampere characteristic, thereby reducing the difficulty of IGBT chip manufacturing, shortening the manufacturing process, and reducing production costs. The method for preparing a three-dimensional semiconductor substrate wafer for IGBT device manufacturing does not require a TAICK process when manufacturing an IGBT chip, and enables a VDMOS chip production line to be compatible with IGBT chip manufacturing, thereby reducing the difficulty of the IGBT chip manufacturing process, process equipment requirements, and production costs, and improving production capacity and substrate material performance.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

FIG. 1 is a three-dimensional semiconductor substrate wafer for IGBT device manufacturing according to an embodiment of the present invention;

FIG2 is a three-dimensional semiconductor substrate wafer for IGBT device manufacturing according to another embodiment of the present invention;

Among them, 1. semiconductor substrate wafer; 2. groove; 3. first conductive layer; 4. second conductive layer and field base layer; 5. collector layer; 6. protective layer.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. The components of the embodiments of the present invention generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents the selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present invention.

Hereinafter, a three-dimensional semiconductor substrate wafer for manufacturing an IGBT device and a preparation method thereof according to an embodiment of the present invention will be specifically described with reference to FIGS. 1-2 .

As shown in Figures 1-2, a three-dimensional semiconductor substrate wafer for manufacturing IGBT devices provided according to an embodiment of the present invention includes a semiconductor substrate wafer 1, a first conductive layer 3, a second conductive layer and a field base layer 4, a collector layer 5 and a protective layer 6, wherein the back side of the semiconductor substrate wafer 1 is provided with a plurality of array-distributed grooves 2; the first conductive layer 3 is provided on the surface of each of the grooves 2; the second conductive layer and the field base layer 4 are provided on the back surface of the semiconductor substrate wafer 1 where the grooves 2 are not provided, and the second conductive layer and the field base layer 4 are connected to the first conductive layer 3; the collector layer 5 is provided on the surface of the first conductive layer 3 and the second conductive layer and the field base layer 4; the protective layer 6 is provided on the surface of the collector layer 5; wherein the grooves 2 are composed of a plurality of doped bodies distributed in an array and extending deep into the interior of the semiconductor substrate wafer 1, and the first conductive layer 3, the collector layer 5 and the protective layer 6 extend deep into the interior of the semiconductor substrate wafer 1.

It should be noted that the semiconductor substrate wafer 1 can be of any semiconductor material, size, shape and thickness; the groove 2 can be conical, columnar, angular, straight or other structures, and the vertical depth, horizontal dimension and doping concentration of the groove 2 entering the substrate material can be adjusted according to needs.

The three-dimensional semiconductor substrate wafer for IGBT device manufacturing and the preparation method thereof of the present invention solve the technical problems in the prior art that it is difficult to obtain an ideal concentration gradient for the vertical distribution of diffused impurities in a silicon wafer, the equipment is expensive, and the ultra-thin wafer is easy to break under doping and annealing stress, and achieves beneficial effects: the three-dimensional semiconductor substrate wafer for IGBT device manufacturing completes the production of the back N/P+ of the IGBT in the substrate material manufacturing stage, and is also suitable for IGCT chip production. The chip thickness is increased by the first conductive layer 3, and the high concentration gradient of the second conductive layer and the field base layer 4 and the semiconductor substrate wafer 1 is controlled by controlling the first conductive layer 3 to present different high concentration gradients in the longitudinal depth, forming an impurity absorption center with irreversibility, which can greatly reduce the defect density inside the chip and improve the chip's anti-burning ability. At the same time, a common collector structure is adopted, which is compatible with the design concepts of the through structure and the cut-off structure, so that the chip has a better volt-ampere characteristic, thereby reducing the difficulty of IGBT chip manufacturing, shortening the manufacturing process, and reducing production costs.

As shown in FIG1 , in one embodiment, the semiconductor substrate wafer 1 is an N-type semiconductor substrate wafer, the first conductive layer 3 is an N+ type conductive layer, the second conductive layer and the field base layer 4 are N-type conductive layers and field base layers, and the collector layer 5 is a P+ type collector layer. Thus, by increasing the chip thickness through a three-dimensional deep junction high-concentration N+ structure, the thermal stress of the semiconductor wafer can be greatly reduced, the semiconductor wafer is flatter and tougher, and is not easy to break during the semiconductor chip manufacturing process, which can greatly reduce the "ultra-thin" requirements of the semiconductor wafer, solve the ultra-thin sheet processing technology problem based on the back metallization of the traditional semiconductor wafer, and achieve the purpose of reducing the difficulty of IGBT chip manufacturing, shortening the manufacturing process, and reducing production costs, and enabling ordinary VDMOS production lines to have IGBT chip production capabilities.

As shown in FIG2 , in another embodiment, the semiconductor substrate wafer 1 is a P-type semiconductor substrate wafer, the first conductive layer 3 is a P+ type conductive layer, the second conductive layer and the field base layer 4 are P-type conductive layers and the field base layer, and the collector layer 5 is an N+ type collector layer. Thus, the chip thickness is increased through the three-dimensional deep junction high concentration P+ structure.

In one embodiment, the back side of the semiconductor substrate wafer 1 is a collector electrode, which is compatible with a through structure and a cut-off structure. Thus, the chip has a better volt-ampere characteristic, effectively improving the current density of the semiconductor chip. The power consumption of the semiconductor chip based on the present invention can be greatly reduced compared with the traditional semiconductor chip.

In one embodiment, the protective layer 6 is a SiO ₂ layer or a polysilicon layer or a combination of a SiO ₂ layer and a polysilicon layer, thereby protecting the semiconductor substrate wafer 1 without affecting the performance of the semiconductor substrate wafer 1 .

In one embodiment, the semiconductor substrate wafer 1 is in the shape of a circular thin sheet, thereby reducing the difficulty in manufacturing the IGBT chip.

In one embodiment, the dopant is conical or columnar, and the dopant presents a high concentration gradient distribution in the vertical depth, thereby improving the conductivity of the semiconductor substrate wafer 1.

In one embodiment, the groove 2 is cone-shaped, column-shaped, or prism-shaped, thereby making the structure of the semiconductor substrate wafer 1 stable.

A preparation method for preparing a three-dimensional semiconductor substrate wafer for IGBT device manufacturing as provided in any of the above embodiments, comprising:

S1: forming the semiconductor substrate wafer 1;

S2: making a plurality of grooves 2 distributed in an array on the back side of the semiconductor substrate wafer 1;

S3: forming the first conductive layer 3 by high-temperature diffusion doping on the surface of the groove 2;

S4: forming the second conductive layer and the field base layer 4 by diffusion doping on the back side of the semiconductor substrate wafer 1;

S5: forming the collector layer 5 by diffusion on the back side of the semiconductor substrate wafer 1;

S6: growing or depositing the protection layer 6 on the back side of the semiconductor substrate wafer 1 .

It should be noted that the shape, spacing, depth and distribution of the array-distributed grooves 2 in S2 are adjusted according to the actual needs of the device; the doping concentration and depth of the first conductive layer 3 in S3 are adjusted according to the actual needs of the device; the doping concentration and depth of the second conductive layer and the field base layer 4 in S4 are adjusted according to the actual needs of the device; the doping concentration and depth of the collector layer 5 in S5 are adjusted according to the actual needs of the device.

Therefore, the method for preparing a three-dimensional semiconductor substrate wafer for IGBT device manufacturing does not require a TAICK process when making IGBT chips, and makes the VDMOS chip production line compatible with IGBT chip production, reduces the difficulty of IGBT chip manufacturing process, process equipment requirements, and production costs, and improves production capacity and substrate material performance. At the same time, it is suitable for IGCT chip production.

In the description of the embodiments of the present invention, it should be understood that the terms "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present invention.

In addition, the terms "first" and "another" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "multiple" and "several" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection, an electrical connection, or communication with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

In the description of this specification, the description with reference to the terms "one embodiment", "one example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction.

Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims (9)

1. A three-dimensional semiconductor substrate wafer for IGBT device fabrication, comprising:

the semiconductor substrate wafer is provided with a plurality of grooves distributed in an array on the back surface;

The first conducting layer is arranged on the surface of each groove;

The second conducting layer and the field base layer are arranged on the back surface of the semiconductor substrate wafer, which is not provided with the groove, and are connected with the first conducting layer;

The current collecting layer is arranged on the surfaces of the first conducting layer, the second conducting layer and the field base layer;

The protective layer is arranged on the surface of the current collecting layer;

The grooves are formed by a plurality of doping bodies which are distributed in an array manner and extend into the semiconductor substrate wafer, and the first conducting layer, the current collecting layer and the protective layer extend into the semiconductor substrate wafer.

2. The three-dimensional semiconductor substrate wafer for IGBT device fabrication of claim 1 wherein the semiconductor substrate wafer is an N-type semiconductor substrate wafer, the first conductive layer is an n+ type conductive layer, the second conductive layer and the field base layer are an N-type conductive layer and a field base layer, and the collector layer is a p+ type collector layer.

3. The three-dimensional semiconductor substrate wafer for IGBT device fabrication of claim 1 wherein the semiconductor substrate wafer is a P-type semiconductor substrate wafer, the first conductive layer is a p+ type conductive layer, the second conductive layer and the field base layer are a P-type conductive layer and a field base layer, and the collector layer is an n+ type collector layer.

4. The three-dimensional semiconductor substrate wafer for IGBT device fabrication of claim 1 wherein the back side of the semiconductor substrate wafer is a collector, compatible with punch-through and cut-off structures.

5. The three-dimensional semiconductor substrate wafer for IGBT device fabrication of claim 1 wherein the protective layer is a SiO ₂ layer or a polysilicon layer or a combination of a SiO ₂ layer and a polysilicon layer.

6. The three-dimensional semiconductor substrate wafer for IGBT device fabrication of claim 1 wherein the semiconductor substrate wafer is in the shape of a circular sheet.

7. The three-dimensional semiconductor substrate wafer for IGBT device fabrication of claim 1 wherein the dopant is cone or pillar shaped, the dopant exhibiting a high concentration gradient profile at a longitudinal depth.

8. The three-dimensional semiconductor substrate wafer for IGBT device fabrication of claim 1 wherein the grooves are cone-shaped or pillar-shaped or prismatic.

9. A method of manufacturing a three-dimensional semiconductor substrate wafer for IGBT device fabrication according to any one of claims 1 to 8, comprising:

S1: forming the semiconductor substrate wafer;

s2: manufacturing a plurality of grooves distributed in an array on the back surface of the semiconductor substrate wafer;

s3: forming the first conducting layer on the surface of the groove through high-temperature diffusion doping;

S4: forming the second conducting layer and the field base layer by diffusion doping on the back surface of the semiconductor substrate wafer;

s5: forming the collector layer by diffusion on the back surface of the semiconductor substrate wafer;

s6: and growing or depositing the protective layer on the back surface of the semiconductor substrate wafer.