CN118335011B - Driving circuit, driving method and display device - Google Patents

Abstract

The application discloses a driving circuit, a driving method and a display device, wherein the driving circuit comprises a plurality of rows of gate lines and a plurality of gate driving units, the input end of each row of gate lines is connected with the output end of a corresponding gate driving unit, and a gate driving signal is received to control the opening or closing of a thin film transistor connected with the gate lines; each row of grid lines at least comprises a first grid line segment and a second grid line segment, and a first refresh rate adjusting circuit is arranged between the first grid line segment and the second grid line segment; the first refresh rate adjustment circuit is configured to control on and off between the first gate line segment and the second gate line segment. According to the application, the grid lines are segmented, and the on and off of the grid line segments are controlled by setting the refresh rate adjusting circuit, so that the dynamic change of different refresh rates of different partitions is realized, a grid driving circuit is not required to be independently arranged corresponding to each partition, the increase of frames is avoided, and the wiring difficulty is increased.

Description

Driving circuit, driving method and display device

Technical Field

The present application relates to the field of display technologies, and in particular, to a driving circuit, a driving method, and a display device.

Background

With the development of display technology, there is an increasing demand for display panels, for example, when the display panels display dynamic images such as video and games, the refresh frequency of the display images needs to be high to prevent flicker, while under static display images such as web page text browsing, the refresh frequency of the display images needs to be low to reduce power consumption.

In the current display panel, the whole pixel adopts the same refresh rate; however, in some product applications, different display partitions of the same display panel do not always need to perform data refreshing under the same display frame, if different display partitions of the same display panel, such as a static area and a dynamic area, use the same refresh rate to perform data refreshing, if both use high-speed brushing, the power consumption of the display panel will increase, and if use low-speed brushing, the dynamic picture display will flicker; in order to realize different refresh rates of different partitions, different gate driving circuits are generally adopted by different refresh partitions, but the frame design of the screen body is widened, and the wiring difficulty is increased.

Disclosure of Invention

The application aims to provide a driving circuit, a driving method and a display device, which can increase the transmittance of a display panel.

The application discloses a driving circuit, which comprises a plurality of rows of gate lines and a plurality of gate driving units, wherein the input end of each row of gate lines is connected with the output end of a corresponding gate driving unit, and receives a gate driving signal to control the opening or closing of a thin film transistor connected with the gate lines; each row of gate lines at least comprises a first gate line segment and a second gate line segment, and a first refresh rate adjusting circuit is arranged between the first gate line segment and the second gate line segment; the first refresh rate adjustment circuit is configured to control on and off between the first gate line segment and the second gate line segment.

Optionally, the first refresh rate adjustment circuit includes a first control unit and a second control unit, where the gate driving unit outputs a gate driving signal to an input end of the first gate segment, the input end of the first control unit is connected to an output end of the first gate segment, the output end is connected to an input end of the second gate segment, and the control end is connected to a first control signal; the input end of the second control unit is connected with a first level signal, the output end of the second control unit is connected with the input end of the second grid line segment, and the control end of the second control unit is connected with a second control signal; the first level signal is a low level signal, and the first control signal and the second control signal are a pair of opposite signals which are alternately turned on at least one frame apart.

Optionally, the driving circuit includes an OLED pixel driving circuit, and the OLED pixel driving circuit further includes a plurality of light emitting control lines disposed in cascade, where the light emitting control lines are disposed parallel to the gate lines and in one-to-one correspondence with the gate lines, the light emitting control lines include a first light emitting control line segment and a second light emitting control line segment, a light emitting control circuit is disposed between the first light emitting control line segment and the second light emitting control line segment, and the light emitting control circuit is configured to control on and off between the first light emitting control line segment and the second light emitting control line segment; the light-emitting control circuit comprises a first light-emitting control unit and a second light-emitting control unit, wherein the input end of the first light-emitting control unit is connected with the output end of the first light-emitting control line segment, the output end of the first light-emitting control unit is connected with the input end of the second light-emitting control line segment, and the control end of the first light-emitting control unit is connected with a first control signal; the input end of the second light-emitting control unit is connected with a second level signal, the output end of the second light-emitting control unit is connected with the input end of the second light-emitting control line segment, and the control end of the second light-emitting control unit is connected with a second control signal.

Optionally, the driving circuit further includes a level signal control circuit, and the level signal control circuit includes a first driving switch and a second driving switch; the first refresh rate adjustment circuit includes a first control switch and a second control switch; the driving circuit comprises an OLED pixel driving circuit, the OLED pixel driving circuit further comprises a plurality of light-emitting control lines which are arranged in a cascading mode, the light-emitting control lines are parallel to the grid lines and are arranged in a one-to-one correspondence mode, the light-emitting control lines comprise first light-emitting control line segments and second light-emitting control line segments, and a first light-emitting control switch and a second light-emitting control switch are arranged between the first light-emitting control line segments and the second light-emitting control line segments; the input end of the first control switch is connected with the output end of the first grid line segment, the output end of the first control switch is connected with the input end of the second grid line segment, and the control end of the first control switch is connected with a first control signal; the input end of the second control switch is connected with a first level signal, the output end of the second control switch is connected with the input end of the second grid line segment, and the control end of the second control switch is connected with the output end of the first drive switch; the input end of the first light-emitting control switch is connected with the output end of the first light-emitting control line segment, the output end of the first light-emitting control switch is connected with the input end of the second light-emitting control line segment, and the control end of the first light-emitting control switch is connected with a first control signal; the input end of the second light-emitting control switch is connected with a second level signal, the output end of the second light-emitting control switch is connected with the input end of the second light-emitting control line segment, and the control end of the second light-emitting control switch is connected with the output end of the first driving switch; the control end of the first driving switch is connected with a first control signal, the input end of the first driving switch is connected with a first level signal, the output end of the first driving switch is connected with the control ends of the second control switch and the second light-emitting control switch, and the first control end of the second driving switch; the input end of the second driving switch is connected with a second level signal and a second control end, and the output end of the second driving switch is connected with the first control end; the first level signal is a low level signal, and the second level signal is a high level signal.

Optionally, each row of gate lines further includes a third gate line segment, and the driving circuit further includes a second refresh rate adjustment circuit, where the second refresh rate adjustment circuit is disposed between the second gate line segment and the third gate line segment; the second refresh rate adjustment circuit is configured to control on and off between the second gate line segment and the third gate line segment; the plurality of gate driving units are divided into a first gate driving unit group and a second gate driving unit group, the first gate driving unit group and the second gate driving unit group are respectively arranged at two ends of the gate line, the first gate driving unit group is connected with the input end of the first gate line segment, and the second gate driving unit group is connected with the input end of the third gate line segment.

Optionally, the driving circuit includes a frame start signal generating module, where the frame start signal generating module is connected to the first gate driving unit group and the second gate driving unit group respectively; when the refresh rate of the area corresponding to the second gate line segment is 2N and the refresh rate of the area corresponding to the first gate line segment and the third gate line segment is N, the frame start signal generating module generates a first frame start signal and a second frame start signal respectively, and outputs the first frame start signal and the second frame start signal to the odd-numbered line gate driving units and the even-numbered line gate driving units of the first gate unit group so that the first gate driving unit group generates a corresponding gate driving signal, and generates a third frame start signal and a fourth frame start signal to the even-numbered line gate driving units and the odd-numbered line gate driving units of the second gate driving unit group so that the second gate driving unit group generates a corresponding driving signal; the first gate driving unit group generates a gate driving signal, and the second gate driving unit group generates a gate driving signal, and the gate driving signal is input to the first gate line segment and the second gate line segment.

Optionally, each row of gate lines further includes a third gate line segment, and the driving circuit further includes a second refresh rate adjustment circuit, where the second refresh rate adjustment circuit is disposed between the second gate line segment and the third gate line segment; the second refresh rate adjustment circuit is configured to control on and off between the second gate line segment and the third gate line segment; the plurality of gate driving units are divided into a first gate driving unit group, a second gate driving unit group and a third gate driving unit group, the first gate driving unit group and the second gate driving unit group are respectively arranged at two ends of a gate line, the first gate driving unit group is connected with an input end of a first gate line segment, the second gate driving unit group is connected with an input end of a third gate line segment, and the third gate driving unit group is connected to an input section of a second gate line segment through a wiring.

Optionally, the first refresh rate adjustment circuit includes a first control unit and a second control unit, where an output end of the first control unit is connected to an output end of the first gate segment, an input end of the first control unit is connected to an input end of the second gate segment, an output end of the gate driving unit receives a gate driving signal, and a control end of the first control unit is connected to the first control signal; the input end of the second control unit is connected with a first level signal, the output end of the second control unit is connected with the input end of the first grid line segment, and the control end of the second control unit is connected with a second control signal; the first level signal is a low level signal, and the first control signal and the second control signal are a pair of opposite signals alternately opened at intervals of frames.

The application also discloses a driving method for driving the driving circuit according to any one of the above, the driving method comprises the following steps:

generating a grid driving signal and a data signal before the next frame of picture is displayed;

Receiving refresh rate data of a display area corresponding to a first grid line segment and a second grid line segment of a next frame; and

When the refresh rates of the display areas corresponding to the first grid line segment and the second grid line segment are different, the first refresh rate adjusting circuit is controlled to be turned off, and the grid driving signal is output to the thin film transistor connected with the first grid line segment and is turned on; when the refresh rates of the display areas corresponding to the first grid line segment and the second grid line segment are the same, the first refresh rate adjusting circuit is controlled to conduct, and the grid driving signal is output to the thin film transistor connected with the first grid line segment and the second grid line segment and is turned on.

The application also discloses a display device which comprises the driving circuit and a display panel, wherein the driving circuit is used for driving the display panel.

Compared with the scheme that each partition is correspondingly provided with one gate driving circuit, the gate line is divided into at least two sections, the refresh rate adjusting circuit is arranged between the gate line sections, the refresh rate between the two gate line sections is controlled by the refresh rate adjusting circuit to be turned on and off, the refresh rate between the two gate line sections can be changed, dynamic changes of different refresh rates of the partitions are realized, the gate driving circuit is not required to be arranged corresponding to each partition, the frame is prevented from being increased, wiring difficulty is increased, the gate line can be divided into multiple sections according to the required partition size, the area size of the partition is adjusted, and further dynamic changes of different refresh rates of different partitions are realized.

Drawings

The accompanying drawings, which are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is evident that the figures in the following description are only some embodiments of the application, from which other figures can be obtained without inventive effort for a person skilled in the art. In the drawings:

FIG. 1 is a schematic diagram of a driving circuit according to a first embodiment of the present application;

FIG. 2 is a schematic diagram of a driving circuit according to a second embodiment of the present application;

FIG. 3 is a schematic diagram of waveforms of driving signals according to a second embodiment of the present application;

FIG. 4 is a schematic diagram of a driving circuit according to a third embodiment of the present application;

Fig. 5 is a schematic diagram of a driving signal waveform of a third embodiment of the present application;

Fig. 6 is a schematic diagram of a driving circuit of a fourth embodiment of the present application;

Fig. 7 is a schematic diagram of a driving signal waveform of a fourth embodiment of the present application;

fig. 8 is a schematic diagram of a driving circuit of a fifth embodiment of the present application;

fig. 9 is a schematic diagram of a driving signal waveform of a fifth embodiment of the present application;

fig. 10 is a schematic diagram of a driving circuit of a sixth embodiment of the present application;

fig. 11 is a schematic diagram of a driving circuit of a seventh embodiment of the present application;

FIG. 12 is a schematic flow chart of a driving method according to an eighth embodiment of the present application;

fig. 13 is a schematic structural view of a display device according to a ninth embodiment of the present application.

100, A driving circuit; 101. a gate driving circuit; 102. an OLED pixel driving circuit; 110. a gate driving unit; 111. a first gate driving unit group; 112. a second gate driving unit group; 113. a third gate driving unit group; 120. a gate line; 121. a first gate line segment; 122. a second gate line segment; 123. a third gate line segment; 130. a refresh rate adjustment circuit; 131. a first refresh rate adjustment circuit; 132. a second refresh rate adjustment circuit; 133. a first control unit; 134. a second control unit; 140. a light emission control line; 141. a first lighting control line segment; 142. a second lighting control line segment; 150. a light emission control circuit; 151. a first light emission control unit; 152. a second light emission control unit; 160. a level signal control circuit; 170. a frame start signal generation module; 180. a timing control chip; 200. a display panel; 210. a first partition; 220. a second partition; 230. a third partition; 300. a display device;

A T-thin film transistor; t1-a first control switch; t2-a second control switch; t1' -first light emitting control switch; t2' -second light emission control switch; ta-a first drive switch; tb-a second drive switch; s (1) -S (n)/S '(1) -S' (n) -gate drive signals; e (1) -E (n)/E '(1) -E' (n) -emission control signals; DF-first control signal; DFB-a second control signal; VGL-first level signal; VGH-second level signal.

Detailed Description

It is to be understood that the terminology used herein, the specific structural and functional details disclosed are merely representative for the purpose of describing particular embodiments, but that the application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.

The application is described in detail below with reference to the attached drawings and alternative embodiments.

Referring to fig. 1, as a first embodiment of the present application, a driving circuit 100 is disclosed, wherein the driving circuit 100 includes a plurality of rows of gate lines 120 and a plurality of gate driving units 110, and an input terminal of each row of gate lines 120 is connected to an output terminal of a corresponding one of the gate driving units 110, and receives a gate driving signal to control on or off of a thin film transistor connected to the gate line 120; each row of gate lines 120 at least comprises a first gate line segment 121 and a second gate line segment 122, and a first refresh rate adjustment circuit 131 is disposed between the first gate line segment 121 and the second gate line segment 122; the first refresh rate adjustment circuit 131 is configured to control on and off between the first gate line segment 121 and the second gate line segment 122.

The application divides the gate line 120 into at least two sections, the refresh rate adjusting circuit 130 is arranged between the gate line 120 sections, the refresh rate between the two gate line 120 sections is controlled by the refresh rate adjusting circuit 130 to be different, the display of different refresh rates of the subareas is realized, thus the grid driving circuit 101 is not required to be arranged separately for each subarea, the frame is prevented from being increased, the wiring difficulty is increased, the gate line 120 can be divided into a plurality of sections according to the required subarea size, the area size of the subareas is adjusted, the dynamic change of different refresh rates of different subareas is realized, and a foundation is provided for the random division of the subareas of the same display panel 200.

As shown in fig. 2 and fig. 3, as a second embodiment of the present application, which is a further refinement and improvement of the first embodiment, the present embodiment is applicable to the liquid crystal display panel 200 and the OLED display panel 200, where the first refresh rate adjustment circuit 131 includes a first control unit 133 and a second control unit 134, the gate driving unit 110 outputs a gate driving signal to the input end of the first gate line segment 121, the input end of the first control unit 133 is connected to the output end of the first gate line segment 121, the output end is connected to the input end of the second gate line segment 122, and the control end is connected to the first control signal; the input end of the second control unit 134 is connected with a first level signal, the output end is connected with the input end of the second grid line segment 122, and the control end is connected with a second control signal; the first level signal is a low level signal, and the first control signal and the second control signal are a pair of opposite signals which are alternately turned on at least one frame apart.

The first gate line segment 121 corresponds to the first partition 210, and the second gate line segment 122 corresponds to the second partition 220; the first control unit 133 includes a first control switch T1, the second control unit 134 includes a second control switch T2, and a first control switch T1 and a second control switch T2 are disposed between the first gate line segment 121 and the second gate line segment 122 in each row of gate lines 120, and a gate driving signal of each row is input into the second partition 220 at the end of the first partition 210 through the respective first control switch T1; the present embodiment discloses a circuit structure of the first refresh rate adjustment circuit 131, which is designed to include two TFTs (T1 & T2), wherein T1 is that the first control switch T1 is controlled by the down-conversion signal DF, i.e. the first control signal, and T2 is controlled by the second control signal DFB; DF and DFB are a pair of inverted signals, and the first level signal is a relatively low voltage constant voltage source.

If the refresh rates of the areas corresponding to the first gate line segment and the second gate line segment 122 are different, in the first period of time, the gate driving unit 110 outputs a gate driving signal to the first gate line segment 121 to control the thin film transistor connected to the first gate line segment 121 to be turned on, and the first refresh rate adjusting circuit 131 disconnects the first gate line segment 121 from the second gate line segment 122 and inputs a first level signal to the second gate line segment 122 to control the thin film transistor connected to the second gate line segment 122 to be turned off; in a second period, the gate driving unit 110 outputs a gate driving signal to the first gate line segment 121 to control the thin film transistor connected to the first gate line segment 121 to be turned on, and the first refresh rate adjustment circuit 131 turns on the connection between the first gate line segment 121 and the second gate line segment 122 and inputs a gate driving signal to the second gate line segment 122 to control the thin film transistor connected to the second gate line segment 122 to be turned on; causing the region of the first gate line segment 121 to realize the display of a first refresh rate and the region of the second gate line segment 122 to realize the display of a second refresh rate, wherein the first refresh rate is n times the second refresh rate, and the multiple relationship between the first refresh rate and the second refresh rate is determined through the interval time setting of the first time period and the second time period; if the refresh rates of the regions corresponding to the first gate line segment and the second gate line segment 122 are the same, the first refresh rate adjustment circuit 131 is kept on in both the first period and the second period, where the first period and the second period are continuous periods, i.e., the end time of the first period is the start time of the second period.

As shown in fig. 4 and fig. 5, as a third embodiment of the present application, which is also a further refinement and improvement of the above-mentioned second embodiment, the present embodiment is mainly directed to a further improvement of the OLED display panel 200, where the driving circuit 100 includes an OLED pixel driving circuit 102, the OLED pixel driving circuit 102 further includes a plurality of light emitting control lines 140 disposed in cascade, where the light emitting control lines 140 are disposed parallel to and in one-to-one correspondence with the gate lines 120, and the light emitting control lines 140 include a first light emitting control line segment 141 and a second light emitting control line segment 142, and a light emitting control circuit 150 is disposed between the first light emitting control line segment 141 and the second light emitting control line segment 142, and the light emitting control circuit 150 is configured to control on and off between the first light emitting control line segment 141 and the second light emitting control line segment 142; the light emission control circuit 150 and the first refresh rate adjustment circuit 131 may use the same control signals, i.e., the first control signal and the second control signal; the light emission control circuit 150 includes a first light emission control unit 151 and a second light emission control unit 152, where an input end of the first light emission control unit 151 is connected to an output end of the first light emission control line segment 141, an output end is connected to an input end of the second light emission control line segment 142, and a control end is connected to a first control signal; the input end of the second light emitting control unit 152 is connected to the second level signal, the output end is connected to the input end of the second light emitting control line segment 142, and the control end is connected to the second control signal.

The first light emitting control unit 151 includes a first light emitting control switch T1', and the second light emitting control unit 152 includes a second light emitting control switch T2', in this embodiment, the gate lines 120 and the light emitting control lines 140 corresponding to the OLED display panel 200 are segmented, and the segmented positions are in the same column region, i.e., the lengths of the two segmented segments of the gate lines 120 are the same as the lengths of the two segmented ends of the light emitting control lines 140, and the widths of the corresponding display regions are the same.

In the OLED pixel driving circuit 102, the pixel driving circuit 100 corresponding to one sub-pixel generally has at least 2 TFT devices, wherein the TFTs responsible for resetting and writing data need to be turned on only briefly in one frame time, and the driving signals required by such TFTs are called Scan signals; another TFT responsible for controlling whether to Emit light needs to be turned off briefly within a frame time, the driving signal required by the TFT is called a light emission control signal Emit, the Emit signal is output by the light emission control line 140, and in the OLED display panel 200, the frequency change of different partitions of the display panel 200 requires the frequency change of the Scan signal and the Emit signal simultaneously; referring to fig. 3, E (1-n) is a signal waveform of a certain Emit signal of n rows of pixels of the whole screen body in the first partition 210, and each E (n) is at a low potential in a shorter time within a frame time, and is shifted backward by one row period (1/n frame periods); e' (1-n) is an Emit signal input waveform of n rows of pixels in the corresponding second partition 220, wherein DF and DFB are a pair of opposite signals alternately opened at intervals, and the second level signal is a relatively high-voltage constant voltage source.

When the refresh rates of the two display areas corresponding to the first gate line segment and the second gate line segment 122 are different, taking the refresh rate of the first partition 210 as 2 times the refresh rate of the second partition 220 as an example, for example, the refresh rate of the first partition 210 is 120Hz, and the refresh rate of the second partition 220 is 60Hz; in a first period, the gate driving unit 110 outputs a gate driving signal to the first gate line segment 121 to control the thin film transistor connected to the first gate line segment 121 to be turned on, the first refresh rate adjusting circuit 131 disconnects the first gate line segment 121 from the second gate line segment 122, and inputs a first level signal to the second gate line segment 122 to control the thin film transistor connected to the second gate line segment 122 to be turned off, the light-emitting control signal is turned off briefly after each pixel in the first partition 210 emits light, and the light-emitting control signal is turned off for one frame time after each pixel in the second partition 220 emits light; in a second period, the gate driving unit 110 outputs a gate driving signal to the first gate line segment 121 to control the thin film transistor connected to the first gate line segment 121 to be turned on, and the first refresh rate adjustment circuit 131 turns on the connection between the first gate line segment 121 and the second gate line segment 122 and inputs a gate driving signal to the second gate line segment 122 to control the thin film transistor connected to the second gate line segment 122 to be turned on; such that the region of the first gate line segment 121 achieves a display of 120Hz refresh rate and the region of the second gate line segment 122 achieves a display of 60Hz refresh rate.

As shown in fig. 6 and fig. 7, as a fourth embodiment of the present application, which is a further refinement and improvement of the above-described first embodiment, the driving circuit 100 further includes a level signal control circuit 160, and the level signal control circuit 160 includes a first driving switch Ta and a second driving switch Tb; the first refresh rate adjustment circuit 131 includes a first control switch T1 and a second control switch T2; the driving circuit 100 includes an OLED pixel driving circuit 102, where the OLED pixel driving circuit 102 further includes a plurality of light emitting control lines 140 disposed in cascade, and the light emitting control lines 140 are disposed parallel to and in one-to-one correspondence with the gate lines 120; the light emitting control line 140 includes a first light emitting control line segment 141 and a second light emitting control line segment 142, and a first light emitting control switch T1 'and a second light emitting control switch T2' are disposed between the first light emitting control line segment 141 and the second light emitting control line segment 142; the input end of the first control switch T1 is connected to the output end of the first gate line segment 121, the output end is connected to the input end of the second gate line segment 122, and the control end is connected to a first control signal; the input end of the second control switch T2 is connected with a first level signal, the output end of the second control switch T2 is connected with the input end of the second grid line segment 122, and the control end of the second control switch T2 is connected with the output end of the first driving switch Ta; the input end of the first light-emitting control switch T1' is connected to the output end of the first light-emitting control line segment 141, the output end is connected to the input end of the second light-emitting control line segment 142, and the control end is connected to a first control signal; the input end of the second light-emitting control switch T2' is connected with a second level signal, the output end of the second light-emitting control switch T2' is connected with the input end of the second light-emitting control line segment 142, and the control end of the second light-emitting control switch T2' is connected with the output end of the first driving switch Ta; the first driving switch Ta is a three-terminal TFT device, the second driving switch Tb is a four-terminal TFT device, and compared with the three-terminal device of the first driving switch Ta, a bottom gate is added, and the threshold voltage of the TFT can be adjusted by the bottom gate voltage.

Further, the control end of the first driving switch Ta is connected with a first control signal, the input end of the first driving switch Ta is connected with a first level signal, and the output end of the first driving switch Ta is connected with the control ends of the second control switch T2 and the second light-emitting control switch T2', and the first control end of the second driving switch Tb; the input end of the second driving switch Tb is connected with a second level signal and a second control end, and the output end of the second driving switch Tb is connected with a first control end; the first level signal is a low level signal, and the second level signal is a high level signal; the gate lines 120 and the light-emitting control lines 140 of the OLED display panel 200 are segmented, and the segmented positions are in the same column region, that is, the lengths of the two segmented segments of the gate lines 120 are the same as the lengths of the two segmented ends of the light-emitting control lines 140, and the widths of the corresponding display regions are consistent; in the case of a fixed partition, the input waveform of the second partition 220 may be adjusted by adjusting the duty cycle of the DF signal to achieve refresh rate adjustment of the second partition 220 such that the refresh rate of the second partition 220 is 1/n (n is a positive integer) of the refresh rate of the first partition 210, as shown in fig. 7.

The present embodiment can cancel the direct input of the DFB signal from the external drive, and automatically generate the DFB signal opposite to DF by the DF signal and VGH/VGL. Specifically, in the first stage: DF is high voltage (such as 15V), ta is opened, VGL voltage (such as-7V) is written into DFB node; at the moment of writing low voltage, tb is kept on because Tb bottom gate is controlled by VGH and potential is high (such as 15V), VGH & VGL are output to DFB node at the same time. By the design of TFT device size, such as (Ta Width) > 10 x (Tb Width), DFB node is gradually written to low potential by VGL; in the second stage: when DF is turned to a low voltage (for example, -7V), VGL is turned to a low voltage (for example, -7V), and Ta is turned off at this time, so VGH continuously outputs a high voltage (15V) to DFB through Tb.

As shown in fig. 8 and 9, as a further development of any of the foregoing embodiments, each row of gate lines 120 further includes a third gate line segment 123, i.e. one gate line 120 is divided into three segments, wherein the driving circuit 100 further includes a second refresh rate adjustment circuit 132, and the second refresh rate adjustment circuit 132 is disposed between the second gate line segment 122 and the third gate line segment 123; the second refresh rate adjustment circuit 132 is configured to control on and off between the second gate line segment 122 and the third gate line segment 123; the plurality of gate driving units 110 are divided into a first gate driving unit group 111 and a second gate driving unit group 112, the first gate driving unit group 111 and the second gate driving unit group 112 are respectively disposed at two ends of the gate line 120, the first gate driving unit group 111 is connected with an input end of the first gate line segment 121, and the second gate driving unit group 112 is connected with an input end of the third gate line segment 123.

In this embodiment, the display area of the display panel 200 may be divided into three areas, i.e. each row of gate lines 120 is divided into three sections, the first gate line section 121 corresponds to the first partition 210, the second gate line section 122 corresponds to the second partition 220, the third gate line section 123 corresponds to the third partition 230, and a refresh rate adjustment circuit 130 is disposed between two adjacent ends to control the communication between two adjacent sections of gate lines 120, in order to avoid that in a large-size case, the gate lines 120 are too long, resulting in deformation of signals received by the area far from the gate driving circuit 101 or reduction of voltage, resulting in brightness reduction, the gate driving units 110 are disposed on two sides of the display panel 200 respectively; the first refresh rate adjustment circuit 131 and the second refresh rate adjustment circuit 132 are combined to control the refresh rates of the three regions, if the refresh rates of the first partition 210 and the third partition 230 are the same, the first partition 210 and the third partition 230 receive the gate driving signals at the same time in the first period or the first frame time, and the two refresh rate adjustment circuits 130 disconnect the first gate line segment 121 and the second gate line segment 122 and the third gate line segment 123 respectively, and in the second period or the second frame time, the first partition 210, the second partition 220 and the third partition 230 receive the gate driving signals at the same time, and one of the refresh rate adjustment circuits 130 between the first gate line segment 121 and the second gate line segment 122 and between the second gate line segment 122 and the third gate line segment 123 is kept on; in addition, if the first refresh rate is 120Hz, the second refresh rate is 60Hz, and the third refresh rate is 30Hz, then both refresh rate adjustment circuits 130 may be turned off during the first period, and the second gate driving unit group 112 does not input the gate driving signal to the third gate line segment 123, that is, only the first partition 210 is displayed, the first refresh rate adjustment circuit 131 is turned on, the second refresh rate adjustment circuit 132 remains turned off, the first partition 210 and the second partition 220 are displayed, the third partition 230 is not displayed, the first refresh rate adjustment circuit 131 and the second refresh rate adjustment circuit 132 are turned on, and the first partition 210, the second partition 220 and the third partition 230 are all displayed, and the gate line 120 segment in the third partition 230 receives the driving signal of the second gate driving unit group 112.

Further, waveforms of the first control signal and the second control signal of the first refresh rate adjustment circuit and the second refresh rate adjustment circuit may be the same or different, assuming that the first control signal of the first refresh rate adjustment circuit is DF1, the second control signal is DFB1, the first control signal of the second refresh rate adjustment circuit is DF2, the second control signal is DFB2, when three areas display the same refresh rate, the waveforms of DF1 and DF2 are the same, the waveforms of DFB1 and DFB2 are the same, and when the refresh rates of the middle area and the two areas are different, the waveforms of DF1 and DF2 are different, and the waveforms of DFB1 and DFB2 are also different; assume that DF2 is low when DF2 is high, or DF1 is low, when DF2 is high, when the middle region is 60Hz and the side regions are 120 Hz.

It should be noted that, the second partition 220 may be displayed at 120Hz, and the first partition 210 and the third partition 230 may be displayed at 60Hz, specifically, the driving circuit 100 includes a frame start signal generating module 170, and the frame start signal generating module 170 is connected to the first gate driving unit group 111 and the second gate driving unit group 112, respectively; when the refresh rate of the area corresponding to the second gate line segment 122 is 2N and the refresh rate of the area corresponding to the first gate line segment 121 and the third gate line segment 123 is N, the frame start signal generating module 170 generates a first frame start signal and a second frame start signal, respectively, and outputs the first frame start signal and the second frame start signal to the odd-numbered row gate driving units 110 and the even-numbered row gate driving units 110 of the first gate unit group so that the first gate driving unit group 111 generates a corresponding gate driving signal, and generates a third frame start signal and a fourth frame start signal, and outputs the third frame start signal and the fourth frame start signal to the even-numbered row gate driving units 110 and the odd-numbered row gate driving units 110 of the second gate driving unit group 112 so that the second gate driving unit group 112 generates a corresponding driving signal; the gate driving signals generated by the first gate driving unit group 111 are input to the first gate line segment 121 and the second gate line segment 122, and the gate driving signals generated by the second gate driving unit group 112 are input to the third gate line segment 123 and the second gate line segment 122.

The driving signals of the second partition 220 can be given to the first partition 210 during displaying, the driving signals of the third partition 230 can be given to the second partition 220 during displaying, and the driving signals of the first partition 210 and the third partition 230 can be cross-staggered, that is, when the first line of the first partition 210 is displayed, the first line of the second partition 220 is synchronously displayed, after the first line of the first partition 210 is displayed, the second line of the third partition 230 starts to be displayed, and simultaneously the second line of the second partition 220 is synchronously displayed, which is equivalent to that in four frames, the first partition 210 is displayed in two frames, the two frames are not displayed, the third partition 230 is displayed in two frames, the two frames of the first partition 210 is displayed in the third partition 230, and the two frames of the third partition 230 is not displayed in the first partition 210 is displayed, and the second partition 220 is displayed in four frames, so that the refresh rate of the middle area can be twice the refresh rate of the two frames.

As shown in fig. 10, as a further development of any of the above embodiments, the driving circuit 100 further includes a second refresh rate adjustment circuit 132, where the second refresh rate adjustment circuit 132 is disposed between the second gate line segment 122 and the third gate line segment 123, and each row of gate lines 120 further includes a third gate line segment 123; the second refresh rate adjustment circuit 132 is configured to control on and off between the second gate line segment 122 and the third gate line segment 123; the plurality of gate driving units 110 are divided into a first gate driving unit group 111, a second gate driving unit group 112 and a third gate driving unit group 113, the first gate driving unit group 111 and the second gate driving unit group 112 are respectively disposed at two ends of the gate line 120, the first gate driving unit group 111 is connected with an input end of the first gate line segment 121, the second gate driving unit group 112 is connected with an input end of the third gate line segment 123, and the third gate driving unit group 113 is connected to an input section of the second gate line segment 122 through a routing.

In this example, the gate driving units 110 are divided into three groups, each group corresponding to one partition, but the first gate driving unit group 111 may control two partitions of the first partition 210 and the second partition 220 in combination with the first refresh rate adjustment circuit 131, and when the second partition 220 wants to achieve a refresh rate higher than that of the two side partitions, the control may be performed by separately inputting driving signals through the second gate driving unit group 112.

As shown in fig. 11, as a further development of the first embodiment of the present application, the first refresh rate adjustment circuit 131 includes a first control unit 133 and a second control unit 134, unlike the second embodiment, where an output end of the first control unit 133 is connected to an output end of the first gate segment 121, an input end is connected to an input end of the second gate segment 122, and an output end of the gate driving unit 110 receives a gate driving signal, and a control end is connected to the first control signal; the input end of the second control unit 134 is connected with a first level signal, the output end is connected with the input end of the first grid line segment 121, and the control end is connected with a second control signal; the first level signal is a low level signal, and the first control signal and the second control signal are a pair of opposite signals alternately opened at intervals of frames.

The present embodiment inputs the gate driving signal into the second partition 220, and outputs the gate driving signal to the first partition 210 or the third partition 230 through the refresh rate adjusting circuit 130, so that the refresh rate of the middle partition is greater than the refresh rate of the two side partitions, which of course may also continue to use the original partition refresh rate changing mode, that is, the gate driving signal is given to the gate line 120 segments of the two side partitions, so as to implement the refresh rate changing mode that the refresh rate of the two side partitions decreases from the middle to the two sides, which may be combined for use, so as to implement the refresh rate decreasing from the middle to the two sides, or implement the refresh rate decreasing from the two sides to the middle region, or implement the multiple adjusting modes that the refresh rate decreases from the left side to the right side in sequence, so as to improve the degree of freedom of changing the refresh rate of the partition.

As shown in fig. 12, as an eighth embodiment of the present application, there is also disclosed a driving method for driving the driving circuit 100 according to any one of the above embodiments, the driving method including the steps of:

s1: generating a grid driving signal and a data signal before the next frame of picture is displayed;

s2: receiving refresh rate data of a display area corresponding to a first grid line segment and a second grid line segment of a next frame;

S3: when the refresh rates of the display areas corresponding to the first grid line segment and the second grid line segment are different, the first refresh rate adjusting circuit is controlled to be turned off, and the grid driving signal is output to the thin film transistor connected with the first grid line segment and is turned on; when the refresh rates of the display areas corresponding to the first gate line segment and the second gate line segment are the same, the first refresh rate adjustment circuit 131 is controlled to conduct, and the gate driving signal is output to the thin film transistor connected to the first gate line segment 121 and the second gate line segment 122 and turned on.

Referring to fig. 2 and 12, in the present embodiment, the adjustment of the partition refresh rate is mainly achieved by controlling the first refresh rate adjustment circuit 131 to be turned off and on; generally, if the refresh rates of the areas corresponding to the first gate line segment and the second gate line segment 122 are 120Hz in the current frame, if the refresh rates of the areas corresponding to the first gate line segment and the second gate line segment 122 are adjusted to different magnitudes, in the first period, the first refresh rate adjustment circuit 131 disconnects the first gate line segment 121 from the second gate line segment 122, and the gate driving unit 110 outputs a gate driving signal to the first gate line segment 121 to control the thin film transistor connected to the first gate line segment 121 to be turned on, and simultaneously inputs a first level signal to the second gate line segment 122 to control the thin film transistor connected to the second gate line segment 122 to be turned off so as to clear the residual voltage of the pixel corresponding to the second gate line segment 122; in a second period, the gate driving unit 110 outputs a gate driving signal to the first gate line segment 121 to control the thin film transistor connected to the first gate line segment 121 to be turned on, and the first refresh rate adjustment circuit 131 turns on the connection between the first gate line segment 121 and the second gate line segment 122 and inputs a gate driving signal to the second gate line segment 122 to control the thin film transistor connected to the second gate line segment 122 to be turned on; causing the region of the first gate line segment 121 to realize the display of a first refresh rate and the region of the second gate line segment 122 to realize the display of a second refresh rate, wherein the first refresh rate is n times the second refresh rate, and the multiple relationship between the first refresh rate and the second refresh rate is determined through the interval time setting of the first time period and the second time period; if the refresh rates of the regions corresponding to the first gate line segment and the second gate line segment 122 are the same, the first refresh rate adjustment circuit 131 is kept on in both the first period and the second period, where the first period and the second period are continuous periods, i.e., the end time of the first period is the start time of the second period.

As shown in fig. 13, as an eighth embodiment of the present application, the present application also discloses a display device 300, the display device 300 includes the driving circuit 100 and the display panel 200 according to any of the above embodiments, the driving circuit 100 is used for driving the display panel 200, the driving circuit 100 includes a gate driving circuit 101, the gate driving circuit includes a plurality of gate driving units 110, the gate driving unit 110 receives the frame start signal and the clock signal generated by the frame start signal generating module 170 of the timing control chip 180 to generate the gate driving signal to output to the segmented gate line segment, and the change of the partition refresh rate is realized in combination with the control circuit of the refresh rate adjusting circuit; on the basis of not adding an additional grid driving circuit, a frequency reducing module, namely a refresh rate adjusting circuit, is adopted to realize refresh partition design of more than or equal to 3 partitions transversely, so that power consumption is reduced, and meanwhile, an additional product frame is not added.

It should be noted that, the limitation of each step in the present solution is not to be considered as limiting the sequence of steps on the premise of not affecting the implementation of the specific solution, that is, the steps written in the previous step may be executed before, or executed after, or even executed simultaneously, so long as the implementation of the present solution is possible, all the steps should be considered as falling within the protection scope of the present application. The inventive concept of the present application can form a very large number of embodiments, but the application documents are limited in size and cannot be listed one by one, so that on the premise of no conflict, the above-described embodiments or technical features can be arbitrarily combined to form new embodiments, and after the embodiments or technical features are combined, the original technical effects can be enhanced.

The above description of the application in connection with specific alternative embodiments is further detailed and it is not intended that the application be limited to the specific embodiments disclosed. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the application, and these should be considered to be within the scope of the application.

Claims (6)

1. The driving circuit is characterized by comprising a plurality of rows of gate lines and a plurality of gate driving units, wherein the input end of each row of gate lines is connected with the output end of a corresponding gate driving unit, and receives a gate driving signal to control the opening or closing of a thin film transistor connected with the gate lines;

each row of gate lines at least comprises a first gate line segment and a second gate line segment, and a first refresh rate adjusting circuit is arranged between the first gate line segment and the second gate line segment; the first refresh rate adjustment circuit is used for controlling on and off between the first gate line segment and the second gate line segment;

the driving circuit further comprises a level signal control circuit, wherein the level signal control circuit comprises a first driving switch and a second driving switch;

the first refresh rate adjustment circuit includes a first control switch and a second control switch;

The driving circuit comprises an OLED pixel driving circuit, the OLED pixel driving circuit further comprises a plurality of light-emitting control lines which are arranged in a cascading mode, the light-emitting control lines are parallel to the grid lines and are arranged in a one-to-one correspondence mode, the light-emitting control lines comprise first light-emitting control line segments and second light-emitting control line segments, and a first light-emitting control switch and a second light-emitting control switch are arranged between the first light-emitting control line segments and the second light-emitting control line segments;

the input end of the first control switch is connected with the output end of the first grid line segment, the output end of the first control switch is connected with the input end of the second grid line segment, and the control end of the first control switch is connected with a first control signal; the input end of the second control switch is connected with a first level signal, the output end of the second control switch is connected with the input end of the second grid line segment, and the control end of the second control switch is connected with the output end of the first drive switch;

The input end of the first light-emitting control switch is connected with the output end of the first light-emitting control line segment, the output end of the first light-emitting control switch is connected with the input end of the second light-emitting control line segment, and the control end of the first light-emitting control switch is connected with a first control signal; the input end of the second light-emitting control switch is connected with a second level signal, the output end of the second light-emitting control switch is connected with the input end of the second light-emitting control line segment, and the control end of the second light-emitting control switch is connected with the output end of the first driving switch;

The control end of the first driving switch is connected with a first control signal, the input end of the first driving switch is connected with a first level signal, the output end of the first driving switch is connected with the control ends of the second control switch and the second light-emitting control switch, and the first control end of the second driving switch;

the input end of the second driving switch is connected with a second level signal and a second control end, and the output end of the second driving switch is connected with the first control end;

The first level signal is a low level signal, and the second level signal is a high level signal.

2. The drive circuit of claim 1, wherein each row of gate lines further comprises a third gate line segment, the drive circuit further comprising a second refresh rate adjustment circuit disposed between the second gate line segment and the third gate line segment; the second refresh rate adjustment circuit is configured to control on and off between the second gate line segment and the third gate line segment;

The plurality of gate driving units are divided into a first gate driving unit group and a second gate driving unit group, the first gate driving unit group and the second gate driving unit group are respectively arranged at two ends of the gate line, the first gate driving unit group is connected with the input end of the first gate line segment, and the second gate driving unit group is connected with the input end of the third gate line segment.

3. The drive circuit according to claim 2, wherein the drive circuit includes a frame start signal generation module that connects the first gate drive unit group and the second gate drive unit group, respectively;

When the refresh rate of the area corresponding to the second gate line segment is 2N and the refresh rate of the area corresponding to the first gate line segment and the third gate line segment is N, the frame start signal generating module generates a first frame start signal and a second frame start signal respectively, and outputs the first frame start signal and the second frame start signal to the odd-numbered line gate driving units and the even-numbered line gate driving units of the first gate unit group so that the first gate driving unit group generates a corresponding gate driving signal, and generates a third frame start signal and a fourth frame start signal to the even-numbered line gate driving units and the odd-numbered line gate driving units of the second gate driving unit group so that the second gate driving unit group generates a corresponding driving signal;

The first gate driving unit group generates a gate driving signal, and the second gate driving unit group generates a gate driving signal, and the gate driving signal is input to the first gate line segment and the second gate line segment.

4. The drive circuit of claim 1, wherein each row of gate lines further comprises a third gate line segment, the drive circuit further comprising a second refresh rate adjustment circuit disposed between the second gate line segment and the third gate line segment; the second refresh rate adjustment circuit is configured to control on and off between the second gate line segment and the third gate line segment;

the plurality of gate driving units are divided into a first gate driving unit group, a second gate driving unit group and a third gate driving unit group, the first gate driving unit group and the second gate driving unit group are respectively arranged at two ends of a gate line, the first gate driving unit group is connected with an input end of a first gate line segment, the second gate driving unit group is connected with an input end of a third gate line segment, and the third gate driving unit group is connected to an input end of a second gate line segment through a wiring.

5. A driving method for driving the driving circuit according to any one of claims 1 to 4, characterized in that the driving method comprises the steps of:

generating a grid driving signal and a data signal before the next frame of picture is displayed;

Receiving refresh rate data of a display area corresponding to a first grid line segment and a second grid line segment of a next frame; and

When the refresh rates of the display areas corresponding to the first grid line segment and the second grid line segment are different, the first refresh rate adjusting circuit is controlled to be turned off, and the grid driving signal is output to the thin film transistor connected with the first grid line segment and is turned on; when the refresh rates of the display areas corresponding to the first grid line segment and the second grid line segment are the same, the first refresh rate adjusting circuit is controlled to conduct, and the grid driving signal is output to the thin film transistor connected with the first grid line segment and the second grid line segment and is turned on.

6. A display device comprising the drive circuit according to any one of claims 1 to 4 and a display panel, the drive circuit being for driving the display panel.