CN118331907B

CN118331907B - Server, data transmission method of server, and storage medium

Info

Publication number: CN118331907B
Application number: CN202410752496.1A
Authority: CN
Inventors: 汉阳
Original assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Current assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Priority date: 2024-06-12
Filing date: 2024-06-12
Publication date: 2024-10-01
Anticipated expiration: 2044-06-12
Also published as: CN118331907A

Abstract

The embodiment of the application provides a server, a data transmission method of the server and a storage medium, wherein the server comprises the following components: the extended chip comprises a first master I3C interface, a front-end I3C bus and a first programmable logic device, wherein the first programmable logic device comprises a first slave I3C interface and a plurality of GPIO interfaces, the front-end I3C bus is an I3C bus connected with the first master I3C interface and the first slave I3C interface, the front-end I3C bus is used for carrying out data transmission between the extended chip and the first programmable logic device, the application solves the problem of poor adaptability of input and output expansion of the server in the related technology, and achieves the effect of improving the adaptability of the input and output expansion of the server.

Description

Server, data transmission method of server, and storage medium

Technical Field

The embodiment of the application relates to the field of computers, in particular to a server, a data transmission method of the server and a storage medium.

Background

The number of GPIOs (General Purpose Input/Output) for most chips within a server is typically fixed. With the development of server architecture, the number of devices and communication protocols to be connected to a chip are more complex, and the number of GPIOs is gradually unable to meet the demands.

In the related art, I/O (Input/Output) expansion of a server may be performed using a communication bus in combination with hardware, for example, a bridge chip is used to connect external devices.

Disclosure of Invention

The embodiment of the application provides a server, a data transmission method of the server and a storage medium, which at least solve the problem that the server in the related technology has poor adaptability of input and output expansion.

According to an embodiment of the present application, there is provided a server including: the device comprises an extended chip, a front-end I3C bus and a first programmable logic device, wherein the extended chip comprises a first main I3C interface, the first programmable logic device comprises a first auxiliary I3C interface and a plurality of GPIO interfaces, the front-end I3C bus is an I3C bus for connecting the first main I3C interface and the first auxiliary I3C interface, and the front-end I3C bus is used for carrying out data transmission between the extended chip and the first programmable logic device, wherein the extended chip is used for carrying out data exchange with the first programmable logic device through the front-end I3C bus so as to realize GPIO extension of the extended chip through the plurality of GPIO interfaces.

According to another embodiment of the present application, there is provided a data transmission method of a server, the server including an extended chip, a front-end I3C bus, and a first programmable logic device, the extended chip including a first master I3C interface, the first programmable logic device including a first slave I3C interface and a plurality of GPIO interfaces, the front-end I3C bus being an I3C bus connecting the first master I3C interface and the first slave I3C interface, the front-end I3C bus being for performing data transmission between the extended chip and the first programmable logic device, wherein the method includes: receiving first control data transmitted by the extended chip through the front-end I3C bus by the first slave I3C interface, wherein the first control data is used for controlling the GPIO interface of the first programmable logic device to execute a first appointed operation, and the GPIO interface of the first programmable logic device is used for extending the GPIO of the extended chip; and responding to the received first control data, and executing the first appointed operation on the GPIO interfaces corresponding to the first control data in the GPIO interfaces.

According to a further embodiment of the application, there is also provided a computer readable storage medium having stored therein a computer program, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.

According to a further embodiment of the application there is also provided an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.

According to a further embodiment of the application, there is also provided a computer program product comprising a computer program which, when executed by a processor, implements the steps of any of the method embodiments described above.

According to the application, the extended chip exchanges data with the programmable logic device through the I3C bus, so that GPIO expansion of the extended chip is realized through the GPIO interface of the programmable logic device, the GPIO expansion is realized by using the programmable logic device, the expansion number can be changed along with the types of the programmable logic device, the number of the programmable logic devices and the internal code setting, the expansion is diversified, the problem of poor adaptability of input and output expansion of a server in the related art can be solved, the number and flexibility of the input and output ports of the server are increased, and therefore, the performance and functions of the server are improved, and the effect of improving the adaptability of the input and output expansion of the server is achieved.

Drawings

Fig. 1 is a schematic diagram of a server according to an embodiment of the present application.

Fig. 2 is a schematic diagram of a CPLD extended internal topology according to an embodiment of the present application.

Fig. 3 is a schematic topology diagram of a CPLD extended IO system according to an embodiment of the present application.

Fig. 4 is a flowchart of a data transmission method of a server according to an embodiment of the present application.

Fig. 5 is a schematic diagram of an exemplary HDR-BT mode frame in accordance with an embodiment of the application.

Fig. 6 is a flowchart of another data transmission method of a server according to an embodiment of the present application.

Fig. 7 is an alternative CPLD extended CPU IO example topology according to an embodiment of the application.

Fig. 8 is a schematic diagram of an I3C entry high speed transmission scheme in accordance with an embodiment of the present application.

Detailed Description

Embodiments of the present application will be described in detail below with reference to the accompanying drawings in conjunction with the embodiments.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.

In this embodiment, a server is provided, fig. 1 is a schematic diagram of a server according to an embodiment of the present application, and as shown in fig. 1, the server includes:

the device comprises an extended chip, a front-end I3C (advanced Inter-INTEGRATED CIRCUIT) bus and a first programmable logic device, wherein the extended chip comprises a first master I3C interface, the first programmable logic device comprises a first slave I3C interface and a plurality of GPIO interfaces, the front-end I3C bus is an I3C bus connected with the first master I3C interface and the first slave I3C interface, the front-end I3C bus is used for carrying out data transmission between the extended chip and the first programmable logic device,

And the extended chip is used for exchanging data with the first programmable logic device through the front-end I3C bus so as to realize GPIO extension of the extended chip through a plurality of GPIO interfaces.

With the advent of Artificial Intelligence (AI) and machine learning workloads, servers tend towards high performance computing power and high storage capacity, requiring faster, more flexible I/O (input/output) options. For chips such as CPU (Central Processing Unit ), GPU (Graphic Processing Unit, graphics processor), BMC (Baseboard Management Controller, controller for server management on server motherboard), the number of GPIOs (General-purpose input/output interfaces) is fixed, but with the development of server architecture, the number of chips connected and communication protocols are more complex, and the number of GPIOs is gradually unable to meet the basic requirements. Choosing a chip with more I/O is naturally a method, but sometimes using bus extensions is more cost effective from a cost perspective. At present, the conventional communication buses such as I2C (Inter-INTEGRATED CIRCUT, serial communication bus of intel design) and the like used for expansion have limitations in terms of speed, flexibility, layout and wiring and the like.

Currently, the I/O extensions to servers include various hardware and software bus solutions. In terms of hardware, the 74HC595 shift register chip provides particular advantages for simple I/O expansion. The bridge chip provides another method for connecting the external device, and enhances the function of the server. In terms of buses, there are systems currently available that use a CPLD to implement I2C bus expansion, where the system uses a BMC to communicate and configure with the CPLD through a front-end I2C bus to establish a mapping for the front-end I2C and the back-end I2C buses to control slave devices connected to the back-end I2C bus. In addition, there are system schemes that extend IO using a bus such as SPI.

However, the 74HC595 chip, while useful for basic tasks, lacks the programmability and complexity required for advanced I/O operations. The bridge chip is used as a fixed function device, and the flexibility and the adaptability of the bridge chip cannot be compared with those of programmable logic devices such as CPLD and the like. Furthermore, in terms of buses, I2C is typically slower than I3C, and additional IO interfaces are required to add in-band interrupt functionality. Due to the continuous clock signal, the SPI consumes more power even without data transmission. And SPI typically requires more pins than I3C, which increases the complexity of the system design.

Overall, scalability, flexibility, and speed remain significant challenges in the field of I/O expansion, with poor hardware adaptability for server I/O expansion. As can be seen from this, the server in the related art has a problem of poor adaptability to input/output expansion.

In order to at least partially solve the above-mentioned problem, in this embodiment, a programmable logic device with an I3C bus is used to extend input/output in a server, the extended programmable logic device is linked with an extended chip by using the I3C bus, and related programs and pin configurations are performed on the extended programmable logic device, so that functions of GPIO extension and I3C extension of the chip are finally realized, and the device has advantages of high transmission rate, in-band interruption, hot joining and the like, and each pin on the programmable logic device can be set as input or output, and the extended chip can read or write these pins, so as to achieve an approximate physical connection effect.

With this embodiment, peripheral signals and redundant I3C buses can be monitored and controlled, and additional I/os can be added to the design, thereby freeing up the GPIOs of the extended chip for other more important functions.

Alternatively, in this embodiment, the first programmable logic device may include a plurality of GPIO interfaces. Here, multiple GPIO interfaces provide users with greater design flexibility, extensibility, parallel processing capability, cost effectiveness, integration, error tolerance, customization options, and convenience of debugging and maintenance.

In one exemplary embodiment, the first programmable logic device further includes: a register, and a GPIO controller, wherein,

The register is used for temporarily storing the data which is received by the first slave I3C interface and is transmitted to the GPIO controller by the extended chip so as to be read by the GPIO controller, and temporarily storing the data which is transmitted to the extended chip by the GPIO controller so as to be transmitted to the extended chip by the front-end I3C bus after being read by the first slave I3C interface;

And the GPIO controller is used for controlling the GPIO interfaces and temporarily storing the data to be transmitted to the extended chip into a register.

The register in the programmable logic device is used for storing and processing data, the GPIO controller is responsible for communicating with external equipment, and the register and the GPIO controller jointly provide flexibility and customizability for the design and the realization of the digital system.

In this embodiment, the extended chip communicates with the programmable logic device through the front-end I3C bus, and configures and reads the internal registers of the programmable logic device through the addressing action of the programmable logic device. And in the programmable logic device, the configuration logic module analyzes the configuration data of the front end I3C, and stores and reads the data according to a frame format preset in advance.

In an exemplary embodiment, the server further comprises at least one memory bank, and the plurality of GPIO interfaces are divided into at least one GPIO interface group, wherein the GPIO interface group in the at least one GPIO interface group is used to connect the memory bank in the at least one memory bank.

For example, in this embodiment, the GPIO controller controls the IO pins of the programmable logic device itself, where the output signals are uniformly set to tri-states (high, low, high resistance can be output); the input signal is connected to the register module after internal metastable state processing to be read by the I3C module. Taking the example that the I3C can transfer 32 bytes of data at a time in this embodiment, 32 IOs can be controlled simultaneously. The byte width may be user defined. In this embodiment, 8 IOs may be used as a group to control a DIMM (Dual In-line Memory Module, dual In-line memory module, referred to as "memory bank", which is a computer hardware). The IO setup is as in FIG. 2.

Wherein, 8 IOs are respectively: the cpu_sa_par, cpu_sb_par, cpu_sa_rsp, cpu_sb_rsp, cpu_dimm1_reset, cpu_dimm1_alert, pwrgd_dimm1, reserved, in particular, the cpu_sa_par (CPU SYSTEM AGENT PARALLEL) signal may be used to transmit a parallel communication signal between the CPU and DIMM 1; the CPU SB PAR (CPU System Bus Parallel) signal may be used to transmit parallel communication signals between the CPU and the front-end I3C bus; the cpu_sa_rsp (CPU SYSTEM AGENT Response) signal may be used to transmit a DIMM1 Response signal to the CPU; the CPU_SB_ RSP (CPU System Bus Response) signal may be used to transmit a response signal from the front-end I3C bus to the CPU; the CPU_DIMM1_RESET signal may be used to RESET the first dual inline memory module (DIMM 1) of the CPU; the CPU_DIMM1_ALERT signal may be used to indicate that the first DIMM of the CPU is in error or needs attention; the pwrgd_dimm1 (Power Good dimm1) signal may be used to indicate that the Power state of the first DIMM of the CPU is Good; the reserved signal may be reserved for future extensions or specific application scenarios.

SCL stands for Serial Clock Line for clock line, SDA stands for SERIAL DATA LINE for data line.

In an exemplary embodiment, the server further comprises a back-end communication bus, the first programmable logic device further comprises a second master I3C interface, wherein the back-end communication bus is one of: the I3C bus and the I2C bus are used for connecting the second master I3C interface and the second slave I3C interface of the slave module of the first programmable logic device.

The back-end communication bus is used for connecting the programmable logic device chip with other external devices or modules after the field programmable gate array is designed, and is responsible for transmitting data between the programmable logic device and other devices, wherein the data can be input data, output data or control signals and the like; through the back-end communication bus, the programmable logic device can send control instructions to control connected external equipment or modules, so that the operation and control of the equipment are realized; the back-end communication bus allows the programmable logic device to be connected with other equipment to form a larger system so as to realize the expansion and upgrading of functions and improve the performance and flexibility of the whole system.

Both the I2C bus and the I3C bus are serial communication protocols for connecting various electronic devices. I2C buses are widely used with lower transmission speeds and simple implementations, while I3C buses provide higher transmission speeds, full duplex communications, and other improved characteristics for higher performance systems.

In an exemplary embodiment, the server further includes at least one memory bank, the plurality of GPIO interfaces are divided into at least one GPIO interface group, the GPIO interface group in the at least one GPIO interface group is used to connect the memory bank in the at least one memory bank, and the slave module of the first programmable logic device includes at least one of: the system comprises a second programmable logic device, a microcontroller, a serial presence detection hub on a memory bank of at least one memory bank, a temperature sensor on a memory bank of at least one memory bank, and a fan on a memory bank of at least one memory bank.

For example, in this embodiment, DDR5 (Double DATA RATE FIFTH-generation Synchronous Dynamic Random-Access Memory), the fifth generation of Double data Rate synchronous dynamic random Access Memory (DDR SDRAM) introduces a sideband bus to Access non-DRAM modules. The sideband bus is based on MIPII C or I3C protocols. In addition to the sideband bus, there is also one SPD, the serial presence detect hub, as the number of components on DDR5 increases. Serial Presence Detect (SPD) is a standardized method for automatically accessing DDR3/4/5 memory module information. When the electronic system is powered on, it begins to automatically configure the system by identifying different hardware components. Through the extension of the CPLD, the CPU can read SPDs on a plurality of DDRs 5 through a single I3C, and can control pins of the DDRs 5 and the like.

Here, DIMMs (Dual-Inline-Memory-Modules) are one type of Memory bank.

In one exemplary embodiment, the first programmable logic device is a complex programmable logic device, the number of first programmable logic devices being a plurality, the plurality of first programmable logic devices being connected in a daisy-chain fashion.

CPLD (Complex Programmable Logic Device ) is a highly integrated programmable logic device, widely used in digital circuit design. The CPLD can be regarded as a combination of a plurality of PLAs (Programmable Logic Array, programmable Gate arrays) or PALs (Programmable Array Logic ), and has higher integration and flexibility.

Daisy chain Connection (DAISY CHAIN Connection) is a bus Connection, mainly for the Connection of multiple devices. In a daisy chain connection, each device is connected to the other devices via an input and an output terminal to form a chain structure, and the output terminal of the last device can be connected back to the input terminal of the first device to form a closed loop structure.

Daisy chain connections can reduce the number of wires required and reduce costs. Daisy chain connections may simplify circuit design so that a designer may more easily implement a connection of multiple devices. Due to the reduction of the number of wires, the daisy chain connection can reduce the failure rate of the circuit and improve the system stability. The daisy chain connection makes it simple to add or remove devices, facilitating system expansion. The daisy chain connection can easily adjust the connection sequence according to the needs, and the flexibility of the system is improved.

For example, in the present embodiment, the CPLD is used to access the extended chip, and the topology of the IO is extended through the I3C as shown in fig. 3. And modifying and expanding CPLD codes, upwardly communicating with chips such as BMC through I3C, obtaining a reading command and transmitting related information through a defined frame format. The information of the pins is read and controlled downwards through the GPIO, and is communicated with other modules (such as a temperature sensor on the DDR5 memory and the like) through the I3C.

In terms of expansion number, the expansion GPIO pin of each CPLD expansion chip is determined by the chip type, the CPLD can be changed automatically according to the demand and cost factors, the CPLD can simulate buses such as I3C, I2C and the like through built-in logic, a plurality of downstream buses can be expanded according to the demand, and chips such as MCU (Microcontroller Unit ) and the like can be cascaded on the downstream buses for use. Furthermore, multiple CPLDs may be selected to be spread, connected in a daisy-chain fashion, the number of links being limited only by the potential signal attenuation/distortion when cascading over many pins. The number of link extension CPLDs may not exceed 11, as suggested by the MIPI (Mobile Industry Processor Interface ) association.

In this embodiment, there is provided a data transmission method of a server, fig. 4 is a schematic diagram of a data transmission method of a server according to an embodiment of the present application, as shown in fig. 4, applied to a first programmable logic device on the server, the server includes an extended chip, a front-end I3C bus and a first programmable logic device, the extended chip includes a first master I3C interface, the first programmable logic device includes a first slave I3C interface and a plurality of GPIO interfaces, the front-end I3C bus is an I3C bus connecting the first master I3C interface and the first slave I3C interface, and the front-end I3C bus is used for data transmission between the extended chip and the first programmable logic device, where the method includes the steps of:

Step S402, receiving first control data transmitted by the extended chip through the front-end I3C bus by a first slave I3C interface, wherein the first control data is used for controlling the GPIO interface of a first programmable logic device to execute a first appointed operation, and the GPIO interface of the first programmable logic device is used for extending the GPIO of the extended chip;

in step S404, in response to the received first control data, a first designating operation is performed on a GPIO interface corresponding to the first control data among the multiple GPIO interfaces.

Through the steps, first control data transmitted by the extended chip through the front-end I3C bus is received through the first slave I3C interface, wherein the first control data is used for controlling the GPIO interface of the first programmable logic device to execute a first appointed operation, and the GPIO interface of the first programmable logic device is used for extending the GPIO of the extended chip; in response to the received first control data, a first appointed operation is executed on the GPIO interface corresponding to the first control data in the GPIO interfaces, so that the problem that the server in the related art is poor in adaptability of input and output expansion is solved, and the effect of improving the adaptability of the input and output expansion of the server is achieved.

In the technical solution provided in step S402, the first programmable logic device receives, through the first slave I3C interface, first control data transmitted by the extended chip via the front-end I3C bus, where the first control data is used to control execution of a first specified operation on the GPIO interface of the first programmable logic device, and the GPIO interface of the first programmable logic device is used to extend the GPIO of the extended chip.

Optionally, in an embodiment of the present application, the extended chip in the server may include, but is not limited to: BMC (baseboard management controller) chip: BMC chips are commonly used for server management, providing remote monitoring and control functions, possibly with GPIO interfaces, allowing administrators to control and monitor server hardware; a CPU chip, the CPU model may have a GPIO interface for communicating with an external device or implementing a specific system function; I/O expansion card: I/O expansion cards used in the server, such as SAS/SATA HBA cards, network cards or PCIe expansion cards, may integrate GPIO interfaces; hardware monitor module (HM): hardware monitoring modules are typically used to monitor and control the environment within the server, such as temperature, voltage, fan speed, etc., and may have GPIO interfaces to communicate with other system components; and a power management chip: some power management chips may have GPIO interfaces for monitoring power state, voltage, current, etc. parameters and communicating with other parts of the server.

Optionally, in this embodiment, the I3C is a serial communication protocol for connecting and communicating integrated circuits such as microcontrollers and sensors. I3C replaces the existing I2C (Inter-INTEGRATED CIRCUIT) protocol. I3C provides higher data transfer rates, lower power consumption, and a more flexible topology.

In an I3C system, there are two types of interfaces:

master I3C interface (Master I3C INTERFACE):

the master I3C interface is responsible for controlling the I3C bus just like the master in I2C. The master device may start, stop and control data transmission. The data may be transmitted to or received from the slave device.

From the I3C interface (Slave I3C INTERFACE):

The slave I3C interface is a passive device connected to the I3C bus. The slave device transmits or receives data in response to a request of the master device. The slave device may respond to the instructions of the master device. In an I3C system, there may be multiple slaves, each having a unique address.

That is, in this embodiment, the master I3C interface is responsible for controlling the bus and data transfer, and the slave I3C interface transmits or receives data in response to a request from the master device.

Optionally, in an embodiment of the present application, the GPIO interface allows the device to exchange data with an external device. The GPIO interface may receive and transmit digital signals for controlling and monitoring various electronic devices and sensors. Expanding the GPIOs of the expanded chips provides a flexible, expandable, easy to program, low cost, and compatible way to connect and control various external devices, thereby enhancing the functionality and application scope of the electronic device.

Optionally, in an embodiment of the present application, the first control data refers to data received from the I3C interface for controlling or configuring the programmable logic device. These data may be transmitted over the front-end I3C bus. I3C is a serial communication protocol for communication between integrated circuits.

The first control data may include, but is not limited to, the following types of information:

1. Configuration data (Configuration Data): for initializing and configuring various parameters inside the programmable logic device, such as clock settings, pin function assignments, etc.

2. Register setting (REGISTER SETTINGS): for setting values of registers within the programmable logic device that may control the behavior, performance, or interface with external devices of the device.

3. State information (Status Information): for indicating the current state of the programmable logic device, such as power state, temperature state, error state, etc.

4. Control Commands (Control Commands): for performing certain operations such as start, stop, reset, etc.

5. Data transmission (DATA TRANSFER): for transferring data between the programmable logic device and other devices, such as reading or writing internal memory, processing external data, etc.

6. Debug and test (Debugging AND TESTING): the method is used for debugging and testing the programmable logic device so as to find and solve the problems in the development and maintenance processes.

Here, the first control data is data for controlling and configuring various parameters and behaviors of the programmable logic device. These data may be transferred over the I3C interface and the front-end I3C bus to enable efficient control and management of the programmable logic device.

In the embodiment provided in step S404, the first programmable logic device performs the first designating operation on the GPIO interface corresponding to the first control data among the plurality of GPIO interfaces in response to the received first control data.

Optionally, in the embodiment of the present application, addresses of the multiple GPIO interfaces may be unique, addresses of the multiple GPIO interfaces are different from each other, and performing the first designating operation on the GPIO interface corresponding to the first control data in the multiple GPIO interfaces may be implemented based on the multiple GPIO interfaces.

Alternatively, in the embodiment of the present application, the addresses of the GPIO interfaces may be static addresses or dynamic addresses, which is not limited in this embodiment.

Here, dynamic addresses refer to addresses that are variable during programming of a programmable logic device and may be specified by a user at the time of programming. This type of address is typically used to communicate with external devices such as memory, other programmable logic devices, or other microprocessors, because the address space of these devices is typically configurable.

The user can customize the address according to the actual demand so as to adapt to different system designs; dynamic addresses can be extended as needed to meet larger address space requirements.

It should be noted that, since the address is variable, it is necessary to ensure that no address collision occurs in the system.

Static addresses refer to addresses that are fixed during programming of a programmable logic device. This address type is commonly used for internal communications such as communications between a programmable logic device internal register or on-chip peripheral and a GPIO.

Static addresses do not require user specification at the time of programming, simplifying the programming process, and address conflicts or errors are not likely to occur because the addresses are fixed.

Namely, the dynamic address is suitable for communication with external equipment, has higher flexibility and expandability, but has higher programming complexity; static addresses are suitable for internal communication, simple and stable, but have low flexibility and expansibility. In practical designs, the appropriate address type is selected according to specific requirements.

As an alternative embodiment, the first control data is configured to configure an interface mode of a first GPIO interface of the plurality of GPIO interfaces as an input mode or an output mode;

s11, responding to the received first control data, executing a first appointed operation on a GPIO interface corresponding to the first control data in a plurality of GPIO interfaces, wherein the operation comprises the following steps:

s12, responding to the received first control data, and executing configuration operation on the interface mode of the first GPIO interface.

Similar to the previous embodiments, the first control data may be configuration data for configuring an interface mode of a first GPIO interface of the plurality of GPIO interfaces to an input mode or an output mode.

The GPIO interface may be configured in an input mode or an output mode, both of which allow the GPIO interface to implement different functions in different application scenarios.

When the GPIO interface is configured in input mode, it functions to receive a digital signal (0 or 1) from an external device. In this mode, the GPIO interface acts as a receiver of digital signals, reading the state of the external device and converting it into data that can be understood by the microcontroller. The input mode is typically used to read sensor data, button status, etc.

When the GPIO interface is configured in output mode, its role is to send a digital signal (0 or 1) to the external device. In this mode, the GPIO interface acts as a transmitter of a digital signal that is sent to an external device according to the instructions of the microcontroller. The output mode is typically used to control LED lamps, relays, motors, etc.

The input mode and the output mode are two basic modes of operation of the GPIO interface. The input mode is for receiving an external device signal, and the output mode is for transmitting a signal to an external device. By configuring the operation mode of the GPIO interface, signal transmission and control functions in various electronic systems can be realized.

As an alternative embodiment, the first control data is used to read an interface state of a second GPIO interface of the plurality of GPIO interfaces;

in response to the received first control data, performing a first specified operation on a GPIO interface of the plurality of GPIO interfaces corresponding to the first control data, including:

s21, responding to the received first control data, and reading the interface state of the second GPIO interface to obtain the interface state information of the second GPIO interface;

S22, transmitting interface state information of the second GPIO interface to the expanded chip through the front-end I3C bus through the first slave I3C interface.

Different programmable logic devices may have different GPIO configuration options and capabilities, the specific state and functionality depending on the technical manual and user requirements of the selected device.

Alternatively, in this embodiment, the GPIO interface states may include, but are not limited to:

Input mode: the GPIO serves as an input and can read the level state of an external signal, such as a high level (logic 1) or a low level (logic 0).

Output mode: the GPIO may send a level state (high or low) to an external device as an output.

Floating state: when a GPIO is neither configured as an output nor connected to a valid input signal, it may be in a floating state, meaning that its output level is indeterminate.

Pull-up/pull-down state: in order for the GPIO to have a certain level in a floating state, an internal or external pull-up or pull-down resistor may be configured to output a high level or a low level when floating.

Tri-state logic: some GPIOs may be configured to tri-state logic states, meaning that they may output a high level, a low level, or a high impedance (equivalent to no connection).

Digital input/output: GPIOs can be used for input and output of digital signals, including simple switching signals, pulse signals, and the like.

Analog input: some types of GPIOs also have analog input functions that can read analog signals and convert them to digital signals.

Special functions: the GPIO may also be configured as an interface with special functions, such as PWM (pulse width modulation) output, I2C (serial communication protocol) interface, SPI (serial peripheral interface), etc., depending on the particular application.

The first programmable logic device responds to the received first control data and can read the interface state of the second GPIO interface to obtain the interface state information of the second GPIO interface; interface state information of the second GPIO interface is transmitted to the extended chip through the front-end I3C bus through the first slave I3C interface.

As an alternative embodiment, the first programmable logic device further includes: a register and a GPIO controller;

S31, responding to the received first control data, and temporarily storing the first control data into a register;

S32, reading the first control data from the register through the GPIO controller, and executing a first appointed operation on the GPIO interface indicated by the first control data in the GPIO interfaces.

The programmable logic device may include various instructions, settings, or status information by receiving control data from the front-end I3C bus from the I3C interface, similar to the previous embodiments. The received data will be sent to the core logic portion of the programmable logic device where it will be parsed and recognized as specific commands or information; according to the received control data, registers in the programmable logic device are updated, and the registers are typically used to store configuration parameters, status information, etc., so that the device can operate normally according to the received instructions.

Correspondingly, once the register is updated, the GPIO controller will control the GPIO port according to the new register value. This may include setting the GPIO pins to input or output modes, configuring the pins' levels, rates, etc.

According to the updated register and GPIO settings, the programmable logic device will perform the corresponding operation. This may include starting or stopping a particular function, adjusting the clock frequency, changing the data transfer rate, etc.

After the corresponding operations are performed, the programmable logic device may feed back some status information or result data from the I3C interface to the extended chip that sends the control data to ensure reliability and synchronization of the communication.

According to the embodiment, after the programmable logic device receives control data from the I3C interface, the register and the GPIO controller work cooperatively, the register is updated according to the received data, the GPIO port is controlled, and corresponding operation is executed, so that the programmable logic device can flexibly respond to external instructions, and a complex and dynamic control function is realized.

As an alternative embodiment, the method further comprises:

S41, receiving input signals of a third GPIO interface in the multiple GPIO interfaces through a GPIO controller;

s42, performing metastable state processing on an input signal of a third GPIO interface through a GPIO controller, and temporarily storing the obtained input data into a register;

S43, reading input data from the register through the first slave I3C interface, and transmitting the read input data to the extended chip through the front-end I3C bus.

Metastable here refers to a state in which a signal is neither 0 nor 1 for some indefinite period of time. This typically occurs when signal propagation delays or clock domains cross. The purpose of metastable processing is to ensure stable signal transmission in the system, preventing errors due to metastability.

The input signal of the GPIO interface is processed in a metastable state through the GPIO controller of the programmable logic device, namely, in the programmable logic device, the GPIO controller is used for processing the input signal so as to eliminate the metastable state and ensure the stability of the signal. The processed input data will be buffered in registers for further processing or transmission as needed.

Through metastable state processing, the stability of the signals of the GPIO interface in the transmission process can be ensured, errors caused by metastable state are avoided, the processed input data are temporarily stored in a register, the data can be quickly accessed when needed, and the response speed of the system is improved.

Similar to the previous embodiment, after performing the corresponding operation based on the received control data, the programmable logic device may ensure reliability and synchronization of communication by feeding back some status information or result data from the I3C interface to the extended chip that transmits the control data, i.e., reading input data from the register through the first slave I3C interface and transmitting the read input data to the extended chip via the front-end I3C bus.

By the embodiment, the metastable state is eliminated, the reliability of the system can be improved, and faults and errors caused by unstable signals are reduced.

As an alternative embodiment, receiving, by the first slave I3C interface, first control data transmitted by the extended chip via the front-end I3C bus, includes:

s51, under the condition that the front-end I3C bus is in an HDR batch transmission mode, a group of preset mode frames transmitted by the extended chip through the front-end I3C bus are received through a first slave I3C interface, wherein the preset mode frames comprise a starting block and at least one data block, frame format commands are carried in the starting block of the preset mode frames, and first control data are carried in the data blocks of the group of preset mode frames.

Optionally, in this embodiment, the I3C bus is a new serial communication protocol based on the I2C bus protocol, where the I3C bus has a higher data transmission rate and a more flexible configuration option. The I3C bus may operate in two modes: standard mode and HDR (High-SPEED DATA RATE) mode.

When the I3C bus is in the HDR bulk transfer mode, communications will occur at a higher data transfer rate. The HDR mode allows devices to communicate at a higher speed, which helps to improve system performance, in which the devices can achieve faster data transfer rates with lower power consumption, thereby improving energy efficiency, and provides more configuration options, making the system design more flexible, and adaptable to a variety of different application requirements.

A frame format command is a special instruction that can be used to define the format and rules of transferring data over the I3C bus. The frame format command ensures that the data sender and receiver remain synchronized during the data transmission process to ensure that the data is not corrupted or lost during the transmission process. The frame format command defines the structure of the data block, including information on the length, type, etc. of the data, so that the receiving party can correctly recognize and parse the transmitted data.

Optionally, the frame format command may also contain some control information, such as transmission rate, address, etc., and some information for error detection and handling, such as checksum, sequence number, etc.

For example, in the present embodiment, the preset mode frame may be an HDR-BT mode frame, and the HDR-BT (High-Definition Range-Batch Transfer) mode frame is an efficient data transmission mode in the I3C bus standard. In this mode, a host device may exchange high-speed, bulk data with a slave device via one or more preset mode frames (including a start-up block and a data block).

The HDR-BT mode allows the host device to transmit a large amount of data in one data frame, thereby reducing overhead and delay in the data transmission process; the HDR-BT mode frames are suitable for programmable logic devices, which can be configured and reconfigured as needed to achieve different functions and capabilities; in the HDR-BT mode, a data frame includes a start block and at least one data block. The starting block carries a frame format command and defines the structure and transmission rule of a data frame; the data block contains the data actually transmitted; the frame format command in the start block helps to ensure synchronization between the data sender and receiver, and control during data transmission;

Alternatively, the HDR-BT mode frame may contain information for error detection and handling, such as checksums, sequence numbers, etc., to improve the reliability of the data transmission.

By the embodiment, high-speed and batch data exchange is realized through the preset mode frame (the starting block and the data block), meanwhile, the reliability and the flexibility of data transmission are maintained, and the synchronization, definition, control and reliability of the data transmission are ensured through the frame format command carried in the starting block.

As an optional embodiment, the preset mode frame further includes a check block, where the check block of the preset mode frame carries a check value;

In the process of receiving the first control data transmitted by the extended chip via the front-end I3C bus through the first slave I3C interface, the method further includes:

S61, after each reception of one preset mode frame, performing the following processing operation with the received preset mode frame as the current mode frame:

Generating a first check value corresponding to the current mode frame based on the current mode frame, and checking the current mode frame by comparing the first check value with a second check value carried in a check block of the current mode frame to obtain a check result of the current mode frame;

Transmitting a check result of the current mode frame to the extended chip through the front-end I3C bus by the first slave I3C interface, so that the extended chip performs a data transmission operation after the current mode frame based on the check result of the current mode frame.

Similar to the foregoing embodiment, the preset mode frame may include information for error detection and processing, such as checksum, serial number, etc., to improve reliability of data transmission, and in this embodiment, the preset mode frame further includes a check block, where the check block of the preset mode frame carries a check value.

The check block in the preset pattern frame refers to a portion for storing a check value. The check value is an error detection mechanism used to ensure the integrity and correctness of the data during transmission. The check value in the check block may help the receiver to detect whether the data is in error during transmission. This may be achieved by comparing the check value of the received data frame with a check value calculated by the receiver itself.

The check value ensures that the data frame remains intact during transmission without losing any parts. If the verification fails, the recipient knows that the data may have been corrupted. By using the check block, the reliability of data transmission can be improved. The check block may help ensure the correctness and integrity of the data even if disturbances or errors occur during the data transmission.

The check value in the check block may be calculated by an algorithm (e.g., CRC-cyclic redundancy check) that generates a value based on other information in the data frame (e.g., the data block content) that is stored in the check block. At the data receiving side, the same algorithm is also used to calculate the received data, and then the data is compared with the check value in the check block, so as to detect whether the data is correct.

According to the embodiment, the accuracy, the integrity and the reliability of data transmission can be ensured through the check block and the check value carried by the check block.

In case that the check result of the current mode frame is obtained, the programmable logic device may perform a data transmission operation after the current mode frame based on the check result of the current mode frame by transmitting the check result of the current mode frame from the I3C interface to the extended chip via the front-end I3C bus.

Alternatively, in this embodiment, the check result of the current mode frame may include pass check and fail check.

As an alternative embodiment, after transmitting the check result of the current mode frame to the extended chip through the front-end I3C bus through the first slave I3C interface, the method further includes:

S71, receiving a verification result of a current mode frame transmitted by a first programmable logic device through a front-end I3C bus through a first main I3C interface;

s72, releasing first sub-control data cached in a cache area of the extended chip under the condition that the verification result of the current mode frame is that verification is passed, wherein the first sub-control data is part of data of the first control data carried in a data block of the current mode frame;

S73, under the condition that second sub-control data exist in a buffer area of the extended chip, generating a preset mode frame according to the second sub-control data to obtain a first mode frame to be transmitted, wherein the second sub-control data are part of data which are not transmitted to the first programmable logic device in the first control data, and part of data in the second sub-control data are carried in a data block of the first mode frame;

s74, transmitting the first mode frame to the first programmable logic device through the front-end I3C bus through the first main I3C interface.

The extended chip may receive a verification result of the current mode frame transmitted by the first programmable logic device via the front-end I3C bus through the first main I3C interface.

When the verification result is that the verification passes, the verification value calculated by the receiving side is matched with the verification value carried by the sending side in the preset mode frame. Thus, it may be considered that no errors have occurred in the data during transmission, or that an occurred error may be detected by a verification algorithm, in which case the receiver does not need to require the sender to retransmit the data, since the data is considered to have been received correctly, and the receiver may proceed with subsequent data processing steps, such as parsing the data, storing, or further processing.

For example, in this embodiment, when the verification result of the current mode frame is that the verification is passed, the first sub-control data cached in the cache area of the extended chip is released, where the first sub-control data is part of the data of the first control data carried in the data block of the current mode frame; and under the condition that second sub-control data exist in a buffer area of the extended chip, generating a preset mode frame according to the second sub-control data to obtain a first mode frame to be transmitted, wherein the second sub-control data are part of data which are not transmitted to the first programmable logic device in the first control data, and part of data in the second sub-control data are carried in a data block of the first mode frame.

The extended chip may transmit the first mode frame to the first programmable logic device via the front-end I3C bus through the first master I3C interface. The first programmable logic device may receive a first mode frame through the first slave I3C interface.

For example, in this embodiment, the HDR-BT may have the receiver verify to the sender whether the transmit CRC value for each frame of information is consistent with the CRC value calculated for the received data. Based on this, the sender can determine whether the buffer can be freed and continue to transmit, or whether the data must be retransmitted (whether immediately or later).

Here, the buffer is an area for temporarily storing data, for temporarily storing data during data transmission for error detection and processing, and when the sender receives an acknowledgement signal (i.e., verification is passed) from the receiver, the buffer can determine that the data has been correctly received, at which time the sender can release the buffer, and use the buffer for storage or transmission of other data.

Once the sender confirms that the data has been properly received (i.e., checked), the buffer may continue to send the next data frame, or perform other data transfer operations, which may increase the efficiency of the data transfer, since the sender does not have to wait for each data frame to be acknowledged before performing subsequent operations.

As an alternative embodiment, after receiving, through the first master I3C interface, a verification result of a current mode frame transmitted by the first programmable logic device via the front-end I3C bus, the method further includes:

s81, regenerating a preset mode frame according to the first sub-control data to obtain a second mode frame to be transmitted under the condition that the verification result of the current mode frame is that the verification is not passed;

s82, the second mode frame is transmitted to the first programmable logic device through the front-end I3C bus through the first main I3C interface.

For example, in this embodiment, similar to the previous embodiments, if the check is not passed, the sender may need to reserve a buffer in order to retransmit the data frame when the receiver requests retransmission.

As an alternative embodiment, in the process of receiving, through the first slave I3C interface, the first control data transmitted by the extended chip via the front-end I3C bus, the method further includes:

s91, after each preset mode frame is received, waiting to receive the next preset mode frame of the currently received preset mode frame under the condition that first indication information is received after the currently received preset mode frame, wherein the first indication information is used for indicating restarting the HDR batch transmission mode;

And S92, under the condition that second instruction information is received after the currently received preset mode frame, data transmission between the first programmable logic device and the extended chip is terminated, and the first programmable logic device is controlled to enter a low-power consumption state, wherein the second instruction information is used for instructing to exit the HDR batch transmission mode.

For example, in this embodiment, fig. 5 illustrates a typical HDR-BT (HDR Bulk Transport Mode, HDR bulk transfer mode) mode frame, containing two HDR-BT transfers and related data. The technical terms referred to in fig. 5 will now be explained as follows:

1. SDR, standard Data Rate standard data rate.

2. HDR, high Data Rate high data rate.

3. S or Sr, start or REPEATED START, start or repeat Start.

4. I3C RESERVED byte (7 'h7 e) (R/w=0), I3C reserved byte (7' h7 e) (read/write=0).

5. NACK, not Acknowledgement (NACK), negative acknowledgement, unacknowledged or refused acknowledgement, NACK being a signal in a communication protocol used to indicate that the receiver has Not received or Not correctly received the sender's data. In one data transmission process, after the sender sends data, the receiver waits for sending an Acknowledgement (ACK) signal. If the receiver fails to properly receive the data due to data errors, loss, or other reasons, it will send a NACK signal to the sender informing the sender that the data needs to be retransmitted.

6. Enter HDR-BT CCC (ENTHDR), enter HDR-BT command control character (ENTHDR).

7. HDR-BT Header (with Command), HDR-BT Header (with Command).

8. HDR-BT Data (1 or more Blocks), HDR-BT Data.

9. HDR-BT CRC Block, HDR-BT CRC Block.

10. HDR RESTART PATTERN, HDR restart mode.

11. HDR Exit Pattern, HDR Exit mode.

12. From Controller to Targe from the controller to the target.

13. Framing (START or STOP), frame partitioning (start or stop).

14. From Controller to Master from the controller to the host.

15. Current I3C Mode (SDR or HDR), current I3C Mode (SDR or HDR): current I3C Mode (standard data rate or high data rate).

16. The Transition Bit (Parity Bit for CCC), the Transition Bit (parity Bit of the universal command code).

17. Bus Free (after STOP) and Bus Free (after STOP).

18. Common Command Codes, universal command code.

19. ACK: acknowledge, acknowledgement.

Acknowledge (SDA Low): when SDA (data line) is low, it indicates that the receiving side has successfully received data and transmits an acknowledgement signal.

20. S, START Condition, START state.

START Condition (S): when SCL (clock line) is high, SDA changes from high to low, indicating that communication starts.

21. Sr REPEATED START Condition, repeating the starting state.

REPEATED START Condition (Sr): when SCL is high, SDA changes from low to high and then low again, indicating that a new round of communication is started without transmitting a stop condition.

22. STOP Condition, STOP Condition.

STOP Condition (P): when SCL is high, SDA changes from low to high, indicating the end of communication.

23. T is Transition Bit, parity Bit (Parity Bit) for CCC.

Transmission Bit (T): a signal indicating ACK (acknowledgement) or NACK (negative acknowledgement), the transition bit replaces the acknowledgement/negative acknowledgement (Transition Bit Alternative to ACK/NACK).

First the CPU sends an address 7' h7E/W followed by a CCC command to start the HDR-BT mode. In one HDR-BT transmission. First one HDR-BT start block (containing frame format commands), then one or more HDR-BT data blocks, and finally one HDR-BTCRC block. One HDR restart mode (i.e., HDR RESTART PATTERN) is then passed to continue the HDR mode, followed by another HDR-BT transmission with a similar flow. Finally, the bus may stop ending the HDR-BT mode with an HDR Exit mode (i.e., HDR Exit Pattern) and I3C.

The HDR restart mode is a special transmission mode, which allows transmission parameters such as data rate, data width, etc. to be dynamically changed during the HDR transmission without restarting a new transmission transaction, and this mode can be implemented by sending a specific HDR restart mode code, which is recognized and responded to by the receiver, and the function of the HDR restart mode is to improve the flexibility of data transmission, and allow the transmission parameters to be adjusted without interrupting the transmission, so as to optimize the transmission efficiency.

The HDR exit mode is a control mode for ending the HDR-BT transmission, and when the data transmission is complete or the transmission needs to be terminated, the sender may notify the receiver by sending a specific HDR exit mode code, and the sending of the HDR exit mode code will cause the I3C bus to revert to the standard mode or stop the transmission, thereby allowing other devices or transmission transactions to proceed.

By the embodiment, the data transmission efficiency and flexibility in the HDR-BT mode are improved through the HDR restarting mode and the HDR exiting mode, and more dynamic and flexible data transmission management is allowed. By using the HDR restart mode and the HDR exit mode, the device may adjust transmission parameters without interrupting the transmission, or end the transmission quickly when needed, thereby improving overall system performance and responsiveness.

As an alternative embodiment, before receiving, by the first slave I3C interface, the first control data transmitted by the extended chip via the front-end I3C bus, the method further comprises:

S101, receiving an I3C broadcast address and a general command code command transmitted by an extended chip through a front-end I3C bus through a first slave I3C interface;

S102, determining an HDR batch transmission mode of the front-end I3C bus in response to the received I3C broadcast address and the universal command code command.

In the case of an extended chip connected to a programmable logic device via an I3C bus, initiating the HDR bulk transfer mode of the I3C bus may involve the steps of:

1. initializing an I3C bus: firstly, ensuring the I3C bus to be initialized correctly comprises configuring an I3C controller at the end of an extended chip and initializing an I3C interface at the end of a programmable logic device.

2. Configuring a programmable logic device: on the programmable logic device side, the corresponding registers need to be configured to support the HDR mode. This may include setting a data transfer rate, a data width, an address mode, and the like.

3. Transmitting an HDR transmission command: the extended chip needs to send specific HDR transfer commands to the programmable logic device to initiate the HDR bulk transfer mode. This is typically accomplished by sending a series of I3C instructions, including commands to set the HDR mode and commands to transfer data.

4. Using the I3C broadcast address: in some cases, an I3C broadcast address may be used if simultaneous communication or initialization with multiple devices is desired. The broadcast address allows a command to be sent to all devices connected to the bus.

5. General command code: the universal command code is used to perform certain operations, such as reading or writing data. When the HDR mode is initiated, it may be necessary to use a specific command code to set transmission parameters or to initialize transmission.

6. Exchanging protocol information: some protocol information may need to be exchanged between the extended chip and the programmable logic device to ensure that both parties can understand and accept the transmission parameters of the HDR mode.

7. Starting transmission: once all parameters are set, the extended chip can send data to the programmable logic device, starting the HDR batch mode.

8. Error handling: during transmission, it may be necessary to implement error detection and handling mechanisms, such as a CRC check, to ensure the reliability of the data transmission.

9. Ending transmission: after the transmission is completed, a specific command or mode code needs to be sent to end the HDR mode, restore to the normal I3C mode, or perform other operations.

For example, in the present embodiment, the extended chip may configure the I3C bus HDR mode by sending a Common Command Code (CCC) over the I3C bus. The configurable patterns and corresponding commands are shown in table 1. I3CBasic contains only HDR mode 0 (HDR-ddr) and HDR mode 3 (HDR-BT). The present example is based on HDR mode 3 (HDR-BT), i.e. the extended chip sends a 0x23 (ENTHDR) command to configure, the programmable logic device responds.

TABLE 1

The use of a common command code and broadcast address to enable the HDR bulk transfer mode may simplify the programming process because separate command codes need not be remembered for each device. This may reduce the likelihood of programming errors and make it easier for developers to implement and maintain the system; by using broadcast addresses, commands can be sent to multiple devices without having to individually address each device; using the HDR bulk transfer mode may increase system efficiency because it allows multiple commands to be sent in a single transfer, which may save time and resources, particularly if multiple commands need to be sent to configure or control multiple devices. The use of universal command codes and broadcast addresses may improve system reliability because the number of commands that need to be remembered and programmed is reduced, may make the system easier to use, and reduces the risk of programming errors.

By this embodiment, initiating the HDR bulk transfer mode by using the I3C broadcast address and the generic command code may improve system performance by simplifying the programming process, increasing flexibility, efficiency, reliability, and compatibility.

As an alternative embodiment, the front end I3C longitudinally includes two serial data lines and one serial clock line;

In the case where the front-end I3C bus is in the HDR bulk transfer mode, receiving, by the first slave I3C interface, a set of preset mode frames transferred by the extended chip via the front-end I3C bus, comprising:

S111, after the received I3C broadcast address and the received universal command code command, under the condition that the clock signals in the serial clock lines are detected to be stable, analyzing the data received through the two serial data lines according to a preset packaging mode to obtain a group of preset mode frames, wherein the preset packaging mode is a mode of packaging the data by using the two serial data lines.

In I3C communications, a serial clock line is used to synchronize data transmissions. Before data transmission starts, it is necessary to detect that the clock signal on the serial clock line SCL line is stable to ensure that the data can be properly transmitted.

In I3C communication, a serial data line (SDA) is used to transmit data.

The preset packing mode may refer to a specific data organization and analysis rule for ensuring that the received data can be correctly interpreted in an expected manner; the preset mode frame may refer to a data frame obtained by parsing according to a specific packing manner. In the I3C protocol, a frame may contain information such as addresses, commands, and data.

After receiving the broadcast address and the universal command code via the I3C communication protocol, the system parses the data received via the serial data line according to a predetermined rule (packing manner) upon detecting that the clock signal on the serial clock line is stable, based on which the system can correctly understand and process the received data, thereby obtaining a set of frames organized according to a predetermined pattern (i.e., predetermined pattern frames), which may contain the device address, command information, and related data, for performing a specific operation or response.

For example, in the present embodiment, the data lines are packetized using double SDA lines. The packing format is shown in table 2.

TABLE 2

Wherein Table 3 (Table 3) is packed as data byte bits: two channels.

TABLE 3 Table 3

As an alternative embodiment, the server further comprises a back-end communication bus, and the first programmable logic device further comprises a second master I3C interface, wherein the back-end communication bus is one of: the I3C bus and the I2C bus are used for connecting a second master I3C interface and a second slave I3C interface of a slave module of the first programmable logic device;

The method further comprises the following steps:

S602, receiving second control data transmitted by the extended chip through the front-end I3C bus through the first slave I3C interface, wherein the second control data is used for controlling a designated slave device of the first programmable logic device to execute a second designated operation;

S604, in response to the received second control data, the second control data is transmitted to the appointed slave device through the second master I3C interface via the back-end communication bus so as to execute a second appointed operation by the appointed slave device.

In connection with fig. 6, considering that the number of GPIO interfaces is limited, and that the designated slave device may not need high-speed communication, the second master I3C interface of the programmable logic device may be connected with the second slave I3C interface of the slave module of the first programmable logic device through the back-end communication bus.

The master I3C interface refers to an interface on the programmable logic device that controls the I3C bus and is responsible for managing data transmission and communication, and the programmable logic device sends control commands and data to other devices (called slaves) connected to the backend communication bus via its master I3C interface.

Each device has a unique address on a back-end communication bus (e.g., an I3C bus). The master I3C interface of the programmable logic device can specify a particular device address, ensuring that data and commands are sent only to that particular slave device.

After receiving the data and the command sent by the programmable logic device, the slave device performs a specific operation according to the information. These operations may include data reads, data writes, device configuration, status reports, and the like.

The back-end communication bus allows multiple devices to be connected to the same bus, which makes the system design more flexible and compact. If a GPIO interface is used, each slave device (e.g., temperature sensor) requires a separate GPIO line, which can occupy a significant amount of GPIO resources when the number of devices is large; if more slaves are to be added, it is only necessary to ensure that the maximum number of devices on the back-end communication bus is not exceeded, and although the back-end communication bus may not be as fast as some GPIO interfaces, the back-end communication bus is sufficiently fast for applications such as temperature sensors that do not require high-speed communication. In addition, the power consumption of the back-end communication bus is relatively low, which is beneficial to reducing the power consumption of the whole system.

With the present embodiment, the master I3C interface on the programmable logic device provides an efficient and flexible way to control and manage one or more peripheral devices connected to the back-end communication bus.

As an alternative embodiment, the server further includes at least one memory bank, the plurality of GPIO interfaces are divided into at least one GPIO interface group, and the GPIO interface group in the at least one GPIO interface group is used for connecting the memory bank in the at least one memory bank;

The slave module of the first programmable logic device includes at least one of: the system comprises a second programmable logic device, a microcontroller, a serial presence detection hub on a memory bank of at least one memory bank, a temperature sensor on a memory bank of at least one memory bank, and a fan on a memory bank of at least one memory bank.

Memory banks, also known as RAM banks (Random Access Memory Module), are hardware components of computers and other digital devices for temporarily storing data, and are of various types including, but not limited to, SDRAM (synchronous dynamic random access memory), DDR (double data rate synchronous dynamic random access memory) and versions thereof (e.g., DDR2, DDR3, DDR4, DDR5, etc.).

SPD (SERIAL PRESENCE DETECT ) is a technology for memory devices (e.g., memory banks) that allows a motherboard to identify the specifications of the memory device, such as size, type, speed, etc., and a serial presence detect hub is a hardware device that connects multiple memory banks and centrally manages their SPD data so that the motherboard can access status information of all memories through one interface. The serial presence detection hub can simplify memory management and improve the expansibility and compatibility of the system.

The temperature sensor on the memory bar is used for monitoring the working temperature of the memory bar in real time, in the high-performance memory bar, the memory temperature can be increased to influence the stability and the service life due to high working frequency and high power consumption, and by monitoring the temperature, the system can take measures, such as adjusting the rotating speed of a fan for cooling or giving out a warning when the temperature is too high, so that the memory bar is protected and the stability of the system is improved.

The fans on the memory strips are used for actively radiating heat, so that the temperature of the memory strips is reduced, more heat can be generated in the operation process in high performance, if the heat radiation is poor, the system is possibly unstable or hardware is possibly damaged, the fans on the memory strips can directly cool the memory strips, the heat radiation efficiency is improved, and the operation under the optimal state of the memory strips is ensured.

According to the embodiment, the stability and reliability of the memory bank are ensured by the slave module of the programmable logic device when the memory bank runs with high performance or high load. Through real-time monitoring and initiative heat dissipation, can help keeping the memory strip in safe operating temperature scope, protect the system from the harm that high temperature led to improve overall performance.

S121, initializing the front-end I3C bus through the extended chip under the condition that the front-end I3C bus is in an SDR mode, and executing a discovery process to detect devices connected on the front-end I3C bus;

S122, acquiring a static address transmitted by the first programmable logic device through the front-end I3C bus through the extended chip, wherein the static address of the first programmable logic device is preset in the first programmable logic device.

For example, in the present embodiment, the extended chip initializes the I3C bus and performs a discovery process to detect all devices on the I3C bus, and the I3C bus adds a dynamic address allocation function, but in the present embodiment, the addresses of the programmable logic devices are fixedly extended, using static addresses. In addition to stability, predictability considerations, devices with static addresses may operate in an I3C high speed HDR mode and may be backwards compatible with I2C devices, increasing stability.

It should be noted that at this time, the I3C bus initializes and configures addresses in the SDR mode.

The SDR mode may refer to a single data rate (SINGLE DATA RATE) mode, which is a data transfer rate configuration. In SDR mode, the data transfer rate is a fixed frequency, typically used for low speed or conventional data transfer requirements.

Each device connected to the I3C bus needs to have a unique address in order for the sender to recognize and send data to a particular recipient; in the initialization process, the bus configures communication parameters of the device, such as clock rate, data transmission rate and the like, so as to ensure that the device can exchange data according to the expected rate and mode; the device may need to be specifically configured after being connected to the bus, such as to set an operation mode, an input-output mode, and the like. Configuring the addresses such that the settings can be made over the I3C bus; the bus controller can manage devices on the network by configuring addresses, including detecting new devices, configuring device parameters, maintaining device lists, etc.; the configuration address may also support broadcast and multicast communications, allowing the same commands or data to be sent to multiple devices.

By the embodiment, the initialization and configuration address in the SDR mode of the I3C bus can ensure that the device can correctly communicate on the bus, and the communication efficiency and safety are improved.

As an alternative exemplary embodiment, in the present application, an extended chip is taken as a CPU, and a first programmable logic device is taken as a CPLD as an example, a data transmission method of a server in the embodiment of the present application is explained.

The present application provides a system and method for extending input/output in a server using a CPLD with an I3C bus. The extended CPLD is linked with the extended chip by using the I3C bus, and relevant programs and pin configuration are carried out on the extended CPLD, so that the functions of GPIO extension and I3C extension of the chip are finally realized, the advantages of high transmission rate, in-band interruption, hot addition and the like are realized, each pin on the CPLD can be set as input or output, and the extended chip can read or write the pins, so that the approximate physical connection effect is realized.

The topology of the I3C expansion IO is as shown in FIG. 3 by using CPLD to access the expanded chip. And modifying and expanding CPLD codes, upwardly communicating with chips such as BMC through I3C, obtaining a reading command and transmitting related information through a defined frame format. The information of the pins is read and controlled downwards through the GPIO, and is communicated with other modules (such as a temperature sensor on the DDR5 memory and the like) through the I3C.

In terms of expansion number, the expansion GPIO pin of each CPLD expansion chip is determined by the chip type, the CPLD can be changed automatically according to the demand and cost factors, the CPLD can simulate buses such as I3C, I2C and the like through built-in logic, a plurality of downstream buses can be expanded according to the demand, and chips such as MCU and the like can be cascaded on the downstream buses for use. Furthermore, multiple CPLDs may be selected to be spread, connected in a daisy-chain fashion, the number of links being limited only by the potential signal attenuation/distortion when cascading over many pins. The number of link extension CPLDs may not exceed 11 according to MIPI association recommendations.

The invention is further described by the following specific embodiments, in which the CPLD is used to perform GPIO expansion on the CPU, so as to link more memories on one CPU. The topology is shown in fig. 7.

In particular, DDR5 introduces a sideband bus to access non-DRAM modules. The sideband bus is based on MIPII C or I3C protocols. In addition to the sideband bus, there is also one SPD, the serial presence detect hub, as the number of components on DDR5 increases. SPD (SERIAL PRESENCE DETECT ) is a standardized method for automatically accessing DDR3/4/5 memory module information. When the electronic system is powered on, it begins to automatically configure the system by identifying different hardware components. Through the extension of the CPLD, the CPU can read SPDs on a plurality of DDRs 5 through a single I3C, and can control pins of the DDRs 5 and the like.

Firstly, a CPU communicates with a CPLD through a front-end I3C bus, and configures and reads an internal register of the CPLD through addressing actions of the CPLD. And in the CPLD, the configuration logic module analyzes the configuration data of the front-end I3C, and stores and reads the data according to a frame format agreed in advance.

The specific steps of the I3C interaction are as follows:

step 1, initializing and discovering equipment: the CPU initializes the I3C bus and performs a discovery process to detect all devices on the I3C bus.

Step 2, address allocation: the I3C bus has a new dynamic address allocation function, but in this embodiment, a static address is used to fixedly expand the CPLD address. In addition to stability, predictability considerations, devices with static addresses may operate in an I3C high speed HDR mode and may be backwards compatible with I2C devices, increasing stability. It should be noted that at this time, the I3C bus initializes and configures addresses in the SDR mode.

Step 3, configuring a high-speed transmission mode: the CPU sends a Common Command Code (CCC) over the I3C bus to configure the I3C bus HDR mode. The configurable patterns and corresponding commands are shown in table 1. I3CBasic contains only HDR mode 0 (HDR-ddr) and HDR mode 3 (HDR-BT). The present example is configured based on HDR mode 3 (HDR-BT), i.e. the CPU sends a 0x23 (ENTHDR) command, the CPLD responds.

After ENTHDR CCC, the SDA is driven after the t bit is complete (i.e., on or after the SCL pulse falling edge of C9), starting the first structured protocol element in the HDR mode according to the HDR mode frame. From this point on, the controller follows the general timing rules to start transmission in HDR mode. After the falling of the SCL pulse of C9, the I3C bus is switched from SDR mode to HDR mode. FIG. 8 shows a timing diagram for entering the universal HDR mode after ENTHDR CCC, where Controller drives Push-Pull (controller drives push-Pull output), referred to herein as the controller driving a signal through push-Pull output; T-Bit FALLING EDGE < = end of SCL pulse (T-Bit falling edge < = SCL pulse end), the falling edge of the T-Bit should be before the pulse end of the clock signal SCL; LOW SCL (LOW SCL): the SCL signal is in a low state; first BT edge (First BT edge): an edge of the first BT signal, which may be a rising edge or a falling edge; second BT edge (first) two BT edges): an edge of the second BT signal, which may be a rising edge or a falling edge; HDR-BT Header Block (per Lane configuration) (HDR-BT Header Block (per channel configuration)): the configuration of each channel may be different for the header blocks associated with the HDR-BT format.

Step 5, data transmission: the CPU sends and receives data packets through the I3C bus to communicate with the CPLD. This includes reading or writing to a register of the CPLD. In this embodiment, the I3C bus is in the HDR bulk transfer mode (HDR-BT), as shown in fig. 8, where the bus will transfer data with two edges of the clock, i.e., 2 SDA lanes change when the SCL clock is stable, and read on the next rising or falling edge of the clock. Since the CPLD drives only SDA and not SCL, SDA changes only after receiving/detecting a change in SCL. Under the double-channel condition, the transmission rate can reach 48.5Mhz, which is close to the clock frequency of the current server CPLD.

Fig. 5 illustrates a typical HDR-BT mode frame, comprising two HDR-BT transmissions and associated data. First the CPU sends an address 7' h7E/W followed by a CCC command to start the HDR-BT mode. In one HDR-BT transmission. First one HDR-BT start block (containing frame format commands), then one or more HDR-BT data blocks, and finally one HDR-BTCRC block. An HDR restart mode is then passed to continue the HDR mode, followed by another HDR-BT transmission with a similar flow. Finally, the bus may end the HDR-BT mode with the HDR exit mode and the I3C stopped.

Another advantage of using HDR-BT is that multiple SDA lines can be transmitted simultaneously. The data lines are packed using double SDA lines in this embodiment. The packing format is shown in table 2.

It should be noted that the HDR-BT also allows the receiver to verify to the sender whether the transmission CRC value of each frame of information is consistent with the CRC value calculated for the received data. In this way, the sender can determine whether the buffer can be freed and the transmission continued, or whether the data must be retransmitted (whether immediately or later).

Step 6, control and state monitoring: the CPU may send control commands to the CPLD via the I3C bus and monitor its status. The CPLD may also use an in-band interrupt (IBI) signal to issue an interrupt signal to the CPU. And the CPLD receives the CPU transmission signal and then transmits a command to the downlink equipment, and controls the GPIO to perform configuration and acceptance. The received information is also passed back to the CPU. The CPLD internal functional topology is shown in fig. 2.

The extended CPLD in this embodiment mainly includes 4 parts: an I3C interface (slave end), an I3C interface (master main end), a register and a GPIO controller. Wherein:

The I3C interface (slave end), i.e., the first slave I3C interface, is a bridge for communication between the CPLD and the upstream extended chip, and is used for implementing functions such as data exchange, protocol information analysis, and register information reading and storing. The number is typically only one.

The I3C interface (master end), that is, the second main I3C interface, is used to link the CPLD with the downstream I3C device, so as to implement the reading and control of the CPLD on the downstream chip information, and may have multiple interfaces.

The register is used for temporarily storing the data of the other three modules, and is convenient for reading and writing.

The GPIO controller controls the IO pin of the CPLD, wherein the output signals are uniformly set to be tri-state (high, low and high resistance can be output); the input signal is connected to the register module after internal metastable state processing to be read by the I3C module. Since the I3C can transfer 32 bytes of data at a time in this embodiment, 32 IOs can be controlled simultaneously. The byte width may be user defined. In this embodiment, 8 IOs are a group to control one DIMM. The IO setup is as in FIG. 5.

Step 7, terminating: after the communication is completed, the CPU may terminate the I3C session and enter the CPLD into a low power consumption state as needed.

According to the embodiment, the expansion of the chips GPIO and buses is realized through the HDR batch transmission mode (HDR-BT) of the CPLD and the I3C buses, and only the chips support single-channel I3C, so that the method is quick, efficient and stable, the number of a plurality of CPLDs and buses can be expanded, and the expansibility is extremely strong.

By this embodiment, the current bus expansion rate is improved, and the used HDR-BT format uses a wide data block for transmission, which can be mapped directly to internal SRAM (e.g., 32 bits, 64 bits, etc.), wide internal bus (e.g., AXI, OCP, etc.), and encryption/decryption modes with inherent block sizes (e.g., 64 bits, 128 bits). The main frequency 50Mhz rate of the CPLD of the current motherboard is realized, and in addition, compared with the I2C, the CPLD has lower power consumption, has extremely high expansibility by adding the checking functions such as CRC16 and the like, and is very suitable for connecting a plurality of DIMMs and other application scenes.

In addition to the HDR-BT mode, I3C has other two-wire modes. The HDR-BT mode may also reduce the SDA line by one but the rate may be halved. In addition, it is also possible to explore the establishment of bus data formats in specific situations, such as one-to-one fixed addresses, specific frames, etc. And control of a plurality of uplink chips to the expansion chip can be explored.

Embodiments of the present application also provide a computer readable storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.

In one exemplary embodiment, the computer readable storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.

An embodiment of the application also provides an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.

In an exemplary embodiment, the electronic device may further include a transmission device connected to the processor, and an input/output device connected to the processor.

Specific examples in this embodiment may refer to the examples described in the foregoing embodiments and the exemplary implementation, and this embodiment is not described herein.

It will be appreciated by those skilled in the art that the modules or steps of the application described above may be implemented in a general purpose computing device, they may be concentrated on a single computing device, or distributed across a network of computing devices, they may be implemented in program code executable by computing devices, so that they may be stored in a storage device for execution by computing devices, and in some cases, the steps shown or described may be performed in a different order than that shown or described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple modules or steps of them may be fabricated into a single integrated circuit module. Thus, the present application is not limited to any specific combination of hardware and software.

The above is only a preferred embodiment of the present application, and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the principle of the present application should be included in the protection scope of the present application.

Claims

1. A server is characterized in that,

Comprising the following steps:

The device comprises an extended chip, a front-end I3C bus and a first programmable logic device, wherein the extended chip comprises a first main I3C interface, the first programmable logic device comprises a first auxiliary I3C interface and a plurality of GPIO interfaces, the front-end I3C bus is an I3C bus for connecting the first main I3C interface and the first auxiliary I3C interface, the front-end I3C bus is used for carrying out data transmission between the extended chip and the first programmable logic device,

The extended chip is used for exchanging data with the first programmable logic device through the front-end I3C bus so as to realize GPIO extension of the extended chip through the multiple GPIO interfaces;

wherein the front-end I3C bus comprises a serial data line and a serial clock line; the first programmable logic device is further configured to send an interrupt signal to the extended chip using an in-band interrupt signal;

the first programmable logic device is further configured to receive, through the first slave I3C interface, a set of preset mode frames transmitted by the extended chip via the front I3C bus when the front I3C bus is in an HDR bulk transmission mode, where the preset mode frames include a start block and at least one data block, the start block of the preset mode frames carries a frame format command, and first control data is carried in the data blocks of the set of preset mode frames;

the first programmable logic device is further configured to parse data received through two serial data lines according to a preset packing mode under the condition that a clock signal in the serial clock line is detected to be stable, so as to obtain a set of preset mode frames, wherein the preset packing mode is a mode of packing the data by using the two serial data lines.

2. The server according to claim 1, wherein the server is configured to,

The first programmable logic device further includes: a register, and a GPIO controller, wherein,

The register is configured to temporarily store data received through the first slave I3C interface and transmitted by the extended chip to the GPIO controller for the GPIO controller to read, and temporarily store data transmitted by the GPIO controller to the extended chip for the first slave I3C interface to read, and then transmit the data to the extended chip through the front-end I3C bus;

the GPIO controller is used for controlling the GPIO interfaces and temporarily storing data to be transmitted to the extended chip into the register.

3. The server according to claim 2, wherein the server is configured to,

The server further comprises at least one memory bank, the plurality of GPIO interfaces are divided into at least one GPIO interface group, wherein the GPIO interface group in the at least one GPIO interface group is used for connecting the memory bank in the at least one memory bank.

4. The server according to claim 2, wherein the server is configured to,

The server further comprises a back-end communication bus, the first programmable logic device further comprises a second main I3C interface, and the back-end communication bus is one of the following: the back-end communication bus is used for connecting the second master I3C interface with a second slave I3C interface of a slave module of the first programmable logic device.

5. The server according to claim 4, wherein the server is configured to,

The server further comprises at least one memory bank, the plurality of GPIO interfaces are divided into at least one GPIO interface group, the GPIO interface group in the at least one GPIO interface group is used for connecting the memory bank in the at least one memory bank, and the slave module of the first programmable logic device comprises at least one of the following: the system comprises a second programmable logic device, a microcontroller, a serial presence detection hub on a memory bank of the at least one memory bank, a temperature sensor on a memory bank of the at least one memory bank, and a fan on a memory bank of the at least one memory bank.

6. The server according to any one of claim 1 to 5, wherein,

The first programmable logic devices are complex programmable logic devices, the number of the first programmable logic devices is a plurality of the first programmable logic devices, and the plurality of the first programmable logic devices are connected in a daisy chain mode.

7. A data transmission method of a server is characterized in that,

The server comprises an extended chip, a front-end I3C bus and a first programmable logic device, wherein the extended chip comprises a first master I3C interface, the first programmable logic device comprises a first slave I3C interface and a plurality of GPIO interfaces, the front-end I3C bus is an I3C bus for connecting the first master I3C interface and the first slave I3C interface, and the front-end I3C bus is used for carrying out data transmission between the extended chip and the first programmable logic device;

the method comprises the following steps:

Receiving first control data transmitted by the extended chip through the front-end I3C bus by the first slave I3C interface, wherein the first control data is used for controlling the GPIO interface of the first programmable logic device to execute a first appointed operation, and the GPIO interface of the first programmable logic device is used for extending the GPIO of the extended chip;

Responding to the received first control data, and executing the first appointed operation on a GPIO interface corresponding to the first control data in the GPIO interfaces;

wherein said receiving, by said first slave I3C interface, first control data transmitted by said extended chip via said front-end I3C bus, comprises: receiving, by the first slave I3C interface, a set of preset mode frames transmitted by the extended chip via the front I3C bus, where the preset mode frames include a start block and at least one data block, the start block of the preset mode frames carries a frame format command, and the first control data is carried in the data blocks of the set of preset mode frames;

under the condition that the clock signals in the serial clock lines are detected to be stable, analyzing the data received through the two serial data lines according to a preset packaging mode to obtain a group of preset mode frames, wherein the preset packaging mode is a mode of packaging the data by using the two serial data lines.

8. The method of claim 7, wherein the step of determining the position of the probe is performed,

The first control data is used for configuring an interface mode of a first GPIO interface in the plurality of GPIO interfaces into an input mode or an output mode;

The responding to the received first control data, executing the first appointed operation on the GPIO interfaces corresponding to the first control data in the GPIO interfaces, including:

and responding to the received first control data, and executing configuration operation on the interface mode of the first GPIO interface.

9. The method of claim 7, wherein the step of determining the position of the probe is performed,

The first control data is used for reading the interface state of a second GPIO interface in the plurality of GPIO interfaces;

responding to the received first control data, reading the interface state of the second GPIO interface, and obtaining the interface state information of the second GPIO interface;

and transmitting interface state information of the second GPIO interface to the extended chip through the front-end I3C bus by the first slave I3C interface.

10. The method of claim 7, wherein the step of determining the position of the probe is performed,

The first programmable logic device further includes: a register and a GPIO controller;

in response to the received first control data, temporarily storing the first control data in the register;

and reading the first control data from the register through the GPIO controller, and executing the first appointed operation on the GPIO interface indicated by the first control data in the GPIO interfaces.

11. The method of claim 10, wherein the step of determining the position of the first electrode is performed,

The method further comprises the steps of:

receiving, by the GPIO controller, an input signal of a third GPIO interface of the plurality of GPIO interfaces;

Performing metastable state processing on the input signal of the third GPIO interface through the GPIO controller, and temporarily storing the obtained input data into the register;

And reading the input data from the register through the first slave I3C interface, and transmitting the read input data to the expanded chip through the front-end I3C bus.

12. The method of claim 7, wherein the step of determining the position of the probe is performed,

The preset mode frame further comprises a check block, wherein the check block of the preset mode frame carries a check value;

In the process of receiving, through the first slave I3C interface, first control data transmitted by the extended chip via the front-end I3C bus, the method further includes:

After each of the preset mode frames is received, the received preset mode frame is used as a current mode frame to execute the following processing operation:

Transmitting a check result of the current mode frame to the extended chip through the first slave I3C interface via the front-end I3C bus, so that the extended chip executes data transmission operation after the current mode frame based on the check result of the current mode frame.

13. The method of claim 12, wherein the step of determining the position of the probe is performed,

After the transmitting, by the first slave I3C interface, the check result of the current mode frame to the extended chip via the front-end I3C bus, the method further includes:

Receiving a verification result of the current mode frame transmitted by the first programmable logic device through the front-end I3C bus through the first main I3C interface;

releasing first sub-control data cached in a cache area of the extended chip under the condition that the verification result of the current mode frame is that verification is passed, wherein the first sub-control data is part of data of the first control data carried in a data block of the current mode frame;

Generating the preset mode frame according to the second sub-control data under the condition that the second sub-control data exists in the buffer area of the extended chip, and obtaining a first mode frame to be transmitted, wherein the second sub-control data is part of data which is not transmitted to the first programmable logic device in the first control data, and part of data in the second sub-control data is carried in a data block of the first mode frame;

The first mode frame is transmitted to the first programmable logic device via the front-end I3C bus over the first master I3C interface.

14. The method of claim 13, wherein the step of determining the position of the probe is performed,

After the receiving, by the first master I3C interface, a check result of the current mode frame transmitted by the first programmable logic device via the front-end I3C bus, the method further includes:

regenerating the preset mode frame according to the first sub-control data under the condition that the verification result of the current mode frame is that the verification is not passed, and obtaining a second mode frame to be transmitted;

And transmitting the second mode frame to the first programmable logic device through the front-end I3C bus by the first main I3C interface.

15. The method of claim 7, wherein the step of determining the position of the probe is performed,

After each preset mode frame is received, under the condition that first indication information is received after the preset mode frame which is currently received, waiting to receive the next preset mode frame of the preset mode frame which is currently received, wherein the first indication information is used for indicating restarting of the HDR batch transmission mode;

and under the condition that second instruction information is received after the currently received preset mode frame, terminating data transmission between the first programmable logic device and the extended chip, and controlling the first programmable logic device to enter a low-power consumption state, wherein the second instruction information is used for indicating to exit the HDR batch transmission mode.

16. The method of claim 7, wherein the step of determining the position of the probe is performed,

Before the receiving, by the first slave I3C interface, first control data transmitted by the extended chip via the front-end I3C bus, the method further includes:

Receiving, by the first slave I3C interface, an I3C broadcast address and a universal command code command transmitted by the extended chip via the front-end I3C bus;

In response to the received I3C broadcast address and the generic command code command, determining to initiate the HDR bulk transfer mode of the front-end I3C bus.

17. The method of claim 7, wherein the step of determining the position of the probe is performed,

The server further comprises a back-end communication bus, the first programmable logic device further comprises a second main I3C interface, and the back-end communication bus is one of the following: the back-end communication bus is used for connecting the second master I3C interface with a second slave I3C interface of a slave module of the first programmable logic device;

The method further comprises the steps of:

Receiving second control data transmitted by the extended chip through the front-end I3C bus through the first slave I3C interface, wherein the second control data is used for controlling a designated slave device of the first programmable logic device to execute a second designated operation;

And in response to the received second control data, transmitting the second control data to the designated slave device through the second master I3C interface via the back-end communication bus to perform the second designated operation by the designated slave device.

18. The method of claim 17, wherein the step of determining the position of the probe is performed,

19. The method according to any one of claims 7 to 18, wherein,

initializing the front-end I3C bus through the extended chip under the condition that the front-end I3C bus is in an SDR mode, and executing a discovery process to detect devices connected on the front-end I3C bus;

And acquiring a static address transmitted by the first programmable logic device through the front-end I3C bus through the extended chip, wherein the static address of the first programmable logic device is preset in the first programmable logic device.

20. A computer-readable storage medium comprising,

The computer readable storage medium having stored therein a computer program, wherein the computer program when executed by a processor implements the steps of the method of any of claims 7 to 19.