CN118331771A - Response management system and method for chip fault processing and vehicle-mounted equipment - Google Patents

Abstract

The application relates to the technical field of vehicle-gauge chip fault processing, and discloses a response management system for chip fault processing, which comprises the following components: the fault response configuration module is used for storing and issuing configuration information; the fault signal state bit module is used for latching an on-chip alarm signal in the chip power-on operation stage to a corresponding chip fault signal; the fault processing route module is respectively connected with the fault response configuration module and the fault signal state bit module and is used for sending a chip fault signal according to the determined fault route; the fault pretreatment executing module is respectively connected with the fault response configuration module and the fault treatment routing module and is used for executing a fault pretreatment mechanism and starting timing; the fault preprocessing timer is respectively connected with the fault response configuration module and the fault preprocessing execution module and is used for timing monitoring of hardware preprocessing and judging whether a fault final processing mechanism is enabled or not; the fault preprocessing response module is connected with the fault preprocessing timer and is used for determining the corresponding software preprocessing state.

Description

Response management system and method for chip fault processing and vehicle-mounted equipment

Technical Field

The application relates to the technical field of vehicle-mounted chip fault processing, in particular to a response management system and method for chip fault processing and vehicle-mounted equipment.

Background

At present, along with the continuous improvement of the intelligent or even unmanned level of automobile control and the continuous acceleration of the integration process of an electronic and electric architecture from a distributed mode to a centralized mode by various large-scale automobile manufacturers, the control range of a single chip is gradually enlarged from a simple external load to a complex whole automobile functional domain, and the influence degree of circuit failure on the running state of the whole automobile is also aggravated, so that the safety problem of an automobile-scale MCU (Microcontrol ler Unit, micro control unit) chip is more and more concerned.

In order to solve the problem of improving the running safety of the vehicle-gauge MCU chip, the related technology performs centralized management on fault events through an independent fault processing unit, receives fault signals detected by safety mechanism modules of all modules in the vehicle-gauge MCU chip, and performs fault processing operation according to user configuration. Therefore, the chip is ensured to enter a safe state in the expected time after the fault occurs, and the fault is prevented from spreading to the whole vehicle functional layer from the internal module of the chip. The behavior of the chip in the face of a fault event is therefore directly dependent on the way the internal fault handling unit operates.

In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art:

The related art can ensure the operation safety of the chip, but after detecting a fault event, the chip directly performs fault processing on the received fault signal based on the configured hardware circuit and the pre-configured fault response measures, so that the chip enters a safe state in the shortest time. However, the fault processing time of the chip is extremely short, and the chip performs system reset while entering a secure state, and the fault processing is performed while causing loss of field data and failure to recover. Thus, the rapid failure handling described above can affect the functionality of other hardware modules that do not fail, adversely affecting the usability of the vehicle system.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the application and thus may include information that does not form the prior art that is already known to those of ordinary skill in the art.

Disclosure of Invention

The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview, and is intended to neither identify key/critical elements nor delineate the scope of such embodiments, but is intended as a prelude to the more detailed description that follows.

The embodiment of the disclosure provides a response management system and method for chip fault processing and vehicle-mounted equipment, so that the system usability of a vehicle-mounted chip is improved while the running safety of the chip is ensured.

In some embodiments, the method comprises: the fault response configuration module is used for storing and transmitting configuration information to complete initialization configuration operation, wherein the configuration information comprises fault types, corresponding fault routes, fault types, corresponding fault processing mechanisms and timing monitoring thresholds which are corresponding to the fault pretreatment mechanisms and used for setting timing overtime states of the fault pretreatment mechanisms, and the fault processing mechanisms comprise a fault pretreatment mechanism setting mechanism and a fault final processing mechanism setting mechanism; the fault signal state bit module is used for latching an on-chip alarm signal in the chip power-on operation stage to a corresponding chip fault signal; the fault processing route module is respectively connected with the fault response configuration module and the fault signal state bit module and is used for determining a fault route according to the configuration information and the chip fault signal and sending the chip fault signal according to the fault route; the fault preprocessing execution module is respectively connected with the fault response configuration module and the fault processing routing module and is used for determining a fault preprocessing mechanism according to the chip fault signals and the configuration information, executing the fault preprocessing mechanism and starting timing operation; the fault preprocessing timer is respectively connected with the fault response configuration module and the fault preprocessing execution module, and is used for determining a timing monitoring threshold value corresponding to the fault preprocessing mechanism according to the configuration information, judging whether the fault final processing mechanism is enabled or not according to the fault preprocessing state after starting timing operation, wherein the fault preprocessing state comprises a timing overtime state and/or a software preprocessing state of the fault preprocessing mechanism; the fault preprocessing response module is connected with the fault preprocessing timer, and is used for determining a corresponding software preprocessing state according to a fault preprocessing result fed back by user software and sending the corresponding software preprocessing state to the fault preprocessing timer; the fault final processing module is respectively connected with the fault response configuration module, the fault processing routing module and the fault preprocessing timer and is used for judging whether to execute a fault final processing mechanism according to the chip fault signal, the timing overtime state and/or the software preprocessing state.

In some embodiments, the fault signal status bit module is further coupled to the security mechanism module, the fault signal status bit module comprising N status bit modules; the fault signal state bit module is used for receiving the on-chip alarm signal sent by the security mechanism module in the on-chip power-on operation stage, latching the on-chip alarm signal into the fault state bit of the corresponding state bit module, and generating a chip fault signal based on the fault state bit latched by the state bit module; wherein, the fault state bits stored by each state bit module are different, and N is an integer greater than or equal to 2.

In some embodiments, setting the fault pre-treatment mechanism includes sending an interrupt request and/or sending a prompt to the user software indicating that the chip is faulty; setting the fault final processing mechanism comprises sending a system reset request and/or outputting alarm information indicating that the current state of the chip is unavailable.

In some embodiments, a fault pre-processing timer enables a fault-terminated processing mechanism if the count value is greater than or equal to a timing-monitoring threshold; and/or, in case the software preprocessing state is failed, enabling a fault final processing mechanism; the fault final processing module executes a fault final processing mechanism under the condition that the count value is greater than or equal to the timing monitoring threshold value; and/or executing a fault final processing mechanism in the case that the software preprocessing state is failed.

In some embodiments, the fault processing routing module is further configured to send a chip fault signal to the fault preprocessing execution module according to the fault route when the fault route includes the fault preprocessing execution module, the fault preprocessing timer, and the fault preprocessing response module; or in the case that the fault route comprises a fault final processing module, sending a chip fault signal to the fault final processing module according to the fault route.

In some embodiments, the fault response configuration module is further configured to set a timing monitoring threshold corresponding to each set fault pretreatment mechanism according to a fault tolerance time of the chip capable of carrying a security requirement.

In some embodiments, the chip is configured with a plurality of hardware circuits, the fault response configuration module is further configured to determine a fault type according to a failure mode and a failure impact range of each hardware circuit, and determine a set fault pre-treatment mechanism of each fault type according to a fault handling policy and a hardware function failure risk of each fault type when the chip is powered up.

In some embodiments, the method is applied to a response management system as described above, the method comprising: under the condition of finishing the initialization configuration operation, latching an on-chip alarm signal in the chip power-on operation stage to a corresponding chip fault signal; the method comprises the steps of initializing configuration operation, wherein the configuration operation comprises the steps of storing and issuing configuration information, the configuration information comprises fault types and corresponding fault routes, fault types and corresponding fault processing mechanisms, and setting timing monitoring thresholds corresponding to the fault pretreatment mechanisms, and the fault processing mechanisms comprise the steps of setting the fault pretreatment mechanisms and setting fault final processing mechanisms; determining a fault route according to the configuration information and the chip fault signal, and sending the chip fault signal according to the fault route; determining a fault pretreatment mechanism and a corresponding timing monitoring threshold value indicating a timing overtime state according to the chip fault signal and the configuration information, executing the fault pretreatment mechanism and controlling a fault pretreatment timer to start timing operation; judging whether a fault final processing mechanism is enabled or not according to the fault preprocessing state after the fault preprocessing timer starts timing operation; and judging whether to execute a fault final processing mechanism according to the chip fault signal and the fault preprocessing state.

In some embodiments, the fault pre-processing state includes a timed-out state of the fault pre-processing mechanism and/or a software pre-processing state, the software pre-processing state being determined by a fault pre-processing result fed back by the user software, and determining whether to enable the fault final-processing mechanism based on the fault pre-processing state after the fault pre-processing timer starts the timing operation, including: enabling a fault final processing mechanism under the condition that the count value is greater than or equal to the timing monitoring threshold value; and/or enabling a fault termination mechanism in the event that the software pre-processing state fails.

In some embodiments, an in-vehicle apparatus includes: the equipment body is provided with a vehicle gauge chip; the response management system for chip fault handling as described above is mounted to the device body.

The response management system and method for chip fault processing and the vehicle-mounted equipment provided by the embodiment of the disclosure can realize the following technical effects:

According to the embodiment of the disclosure, the fault pretreatment process is added in the response management system for chip fault treatment, the timing monitoring of hardware pretreatment is performed by using the fault pretreatment timer, meanwhile, the monitoring of software pretreatment is performed by using the fault pretreatment response module, corresponding fault treatment mechanisms can be executed for different fault types, the echelon of fault treatment is realized, the repairable faults of the chip and the interception of unrepairable faults of the chip are ensured, the defects of single fault treatment scheme and the interruption of the current running state of the chip in the related technology are overcome, and therefore, the system availability of the vehicle-mounted chip is improved while the running safety of the chip is ensured.

The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which like reference numerals refer to similar elements, and in which:

FIG. 1 is a hardware schematic of a response management system for chip fault handling provided by an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of another response management system for chip fault handling provided by an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a response management method for chip fault handling provided by an embodiment of the present disclosure;

FIG. 4 is a schematic illustration of one application provided by an embodiment of the present disclosure;

FIG. 5 (a) is a timing diagram of a response management system for chip fault handling provided by embodiments of the present disclosure;

FIG. 5 (b) is a timing diagram of another response management system for chip fault handling provided by an embodiment of the present disclosure;

Fig. 6 is a schematic diagram of a response management apparatus for chip fault handling according to an embodiment of the present disclosure.

Reference numerals:

100: a fault response configuration module; 101: a fault signal status bit module; 102: a fault handling routing module;

103: a fault preprocessing execution module; 104: a fault pre-processing timer; 105: a fault preprocessing response module;

106: a fault final processing module;

200: the response management system is used for processing the chip faults; 300, a security mechanism module;

70: response management means for chip failure handling;

700: a processor; 701: a memory; 702: a communication interface; 703: a bus.

Detailed Description

So that the manner in which the features and techniques of the disclosed embodiments can be understood in more detail, a more particular description of the embodiments of the disclosure, briefly summarized below, may be had by reference to the appended drawings, which are not intended to be limiting of the embodiments of the disclosure. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawing.

The terms first, second and the like in the description and in the claims of the embodiments of the disclosure and in the above-described figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe embodiments of the present disclosure. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.

The term "plurality" means two or more, unless otherwise indicated.

In the embodiment of the present disclosure, the character "/" indicates that the front and rear objects are an or relationship. For example, A/B represents: a or B.

The term "and/or" is a corresponding relationship that describes an object, meaning that three relationships may exist. For example, a and/or B, represent: a or B, or, A and B.

The term "corresponding" may refer to a corresponding relationship or binding relationship, and the correspondence between a and B refers to a corresponding relationship or binding relationship between a and B.

As shown in fig. 1, the embodiment of the disclosure provides a response management system 200 for chip fault handling, which includes a fault response configuration module 100, a fault signal status bit module 101, a fault handling routing module 102, a fault pre-processing execution module 103, a fault pre-processing timer 104, a fault pre-processing response module 105, and a fault final processing module 106.

The fault response configuration module 100 is configured to save and issue configuration information to complete an initialization configuration operation, where the configuration information includes a fault type and a corresponding fault route, a fault type and a corresponding fault handling mechanism, and a timing monitoring threshold corresponding to the fault pretreatment mechanism and indicating a timing timeout state, and the fault handling mechanism includes a fault pretreatment mechanism setting and a fault final handling mechanism setting. It should be noted that the failure type and the storage type of the corresponding failure handling mechanism include one or more of the following: database, function model, cache. The storage type for setting the fault pre-treatment mechanism and setting the corresponding timing monitoring threshold value indicating the timing overtime state of the fault pre-treatment mechanism comprises one or more of the following: database, function model and cache. The storage type of the correspondence relationship in the embodiment of the present disclosure may not be specifically limited.

The fault signal state bit module 101 is configured to latch an on-chip alarm signal in a chip power-on operation stage to a corresponding chip fault signal.

The fault processing route module 102 is respectively connected with the fault response configuration module 100 and the fault signal state bit module 101, and is used for determining a fault route according to the configuration information and the chip fault signal and sending the chip fault signal according to the fault route. It should be noted that, after determining the fault type corresponding to the chip fault signal according to the chip fault signal, the fault processing routing module 102 determines a fault route according to the fault type and the corresponding fault route, and sends the chip fault signal according to the fault route. As an example, the fault handling routing module 102 determines, from the chip fault signals, a fault type corresponding to the chip fault signals, including: the fault processing routing module 102 determines a fault state bit corresponding to the chip fault signal according to the chip fault signal, and determines a fault type corresponding to the chip fault signal according to the fault state bit; or the fault handling routing module 102 obtains the set correspondence between the chip fault signals and the fault types, and determines the fault types corresponding to the chip fault signals according to the set correspondence. The method for determining the fault type corresponding to the chip fault signal in the embodiment of the present disclosure may not be specifically limited.

The fault preprocessing execution module 103 is respectively connected with the fault response configuration module 100 and the fault processing routing module 102, and is used for determining a fault preprocessing mechanism according to the chip fault signals and the configuration information, executing the fault preprocessing mechanism and starting timing operation. Note that the fault pre-processing execution module 103 starts a timer operation while executing the fault pre-processing mechanism. Thus, the accuracy of the hardware preprocessing timing monitoring is ensured.

The fault preprocessing timer 104 is respectively connected with the fault response configuration module 100 and the fault preprocessing execution module 103, and is configured to determine a timing monitoring threshold corresponding to the fault preprocessing mechanism according to the configuration information, and determine whether to enable the fault final processing mechanism according to a fault preprocessing state after starting timing operation, where the fault preprocessing state includes a timing timeout state and/or a software preprocessing state of the fault preprocessing mechanism.

The fault preprocessing response module 105 is connected with the fault preprocessing timer 104, and is configured to determine a corresponding software preprocessing state according to a fault preprocessing result fed back by the user software, and send the corresponding software preprocessing state to the fault preprocessing timer 104.

The fault final processing module 106 is connected to the fault response configuration module 100, the fault processing routing module 102, and the fault preprocessing timer 104, and is configured to determine whether to execute the fault final processing mechanism according to the chip fault signal, the timing timeout state, and/or the software preprocessing state.

By adopting the response management system 200 for chip fault processing provided by the embodiment of the disclosure, the fault response configuration module is used for storing and transmitting configuration information to other related modules to complete initialization configuration operation, and the fault signal state bit module latches an on-chip alarm signal in a chip power-on operation stage to a corresponding chip fault signal so as to ensure that a fault state cannot dynamically change. The fault processing route module obtains the fault type and the corresponding fault route according to the configuration information issued by the fault response module, determines the fault route according to the fault type and the chip fault signal, and sends the chip fault signal according to the fault route so as to execute a fault pretreatment mechanism or a fault final processing mechanism according to the chip fault signal. The fault preprocessing execution module obtains the fault type and the corresponding fault processing mechanism according to the chip fault signal and the configuration information issued by the fault response module, sets the timing monitoring threshold corresponding to the fault preprocessing mechanism, determines and executes the fault preprocessing mechanism according to the fault type and the chip fault signal, and starts timing operation. The fault preprocessing timer determines a timing monitoring threshold value of a time margin corresponding to the fault preprocessing mechanism and providing hardware preprocessing according to configuration information issued by the fault response module, and judges whether to enable the fault final processing mechanism according to the fault preprocessing state after starting timing operation. The fault preprocessing response module determines a corresponding software preprocessing state according to a fault preprocessing result fed back by the user software and feeds back the corresponding software preprocessing state to the fault preprocessing timer, and the fault terminal processing module judges whether to execute a fault terminal processing mechanism according to the chip fault signal and the timing overtime state and/or the software preprocessing state. In this way, in the embodiment of the disclosure, by adding a fault preprocessing process in the response management system for chip fault processing and performing timing monitoring of hardware preprocessing by using the fault preprocessing timer, and simultaneously performing monitoring of software preprocessing by using the fault preprocessing response module, a corresponding fault processing mechanism can be executed for different fault types and gradient of fault processing is realized, so that repair of repairable faults of a chip and interception of unrepairable faults of the chip are ensured, defects of single fault processing scheme and interruption of the current running state of the chip in the related art are overcome, and therefore, the system availability of the vehicle-mounted chip is improved while the running safety of the chip is ensured.

Optionally, as shown in connection with fig. 2, the fault signal status bit module 101 is further connected to the safety mechanism module 300, where the fault signal status bit module 101 includes N status bit modules (first status bit module,..sub.n-th status bit module). The fault signal state bit module 101 receives an on-chip alarm signal sent by the security mechanism module 300 in the on-chip power-on operation stage, latches the on-chip alarm signal into a fault state bit of a corresponding state bit module, and generates a chip fault signal based on the fault state bit latched by the state bit module; wherein, the fault state bits stored by each state bit module are different, and N is an integer greater than or equal to 2. Therefore, the classified latching of different fault state bits is realized, and the chip fault signals are ensured not to dynamically change in the subsequent fault processing process.

Optionally, setting the fault pretreatment mechanism includes sending an interrupt request and/or sending a prompt message indicating that the chip has a fault to user software; setting the fault final processing mechanism comprises sending a system reset request and/or outputting alarm information indicating that the current state of the chip is unavailable.

In this way, the embodiment of the disclosure sends the interrupt request and/or sends the prompt information indicating the chip failure to the user software, so that the chip performs hardware preprocessing under the timing monitoring of the failure preprocessing timer, and the user software performs software preprocessing according to the received prompt information, so as to cooperate with the software and hardware to perform the inspection of related chip failure, the removal of failure source and the recovery of field data, so that the chip system affected by the failure can resume normal operation, the chip is prevented from directly entering a safe state due to the influence of the failure, and the system availability of the vehicle-mounted chip is ensured. Meanwhile, if the timing overtime state indicates that the hardware preprocessing overtime and the software preprocessing state indicates that the software preprocessing fails, the method indicates that the hardware preprocessing and the software preprocessing cannot eliminate faults, and a system reset request is sent and/or alarm information indicating that the current state of the chip is unavailable is output, so that the vehicle-mounted chip system is ensured to enter a safe state before the fault influences are diffused, and the running safety of the chip is ensured.

Optionally, the fault pre-processing timer 104 enables the fault final processing mechanism if the count value is greater than or equal to the timing monitoring threshold; and/or enabling a fault termination mechanism in the event that the software pre-processing state fails.

A fault end processing module 106 that executes a fault end processing mechanism if the count value is greater than or equal to the timing monitor threshold; and/or executing a fault final processing mechanism in the case that the software preprocessing state is failed.

Thus, the fault pre-processing timer indicates that the hardware pre-processing is overtime when the count value is greater than or equal to the timing monitoring threshold value, determines that the hardware pre-processing cannot eliminate the fault, and/or determines that the software pre-processing cannot eliminate the fault when the software pre-processing state is failed. At this point, the fault termination mechanism is enabled. Correspondingly, the fault final processing module executes a fault final processing mechanism when the count value is greater than or equal to the timing monitoring threshold value and/or when the software preprocessing state is failure, so as to avoid the rapid fault diffusion of the vehicle-mounted chip system, ensure that the vehicle-mounted chip system enters a safe state before the fault influences the diffusion, and ensure the running safety of the chip and the usability of the system.

Optionally, the fault handling routing module 102 is further configured to send a chip fault signal to the fault pre-processing execution module 103 according to the fault route in a case that the fault route includes the fault pre-processing execution module 103, the fault pre-processing timer 104, and the fault pre-processing response module 105; or in the case where the fault route includes a fault termination processing module 106, send a chip fault signal to the fault termination processing module 106 in accordance with the fault route.

In this way, when the fault route comprises a fault preprocessing execution module, a fault preprocessing timer and a fault preprocessing response module, the fault processing route module sends a chip fault signal to the fault preprocessing execution module according to the fault route so that the fault preprocessing execution module executes a fault preprocessing mechanism, and the fault preprocessing timer is utilized to perform timing monitoring of hardware preprocessing and the fault preprocessing response module is utilized to acquire a software preprocessing state corresponding to a fault preprocessing result fed back by user software, so that timing monitoring of the hardware preprocessing and monitoring of the software preprocessing are realized. And when the fault route comprises a fault final processing module, the fault processing routing module sends a chip fault signal to the fault final processing module according to the fault route so as to realize system-level fault processing. Therefore, the embodiment of the disclosure can realize echelon fault processing, and can execute corresponding fault processing mechanisms aiming at different fault types, so that the repairable faults of the chip and the unrepairable faults of the chip are ensured to be repaired, the defects of single fault processing scheme and interruption of the current running state of the chip in the related technology are overcome, and the availability and safety of a system for running the vehicle-mounted chip are ensured.

Optionally, the fault response configuration module 105 is further configured to set a timing monitoring threshold corresponding to each set fault pretreatment mechanism according to the fault tolerance time of the chip capable of carrying the security requirement.

Therefore, the fault response configuration module sets the timing monitoring threshold corresponding to each set fault pretreatment mechanism according to the fault tolerance time of the chip capable of bearing the safety requirement, can prevent the fault treatment from falling into a circulating state or the situation that the chip system cannot respond normally due to the fact that the fault influence is spread, and ensures the system availability of the operation of the vehicle-mounted chip.

Optionally, the chip is configured with a plurality of hardware circuits. The fault response configuration module 100 is further configured to determine a fault type according to a failure mode and a failure impact range of each hardware circuit, and determine a set fault pretreatment mechanism of each fault type according to a fault handling policy and a hardware function failure risk of each fault type when the chip is powered on.

Therefore, the set fault pretreatment mechanism stored by the fault response module is beneficial to the inspection of chip faults, the removal of fault sources and the recovery of field data, the chip faults are eliminated rapidly through hardware pretreatment, the availability and the safety of a system for running the vehicle-mounted chip are ensured, and meanwhile, the reliability and the efficiency of chip fault treatment are improved.

As an example, a chip is configured with a memory circuit and a security mechanism circuit. The fault type includes a repairable data fault of the storage circuit and a self fault of the safety mechanism circuit. When the chip is electrified, the fault response configuration module determines that the fault type of the storage circuit is repairable data fault of the storage circuit according to the failure mode and the failure influence range of the storage circuit, and determines that the fault type of the safety mechanism circuit is self fault of the safety mechanism circuit according to the failure mode and the failure influence range of the hardware circuit safety mechanism circuit. And determining the set fault pretreatment mechanism of each fault type according to the fault treatment strategies of the two fault types and the hardware functional failure risk.

As shown in fig. 3, the embodiment of the disclosure further provides a response management method for chip fault handling, which is applied to the response management system for chip fault handling, and the method includes:

S01, under the condition that the initialization configuration operation is completed, the fault response configuration module 100 latches an on-chip alarm signal in the chip power-on operation stage to a corresponding chip fault signal. The configuration operation is initialized, wherein the configuration information is stored and issued, the configuration information comprises fault types and corresponding fault routes, fault types and corresponding fault processing mechanisms, and timing monitoring thresholds corresponding to the fault pretreatment mechanisms are set, and the fault processing mechanisms comprise fault pretreatment mechanism setting and fault final processing mechanism setting.

S02, the fault processing route module 102 determines a fault route according to the configuration information and the chip fault signal, and sends the chip fault signal according to the fault route.

S03, the fault preprocessing execution module 103 determines a fault preprocessing mechanism and a corresponding timing monitoring threshold value indicating a timing overtime state according to the chip fault signal and the configuration information, executes the fault preprocessing mechanism and controls the fault preprocessing timer 104 to start timing operation.

S04, judging whether to enable the fault final processing mechanism according to the fault preprocessing state after the fault preprocessing timer 104 starts timing operation.

S05, the fault final processing module 106 judges whether to execute a fault final processing mechanism according to the chip fault signal and the fault preprocessing state.

By adopting the response management method for chip fault processing provided by the embodiment of the disclosure, the embodiment of the disclosure adds the fault pretreatment process in the response management system for chip fault processing, and performs timing monitoring of hardware pretreatment by using the fault pretreatment timer, and simultaneously, performs monitoring of software pretreatment by using the fault pretreatment response module, so that corresponding fault processing mechanisms can be executed aiming at different fault types, echelon of fault processing is realized, repair of chip repairable faults and interception of chip repairable faults are ensured, defects of single fault processing scheme and interruption of the current running state of the chip in the related art are overcome, and the system availability of the vehicle-mounted chip is improved while the running safety of the chip is ensured.

Optionally, the fault pre-processing state includes a timed-out state of the fault pre-processing mechanism and/or a software pre-processing state. The software preprocessing state is determined by the fault preprocessing result fed back by the user software. Judging whether to enable the fault final processing mechanism according to the fault preprocessing state after the fault preprocessing timer 104 starts the timing operation, including:

In the event that the count value is greater than or equal to the timing monitor threshold, the fault pre-processing timer 104 enables a fault-terminated processing mechanism; and/or the number of the groups of groups,

In the event that the software preprocessing state is failed, the fault preprocessing timer 104 enables the fault termination mechanism.

Thus, the fault pre-processing timer indicates that the hardware pre-processing is overtime when the count value is greater than or equal to the timing monitoring threshold value, determines that the hardware pre-processing cannot eliminate the fault, and/or determines that the software pre-processing cannot eliminate the fault when the software pre-processing state is failed. At this time, a fault final processing mechanism is enabled to avoid the rapid fault diffusion of the vehicle-mounted chip system, ensure that the vehicle-mounted chip system enters a safe state before the fault influences the diffusion, and ensure the running safety of the chip and the usability of the system.

In practical application, as shown in fig. 4, the response management method for chip fault handling specifically includes the following steps:

In step S101, the fault response configuration module 100 latches the on-chip alarm signal in the chip power-on operation stage to the corresponding chip fault signal when the initialization configuration operation is completed. The configuration operation is initialized, wherein the configuration information is stored and issued, the configuration information comprises fault types and corresponding fault routes, fault types and corresponding fault processing mechanisms, and timing monitoring thresholds corresponding to the fault pretreatment mechanisms are set, and the fault processing mechanisms comprise fault pretreatment mechanism setting and fault final processing mechanism setting. Step S102 or S103 is performed.

In step S102, the fault handling routing module 102 sends a chip fault signal to the fault preprocessing execution module 103 according to the fault route in the case that the fault route includes a local path. The local path includes a path formed by the fault preprocessing execution module 103, the fault preprocessing timer 104 and the fault preprocessing response module 105.

Step S103, in the case that the fault route includes the system path, the fault handling routing module 102 sends a chip fault signal to the fault final handling module 106 according to the fault route, and performs step S107. Wherein the system path includes a fault termination module 106.

In step S104, the fault pre-processing execution module 103 determines a fault pre-processing mechanism according to the chip fault signal and the configuration information, executes the fault pre-processing mechanism, and starts a timing operation. Wherein performing the fault pre-treatment mechanism comprises: and sending an interrupt request and/or sending prompt information indicating that the chip fails to the user software.

In step S105, the fault preprocessing response module 105 determines a corresponding software preprocessing state according to the fault preprocessing result fed back by the user software, and sends the software preprocessing state to the fault preprocessing timer 104. Step S106 or S108 is performed.

In step S106, the fault pre-processing execution module 100 enables the fault final processing mechanism when the count value is greater than or equal to the timing monitoring threshold and the software pre-processing state is failed.

In step S107, the failure end processing module 106 executes a failure end processing mechanism.

In step S108, the fault pre-processing execution module 100 resumes the normal operation of the chip when the count value is smaller than the timing monitoring threshold or the software pre-processing state is successful.

In another practical application, fig. 5 (a) is a timing diagram of a response management system for chip fault handling according to an embodiment of the present disclosure, and fig. 5 (b) is a timing diagram of another response management system for chip fault handling according to an embodiment of the present disclosure.

Referring to fig. 5 (a), after a chip fails, the security mechanism module performs security mechanism detection to realize failure diagnosis, obtains an on-chip alarm signal, and reports the on-chip alarm signal to a response management system for processing the chip failure. The response management system for chip failure processing performs hardware failure preprocessing based on the configuration information and the user software performs software failure preprocessing to implement local path failure preprocessing. But none of the local path failures can handle the failure. Because the fault condition is complex or the fault affects the chip upgrade, the response management system for chip fault processing executes a fault final processing mechanism to realize system-level fault processing. Thereby avoiding continued spread of faults.

Referring to fig. 5 (b), after a chip fails, the security mechanism module performs security mechanism detection to realize failure diagnosis, obtains an on-chip alarm signal, and reports the on-chip alarm signal to a response management system for processing the chip failure. The response management system for chip fault processing executes hardware fault preprocessing based on the configuration information, user software checks relevant fault information according to the received prompt, fault source clearing and on-site data recovery are carried out, and the hardware fault preprocessing completes all fault processing flows within a timing monitoring threshold value, so that the chip system affected by the fault is recovered to normal operation.

As shown in connection with fig. 6, an embodiment of the present disclosure provides a response management apparatus 70 for chip fault handling, including a processor (processor) 700 and a memory (memory) 701. Optionally, the apparatus 70 may further comprise a communication interface (Communicat ion I NTERFACE) 702 and a bus 703. The processor 700, the communication interface 702, and the memory 701 may communicate with each other through the bus 703. The communication interface 702 may be used for information transfer. The processor 700 may call logic instructions in the memory 701 to perform the response management method for chip failure handling of the above-described embodiments.

Further, the logic instructions in the memory 701 may be implemented in the form of software functional units and may be stored in a computer readable storage medium when sold or used as a stand alone product.

The memory 701 is used as a computer readable storage medium for storing a software program, a computer executable program, and program instructions/modules corresponding to the methods in the embodiments of the present disclosure. The processor 700 executes the functional applications and data processing by executing the program instructions/modules stored in the memory 701, i.e., implements the response management method for chip failure processing in the above-described embodiment.

Memory 701 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, at least one application program required for a function; the storage data area may store data created according to the use of the terminal device, etc. In addition, the memory 701 may include a high-speed random access memory, and may also include a nonvolatile memory.

The embodiment of the disclosure provides a vehicle-mounted device, which comprises: an apparatus body, and the response management system 200 for chip failure processing described above. And the equipment body is provided with a vehicle gauge chip. The response management system 200 for chip failure processing is mounted to the device body. The mounting relationship described herein is not limited to being placed inside the device body, but includes mounting connection with other components of the in-vehicle device, including but not limited to physical connection, electrical connection, signal transmission connection, or the like. Those skilled in the art will appreciate that the response management system 200 for chip fault handling may be adapted to a viable device body to implement other viable embodiments.

Embodiments of the present disclosure provide a computer-readable storage medium storing computer-executable instructions configured to perform the above-described response management method for chip failure processing.

Embodiments of the present disclosure may be embodied in a software product stored on a storage medium, including one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of a method according to embodiments of the present disclosure. While the aforementioned storage medium may be a non-transitory storage medium, such as: a usb disk, a removable hard disk, a Read-only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or the like, which can store program codes.

The above description and the drawings illustrate embodiments of the disclosure sufficiently to enable those skilled in the art to practice them. Other embodiments may involve structural, logical, electrical, process, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for, those of others. Moreover, the terminology used in the present application is for the purpose of describing embodiments only and is not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a," "an," and "the" (the) are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this disclosure is meant to encompass any and all possible combinations of one or more of the corresponding listed. Furthermore, when used in the present disclosure, the terms "comprises" (compr ise) and its variants "comprising" (compr ises) and/or comprising (compr ising) and the like, are intended to refer to the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Without further limitation, an element defined by the phrase "comprising one …" does not exclude the presence of other like elements in a process, method or apparatus that includes the element. In this context, each embodiment may be described with emphasis on the differences from the other embodiments, and the same similar parts between the various embodiments may be referred to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method sections disclosed in the embodiments, the description of the method sections may be referred to for relevance.

Those of skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. The skilled artisan may use different methods for each particular application to achieve the described functionality, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.

In the embodiments disclosed herein, the disclosed methods, articles of manufacture (including but not limited to devices, apparatuses, etc.) may be practiced in other ways. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the units may be merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. In addition, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form. The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to implement the present embodiment. In addition, each functional unit in the embodiments of the present disclosure may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. In the description corresponding to the flowcharts and block diagrams in the figures, operations or steps corresponding to different blocks may also occur in different orders than that disclosed in the description, and sometimes no specific order exists between different operations or steps. For example, two consecutive operations or steps may actually be performed substantially in parallel, they may sometimes be performed in reverse order, which may be dependent on the functions involved. Each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Claims (10)

1. A response management system for chip fault handling, comprising:

The fault response configuration module is used for storing and transmitting configuration information to complete initialization configuration operation, wherein the configuration information comprises fault types, corresponding fault routes, fault types, corresponding fault processing mechanisms and timing monitoring thresholds which are corresponding to the fault pretreatment mechanisms and used for setting timing overtime states of the fault pretreatment mechanisms, and the fault processing mechanisms comprise a fault pretreatment mechanism setting mechanism and a fault final processing mechanism setting mechanism;

The fault signal state bit module is used for latching an on-chip alarm signal in the chip power-on operation stage to a corresponding chip fault signal;

The fault processing route module is respectively connected with the fault response configuration module and the fault signal state bit module and is used for determining a fault route according to the configuration information and the chip fault signal and sending the chip fault signal according to the fault route;

the fault preprocessing execution module is respectively connected with the fault response configuration module and the fault processing routing module and is used for determining a fault preprocessing mechanism according to the chip fault signals and the configuration information, executing the fault preprocessing mechanism and starting timing operation;

The fault preprocessing timer is respectively connected with the fault response configuration module and the fault preprocessing execution module, and is used for determining a timing monitoring threshold value corresponding to the fault preprocessing mechanism according to the configuration information, judging whether the fault final processing mechanism is enabled or not according to the fault preprocessing state after starting timing operation, wherein the fault preprocessing state comprises a timing overtime state and/or a software preprocessing state of the fault preprocessing mechanism;

The fault preprocessing response module is connected with the fault preprocessing timer, and is used for determining a corresponding software preprocessing state according to a fault preprocessing result fed back by user software and sending the corresponding software preprocessing state to the fault preprocessing timer;

The fault final processing module is respectively connected with the fault response configuration module, the fault processing routing module and the fault preprocessing timer and is used for judging whether to execute a fault final processing mechanism according to the chip fault signal, the timing overtime state and/or the software preprocessing state.

2. The response management system of claim 1, wherein the fault signal status bit module is further coupled to the security mechanism module, the fault signal status bit module comprising N status bit modules; the fault signal state bit module is used for receiving the on-chip alarm signal sent by the security mechanism module in the on-chip power-on operation stage, latching the on-chip alarm signal into the fault state bit of the corresponding state bit module, and generating a chip fault signal based on the fault state bit latched by the state bit module;

Wherein, the fault state bits stored by each state bit module are different, and N is an integer greater than or equal to 2.

3. The response management system according to claim 1, wherein setting the fault pre-treatment mechanism includes sending an interrupt request and/or sending a prompt message to the user software indicating that the chip is faulty;

Setting the fault final processing mechanism comprises sending a system reset request and/or outputting alarm information indicating that the current state of the chip is unavailable.

4. The response management system according to claim 1, wherein the fault pre-processing timer enables the fault final processing mechanism if the count value is greater than or equal to the timing monitor threshold; and/or, in case the software preprocessing state is failed, enabling a fault final processing mechanism;

The fault final processing module executes a fault final processing mechanism under the condition that the count value is greater than or equal to the timing monitoring threshold value; and/or executing a fault final processing mechanism in the case that the software preprocessing state is failed.

5. The response management system of claim 1, wherein the fault handling routing module is further configured to send a chip fault signal to the fault pre-processing execution module according to the fault route in the case that the fault route includes the fault pre-processing execution module and the fault pre-processing timer, the fault pre-processing response module; or alternatively

And sending a chip fault signal to the fault final processing module according to the fault route under the condition that the fault route comprises the fault final processing module.

6. The response management system according to any one of claims 1 to 5, wherein the fault response configuration module is further configured to set a timing monitoring threshold corresponding to each set fault pre-treatment mechanism according to a fault tolerance time for which the chip can carry a security requirement.

7. The response management system according to any one of claims 1 to 5, wherein the chip is configured with a plurality of hardware circuits, the fault response configuration module is further configured to determine a fault type based on a failure mode and a failure impact range of each hardware circuit, and determine a set fault pre-treatment mechanism for each fault type based on a fault handling policy and a hardware function failure risk of each fault type, at power-up of the chip.

8. A response management method for chip fault handling, characterized in that it is applied to the response management system according to any one of claims 1 to 7, the method comprising:

Under the condition of finishing the initialization configuration operation, latching an on-chip alarm signal in the chip power-on operation stage to a corresponding chip fault signal; the method comprises the steps of initializing configuration operation, wherein the configuration operation comprises the steps of storing and issuing configuration information, the configuration information comprises fault types and corresponding fault routes, fault types and corresponding fault processing mechanisms, and setting timing monitoring thresholds corresponding to the fault pretreatment mechanisms, and the fault processing mechanisms comprise the steps of setting the fault pretreatment mechanisms and setting fault final processing mechanisms;

Determining a fault route according to the configuration information and the chip fault signal, and sending the chip fault signal according to the fault route;

Determining a fault pretreatment mechanism and a corresponding timing monitoring threshold value indicating a timing overtime state according to the chip fault signal and the configuration information, executing the fault pretreatment mechanism and controlling a fault pretreatment timer to start timing operation;

Judging whether a fault final processing mechanism is enabled or not according to the fault preprocessing state after the fault preprocessing timer starts timing operation;

And judging whether to execute a fault final processing mechanism according to the chip fault signal and the fault preprocessing state.

9. The response management method according to claim 8, wherein the fault preprocessing state includes a time-out state of timing of the fault preprocessing mechanism and/or a software preprocessing state, the software preprocessing state being determined by a result of fault preprocessing fed back by the user software, the determining whether to enable the fault end processing mechanism based on the fault preprocessing state after the fault preprocessing timer starts the timing operation includes:

Enabling a fault final processing mechanism under the condition that the count value is greater than or equal to the timing monitoring threshold value; and/or the number of the groups of groups,

In the event that the software preprocessing state is failed, the fault termination mechanism is enabled.

10. An in-vehicle apparatus, characterized by comprising:

the equipment body is provided with a vehicle gauge chip;

A response management system for chip failure handling according to any one of claims 1 to 7, mounted to the device body.