CN118315433B - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present invention provides a semiconductor device and a preparation method thereof, comprising: a substrate, an isolation oxide layer and a gate structure, wherein the substrate comprises an adjacent fin structure region and a deep trench region, the fin structure region and the deep trench region both comprise a buried oxide layer, the fin structure region further comprises a fin structure located on the buried oxide layer, the deep trench region further comprises a plurality of deep trench capacitors penetrating the buried oxide layer, the deep trench capacitor comprises a trench portion and a fin portion located on the trench portion, the top of the trench portion is lower than the top of the buried oxide layer, the top of the fin portion is higher than the top of the buried oxide layer, and a groove is provided between the fin portion and the buried oxide layer; the isolation oxide layer is located on the trench portion and fills the groove and covers the sidewall of the fin portion; the gate structure is located on a portion of the deep trench capacitor, a portion of the isolation oxide layer, a portion of the buried oxide layer and a portion of the fin structure. The present invention can increase the isolation performance of the device to ensure the electrical performance of the device.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same.

Background Art

A deep trench capacitor (DTC) is a vertical semiconductor device used to provide capacitance for various integrated circuits; for example, semiconductor integrated circuits including field effect transistors (FETs) or metal oxide semiconductor FETs (MOSFETs) have been committed to providing higher speeds, higher integration density, and more optimized functions. The deep trench capacitor is located in the substrate. The deep trench capacitor generally includes a trench portion and a fin portion located on the trench portion. The top of the trench portion is lower than the top of the substrate, the top of the fin portion is higher than the top of the substrate, the width of the fin portion is smaller than the width of the trench portion, and there is a groove between the substrate and the fin portion, and the groove is located on the trench portion. An isolation layer needs to be formed in the groove. On the one hand, it prevents the subsequent etching process from affecting the deep trench capacitor and causing the risk of short circuit. On the other hand, the subsequent gate structure needs to be formed on part of the deep trench capacitor, and the gate structure will also cover the isolation layer in the groove. The quality and structure of the isolation layer determine the isolation performance of the device. If there is a problem with the isolation layer, it will cause the risk of short circuit in the device and increase the possibility of device leakage.

Summary of the invention

The object of the present invention is to provide a semiconductor device and a method for preparing the same, so as to increase the isolation performance of the device and ensure the electrical performance of the device.

In order to achieve the above object, the present invention provides a semiconductor device, comprising:

A substrate, the substrate comprising adjacent fin structure regions and deep trench regions, the fin structure regions and the deep trench regions both comprising a buried oxide layer, the fin structure region further comprising a fin structure located on the buried oxide layer, the deep trench region further comprising a plurality of deep trench capacitors penetrating the buried oxide layer, the deep trench capacitors comprising a trench portion and a fin portion located on the trench portion, the top of the trench portion being lower than the top of the buried oxide layer, the top of the fin portion being higher than the top of the fin structure, and a groove being provided between the fin portion and the buried oxide layer;

an isolation oxide layer, located on the trench portion and filling the recess and covering the sidewall of the fin portion;

The gate structure is located on a portion of the deep trench capacitor, a portion of the isolation oxide layer, a portion of the buried oxide layer and a portion of the fin structure.

Optionally, the isolation oxide layer also extends onto the buried oxide layer in the deep trench region.

Optionally, the width of the isolation oxide layer extending to the buried oxide layer in the deep trench region is greater than 2 nm and less than 10 nm.

Optionally, the gate structure includes a gate polysilicon layer, and the gate polysilicon layer located on the deep trench capacitor is vertically aligned with a sidewall of the trench portion away from a sidewall of the fin structure.

Optionally, the gate structure includes a gate polysilicon layer, and the gate polysilicon layer located on the deep trench capacitor covers the isolation oxide layer.

Optionally, a portion of the top surface of the deep trench capacitor under the gate structure close to the fin structure is exposed.

Optionally, a width of a portion of a top surface of the deep trench capacitor under the gate structure close to the fin structure that is exposed is greater than 5 nm and less than 10 nm.

The present invention also provides a method for preparing a semiconductor device, comprising:

A substrate is provided, wherein the substrate comprises a fin structure region and a deep trench region adjacent to each other, wherein the fin structure region and the deep trench region both comprise a buried oxide layer, the fin structure region further comprises a fin structure located on the buried oxide layer, the deep trench region further comprises a plurality of deep trench capacitors penetrating the buried oxide layer, the deep trench capacitors comprising a trench portion and a fin portion located on the trench portion, wherein a top of the trench portion is lower than a top of the buried oxide layer, a top of the fin portion is higher than a top of the fin structure, and a groove is provided between the fin portion and the buried oxide layer;

forming an isolation oxide layer on the trench portion and filling the recess and covering the sidewall of the fin portion;

A gate structure is formed on a portion of the deep trench capacitor, a portion of the isolation oxide layer, a portion of the buried oxide layer and a portion of the fin structure.

Optionally, the step of forming the isolation oxide layer includes:

The isolation oxide layer is formed by a deposition process to fill the groove and cover the sidewall and top of the fin and extend to cover the fin structure and the buried oxide layer;

A dry etching process is used to etch and remove the isolation oxide layer on the fin structure, the isolation buried oxide layer on the top of the fin, and the isolation oxide layer on part of the buried oxide layer. After etching, the isolation oxide layer is located on the groove portion and fills the groove and covers the side wall of the fin, and the isolation oxide layer also extends to the buried oxide layer in the deep groove area.

Optionally, the thickness of the isolation oxide layer is greater than 35 nm and less than 70 nm.

The semiconductor device and its preparation method provided by the present invention include: a substrate, an isolation oxide layer and a gate structure, wherein the substrate includes adjacent fin structure regions and deep trench regions, the fin structure regions and the deep trench regions both include buried oxide layers, the fin structure region also includes a fin structure located on the buried oxide layer, the deep trench region also includes a number of deep trench capacitors penetrating the buried oxide layer, the deep trench capacitor includes a trench portion and a fin portion located on the trench portion, the top of the trench portion is lower than the top of the buried oxide layer, the top of the fin portion is higher than the top of the buried oxide layer, and there is a groove between the fin portion and the buried oxide layer; the isolation oxide layer is located on the trench portion and fills the groove and covers the sidewall of the fin portion; the gate structure is located on part of the deep trench capacitor, part of the isolation oxide layer, part of the buried oxide layer and part of the fin structure. In the present invention, an isolation oxide layer is provided to fill the groove and cover the sidewall of the fin portion, which can better isolate the gate structure and the sidewall of the fin portion, increase the isolation performance of the device, reduce the possibility of device leakage, and thus ensure the electrical performance of the device; and can avoid the problem of depression in the isolation oxide layer in the deep trench region, reducing the risk of device short circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top view of a fin structure and a deep trench capacitor in a semiconductor device provided in Embodiment 1 of the present invention.

FIG. 2 is a schematic cross-sectional view of a semiconductor device along a cross-sectional line A1A2 according to a first embodiment of the present invention.

FIG3 is a schematic cross-sectional view of the semiconductor device provided in the first embodiment of the present invention along the B1B2 cross-sectional line.

4 is a schematic cross-sectional view of the semiconductor device along the A1A2 cross-sectional line after providing a substrate in the method for preparing the semiconductor device provided in the first embodiment of the present invention.

5 is a schematic cross-sectional view of the semiconductor device along the B1B2 cross-sectional line after providing a substrate in the method for preparing the semiconductor device provided in the first embodiment of the present invention.

6 is a schematic cross-sectional view of the semiconductor device along the A1A2 cross-sectional line after the isolation oxide layer is formed in the method for preparing the semiconductor device provided in the first embodiment of the present invention.

7 is a schematic cross-sectional view of the semiconductor device along the B1B2 cross-sectional line after the isolation oxide layer is formed in the method for preparing the semiconductor device provided in the first embodiment of the present invention.

8 is a schematic cross-sectional view of the semiconductor device along the A1A2 cross-sectional line after etching the isolation oxide layer in the method for preparing the semiconductor device provided in the first embodiment of the present invention.

9 is a schematic cross-sectional view of the semiconductor device along the B1B2 cross-sectional line after etching the isolation oxide layer in the method for preparing the semiconductor device provided in the first embodiment of the present invention.

10 is a schematic cross-sectional view of the semiconductor device along the A1A2 section line after a sacrificial oxide layer is formed in the method for preparing the semiconductor device provided in the first embodiment of the present invention.

11 is a schematic cross-sectional view of the semiconductor device along the B1B2 cross-sectional line after a sacrificial oxide layer is formed in the method for preparing the semiconductor device provided in the first embodiment of the present invention.

12 is a schematic cross-sectional view of the semiconductor device along the A1A2 cross-sectional line after a patterned photoresist layer is formed in the method for preparing the semiconductor device provided in the first embodiment of the present invention.

13 is a schematic cross-sectional view of the semiconductor device along the B1B2 cross-sectional line after a patterned photoresist layer is formed in the method for preparing the semiconductor device provided in the first embodiment of the present invention.

14 is a schematic cross-sectional view of the semiconductor device along the A1A2 section line after a portion of the sacrificial oxide layer is etched away in the method for preparing the semiconductor device provided in the first embodiment of the present invention.

15 is a schematic cross-sectional view of the semiconductor device along the B1B2 cross-sectional line after a portion of the sacrificial oxide layer is etched away in the method for preparing the semiconductor device provided in the first embodiment of the present invention.

16 is a schematic cross-sectional view of the semiconductor device along the A1A2 cross-sectional line after a portion of the pad nitride layer is etched away in the method for preparing the semiconductor device provided in the first embodiment of the present invention.

17 is a schematic cross-sectional view of the semiconductor device along the B1B2 cross-sectional line after a portion of the pad nitride layer is etched away in the method for preparing the semiconductor device provided in the first embodiment of the present invention.

18 is a schematic cross-sectional view of the semiconductor device along the A1A2 section line after the remaining sacrificial oxide layer and a portion of the pad oxide layer are etched away in the method for preparing the semiconductor device provided in the first embodiment of the present invention.

19 is a schematic cross-sectional view of the semiconductor device along the B1B2 cross-sectional line after the remaining sacrificial oxide layer and a portion of the pad oxide layer are etched away in the method for preparing the semiconductor device provided in the first embodiment of the present invention.

20 is a schematic cross-sectional view of the semiconductor device along the A1A2 cross-sectional line after a gate oxide layer is formed in the method for preparing the semiconductor device provided in the first embodiment of the present invention.

21 is a schematic cross-sectional view of the semiconductor device along the B1B2 cross-sectional line after a gate oxide layer is formed in the method for preparing the semiconductor device provided in the first embodiment of the present invention.

FIG. 22 is a schematic cross-sectional view of the semiconductor device along the A1A2 section line provided in the second embodiment of the present invention.

Wherein, the accompanying drawings are marked as follows:

10a-fin structure area; 10b-deep trench area; 11-buried oxide layer; 12-fin structure; 13-deep trench capacitor; 131-trench portion; 132-fin portion; 14-recess; 21-pad oxide layer; 22-pad nitride layer; 30-isolation oxide layer; 40-sacrificial oxide layer; 50-patterned photoresist layer; 60-gate structure; 61-gate oxide layer; 62-gate polysilicon layer; 71-first mask layer; 72-second mask layer; 80-side wall.

DETAILED DESCRIPTION

In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

Embodiment 1

FIG. 1 is a top view of a fin structure and a deep trench capacitor in a semiconductor device provided in this embodiment; FIG. 2 is a cross-sectional schematic diagram of a semiconductor device provided in this embodiment along the A1A2 cross-sectional line; FIG. 3 is a cross-sectional schematic diagram of a semiconductor device provided in this embodiment along the B1B2 cross-sectional line, and FIG. 2 and FIG. 3 are cross-sectional schematic diagrams along the A1A2 cross-sectional line and along the B1B2 cross-sectional line in FIG. 1, respectively. Referring to FIG. 1 to FIG. 3, this embodiment provides a semiconductor device, including a substrate, an isolation oxide layer 30, and a gate structure 60, wherein the substrate includes adjacent fin structure regions 10a and deep trench regions 10b, the fin structure regions 10a and the deep trench regions 10b both include a buried oxide layer 11, the fin structure region 10a also includes a fin structure 12 located on the buried oxide layer 11, and the deep trench region 10b also includes a plurality of deep trench capacitors 13 penetrating the buried oxide layer 11; the substrate is preferably an SOI substrate, and the substrate may further include a doped substrate layer (not shown in the figure), the buried oxide layer 11 is located on the doped substrate layer, and the deep trench capacitor 13 extends into the doped substrate layer. In this embodiment, the material of the substrate is preferably silicon, the material of the buried oxide layer 11 is preferably silicon oxide, and the material of the fin structure 12 is preferably silicon, but the present invention is not limited thereto.

The deep trench capacitor 13 includes a trench portion 131 and a fin portion 132 located on the trench portion 131. The top of the trench portion 131 is lower than the top of the buried oxide layer 11, and the top of the fin portion 132 is higher than the top of the buried oxide layer 11. The top of the fin portion 132 may be flush with the top of the fin structure 12 or higher than the top of the fin structure 12. The width of the fin portion 132 is smaller than the width of the trench portion 131 (the width is the lateral dimension in the figure), and there is a groove 14 between the fin portion 132 and the buried oxide layer 11. The trench portion 131 includes a doped polysilicon layer, and may also include a dielectric layer and a barrier layer. The barrier layer and the dielectric layer are sequentially stacked on the bottom and sidewalls of the doped polysilicon layer. The fin portion 132 includes a doped polysilicon layer. Along the A1A2 direction, the fin structure 12 and the deep trench capacitor 13 are adjacent; along the B1B2 direction, there is a gap between the fin structure 12 and the deep trench capacitor 13.

Furthermore, it also includes a pad oxide layer 21 and a pad nitride layer 22, which are stacked in sequence to cover the bottom and side walls of the groove 14, and extend to cover the side walls and part of the top of the fin 132 and part of the surface of the buried oxide layer 11; the material of the pad oxide layer 21 is preferably silicon oxide, and the material of the pad nitride layer 22 is preferably silicon nitride, but is not limited to this.

The isolation oxide layer 30 is located on the groove portion 131 and fills the groove 14 and covers the sidewall of the fin 132. Due to the presence of the pad oxide layer 21 and the pad nitride layer 22, the isolation oxide layer 30 is in contact with the pad nitride layer 22 in the groove 14, and the top of the isolation oxide layer 30 can be flush with the top of the fin 132 or higher than the top of the fin 132. In this embodiment, the material of the isolation oxide layer 30 is preferably silicon oxide, and the isolation oxide layer 30 also extends to the buried oxide layer 11 of the deep trench region 10b (along the A1A2 direction), and the width S1 of the isolation oxide layer 30 extending to the buried oxide layer 11 of the deep trench region 10b is greater than 2nm and less than 10nm, and is not limited to this range; the isolation oxide layer 30 also extends to the buried oxide layer 11 of the deep trench region 10b to increase the isolation performance between the gate structure 60 and the fin 132.

The gate structure 60 is located on part of the deep trench capacitor 13, part of the isolation oxide layer 30, part of the buried oxide layer 11 and part of the fin structure 12; specifically, along the A1A2 direction, the gate structure 60 is located on the deep trench capacitor 13, the isolation oxide layer 30 and part of the fin structure 12, and along the B1B2 direction, the gate structure 60 is located on the buried oxide layer 11 and the fin structure 12. Since the gate structure 60 is located on the deep trench capacitor 13 along the A1A2 direction, the gate structure 60 will also be located on the isolation oxide layer 30 that contacts the corresponding deep trench capacitor 13. The isolation oxide layer 30 is set to fill the groove 14 and cover the side wall of the fin 132, which increases the distance between the gate structure 60 and the side wall of the fin 132, reduces the possibility of a leakage path formed between the gate structure 60 and the fin 132, and thus reduces the possibility of device leakage. The isolation oxide layer 30 also extends to the buried oxide layer 11 of the deep trench area 10b, further increasing the isolation performance between the gate structure 60 and the fin 132. Generally, the gate structure 60 will partially extend to the side wall of the fin 132, and the gate structure 60 will directly contact the pad nitride layer 22 of the side wall of the fin 132, which may form a leakage path between the gate structure 60 and the fin 132.

Furthermore, the gate structure 60 includes a gate oxide layer 61 and a gate polysilicon layer 62, wherein the gate oxide layer 61 is located on a portion of the deep trench capacitor 13, a portion of the isolation oxide layer 30, a portion of the buried oxide layer 11 and a portion of the fin structure 12, and the gate polysilicon layer 62 is located on a portion of the gate oxide layer 61; the material of the gate oxide layer 61 is preferably silicon oxide, and the material of the gate polysilicon layer 62 is preferably doped polysilicon. In this embodiment, the gate polysilicon layer 62 located on the deep trench capacitor 13 is vertically aligned with the sidewall of the trench portion 131 away from the sidewall of the fin structure 12 (see FIG. 2 , the vertical direction is the longitudinal direction in FIG. 2 ).

Furthermore, it also includes a first mask layer 71, a second mask layer 72 and a side wall 80, wherein the first mask layer 71 and the second mask layer 72 are stacked in sequence on the gate structure 60, and the side wall 80 is located on the gate oxide layer 61 and covers the side wall of the gate polysilicon layer 62 and part of the side wall of the first mask layer 71; the material of the first mask layer 71 is preferably silicon nitride, the material of the second mask layer 72 is preferably silicon oxide, and the material of the side wall 80 is preferably at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride, but is not limited to the above materials.

Furthermore, a portion of the top surface of the deep trench capacitor 13 (fin 132) below the gate structure 60 close to the fin structure 12 is exposed (see FIG. 2 ), and a width S2 of a portion of the top surface of the deep trench capacitor 13 (fin 132) below the gate structure 60 close to the fin structure 12 is exposed that is greater than 5 nm and less than 10 nm, but is not limited thereto.

In the present embodiment, an isolation oxide layer 30 is provided to fill the groove 14 and cover the side wall of the fin 132, so as to better isolate the gate structure 60 and the side wall of the fin 132, increase the isolation performance of the device, reduce the possibility of device leakage, and thus ensure the electrical performance of the device; and can avoid the problem of depression in the isolation oxide layer 30 in the deep groove area 10b, which affects the quality of the isolation oxide layer 30 and reduces the risk of device short circuit.

This embodiment further provides a method for preparing a semiconductor device, which is used to prepare the above-mentioned semiconductor device, comprising:

Step S1: providing a substrate, the substrate comprising adjacent fin structure regions and deep trench regions, the fin structure regions and the deep trench regions both comprising a buried oxide layer, the fin structure region further comprising a fin structure located on the buried oxide layer, the deep trench region further comprising a plurality of deep trench capacitors penetrating the buried oxide layer, the deep trench capacitors comprising a trench portion and a fin portion located on the trench portion, the top of the trench portion being lower than the top of the buried oxide layer, the top of the fin portion being higher than the top of the fin structure, and a groove being provided between the fin portion and the buried oxide layer;

Step S2: forming an isolation oxide layer on the trench portion and filling the groove and covering the sidewall of the fin portion;

Step S3: forming a gate structure on a portion of the deep trench capacitor, a portion of the isolation oxide layer, a portion of the buried oxide layer and a portion of the fin structure.

4 to 21 are cross-sectional schematic diagrams of corresponding steps in the method for preparing a semiconductor device provided in this embodiment, and FIGS. 4 to 21 are cross-sectional schematic diagrams along the A1A2 section line and along the B1B2 section line in FIG. 1. The method for preparing a semiconductor device provided in this embodiment is described in detail below in conjunction with FIGS. 4 to 21.

Please refer to Figures 4 and 5, and perform step S1: provide a substrate, the substrate includes adjacent fin structure regions 10a and deep trench regions 10b, the fin structure regions 10a and the deep trench regions 10b both include a buried oxide layer 11, the fin structure region 10a also includes a fin structure 12 located on the buried oxide layer 11, and the deep trench region 10b also includes a number of deep trench capacitors 13 penetrating the buried oxide layer 11; the substrate is preferably an SOI substrate, and the substrate may further include a doped substrate layer (not shown in the figure), the buried oxide layer 11 is located on the doped substrate layer, and the deep trench capacitors 13 extend into the doped substrate layer.

The deep trench capacitor 13 includes a trench portion 131 and a fin portion 132 located on the trench portion 131. The top of the trench portion 131 is lower than the top of the buried oxide layer 11, and the top of the fin portion 132 is higher than the top of the buried oxide layer 11. The top of the fin portion 132 may be flush with the top of the fin structure 12 or higher than the top of the fin structure 12. The width of the fin portion 132 is smaller than the width of the trench portion 131 (the width is the lateral dimension in the figure), and there is a groove 14 between the fin portion 132 and the buried oxide layer 11. The trench portion 131 includes a doped polysilicon layer, and may also include a dielectric layer and a barrier layer. The barrier layer and the dielectric layer are sequentially stacked on the bottom and sidewalls of the doped polysilicon layer. The fin portion 132 includes a doped polysilicon layer. Along the A1A2 direction, the fin structure 12 and the deep trench capacitor 13 are adjacent; along the B1B2 direction, there is a gap between the fin structure 12 and the deep trench capacitor 13.

Furthermore, a pad oxide layer 21 and a pad nitride layer 22 are stacked in sequence to cover the fin structure 12 , the buried oxide layer 11 and the deep trench capacitor 13 (including the bottom and sidewalls of the groove 14 ); the materials of the above structures are as described above.

Execute step S2: The step of forming an isolation oxide layer includes: please refer to Figures 6 and 7, and use a deposition process to form an isolation oxide layer 30 to fill the groove 14 and cover the side wall and top of the fin 132 and extend to cover the fin structure 12 and the buried oxide layer 11. Due to the presence of the pad oxide layer 21 and the pad nitride layer 22, an isolation oxide layer 30 is formed to cover the pad nitride layer 22. The thickness of the isolation oxide layer 30 is preferably greater than 35nm and less than 70nm, but is not limited to this; the material of the isolation oxide layer 30 is as described above. Please refer to Figures 8 and 9. The isolation oxide layer 30 on the fin structure 12, the isolation buried oxide layer 30 on the top of the fin 132, and part of the isolation oxide layer 30 on the buried oxide layer 11 are etched and removed by a dry etching process. The etched isolation oxide layer 30 is located on the groove portion 131 and fills the groove 14 and covers the side wall of the fin 132. The isolation oxide layer 30 is in contact with the pad nitride layer 22 in the groove 14. The top of the isolation oxide layer 30 can be flush with the top of the fin 132 or higher than the top of the fin 132; and the isolation oxide layer 30 also extends to the buried oxide layer 11 of the deep groove area 10b (along the A1A2 direction), and the width S1 of the isolation oxide layer 30 extending to the buried oxide layer 11 of the deep groove area 10b is greater than 2nm and less than 10nm, but is not limited to this range; and part of the isolation oxide layer 30 on the side wall of the fin structure 12 is retained (see Figure 9).

Further, please refer to FIG. 10 and FIG. 11 , after etching the isolation oxide layer 30 , a sacrificial oxide layer 40 is formed to cover the isolation oxide layer 30 and the pad nitride layer 22 . The material of the sacrificial oxide layer 40 is preferably silicon oxide, but is not limited thereto.

12 and 13 , after etching the sacrificial oxide layer 40 , a patterned photoresist layer 50 is formed to cover the deep trench region 10 b and a portion of the fin structure region 10 a adjacent to the deep trench region 10 b along the A1A2 direction (see FIG. 12 ).

14 and 15 , using the patterned photoresist layer as a mask, a portion of the sacrificial oxide layer 40 and the isolation oxide layer 30 on the sidewall of the fin structure 12 are etched away to expose a portion of the pad nitride layer 22 ; thereafter, the patterned photoresist layer is removed.

Please refer to Figures 16 and 17. Using the sacrificial oxide layer 40 as a mask, the exposed pad nitride layer 22 is etched away to expose a portion of the pad oxide layer 21. After etching, the sacrificial oxide layer 40 and the pad nitride layer 22 extend along the A1A2 direction to a portion of the fin structure 12 in the fin structure area 10a adjacent to the deep trench area 10b. The extension width S3 is 2nm~10nm, but is not limited to this.

18 and 19 , the exposed pad oxide layer 21 is removed by etching to expose the fin structure 12 , the isolation oxide layer 30 , a portion of the buried oxide layer 11 and a portion of the pad nitride layer 22 .

Execute step S3: The step of forming a gate structure includes: please refer to Figures 20 and 21, forming a gate oxide layer 61 to cover the fin structure 12, the isolation oxide layer 30, a portion of the buried oxide layer 11 and a portion of the pad nitride layer 22; please continue to refer to Figures 2 and 3, and sequentially form a gate polysilicon layer 62, a first mask layer 71 and a second mask layer 72 located on the gate oxide layer 61, and then sequentially etch the second mask layer 72, the first mask layer 71 and the gate polysilicon layer 62 to form a gate structure 60, and the specific description of the gate structure 60 is as described above; further, forming a side wall 80 located on the gate oxide layer 61 and covering the side wall of the gate polysilicon layer 62 and a portion of the side wall of the first mask layer 71, and the material of the above structure is as described above.

Embodiment 2

FIG22 is a schematic cross-sectional view of the semiconductor device provided in this embodiment along the A1A2 section line, and FIG22 is a schematic cross-sectional view along the A1A2 section line in FIG1 . Referring to FIG22 , the difference between this embodiment and the first embodiment is that: the gate polysilicon layer 62 located on the deep trench capacitor 13 completely covers the isolation oxide layer 30, that is, the sidewall of the gate polysilicon layer 62 located on the deep trench capacitor 13 along the A1A2 direction away from the fin structure 12 is vertically aligned with the sidewall extending from the isolation oxide layer 30 to the buried oxide layer 11 (see the vertical dotted line in FIG22 ), and the other structures are the same as the first embodiment; and in terms of the preparation method, except for the different pattern of etching to form the gate polysilicon layer 62 in step S3, the other preparation methods are the same as the first embodiment.

In summary, the semiconductor device and its preparation method provided by the present invention include: a substrate, an isolation oxide layer and a gate structure, wherein the substrate includes adjacent fin structure regions and deep trench regions, the fin structure regions and the deep trench regions both include a buried oxide layer, the fin structure region also includes a fin structure located on the buried oxide layer, the deep trench region also includes a number of deep trench capacitors penetrating the buried oxide layer, the deep trench capacitor includes a trench portion and a fin portion located on the trench portion, the top of the trench portion is lower than the top of the buried oxide layer, the top of the fin portion is higher than the top of the buried oxide layer, and there is a groove between the fin portion and the buried oxide layer; the isolation oxide layer is located on the trench portion and fills the groove and covers the sidewall of the fin portion; the gate structure is located on part of the deep trench capacitor, part of the isolation oxide layer, part of the buried oxide layer and part of the fin structure. In the present invention, an isolation oxide layer is provided to fill the groove and cover the sidewall of the fin portion, which can better isolate the gate structure and the sidewall of the fin portion, increase the isolation performance of the device, reduce the possibility of device leakage, and thus improve the electrical performance of the device; and can avoid the problem of depression in the isolation oxide layer in the deep trench region, reducing the risk of device short circuit.

The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims (10)

1. A semiconductor device, comprising:

The substrate comprises a fin structure area and a deep trench area which are adjacent to each other, wherein the fin structure area and the deep trench area both comprise a buried oxide layer, the fin structure area further comprises a fin structure positioned on the buried oxide layer, the deep trench area further comprises a plurality of deep trench capacitors penetrating through the buried oxide layer, each deep trench capacitor comprises a trench portion and a fin portion positioned on the trench portion, the top of each trench portion is lower than the top of the buried oxide layer, the top of each fin portion is higher than the top of the fin structure, and a groove is formed between each fin portion and the buried oxide layer;

The isolation oxide layer is positioned on the groove part, fills the groove and covers the side wall of the fin part, and the top of the isolation oxide layer is flush with or higher than the top of the fin part;

And the grid structure is positioned on part of the deep trench capacitor, part of the isolation oxide layer, part of the buried oxide layer and part of the fin structure, and is positioned on the isolation oxide layer contacted with the deep trench capacitor along the first direction.

2. The semiconductor device of claim 1, wherein the isolation oxide layer further extends onto a buried oxide layer of the deep trench region.

3. The semiconductor device of claim 2, wherein a width of the isolation oxide layer extending onto the buried oxide layer of the deep trench region is greater than 2nm and less than 10nm.

4. The semiconductor device of claim 2, wherein the gate structure comprises a gate polysilicon layer located on the deep trench capacitor in vertical alignment with sidewalls of the trench portion away from sidewalls of the fin structure.

5. The semiconductor device of claim 2, wherein the gate structure comprises a gate polysilicon layer overlying the deep trench capacitor covering the isolation oxide layer.

6. The semiconductor device of claim 1, wherein a portion of the deep trench capacitor under the gate structure is exposed proximate to a top surface of the fin structure.

7. The semiconductor device of claim 6, wherein a portion of the deep trench capacitor under the gate structure proximate a top surface of the fin structure is exposed to a width greater than 5nm and less than 10nm.

8. A method of manufacturing a semiconductor device, comprising:

Providing a substrate, wherein the substrate comprises a fin structure area and a deep trench area which are adjacent, the fin structure area and the deep trench area both comprise a buried oxide layer, the fin structure area further comprises a fin structure positioned on the buried oxide layer, the deep trench area further comprises a plurality of deep trench capacitors penetrating through the buried oxide layer, the deep trench capacitors comprise trench parts and fin parts positioned on the trench parts, the tops of the trench parts are lower than the tops of the buried oxide layer, the tops of the fin parts are higher than the tops of the fin structure, and grooves are formed between the fin parts and the buried oxide layer;

Forming an isolation oxide layer which is positioned on the groove part, fills the groove and covers the side wall of the fin part, wherein the top of the isolation oxide layer is flush with or higher than the top of the fin part;

Forming a gate structure on a part of the deep trench capacitor, a part of the isolation oxide layer, a part of the buried oxide layer and a part of the fin structure, wherein the gate structure is positioned on the isolation oxide layer contacted with the deep trench capacitor along a first direction.

9. The method of manufacturing a semiconductor device according to claim 8, wherein the step of forming the isolation oxide layer comprises:

forming the isolation oxide layer by adopting a deposition process to fill the groove, cover the side wall and the top of the fin part and extend to cover the fin structure and the oxygen burying layer;

and etching and removing the isolation oxide layer on the fin structure, the isolation buried oxide layer on the top of the fin part and part of the isolation oxide layer on the buried oxide layer by adopting a dry etching process, wherein after etching, the isolation oxide layer is positioned on the groove part, fills the groove and covers the side wall of the fin part, and the isolation oxide layer also extends to the buried oxide layer of the deep groove region.

10. The method of manufacturing a semiconductor device according to claim 9, wherein a thickness of the isolation oxide layer is greater than 35nm and less than 70nm.