CN118315422B - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The invention relates to a semiconductor device and a preparation method thereof, wherein the semiconductor device comprises a functional layer, a dielectric layer, an electrode structure, a bonding pad structure and a regulating structure, wherein a first two-dimensional carrier gas is formed in a first functional region of the functional layer; the dielectric layer is formed above the functional layer; the electrode structure comprises a source electrode structure, a drain electrode structure and a grid electrode structure, and the source electrode structure and the drain electrode structure are respectively and electrically connected with the first two-dimensional carrier; the surface of the pad structure is exposed out of the upper surface of the dielectric layer and comprises a source electrode pad, a drain electrode pad and a grid electrode pad respectively; the regulation structure comprises a regulation metal layer formed on the dielectric layer, and the regulation metal layer and the drain electrode structure and/or the drain electrode bonding pad form a first capacitor. The embodiment of the invention realizes the switching speed control of the device, avoids using an external capacitor, and reduces the preparation cost of the device and the complexity of circuit design.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same.

Background Art

III-V nitrides are important semiconductor materials, such as AlN, GaN, InN and compounds of these materials, such as AlGaN, InGaN, AlInGaN, etc. III-V nitrides have the advantages of direct band gap, wide bandgap, high breakdown electric field strength, etc. In recent years, high electron mobility transistors (HEMTs) prepared from III-nitride semiconductors represented by GaN have been widely used in light-emitting devices, power electronics, radio frequency devices and other fields. HEMTs usually include two types: depletion type and enhancement type. For depletion type HEMTs, since they are normally-on devices, they are usually combined with low-voltage enhancement type devices to form a common source and common gate structure (Cascode) device when used. Figure 1 is a schematic diagram of the principle of the Cascode device in the prior art. The Cascode device includes a high-voltage depletion type transistor (such as a depletion type HEMT) Q2 and a low-voltage enhancement type transistor (such as a MOSFET) Q1. When the Cascode device is connected to the application circuit as a power switch, its drain D and source S are connected to the circuit, and the gate G is connected to the drive circuit. When the driving signal received by the gate G of the Cascode device is at a high level, MOSFET Q1 is turned on, and both the HEMT Q2 and MOSFET Q1 in the Cascode device are in the on state, so the entire Cascode device is in a low resistance state and a large current can flow through it. When the driving signal received by the gate G is at a low level, the MOSFET Q1 of the Cascode device is disconnected, the Cascode device is in a high resistance state, and the device can withstand a higher voltage. From the working principle of the aforementioned Cascode device, it can be seen that the switching state of the Cascode device is controlled by MOSFET Q1.

In practical applications, when the dv/dt or di/dt (i.e., switching speed) of a power device is too large, the electromagnetic interference (EMI) of the system will exceed the standard, and the voltage spike stress of the load circuit will exceed the standard and damage the load circuit. Therefore, it is necessary to be able to adjust the switching speed of the power device to meet the requirements. The switching speed of the transistor can generally be achieved by adjusting the charge and discharge time of the drain-gate capacitance Cdg through the gate resistor. However, since the drain-gate capacitance Cdg inside the Cascode device is relatively small, and the gate resistor of the Cascode device can only indirectly control the HEMT, this method is not ideal for adjusting the switching speed.

Summary of the invention

In view of the technical problems existing in the prior art, the present invention provides a semiconductor device and a preparation method thereof, which are used to adjust the switching speed of the device.

According to one aspect of the present invention, the present invention provides a semiconductor device, including a functional layer, a dielectric layer, an electrode structure, a pad structure and a control structure; wherein a first two-dimensional carrier gas is formed in a first functional area in the functional layer; the dielectric layer is formed above the functional layer; the electrode structure is formed in the first functional area, including a source structure, a drain structure and a gate structure, and the source structure and the drain structure are electrically connected to the first two-dimensional carrier gas respectively; the surface of the pad structure exposes the upper surface of the dielectric layer, and includes a source pad, a drain pad and a gate pad respectively, and the source pad, the drain pad and the gate pad are electrically connected to the source structure, the drain structure and the gate structure respectively through dielectric holes to form the source, drain and gate of the device; the control structure includes a control metal layer formed on the dielectric layer, and the control metal layer forms a first capacitor with the drain.

Optionally, the drain pad includes a first area exposed on the upper surface of the dielectric layer and a second area placed inside the dielectric layer in parallel with the first area, and the control metal layer is a control end pad located on the upper surface of the dielectric layer, and the control end pad is located on the upper surface of the dielectric layer above the second area of the drain pad, wherein the control end pad and the second area of the drain pad form the first capacitor.

Optionally, the regulation metal layer includes a regulation end pad located on the upper surface of the dielectric layer and a first metal layer formed inside or on the upper surface of the dielectric layer, and the regulation end pad is electrically connected to the first metal layer through a dielectric hole; when the first metal layer is located inside the dielectric layer, the first metal layer is located a preset distance below the drain pad and/or the first metal layer is located a preset distance above the drain structure; when the first metal layer is located on the upper surface of the dielectric layer, the drain pad includes a first area exposed on the upper surface of the dielectric layer and a second area placed inside the dielectric layer in parallel with the first area, and the first metal layer is located a preset distance above the second area of the drain pad; wherein the first metal layer and the drain pad and/or the drain structure form the first capacitor.

Optionally, a portion of the first metal layer extends to a preset distance above the gate structure and/or a portion of the first metal layer extends to a preset distance below the gate pad, wherein the first metal layer forms a second capacitor with the gate structure and/or the gate pad.

Optionally, a portion of the first metal layer extends to a preset distance above the source structure and/or a portion of the first metal layer extends to a preset distance below the source pad, wherein the first metal layer forms a third capacitor with the source structure and/or the source pad.

Optionally, the semiconductor device also includes a second metal layer, which is electrically connected to the regulating end pad or the first metal layer through a dielectric hole; the second metal layer is located a preset distance above the gate structure and/or the second metal layer is located a preset distance below the gate pad, wherein the second metal layer and the gate structure and/or the gate pad form a second capacitor.

Optionally, the semiconductor device also includes a third metal layer, which is electrically connected to the regulating end pad or the first metal layer through a dielectric hole; the third metal layer is located a preset distance above the source structure and/or the third metal layer is located a preset distance below the source pad, wherein the third metal layer and the source structure and/or the source pad form a third capacitor.

Optionally, the control structure also includes a first strip metal layer formed on the dielectric layer, a first end of which is electrically connected to the first metal layer, and a second end of which is electrically connected to the control end pad, wherein the first strip metal layer constitutes a first resistor with a preset resistance value.

Optionally, there are multiple regulating end pads located on the upper surface of the dielectric layer, and the first strip metal layer includes connection points at different distances from the first end, and each regulating end pad is electrically connected to the corresponding connection point; wherein each connection point is electrically connected to the strip metal layer between the first end of the first strip metal layer to form a first resistor with a preset resistance value.

Optionally, the control structure also includes a first electrode and one or more second electrodes; wherein, the first electrode and the one or more second electrodes are formed in the second functional area of the functional layer, and are ohmically connected to the second two-dimensional carrier gas inside the second functional area, and the first electrode is electrically connected to the first metal layer; when the second electrode is one, it is electrically connected to the control end pad through a dielectric hole, and when the second electrode is multiple, the control end pad is a corresponding multiple, and each second electrode is electrically connected to the corresponding control end pad through a dielectric hole; wherein, the first electrode and each of the second electrodes respectively form a first resistor with a preset resistance through the second two-dimensional carrier.

Optionally, the control structure also includes a diode, wherein a diode anode and a diode cathode are formed in the third functional region of the functional layer, the diode cathode is ohmically connected to the third two-dimensional carrier gas in the third functional region, the diode anode is Schottky connected to the third two-dimensional carrier gas in the third functional region, the diode anode is electrically connected to the control end pad, and the diode cathode is electrically connected to the first metal layer.

Optionally, the semiconductor device further comprises a second strip metal layer formed on the dielectric layer, a first end of which is electrically connected to the first metal layer, and a second end of which is electrically connected to the cathode of the diode, and the second strip metal layer constitutes a second resistor with a preset resistance.

Optionally, the semiconductor device also includes a third electrode and a fourth electrode, wherein the third electrode and the fourth electrode are formed in a fourth functional region of the functional layer and are ohmically connected to a fourth two-dimensional carrier gas inside the fourth functional region, the third electrode is electrically connected to the first metal layer, and the fourth electrode is electrically connected to a cathode of the diode; a second resistor with a preset resistance is formed between the third electrode and the fourth electrode through the fourth two-dimensional carrier.

Optionally, an electrically insulating isolation region is included between the first functional region, the second functional region, the third functional region and the fourth functional region, and a depth of the isolation region is greater than a depth of a region where the two-dimensional carrier gas is located.

Optionally, the functional layer at least includes a channel layer and a barrier layer, and a two-dimensional carrier gas is formed in a region of the channel layer close to the barrier layer; the channel layer and the barrier layer are III-V group compounds.

According to another aspect of the present invention, the present invention also provides a semiconductor device, including a first transistor and a second transistor, wherein the first transistor is the aforementioned semiconductor device, and the second transistor is an enhancement-type silicon-based transistor; the drain of the first transistor serves as the first electrode of the device as a whole, the source of the first transistor is electrically connected to the drain of the second transistor, and the source of the second transistor is the second electrode of the device as a whole; the gate of the first transistor is electrically connected to the source of the second transistor; the control terminal pad of the first transistor is electrically connected to the gate of the second transistor; the gate of the second transistor is the control electrode of the device as a whole, and is used to connect to a drive circuit; wherein, when the semiconductor device is controlled to be turned on or off by the drive circuit, the switching speed of the semiconductor device is adjusted by adjusting the resistance value of the resistor connected to the control terminal pad in the drive circuit.

According to another aspect of the present invention, the present invention also provides a method for preparing a semiconductor device, comprising:

A semiconductor epitaxial wafer is provided as a functional layer, wherein the functional layer at least comprises a channel layer and a barrier layer, wherein a two-dimensional carrier gas is formed in a region of the channel layer close to the barrier layer; and the channel layer and the barrier layer are III-V group compounds;

forming an electrode structure in the first functional region of the functional layer, the electrode structure comprising a source structure, a drain structure and a gate structure, the source structure and the drain structure being electrically connected to the first two-dimensional carrier gas respectively;

Depositing a first dielectric layer of a preset thickness above the electrode structure;

Depositing metal on the first dielectric layer to obtain a first metal layer, wherein the first metal layer is located above the drain structure, or the first metal layer is located above the drain structure and a portion of the first metal layer extends to the gate structure and/or the source structure;

Depositing a second dielectric layer on the first metal layer and on the first dielectric layer not covered with metal;

Etching dielectric holes respectively connected to the source structure, the drain structure, the gate structure and the first metal layer from the second dielectric layer downwards; and

Depositing metal in the dielectric hole and on the upper surface of the second dielectric layer to obtain a pad structure, wherein the pad structure includes a source pad, a drain pad, a gate pad and a control end pad, and the source pad, the drain pad, the gate pad and the control end pad are respectively electrically connected to the source structure, the drain structure, the gate structure and the first metal layer through the dielectric hole to form the source, the drain, the gate and the control structure of the device;

Wherein, the first metal layer and/or the regulating terminal pad and the drain structure and/or the drain pad form a first capacitor.

According to another aspect of the present invention, the present invention also provides a method for preparing a semiconductor device, comprising:

A semiconductor epitaxial wafer is provided as a functional layer, wherein the functional layer at least comprises a channel layer and a barrier layer, wherein a two-dimensional carrier gas is formed in a region of the channel layer close to the barrier layer; and the channel layer and the barrier layer are III-V group compounds;

forming an electrode structure in the first functional region of the functional layer, the electrode structure comprising a source structure, a drain structure and a gate structure, the source structure and the drain structure being electrically connected to the first two-dimensional carrier gas respectively;

Depositing a first dielectric layer of a preset thickness above the electrode structure;

Etching the first dielectric layer to obtain dielectric holes connected to the source structure, the drain structure and the gate structure respectively;

Depositing metal in the dielectric hole and on the upper surface of the first dielectric layer to obtain a pad structure, wherein the pad structure includes a source pad, a drain pad and a gate pad, and the source pad, the drain pad and the gate pad are respectively electrically connected to the source structure, the drain structure and the gate structure through the dielectric hole to form the source, the drain and the gate of the device;

Depositing a second dielectric layer above the pad structure and on the upper surface of the first dielectric layer where no metal is deposited; and

Depositing metal on the upper surface of the second dielectric layer opposite to the second region of the drain pad to obtain a regulating terminal pad; and etching the second dielectric layer to expose the first region of the pad structure not opposite to the regulating terminal pad, the source pad and the gate pad;

Alternatively, a first dielectric hole is obtained by etching downwards to a first depth from the upper surface of the second dielectric layer opposite to the second area of the drain pad, and a second depth is respectively etched downwards from the upper surface of the second dielectric layer opposite to the first area of the drain pad, the source pad and the gate pad until the first area of the drain pad, the source pad and the gate pad are exposed to obtain corresponding multiple second dielectric holes, wherein the first depth is less than the second depth; metal is deposited at least in the first dielectric hole to obtain a regulating end pad; the regulating end pad forms a first capacitor with the second area of the drain pad.

The present invention integrates a capacitor formed with the drain electrode inside the semiconductor device, through which the switching speed of the device can be effectively controlled, and the breakdown voltage of the capacitor matches the breakdown voltage of the device. When applied, there is no need to add an additional external capacitor, which saves materials and avoids malfunctions caused by the mismatch between the external capacitor and the voltage of the device itself, thereby reducing the device cost and the complexity of circuit design.

BRIEF DESCRIPTION OF THE DRAWINGS

The preferred embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, wherein:

FIG1 is a schematic diagram of the principle of a Cascode device in the prior art;

FIG2 is a schematic diagram of the structural principle of a semiconductor device according to an embodiment of the present invention;

3 is an electrical schematic diagram of a semiconductor device according to Embodiment 1 of the present invention;

4 is a schematic diagram of the upper surface structure of a semiconductor device according to Embodiment 1 of the present invention;

FIG5 is a schematic diagram of a partial structure cut along line A-A' in FIG4;

6 is a flow chart of a method for manufacturing a semiconductor device according to Embodiment 1 of the present invention;

7 is an electrical schematic diagram of a cascode device formed by using a semiconductor device according to Embodiment 1 of the present invention;

8 is a schematic diagram of the upper surface structure of a semiconductor device according to Embodiment 2 of the present invention;

FIG9 is a schematic diagram of a portion of the structure cut along line B-B' in FIG8;

10 is a flow chart of a method for manufacturing a semiconductor device according to Embodiment 2 of the present invention;

FIG11 is a schematic diagram of a portion of the structure cut along line B-B' in FIG8;

12 is an electrical schematic diagram of a semiconductor device according to Embodiment 3 of the present invention;

FIG13 is a schematic diagram of a partial structure cut along the line B-B' in FIG8;

14 is an electrical schematic diagram of a semiconductor device according to a fourth embodiment of the present invention;

15 is a schematic diagram of a partially cutaway structure of a semiconductor device according to a fifth embodiment of the present invention;

16 is an electrical schematic diagram of a semiconductor device according to a fifth embodiment of the present invention;

17 is a schematic diagram of a partially cutaway structure of a semiconductor device according to a sixth embodiment of the present invention;

18 is a schematic diagram of the electrical principle of a semiconductor device according to Embodiment 7 of the present invention;

19 is a schematic diagram of the upper surface structure of a semiconductor device according to Embodiment 7 of the present invention;

FIG20 is a schematic diagram of a resistor structure according to an embodiment of the present invention;

21 is a schematic diagram of the top surface structure of another semiconductor device according to Embodiment 7 of the present invention;

22 is a schematic diagram of a partially cutaway structure of a semiconductor device according to an eighth embodiment of the present invention;

23 is a schematic diagram of the electrical principle of a semiconductor device according to Embodiment 9 of the present invention;

FIG24 is a schematic diagram of a partially cutaway structure of a semiconductor device according to a ninth embodiment of the present invention; and

FIG. 25 is a schematic diagram of an electrical principle of a semiconductor device according to a tenth embodiment of the present invention.

DETAILED DESCRIPTION

In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

In the following detailed description, reference may be made to the various specification drawings that are part of the present application and are used to illustrate specific embodiments of the present application. The structures shown in the drawings of the present application are only used to illustrate the principles of the device and do not represent the actual size and/or positional relationship of the actual device. The various specific embodiments of the present application are described in sufficient detail below so that ordinary technicians with relevant knowledge and skills in the field can implement the technical solutions of the present application according to the common sense in the field. It should be understood that under the inspiration of the various specific embodiments of the present application, ordinary technicians in the field can also use other embodiments to make structural, logical or electrical changes to the embodiments of the present application.

FIG2 is a schematic diagram of the structural principle of a semiconductor device according to an embodiment of the present invention. The structure of the semiconductor device includes a functional layer 10, a dielectric layer 20 and an electrode. The functional layer 10 includes a substrate 100 and an epitaxial layer 110. The material of the substrate 100 is, for example, intrinsic GaN or materials such as silicon (Si), silicon carbide (SiC) or sapphire (Al ₂ O ₃ ). When the substrate 100 is a non-intrinsic substrate, a buffer layer may be further introduced to reduce the influence of lattice differences. The buffer layer may be one or more of aluminum nitride (AlN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum indium nitride (AlInN) and aluminum gallium indium nitride (AlGaInN), to reduce the influence of differences in lattice constants and thermal expansion coefficients between the substrate 100 and the epitaxial layer 110, and effectively avoid cracking of the nitride epitaxial layer. The buffer layer is an optional structure, and the buffer layer may be a multilayer structure, in which each layer is composed of different materials. When the substrate used is silicon (Si), a nucleation layer may be introduced between the substrate and the buffer layer to avoid a melt-back effect. When the substrate used is sapphire or silicon carbide, a nucleation layer may also be introduced to improve the quality of the epitaxial layer.

The epitaxial layer 110 includes a channel layer and a barrier layer, wherein the material of the channel layer is, for example, GaN, and the material of the barrier layer is, for example, AlGaN, and the channel layer and the barrier layer constitute a heterojunction, wherein a two-dimensional carrier gas is provided, such as a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG). The material of the channel layer and the barrier layer constituting the heterojunction may also be other III-V semiconductor materials, such as AlN, GaN, InN, and compounds of these materials, such as AlGaN, InGaN, AlInGaN, etc.

Above the epitaxial layer 110 is a passivation layer 200, which can be used as a gate dielectric layer. The material of the passivation layer 200 is, for example, silicon nitride, silicon oxide, hafnium oxide or aluminum oxide. The third dielectric layer 203 can be a single-layer structure or a multi-layer structure, such as silicon nitride near the barrier layer and silicon oxide near the electrode. It is worth noting that the same material prepared by different equipment or the same material prepared by the same equipment with different process parameters can be regarded as different layers if their electrical properties are greatly different. The multi-layer dielectric above the epitaxial layer 110 constitutes the dielectric layer 20, and the materials used include silicon oxide, silicon nitride and aluminum oxide.

In the present invention, in order to distinguish the region of the functional layer used to form other devices such as resistors and diodes, the region of the functional layer used to obtain the active region structure of the semiconductor device (such as HEMT) is referred to as the first functional region, and the two-dimensional carrier gas therein is referred to as the first two-dimensional carrier gas. Different functional regions are insulated by isolation regions. For example, according to the required area size and position, an isolation groove with a depth exceeding the two-dimensional carrier gas is etched on the functional layer, and then a dielectric is filled in the isolation groove to obtain an electrically insulating isolation region, or an electrically insulating isolation region can be obtained by injecting insulating ions from the top layer downward.

An electrode structure is formed in the first functional area, such as a source structure 31 , a drain structure 32 and a gate structure 33 in the figure. The source structure 31 and the drain structure 32 are electrically connected to the first two-dimensional carrier gas 111 , respectively.

The semiconductor device also includes a pad structure 40 for wire bonding. The upper surface of the pad structure 40 and the upper surface of the dielectric layer 20 may be basically on the same plane, or may not be on the same plane. And the upper surface of the pad structure 40 and the upper surface of the dielectric layer 20 may also be uneven surfaces. The dielectric layer 20 may partially cover the upper surface of the pad structure 40, as long as there is enough space on the upper surface of the pad structure 40 to form an electrical connection with the outside. The pad structure 40 includes a source pad 41, a drain pad 42, and a gate pad 43. The source pad 41, the drain pad 42, and the gate pad 43 are respectively electrically connected to the source structure 31, the drain structure 32, and the gate structure 33 through the dielectric hole to form the source S, the drain D, and the gate G of the device. In order to show the connection relationship between the pad structure and the electrode structure, FIG. 2 shows the pad structure 40 and the electrode structure 30 at the same time. However, it should be noted that FIG. 2 is only a schematic diagram and does not represent the actual positional relationship. According to the wiring requirements of the device, the position and number of the pads on the device surface are determined according to the requirements, and there can usually be multiple pads of the same type. The electrode structure shown in the figure is the electrode structure of a cell. There will be multiple cells of the same structure inside the actual device. The same electrode structures of multiple cells are electrically connected to the same pads on the surface through dielectric holes. The following description is the same and will not be repeated.

Embodiment 1

Fig. 3 is an electrical schematic diagram of a semiconductor device according to Embodiment 1 of the present invention. The integrated control structure in the internal structure of the semiconductor device in this embodiment constitutes a first capacitor C1, one end of the first capacitor C1 is a drain electrode D, and the other end is a control terminal C, which is used to be electrically connected to other components when used.

FIG4 is a schematic diagram of the upper surface structure of a semiconductor device according to an embodiment of the present invention. The control structure in the embodiment of the present invention is composed of a metal pad, that is, the control terminal pad 51 exposed on the upper surface of the dielectric layer 20 in FIG4, which is an embodiment of the control metal layer. FIG5 is a schematic diagram of a partial structure after being cut along the A-A' line in FIG4. In this embodiment, the drain pad 42 includes a first area A1 exposed on the upper surface of the dielectric layer 20 and a second area A2 placed inside the dielectric layer 20 in parallel therewith, and the control terminal pad 51 is located at a preset distance above the second area A2, and a dielectric is filled between the control terminal pad 51 and the second area A2 of the drain pad. Among them, by setting the relative area of the second area A2 of the drain pad and the control terminal pad 51 and the distance between the two and the type of the dielectric, a first capacitor C1 with a corresponding capacitance can be obtained. In one embodiment, the capacitance of the first capacitor C1 formed by the second area A2 of the drain pad and the control terminal pad 51 is between 0.1-100pF.

FIG6 is a flow chart of a method for preparing a semiconductor device according to Embodiment 1 of the present invention. In this embodiment, the method comprises the following steps:

Step S11, providing a semiconductor epitaxial wafer as a functional layer of a semiconductor device. Referring to FIG. 2, in this embodiment, first, an epitaxial channel layer and a barrier layer are sequentially epitaxially grown on the surface of a substrate 100 using an epitaxial process to obtain an epitaxial layer 110. In addition, before the epitaxial channel layer and the barrier layer are formed, one or more layers of aluminum nitride (AlN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum indium nitride (AlInN) and aluminum gallium indium nitride (AlGaInN) may be deposited on the surface of the substrate 100 as a buffer layer to reduce the influence of differences in lattice constant and thermal expansion coefficient between the substrate 100 and the epitaxial layer 110. Preferably, a nucleation layer may be deposited on the surface of the substrate 100 first, and then a buffer layer and an epitaxial layer 110 may be deposited in sequence. In addition, a passivation layer 200 may be deposited on the upper surface of the epitaxial layer 110 to serve as a gate dielectric layer.

Step S12, forming an electrode structure in the first functional area of the semiconductor epitaxial wafer. In combination with the structure shown in FIG2 , the specific steps of forming the electrode structure include, for example: first, depositing a third dielectric layer 203 on the passivation layer 200 of the current semiconductor epitaxial wafer; then etching the third dielectric layer 203 in the region for forming the electrode to obtain a dielectric hole for generating the drain structure 32 and the source structure 31; then depositing metal in the dielectric hole, and then performing an annealing process to form an ohmic contact between the metal and the epitaxial layer 110, so that the obtained drain structure 32 and the source structure 31 can be electrically connected to the two-dimensional carrier gas in the epitaxial layer 110; then etching the third dielectric layer 203 in the region for forming the gate to obtain a dielectric hole for generating the gate structure 33, wherein the sidewall of the dielectric hole may have multiple steps, and then depositing the gate metal in the dielectric hole, so as to obtain the gate structure 33 with a field plate.

Step S13, depositing a first dielectric layer 201 with a preset thickness on the electrode structure.

Step S14: etching the first dielectric layer 201 to obtain a plurality of dielectric holes connected to various electrode structures.

Step S15, depositing metal on the upper surface of the first dielectric layer 201 and in the dielectric holes to obtain a pad structure 40, wherein the pad structure includes a source pad 41, a drain pad 42 and a gate pad 43, respectively. The source pad 41, the drain pad 42 and the gate pad 43 are respectively electrically connected to the source structure 31, the drain structure 32 and the gate structure 33 through the dielectric holes to form the source S, the drain D and the gate G of the device, that is, the structure shown in FIG. 2 is obtained.

Step S16, depositing a second dielectric layer 202 of a preset thickness above the pad structure 40 and on the upper surface of the first dielectric layer 201 where no metal is deposited.

Step S171, depositing metal on the upper surface of the second dielectric layer 202 opposite to the second area A2 of the drain pad 42 below the second dielectric layer 202 to obtain a regulating terminal pad 51.

Step S181, etching the second dielectric layer 202 to expose the first area A1 of the pad structure that is not opposite to the regulating end pad 51, and to expose the source pad 41 and the gate pad 43.

Alternatively, in step S172, the second dielectric layer 202 is etched to obtain a plurality of dielectric holes, wherein the second dielectric layer 202 is etched downward to a first depth in an area opposite to the second area A2 of the drain pad 42 to obtain a shallower first dielectric hole, and the second dielectric layer 202 is etched downward to a area opposite to the first area A1 of the drain pad 42 and the source pad 41 and the gate pad 43 until the pad metal is reached to obtain a second dielectric hole, and the etching depth is a second depth, which is greater than the first depth, thereby exposing the first area A1 of the drain pad 42 and the source pad 41 and the gate pad 43.

Step S182, depositing metal in multiple dielectric holes of the current second dielectric layer 202, wherein the metal in the first dielectric hole above the second area A2 of the drain pad 42 constitutes the regulating terminal pad 51, and the metal in other second dielectric holes thickens the current pads, thereby obtaining a flat device surface.

FIG7 is an electrical schematic diagram of a Cascode device formed by using the semiconductor device of the first embodiment of the present invention. In this embodiment, when the semiconductor device in this embodiment is used as a cascode device cascaded with HEMT Q2 and MOSFET Q1, when the device is packaged, the control terminal C in FIG3 (corresponding to the control terminal pad 51 in FIG4 and FIG5) is electrically connected to the gate of MOSFET Q1 by wire bonding, thereby increasing the drain-gate capacitance Cdg in the Cascode device. When combined with the gate resistance of the driving circuit, the switching speed of the Cascode device can be effectively adjusted, and there is no need to add an additional external capacitor, nor to consider the voltage matching problem between the external capacitor and the HEMT Q2, which saves materials, reduces the preparation process of the device, and avoids failures caused by the mismatch between the external capacitor and the voltage of the device itself.

Embodiment 2

FIG8 is a schematic diagram of the upper surface structure of a semiconductor device according to Embodiment 2 of the present invention. FIG9 is a schematic diagram of a portion of the structure after being cut along the B-B' line in FIG8. In this embodiment, the regulating metal layer of the regulating structure includes a regulating end pad 51 exposed on the upper surface of the dielectric layer 20 and a first metal layer 52 formed inside the dielectric layer, and the regulating end pad 51 is electrically connected to the first metal layer 52 through a dielectric hole. In this embodiment, the first metal layer 52 is located at a preset distance below the drain pad 42, and the area directly facing the two forms a first capacitor C1. The first metal layer 52 can also be located at a preset distance above the drain structure 32 in the dielectric layer 20, and the area directly facing the first metal layer 52 and the drain structure 32 forms a first capacitor C1. When the first metal layer 52 is located both above the drain structure 32 and below the drain pad 42 in the dielectric layer 20, the first capacitor C1 is composed of two capacitors. The electrical schematic diagram of the semiconductor device obtained based on this structure is shown in FIG3. It should be noted that, in the present embodiment, most of the capacitance of the first capacitor C1 is provided by the capacitors formed by the aforementioned structures. However, it can be known that even if the first metal layer 52 does not form a directly opposite relationship with the drain structure 32 or the drain pad 42, a capacitor with very small capacitance will be formed. Therefore, the actual capacitance of the first capacitor C1 in the present invention is the total capacitance of all capacitors. However, since the capacitance of the first metal layer 52 is very small when it does not form a directly opposite relationship with the drain structure 32 or the drain pad 42, when describing the composition of the first capacitor C1, the present invention only describes the structure that provides the main capacitance, and other structures are ignored and no longer described.

FIG10 is a flow chart of a method for preparing a semiconductor device according to a second embodiment of the present invention. In this embodiment, steps S21 to S23 are the same as steps S11 to S13 in the method shown in FIG6 , and are not described in detail here. In this embodiment, the method includes, after step S23:

Step S24: depositing metal on the first dielectric layer 201 to obtain a first metal layer 52.

Step S25: depositing a second dielectric layer 202 on the first metal layer 52 and on the first dielectric layer 201 not covered with metal.

Step S26, etching dielectric holes downward from the second dielectric layer 202, including dielectric holes respectively connected to the source structure 31, the drain structure 32, the gate structure 33 and the first metal layer 52.

Step S27, depositing metal in the dielectric hole and on the upper surface of the second dielectric layer 202 to obtain a pad structure, the pad structure respectively includes a source pad 41, a drain pad 42, a gate pad 43 and a control terminal pad 51, the source pad 41, the drain pad 42, the gate pad 43 and the control terminal pad 51 are respectively electrically connected to the source structure 31, the drain structure 32, the gate structure 33 and the first metal layer 52 through the dielectric hole to form the source S, drain D, gate G and control structure of the device. See Figures 8 and 9, wherein, in order to facilitate the illustration of the position of the first metal layer 52, the dielectric hole is not shown in Figure 9. In this embodiment, the first metal layer 52 is located below the drain pad 43. Of course, the position of the first metal layer 52 on the first dielectric layer 201 can also be controlled so that the first metal layer 52 is opposite to the drain structure 33, or is opposite to the drain structure 33 and the drain pad 43 at the same time. One end of the first capacitor C1 formed by the first metal layer 52 and the drain is the drain D, and the other end is the first metal layer 52. The metal layer 52 is electrically connected to the first regulating end pad 51 to form an equipotential, so that the non-drain end of the first capacitor C1 is brought to the surface, thereby facilitating electrical connection with other components.

Embodiment 3

The upper surface structural schematic diagram of the semiconductor device of the third embodiment is the same as FIG8, and FIG11 is a partial structural schematic diagram after being cut along the B-B' line in FIG8. In the present embodiment, the first metal layer 52 is formed inside the dielectric layer 20, located at a preset distance below the drain pad 42, and a part of its area extends to a preset distance above the gate structure 33. Therefore, the first metal layer 52 forms a first capacitor C1 with the drain pad 42 above it, and the first metal layer 52 forms a second capacitor C2 with the gate structure 33 below it, and the first metal layer 52 is electrically connected to the regulating end pad 51 through the dielectric hole to form an equipotential. FIG12 is an electrical schematic diagram of a semiconductor device according to the third embodiment of the present invention. In the present embodiment, one end of the first capacitor C1 and one end of the second capacitor C2 are electrically connected to the regulating end C, the other end of the first capacitor C1 is the drain D, and the other end of the second capacitor C2 is the gate G. The corresponding capacitance can be obtained by adjusting the distance and relative area between the first metal layer 52 and the gate structure 33. Among them, the size of the second capacitor C2 is 0.1-1000pF. In this embodiment, a first metal layer 52 is inserted between the drain D and the gate G of the device, which reduces the relative area between the gate structure 33 and the drain pad 42, thereby reducing the drain-gate capacitance Cdg of the device itself, thereby reducing the switching loss of the device.

In another solution, by setting the position of the first metal layer 52 in the dielectric layer 20 , a portion of the first metal layer 52 can be extended to a preset distance below the gate pad 43 , thereby reducing the drain-gate capacitance Cdg of the device itself.

In this embodiment, when the semiconductor device in this embodiment is used as a cascode device cascaded with HEMT Q2 and MOSFET Q1, when the device is packaged, the control terminal C in FIG. 12 (corresponding to the control terminal pad 51 in FIG. 8 ) is electrically connected to the gate of MOSFET Q1 by wire bonding, so that the drain-gate capacitance Cdg is added to the cascode device, and when it cooperates with the gate resistance of the driving circuit, the switching speed of the cascode device can be effectively adjusted. In addition, the drain-gate capacitance Cdg of the HEMT Q2 itself in this embodiment is small, thereby further reducing the switching loss of the device.

Embodiment 4

The upper surface structural schematic diagram of the semiconductor device of the fourth embodiment is the same as FIG8, and FIG13 is a partial structural schematic diagram after being cut along the B-B' line in FIG8. In the present embodiment, the first metal layer 52 is located below the drain pad 42, and a part of its area extends to a preset distance above the source structure 31, so that the first metal layer 52 and the drain pad 42 above it form a first capacitor C1, and the first metal layer 52 and the source structure 31 below it form a third capacitor C3. The first metal layer 52 is electrically connected to the regulating end pad 51 on the upper surface of the dielectric layer 20 through the dielectric hole to form an equipotential, so that one end of the first capacitor C1 and one end of the third capacitor C1 in the present embodiment are electrically connected together as the regulating end C, the other end of the first capacitor C1 is the drain D, and the other end of the third capacitor C3 is the source S, so the electrical schematic diagram of the semiconductor device of the fourth embodiment is shown in FIG14. The corresponding capacitance can be obtained by adjusting the distance and relative area between the first metal layer 52 and the source structure 31. The third capacitor C3 has a value of 0.1-10000 pF.

In this embodiment, due to the position of the first metal layer 52, the relative area between the source structure 31 and the drain pad 42 is reduced, and the drain-source capacitance Cds between the drain and source of the device is partially converted into a capacitance of C1 and C3 in series, thereby reducing the drain-source capacitance Cds of the device itself.

When the semiconductor device in this embodiment is used as a cascode device cascaded with HEMT Q2 and MOSFET Q1, when the device is packaged, the control terminal C (corresponding to the control terminal pad 51) in FIG. 14 is electrically connected to the gate of MOSFET Q1 by wire bonding, so that the drain-gate capacitance Cdg is added to the cascode device, and when it is matched with the gate resistance of the driving circuit, the switching speed of the cascode device can be effectively adjusted. In addition, since the drain-source capacitance of HEMT Q2 itself in this embodiment is low, a lower dynamic midpoint potential can be obtained. The midpoint refers to the connection point between the source of HEMT Q2 and the drain of MOSFETQ1. When the Cascode device is turned off, when the drain-source voltage Vds rises to the absolute value of the turn-off threshold Vth of the HEMT device, the channel of HEMT Q2 is turned off, and the capacitance matching process of the drain-source capacitance Cds of HEMT Q2 itself and the capacitance Coss of MOSFET Q1 itself (referring to the sum of the drain-source capacitance and the drain-gate capacitance of MOSFET Q1 itself) is entered. The magnitude of the drain-source Vds voltage (midpoint potential) of MOSFET Q1 is related to the drain-source capacitance Cds of HEMT Q2 itself. The smaller the drain-source capacitance Cds of HEMT Q2 itself, the lower the midpoint potential. If the midpoint potential is too high, it will cause MOSFET Q1 to avalanche. Therefore, the smaller the drain-source capacitance Cds of HEMT Q2 itself, the higher the reliability of the Cascode device. In this embodiment, the drain-source capacitance Cds of HEMT Q2 itself is reduced by the first metal layer 52 inside HEMT Q2, thereby improving the reliability of the device when it is used.

Embodiment 5

FIG15 is a schematic diagram of the structure of a semiconductor device according to the fifth embodiment of the present invention after partial sectioning. In this embodiment, the schematic diagram of the upper surface structure of the semiconductor device is the same as FIG8. In this embodiment, the partial area of the first metal layer 52 extends to the preset distance above the source structure 31 and the gate structure 32 in sequence, so that the first metal layer 52 and the drain pad 42 above it form a first capacitor C1, and at the same time, the first metal layer 52 and the gate structure 32 below it form a second capacitor C2, and the first metal layer 52 and the source structure 31 below it form a third capacitor C3. The first metal layer 52 is electrically connected to the control terminal pad 51 on the upper surface of the dielectric layer 20 through the dielectric hole to form an equipotential, so that one end of the first capacitor C1, one end of the second capacitor C2 and one end of the third capacitor C1 in this embodiment are electrically connected together as the control terminal C, the other end of the first capacitor C1 is the drain D, the other end of the second capacitor C2 is the gate G, and the other end of the third capacitor C3 is the source S, so the electrical schematic diagram of the semiconductor device of the fifth embodiment is shown in FIG16.

In this embodiment, while integrating the first capacitor C1, the drain-gate capacitance Cdg of the HEMT itself is also reduced, which can reduce the switching loss of the device. At the same time, the drain-source capacitance Cds of the HEMT itself is also reduced. Therefore, when forming a cascade device, the control terminal C is electrically connected to the gate of the MOSFET, which can not only adjust the switching speed of the cascade device, but also reduce the switching loss, reduce the midpoint potential, and improve the reliability of the device.

Embodiment 6

In the aforementioned fifth embodiment, the metal layer forming the first capacitor C1, the second capacitor C2 and the third capacitor C3 is the same metal layer, and of course, it can also be a plurality of separate metal layers. Figure 17 is a schematic diagram of the structure of a semiconductor device according to the sixth embodiment of the present invention after partial dissection. In this embodiment, a second metal layer 53 is added at a preset distance above the gate structure 33, thereby obtaining a second capacitor C2. For another example, a third metal layer 54 is added at a preset distance above the source structure 31, thereby obtaining a third capacitor C3. The second metal layer 53 and the third metal layer 54 can be electrically connected to the regulating end pad 51 on the surface through the dielectric hole, thereby obtaining the electrical connection relationship shown in Figure 16.

The second metal layer 53 may also be disposed below the gate pad 43 , and the third metal layer 54 may also be disposed below the source pad 41 .

Embodiment 7

FIG18 is a schematic diagram of the electrical principle of a semiconductor device according to Embodiment 7 of the present invention. In this embodiment, the control metal layer in the control structure integrated in the semiconductor device includes a control terminal pad 51 located on the upper surface of the dielectric layer 20 and a metal layer formed on the upper surface of the dielectric layer 20. In order to distinguish the first metal layer 52 formed inside the dielectric layer 20, the metal layer formed on the upper surface of the dielectric layer 20 is named as the fourth metal layer 55. Correspondingly, the control structure in this embodiment includes a structure for forming a resistor. Referring to FIG18, the first resistor R1 is connected in series with the first capacitor C1, so as to more conveniently adjust or control the switching rate of the device. FIG19 is a schematic diagram of the upper surface structure of the semiconductor device according to Embodiment 7 of the present invention. In this embodiment, in step S171 shown in FIG. 6, the fourth metal layer 55 is deposited on the upper surface of the second dielectric layer 202 opposite to the second area A2 of the drain pad 42 below the second dielectric layer 202, and the metal layer deposited at other positions is used as the regulating terminal pad 51, or, when etching the second dielectric layer 202 in step S172, a dielectric hole is also etched in other areas outside the pad structure, and in step S182, the metal layer deposited in the dielectric hole is used as the regulating terminal pad 51, and the second dielectric layer 202 is etched in the area opposite to the second area A2 of the drain pad 42 to obtain a shallower first A fourth metal layer 55 is deposited in a dielectric hole, and a first strip metal layer 62 is also deposited on the upper surface of the second dielectric layer 202 during the aforementioned metal deposition, wherein the fourth metal layer 55 and the second area A2 of the drain pad 42 located in the dielectric layer 20 below it form a first capacitor C1, and its structure is the same as that of FIG5 , except that the structure forming the first capacitor C1 with the second area A2 of the drain pad 42 in FIG5 is the regulating end pad 51, while in this embodiment it is the fourth metal layer 55, and the first end 6201 of the first strip metal layer 62 is connected to the fourth metal layer 55, and the connection point corresponds to the connection point C' in FIG18. The second end 6202 of the first strip metal layer 62 is connected to the regulating end pad 51, thereby obtaining the electrical connection relationship in the electrical schematic diagram shown in FIG18.

In this embodiment, the corresponding resistance value can be obtained by controlling the length, width and thickness of the first strip-shaped metal layer 62 , thereby obtaining the first resistor R1 with a preset resistance value.

In order to save the occupied area on the surface, the first strip-shaped metal layer 62 in this embodiment is in a zigzag shape, and its two end points are respectively the two ends of the resistor.

In some embodiments, the first strip metal layer 62 may be connected to a plurality of resistance connection points, each of which is electrically connected to a control end pad on the upper surface of the dielectric layer 20, such as the second control end pad 621 and the third control end pad 622 shown in FIG20. Each resistance connection point is at a different distance from the first end 6201 of the first strip metal layer, and has a different resistance value, so each corresponding control end pad corresponds to a specific resistance value, as shown in FIG20, and the resistor in the figure has three different resistance values.

When the semiconductor device in this embodiment is used as a cascode device cascaded with HEMT Q2 and MOSFET Q1, the control terminal pad 51, the second control terminal pad 621 or the third control terminal pad 622 is electrically connected to the gate of MOSFET Q1 as needed, and the switching speed of the device can be further effectively adjusted in cooperation with the driving circuit.

When the first capacitor C1 is formed by the first metal layer 52 inside the dielectric layer 20 and the drain, referring to the process shown in FIG. 10 , in step S27, when metal is deposited in the dielectric hole and on the upper surface of the second dielectric layer 202 to obtain a pad structure, a first strip metal layer 62 is also obtained at the same time, wherein the first end 6201 is connected to the first metal layer 52 through the dielectric hole, and the second end is connected to the regulating end pad 51.

In some other embodiments, the first strip metal layer 62 may also be located inside the dielectric layer 20. For example, referring to the flowchart shown in FIG. 10, in step S24, metal is deposited on the first dielectric layer 201 to obtain the first metal layer 52, and the first metal layer 52 is deposited to obtain the first end 6201 of the first strip metal layer 62. The first metal layer 52 is connected to the first end 6201 of the first strip metal layer 62. In the dielectric hole obtained by etching the second dielectric layer 202 in step S26, one dielectric hole is connected to the second end 6202 of the first strip metal layer 62. Therefore, when metal is deposited in the dielectric hole in step S27, it can be electrically connected to the control terminal pad 51 on the surface. Therefore, the upper surface structure of the device is the same as the upper surface structure of the device shown in FIG. 8. When multiple resistance values are required, each resistance connection point can be electrically connected to a control terminal pad on the upper surface of the dielectric layer 20 through the dielectric hole, and the obtained device upper surface structure diagram is shown in FIG. 21. Among them, the control terminal pad 51, the second control terminal pad 621 or the third control terminal pad 622 are respectively for different resistance values.

Embodiment 8

The electrical principle of the device of the eighth embodiment is similar to that of the seventh embodiment, except that the resistor in the present embodiment is formed by using a two-dimensional carrier gas in the second functional region 130 of the functional layer 10. Specifically, refer to FIG. 22, which is a schematic diagram of the structure of a semiconductor device according to the eighth embodiment of the present invention after partial cross-section. In the present embodiment, after providing a semiconductor epitaxial wafer, an isolation region 140 is formed on the semiconductor epitaxial wafer, the depth of the isolation region 140 is greater than the depth of the region where the two-dimensional carrier gas is located, and the isolation region 140 isolates the region of the functional layer from at least the second functional region 130 insulated from the first functional region 120. Wherein, while the electrode structure 30 is formed in the first functional region 120, the first electrode 71 and the second electrode 72 are formed in the second functional region 130. Specifically, the second functional region is etched downward to at least reach the second two-dimensional carrier gas 112, and then a metal is generated in the etched region to obtain the first electrode 71 and the second electrode 72, and the first electrode 71 and the second electrode 72 can be conductive through the second two-dimensional carrier gas 112.

Referring to Figure 10, before step S24, the first dielectric layer 201 is etched to obtain a dielectric hole connected to the first electrode 71. In step S24, metal is deposited on the first dielectric layer 201 to obtain the first metal layer 52 and at the same time, metal is deposited in the dielectric hole to electrically connect the first metal layer 52 to the first electrode 71. In step S26, a dielectric hole connected to the second electrode 72 is obtained when the second dielectric layer 202 is etched. When metal is deposited in the dielectric hole and on the upper surface of the second dielectric layer 202 to obtain a pad structure in step S27, the regulating end pad 51 is electrically connected to the second electrode 72 through the dielectric hole.

In this embodiment, the first metal layer 52 in the dielectric layer 20 and the drain pad on the upper surface constitute a first capacitor C1, the first electrode 71 is electrically connected to the first metal layer 52 via the dielectric hole, the second electrode 72 is led to the upper surface of the dielectric layer 20 via the dielectric hole, and is electrically connected to the regulating end pad 51 on the upper surface. At this time, the device upper surface structure obtained is the same as the device upper surface structure shown in Figure 8.

In addition, in order to obtain multiple resistance values, multiple electrodes can be generated in the second functional area 130, and as shown in FIG. 22, a third electrode 73 is also included, wherein the first electrode 71 and the third electrode 73 constitute a resistor with a resistance value, and the first electrode 71 and the second electrode 72 constitute a resistor with a resistance value. Similarly, the third electrode 73 is led to the upper surface of the dielectric layer 20 through the dielectric hole and is electrically connected to the second control terminal pad 621 deposited on the upper surface of the dielectric layer 20. When the semiconductor device in this embodiment is used as a cascode device cascaded with the HEMT Q2 and the MOSFET Q1, the control terminal pad 51 or the second control terminal pad 621 is electrically connected to the gate of the MOSFET Q1 as needed.

Embodiment 9

Figure 23 is an electrical schematic diagram of a semiconductor device according to Embodiment 9 of the present invention. In this embodiment, a first resistor R1 and a diode D1 are integrated in the semiconductor device. The first resistor R1 and the diode D1 are connected in parallel and then connected in series with the first capacitor C1. The first resistor R1 and the diode D1 are used to individually control the opening and closing rates of the device. In the application scenario, when the semiconductor device in this embodiment is used to form a cascaded Cascode device with a MOSFET, the control terminal C is electrically connected to the gate of the MOSFET. During the shutdown process, the turn-off rate of the cascaded Cascode device can be controlled by the cooperation of the first resistor R1 and the first capacitor C1. During the opening process, the opening rate of the cascaded Cascode device can be controlled by the diode D1 and the first capacitor C1, thereby realizing the individual control of the opening and closing rates of the device.

FIG24 is a schematic diagram of the structure of a diode in a semiconductor device according to Embodiment 9 of the present invention. This embodiment can be combined with the structures of the aforementioned embodiments with integrated resistors. For simplicity, this embodiment only illustrates a schematic diagram of the structure of a diode. A diode D1 is formed in the third functional region 150. The third functional region 150 is electrically insulated from the first functional region 120 by the isolation region 160. While the electrode structure 30 is formed in the first functional region 120, a diode D1 is formed in the third functional region 150. Specifically, when etching the semiconductor epitaxial wafer, the third functional region 150 is etched downward to at least reach the third two-dimensional carrier gas 113, and then a metal is grown in the etched area to obtain a diode cathode 81 and a diode anode 82, the diode cathode 81 forms an ohmic contact with the third functional region 150, and the diode anode 82 forms a Schottky contact with the third functional region 150, so that the current can be unidirectionally transmitted between the diode cathode 81 and the diode anode 82 through the third two-dimensional carrier gas 113.

Referring to Figure 10, before step S24, the first dielectric layer 201 is etched to obtain a dielectric hole connected to the diode cathode 81. In step S24, while depositing metal on the first dielectric layer 201 to obtain the first metal layer 52, metal is deposited in the dielectric hole to electrically connect the first metal layer 52 to the diode cathode 81. In step S26, a dielectric hole obtained when etching the second dielectric layer 202 is connected to the diode anode 82. When metal is deposited in the dielectric hole and on the upper surface of the second dielectric layer 202 to obtain a pad structure in step S27, the regulating end pad 51 is electrically connected to the diode anode 82.

The diode anode 82 in this embodiment is led to the upper surface of the dielectric layer 20 through the dielectric hole, and is electrically connected to the regulating end pad 51 on the upper surface. The diode cathode is electrically connected to the first metal layer 52 through the dielectric hole, and of course can also be electrically connected to the first electrode 71 in Figure 20. Similarly, the diode cathode 81 can also be electrically connected to the second electrode 72 through the dielectric hole, thereby obtaining the electrical connection relationship shown in Figure 23.

When the semiconductor device in this embodiment is used as a cascode device cascaded with the HEMT Q2 and the MOSFET Q1, the control terminal pad 51 is electrically connected to the gate of the MOSFET Q1, so that a control structure consisting of the first capacitor C1, the first resistor R1, and the diode D1 is added to the cascode device, and the on and off speeds of the device can be effectively and separately controlled in cooperation with the drive circuit.

Embodiment 10

25 is a schematic diagram of the electrical principle of a semiconductor device according to Embodiment 10 of the present invention. In this embodiment, the control structure integrated in the semiconductor device includes a first resistor R1, a second resistor R2 and a diode D1, wherein the second resistor R2 and the diode D1 are connected in series and then connected in parallel with the first resistor R1, and then connected in series with the first capacitor C1. The branch formed by the second resistor R2 and the diode D1 and the first resistor R1 are respectively used to separately control the opening and closing rates of the device. The structure of the semiconductor device of Embodiment 10 can be realized by forming another resistor in the structure of the semiconductor device in Embodiment 9, and the resistor can also be the structure in Embodiment 7 or Embodiment 8, which will not be repeated here.

It should be noted that the capacitor integrated in the seventh to tenth embodiments may also be any capacitor structure integrated in the second to sixth embodiments. For details, please refer to the relevant embodiments and will not be described in detail here.

In the semiconductor device provided by the present invention or the cascode cascade device formed by using the semiconductor device, since the control structure is integrated inside, including at least the drain-gate capacitor Cdg, there is no need to add additional capacitors outside the device, saving material costs. Moreover, since the drain-gate capacitor Cdg is integrated in the high-voltage device, its breakdown voltage parameters match the device, solving the problem that the parameters of the external capacitor are not easy to match the device parameters, and reducing the complexity of the circuit design.

The above embodiments are only used to illustrate the present invention, but not to limit the present invention. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the scope of the present invention. Therefore, all equivalent technical solutions should also fall within the scope of the present invention.

Claims (15)

1. A semiconductor device, comprising: a functional layer, wherein a first two-dimensional carrier gas is formed in a first functional region; a dielectric layer formed above the functional layer; an electrode structure, formed in the first functional area, comprising a source structure, a drain structure and a gate structure, wherein the source structure and the drain structure are electrically connected to the first two-dimensional carrier gas respectively; A pad structure, the surface of which is exposed to the upper surface of the dielectric layer, and includes a source pad, a drain pad and a gate pad, respectively, wherein the source pad, the drain pad and the gate pad are respectively electrically connected to the source structure, the drain structure and the gate structure through dielectric holes to form the source, drain and gate of the device; and A regulating structure, comprising a regulating metal layer formed on the upper surface of the dielectric layer, wherein the regulating metal layer and the drain electrode form a first capacitor; The drain pad includes a first area exposed on the upper surface of the dielectric layer and a second area placed inside the dielectric layer in parallel with the first area. The control metal layer is a control end pad located on the upper surface of the dielectric layer. The control end pad is located on the upper surface of the dielectric layer above the second area of the drain pad, wherein the control end pad and the second area of the drain pad form the first capacitor. 2. A semiconductor device, comprising: a functional layer, wherein a first two-dimensional carrier gas is formed in a first functional region; a dielectric layer formed above the functional layer; an electrode structure, formed in the first functional area, comprising a source structure, a drain structure and a gate structure, wherein the source structure and the drain structure are electrically connected to the first two-dimensional carrier gas respectively; A pad structure, the surface of which is exposed to the upper surface of the dielectric layer, and includes a source pad, a drain pad and a gate pad, respectively, wherein the source pad, the drain pad and the gate pad are respectively electrically connected to the source structure, the drain structure and the gate structure through dielectric holes to form the source, drain and gate of the device; and A regulating structure, comprising a regulating metal layer formed on the dielectric layer, wherein the regulating metal layer and the drain electrode form a first capacitor; The regulating metal layer includes a regulating end pad located on the upper surface of the dielectric layer and a first metal layer formed inside or on the upper surface of the dielectric layer, and the regulating end pad is electrically connected to the first metal layer through a dielectric hole; when the first metal layer is located inside the dielectric layer, the first metal layer is located at a preset distance below the drain pad and/or the first metal layer is located at a preset distance above the drain structure; when the first metal layer is located on the upper surface of the dielectric layer, the drain pad includes a first area exposed on the upper surface of the dielectric layer and a second area placed inside the dielectric layer in parallel with the first area, and the first metal layer is located at a preset distance above the second area of the drain pad; wherein the first metal layer and the drain pad and/or the drain structure form the first capacitor; The control structure also includes a first strip metal layer, which is formed on the upper surface or inside the dielectric layer, whose first end is electrically connected to the first metal layer, and whose second end is electrically connected to the control end pad, wherein the first strip metal layer constitutes a first resistor with a preset resistance value. 3. The semiconductor device according to claim 2 is characterized in that a partial area of the first metal layer extends to a preset distance above the gate structure and/or a partial area of the first metal layer extends to a preset distance below the gate pad, wherein the first metal layer forms a second capacitor with the gate structure and/or the gate pad. 4. The semiconductor device according to claim 2 is characterized in that a partial area of the first metal layer extends to a preset distance above the source structure and/or a partial area of the first metal layer extends to a preset distance below the source pad, wherein the first metal layer forms a third capacitor with the source structure and/or the source pad. 5. The semiconductor device according to claim 2 is characterized in that it also includes a second metal layer, which is electrically connected to the control end pad or the first metal layer through a dielectric hole; the second metal layer is located at a preset distance above the gate structure and/or the second metal layer is located at a preset distance below the gate pad, wherein the second metal layer and the gate structure and/or the gate pad form a second capacitor; and/or also includes a third metal layer, which is electrically connected to the control end pad or the first metal layer through a dielectric hole; the third metal layer is located at a preset distance above the source structure and/or the third metal layer is located at a preset distance below the source pad, wherein the third metal layer and the source structure and/or the source pad form a third capacitor. 6. The semiconductor device according to claim 2 is characterized in that there are multiple control end pads located on the upper surface of the dielectric layer, the first strip metal layer includes connection points at different distances from the first end, and each control end pad is electrically connected to the corresponding connection point; wherein each connection point is electrically connected to the strip metal layer between the first end of the first strip metal layer to form a first resistor with a preset resistance value. 7. The semiconductor device according to claim 2 is characterized in that the control structure also includes a first electrode and one or more second electrodes; wherein the first electrode and the one or more second electrodes are formed in the second functional area of the functional layer, and are ohmically connected to the second two-dimensional carrier gas inside the second functional area, and the first electrode is electrically connected to the first metal layer; when the second electrode is one, it is electrically connected to the control end pad through a dielectric hole, and when the second electrode is multiple, the control end pad is a corresponding multiple, and each second electrode is electrically connected to the corresponding control end pad through a dielectric hole; wherein the first electrode and each of the second electrodes respectively form a first resistor with a preset resistance through the second two-dimensional carrier. 8. The semiconductor device according to claim 7 is characterized in that the control structure also includes a diode, wherein a diode anode and a diode cathode are formed in the third functional area of the functional layer, the diode cathode is ohmically connected to the third two-dimensional carrier gas in the third functional area, the diode anode is Schottky connected to the third two-dimensional carrier gas in the third functional area, the diode anode is electrically connected to the control end pad, and the diode cathode is electrically connected to the first metal layer. 9. The semiconductor device according to claim 8, further comprising a second strip metal layer, a first end of which is electrically connected to the first metal layer, and a second end of which is electrically connected to the cathode of the diode, and the second strip metal layer constitutes a second resistor with a preset resistance. 10. The semiconductor device according to claim 8 is characterized in that it also includes a third electrode and a fourth electrode, wherein the third electrode and the fourth electrode are formed in the fourth functional area of the functional layer and are ohmically connected to the fourth two-dimensional carrier gas inside the fourth functional area, the third electrode is electrically connected to the first metal layer, and the fourth electrode is electrically connected to the cathode of the diode; a second resistor with a preset resistance is formed between the third electrode and the fourth electrode through the fourth two-dimensional carrier. 11 . The semiconductor device according to claim 10 , wherein an electrically insulating isolation region is included between the first functional region, the second functional region, the third functional region and the fourth functional region, and a depth of the isolation region is greater than a depth of a region where the two-dimensional carrier gas is located. 12. The semiconductor device according to claim 1 or 2, characterized in that the functional layer comprises at least a channel layer and a barrier layer, a two-dimensional carrier gas is formed in a region of the channel layer close to the barrier layer; and the channel layer and the barrier layer are III-V compounds. 13. A semiconductor device, comprising a first transistor and a second transistor, wherein the first transistor is the semiconductor device according to any one of claims 1 to 12, and the second transistor is an enhancement-mode silicon-based transistor; the drain of the first transistor serves as the first electrode of the entire device, the source of the first transistor is electrically connected to the drain of the second transistor, and the source of the second transistor is the second electrode of the entire device; the gate of the first transistor is electrically connected to the source of the second transistor; the regulating terminal pad of the first transistor is electrically connected to the gate of the second transistor; the gate of the second transistor is the control electrode of the entire device, and is used to connect to a drive circuit; When the semiconductor device is controlled to be turned on or off by a driving circuit, the switching speed of the semiconductor device is adjusted by adjusting the resistance value of the resistor connected to the regulating terminal pad in the driving circuit. 14. A method for preparing a semiconductor device, comprising: A semiconductor epitaxial wafer is provided as a functional layer, wherein the functional layer at least comprises a channel layer and a barrier layer, wherein a two-dimensional carrier gas is formed in a region of the channel layer close to the barrier layer; and the channel layer and the barrier layer are III-V group compounds; forming an electrode structure in the first functional region of the functional layer, the electrode structure comprising a source structure, a drain structure and a gate structure, the source structure and the drain structure being electrically connected to the two-dimensional carrier gas respectively; Depositing a first dielectric layer of a preset thickness above the electrode structure; Depositing metal on the first dielectric layer to obtain a first metal layer, wherein the first metal layer is located above the drain structure, or the first metal layer is located above the drain structure and a portion of the first metal layer extends to the gate structure and/or the source structure; Depositing a second dielectric layer on the first metal layer and on the first dielectric layer not covered with metal; Etching dielectric holes respectively connected to the source structure, the drain structure, the gate structure and the first metal layer from the second dielectric layer downwards; and Depositing metal in the dielectric hole and on the upper surface of the second dielectric layer to obtain a pad structure, wherein the pad structure includes a source pad, a drain pad, a gate pad and a control end pad, and the source pad, the drain pad, the gate pad and the control end pad are respectively electrically connected to the source structure, the drain structure, the gate structure and the first metal layer through the dielectric hole to form the source, the drain, the gate and the control structure of the device; Wherein, the first metal layer and the drain structure and/or the drain pad form a first capacitor; The semiconductor device also includes a first strip metal layer, which is formed on the upper surface or inside the dielectric layer, and whose first end is electrically connected to the first metal layer and whose second end is electrically connected to the regulating end pad, wherein the first strip metal layer constitutes a first resistor with a preset resistance value. 15. A method for preparing a semiconductor device, comprising: A semiconductor epitaxial wafer is provided as a functional layer, wherein the functional layer at least comprises a channel layer and a barrier layer, wherein a two-dimensional carrier gas is formed in a region of the channel layer close to the barrier layer; and the channel layer and the barrier layer are III-V group compounds; forming an electrode structure in the first functional region of the functional layer, the electrode structure comprising a source structure, a drain structure and a gate structure, the source structure and the drain structure being electrically connected to the two-dimensional carrier gas respectively; Depositing a first dielectric layer of a preset thickness above the electrode structure; Etching the first dielectric layer to obtain dielectric holes connected to the source structure, the drain structure and the gate structure respectively; Depositing metal in the dielectric hole and on the upper surface of the first dielectric layer to obtain a pad structure, wherein the pad structure includes a source pad, a drain pad and a gate pad, and the source pad, the drain pad and the gate pad are respectively electrically connected to the source structure, the drain structure and the gate structure through the dielectric hole to form the source, the drain and the gate of the device; Depositing a second dielectric layer above the pad structure and on the upper surface of the first dielectric layer where no metal is deposited; and Depositing metal on the upper surface of the second dielectric layer opposite to the second region of the drain pad to obtain a regulating terminal pad; and etching the second dielectric layer to expose the first region of the pad structure that is not opposite to the regulating terminal pad, the source pad, and the gate pad; Alternatively, a first dielectric hole is obtained by etching downwards to a first depth from the upper surface of the second dielectric layer opposite to the second area of the drain pad, and a second depth is respectively etched downwards from the upper surface of the second dielectric layer opposite to the first area of the drain pad, the source pad and the gate pad until the first area of the drain pad, the source pad and the gate pad are exposed to obtain corresponding multiple second dielectric holes, wherein the first depth is less than the second depth; metal is deposited at least in the first dielectric hole to obtain a regulating end pad; the regulating end pad forms a first capacitor with the second area of the drain pad.