CN118315332A

CN118315332A - Semiconductor structure, forming method thereof and method for forming through substrate via

Info

Publication number: CN118315332A
Application number: CN202410300665.8A
Authority: CN
Inventors: 许琍雯; 王良玮; 邱志斌; 陈殿豪
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2023-03-17
Filing date: 2024-03-15
Publication date: 2024-07-09

Abstract

Disclosed herein are via structures and methods of making the same. An exemplary method includes forming a trench extending through an insulating layer and into a substrate. The substrate has a first side (e.g., front side) and a second side (e.g., back side). An insulating layer is disposed over the first side of the substrate. The method comprises the following steps: filling the trench with a dielectric material; and performing a thinning process on the second side of the substrate, the thinning process exposing the dielectric material. After the thinning process and removal of dielectric material from the trench, the method includes forming a conductive structure (e.g., a barrier liner encasing the conductive plug) in the trench, the conductive structure extending through the substrate from the first side to the second side. The portion of the barrier liner forming the top of the conductive structure is disposed in the insulating layer. Embodiments of the present application also relate to semiconductor structures, methods of forming the same, and methods of forming through substrate vias.

Description

Semiconductor structure, forming method thereof and method for forming through substrate via

Technical Field

Embodiments of the present application relate to semiconductor structures, methods of forming semiconductor structures, and methods of forming through-substrate vias.

Background

Advanced IC packaging techniques have evolved to further reduce the density of Integrated Circuits (ICs) and/or improve the performance of ICs, which are incorporated into many electronic devices. For example, IC packages have evolved such that multiple ICs may be vertically stacked in a three-dimensional ("3D") package or a 2.5D package (e.g., a package implementing an interposer). Vias, also known as Through Silicon Vias (TSVs), are one technique for electrically and/or physically connecting stacked ICs and/or chips. While existing TSV structures and methods of fabricating them are generally adequate for their intended purpose, they are not entirely satisfactory in all respects, as IC component sizes (including TSV sizes) decrease as IC technology nodes shrink.

Disclosure of Invention

Some embodiments of the present application provide a method for forming a through substrate via, the method comprising: forming a trench extending through an insulating layer and into a substrate, wherein the substrate has a first side and a second side, the insulating layer is disposed over the first side of the substrate, and the second side is opposite the first side; filling the trench with a dielectric material; performing a thinning process on the second side of the substrate, wherein the thinning process exposes the dielectric material; and forming a conductive structure in the trench after performing the thinning process and removing the dielectric material from the trench, wherein the conductive structure extends through the substrate from the first side to the second side.

Other embodiments of the present application provide a method of forming a semiconductor structure, comprising: receiving a workpiece having a device substrate and a multilayer interconnect (MLI) feature, wherein the device substrate has a first thickness between a first side and a second side thereof, and the multilayer interconnect feature is disposed over the first side; forming a via opening extending through the insulating layer of the multilayer interconnect component and into the device substrate to a depth, wherein the depth is less than the first thickness and the via opening has a first aspect ratio; filling the via opening with a sacrificial material; removing a portion of the device substrate to reduce the first thickness to a second thickness, wherein removing the portion of the device substrate further comprises removing a portion of the sacrificial material; selectively removing the sacrificial material relative to the insulating layer and the device substrate, wherein the via opening has a second aspect ratio after selectively removing the sacrificial material, and the second aspect ratio is less than the first aspect ratio; and forming a via in the via opening having the second aspect ratio, wherein the via includes a barrier liner surrounding a conductive plug, and the barrier liner and the insulating layer form a top surface of the workpiece.

Still further embodiments of the present application provide a semiconductor structure comprising: a device substrate having a first side and a second side; an insulating layer disposed over the first side of the device substrate; and a via extending through the insulating layer and through the device substrate from the first side to the second side, wherein: the via includes a body layer disposed over a barrier layer, the barrier layer being between the body layer and the device substrate, the barrier layer being between the body layer and the insulating layer, the barrier layer having a first portion forming a first sidewall of the via, a second portion forming a second sidewall of the via, and a third portion extending between the first portion and the second portion, and the third portion being disposed in the insulating layer.

Drawings

The disclosed embodiments are best understood from the following detailed description when read with the accompanying drawing figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. The dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a partial or overall cross-sectional view of a semiconductor structure having an improved via structure design, such as an improved Through Silicon Via (TSV), in accordance with aspects of an embodiment of the present disclosure.

Fig. 2 is a top view of a portion or an entirety of a semiconductor structure, such as the semiconductor structure of fig. 1, in accordance with aspects of an embodiment of the present disclosure.

Fig. 3 is a cross-sectional view of a portion or an entirety of a semiconductor arrangement (which includes a via, such as the TSV of the semiconductor structure of fig. 1 and 2) in accordance with aspects of an embodiment of the present disclosure.

Fig. 4 is a cross-sectional view of a portion or whole of another semiconductor arrangement (which includes vias, such as TSVs of the semiconductor structure of fig. 1 and 2) in accordance with aspects of an embodiment of the present disclosure.

Fig. 5A-5O are partial or complete cross-sectional views of a workpiece at various stages of fabrication in forming vias, such as TSVs of the semiconductor structure of fig. 1 and 2, in accordance with various aspects of an embodiment of the present disclosure.

Fig. 6A-6E are partial or complete cross-sectional views of a workpiece at various stages of fabrication in forming trenches for vias (which may be implemented in the stages of fabrication of fig. 5E) in accordance with various aspects of an embodiment of the present disclosure.

Fig. 7 is a flow chart of a portion or whole of a method for fabricating the via, TSV depicted in fig. 1 and 2, in accordance with aspects of an embodiment of the present disclosure.

Fig. 8 is a cross-sectional view of a portion or an entirety of a device substrate (which may be implemented in a semiconductor structure, such as the semiconductor structure of fig. 1 and 2) in accordance with aspects of an embodiment of the present disclosure.

Detailed Description

Embodiments of the present disclosure relate generally to Integrated Circuit (IC) packages, and more particularly to vias (also referred to as semiconductor vias (TSVs)).

The following disclosure provides many different embodiments, or examples, for implementing different features of embodiments of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure embodiments. These are, of course, merely examples and are not intended to limit the disclosed embodiments. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, for ease of understanding of the disclosed embodiments, spatially relative terms such as "lower," "upper," "horizontal," "vertical," "above …," "above …," "below …," "below …," "upward," "downward," "top," "bottom," and the like, as well as derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.), are used to describe one element's relationship to another element. Spatially relative terms are intended to cover different orientations of a device comprising the component.

Furthermore, when values or ranges of values are described as "about," "approximately," "substantially," etc., as understood by one of ordinary skill in the art, the term is intended to encompass values within a reasonable range that take into account variations inherently present during manufacture. For example, a value or range of values encompasses a reasonable range including the recited value, such as within +/-10% of the recited value, based on known manufacturing tolerances associated with manufacturing components having characteristics associated with the value. For example, a material layer having a thickness of "about 5nm" may include a size range from 4.5nm to 5.5nm, with a manufacturing tolerance of +/-10% associated with depositing the material layer as known to one of ordinary skill in the art. In another example, two components described as having "substantially the same" dimensions and/or "substantially" oriented in a particular direction and/or configuration (e.g., "substantially parallel" or "substantially perpendicular") encompass dimensional differences between the two components and/or minor orientation differences of the two components from precisely specified orientations, which may be inherent but not intentionally caused by manufacturing tolerances associated with manufacturing the two components. Still further, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed herein.

Advanced IC packaging techniques have evolved to further reduce the density of Integrated Circuits (ICs) and/or improve the performance of ICs, which are incorporated into many electronic devices. For example, IC packages have evolved such that multiple ICs may be vertically stacked in a three-dimensional ("3D") package or a 2.5D package (e.g., a package implementing an interposer). Vias, also known as Through Silicon Vias (TSVs), are one technique for electrically and/or physically connecting stacked ICs. For example, in the case where a first chip is vertically stacked above a second chip, TSVs may be formed that vertically extend through the first chip to the second chip. The TSVs may electrically and/or physically connect a first conductive structure (e.g., a first wire) of a first chip to a second conductive structure (e.g., a second wire) of a second chip. TSVs are conductive structures, such as copper structures, and may extend through the device substrate of the first chip to the second chip.

Guard rings are typically formed around the TSVs to protect the TSVs, improve TSV performance, improve TSV structural stability, shield and/or reduce TSV induced noise that may adversely affect the first chip and/or the second chip, or a combination thereof. The guard ring may be formed when forming a back-end-of-line (BEOL) structure of the first chip, such as a first wire of the first chip. The first wiring may be disposed over and connected to the first device substrate of the first chip and facilitate operation and/or electrical communication of devices and/or structures of the first device substrate. After forming the BEOL structure, the TSV may be formed, for example, by: etching through the dielectric layer of the BEOL structure in the region defined by the guard ring and into the first device substrate to form a TSV trench; filling the TSV trench (e.g., a bulk copper layer over the barrier/seed layer) with a conductive structure; and thinning the first device substrate (e.g., from a backside thereof) to expose the conductive structure (e.g., by a planarization process and/or an abrasive process). The topmost metallization layer of the BEOL structure of the first chip may be formed before and/or after thinning, and may comprise a top metallization layer of the TSV that may be physically and/or electrically connected to the guard ring. In some embodiments, the first chip is attached to the second chip after the TSVs and the topmost metallization layer are formed.

As IC technology nodes shrink, TSV width (e.g., critical dimensions) may be reduced to reduce TSV footprint (i.e., area overhead) and/or reduce power consumption, while TSV depth/height may be increased to improve mechanical characteristics. But decreasing the TSV width and increasing the TSV depth/width results in a TSV trench (and thus TSV) having a higher aspect ratio (i.e., depth/height much greater than width), which results in undesirable void formation in the TSV. Accordingly, TSV fabrication techniques are disclosed that may reduce the TSV aspect ratio, thereby improving gap filling and/or reducing void formation in the TSV. The TSV manufacturing technology comprises the following steps: etching through the dielectric layer of the BEOL structure (e.g., in the region defined by the guard ring) and into the device substrate to form a TSV trench; filling the TSV trench with a sacrificial material; thinning the device substrate (e.g., from its back side) to expose the dielectric material; removing the dielectric material; and filling the TSV trench with a conductive structure. Filling the trench with the conductive structure may include: forming a dielectric liner (e.g., an oxide liner) along sidewalls (e.g., formed from dielectric layers of the BEOL structure) and bottom (e.g., formed from carrier wafer/substrate); forming a barrier/seed layer over the oxide liner; and forming a bulk conductive layer over the barrier/seed layer. In such embodiments, the material of the conductive structure is deposited over the backside of the device substrate such that the bottom of the trench is disposed in the dielectric layer of the BEOL structure and the top of the TSV is provided. Thus, the portion of the barrier/seed layer extending between the sidewall portions of the barrier/seed layer forms the top of the TSV and is disposed in the dielectric layer of the BEOL structure. Since the thinning is performed before the conductive structure is formed, the aspect ratio of the TSV may be reduced without damaging the TSV, and the dielectric material may prevent the TSV trench from changing in shape during the thinning. Reducing the aspect ratio of the TSV trench (and thus the TSV) reduces and/or prevents voids from forming in the TSV, and reduces the size, area overhead, power consumption, or a combination thereof of the TSV. Details of the proposed TSV structures and/or dimensions and/or their fabrication are described herein. Different embodiments may have different advantages, and no particular advantage is required for any embodiment.

Fig. 1 is a cross-sectional view of a portion or an entirety of a semiconductor structure 100 having an improved via structure design, such as an improved Through Silicon Via (TSV), in accordance with aspects of an embodiment of the present disclosure. Fig. 2 is a top view of a portion or an entirety of a semiconductor structure 100 in accordance with aspects of embodiments of the present disclosure. The cross-sectional view of fig. 1 is along line 2-2' of fig. 2 and the top contact layer TC of the semiconductor structure 100 depicted in fig. 1 is removed in fig. 2. For ease of description and understanding, fig. 1 and 2 are discussed herein simultaneously. For clarity, fig. 1 and 2 have been simplified to better understand the inventive concepts of the disclosed embodiments. Additional components may be added to semiconductor structure 100 and/or components thereof, and some of the components described below may be replaced, modified, or eliminated in other embodiments of semiconductor structure 100 and/or components thereof.

In fig. 1, a device substrate 102 is depicted having a side 104 (e.g., front side) and a side 106 (e.g., back side) opposite the side 104. The device substrate 102 may include circuitry (not shown) fabricated on and/or over the side 104 by front end of line (FEOL) processing. For example, the device substrate 102 may include various device components/features such as a semiconductor substrate, doped wells (e.g., n-wells and/or p-wells), isolation features (e.g., shallow Trench Isolation (STI) structures and/or other suitable isolation structures), gates (e.g., gate stacks with gate electrodes and gate dielectrics), gate spacers along sidewalls of the gates, source/drains (e.g., epitaxial source/drains), other suitable device components and/or device features, or combinations thereof. In some embodiments, the device substrate 102 comprises a planar transistor, wherein a channel of the planar transistor is formed in the semiconductor substrate between the respective source/drains and the respective gates are disposed on the channel (e.g., on a portion of the semiconductor substrate forming the channel). In some embodiments, the device substrate 102 includes a non-planar transistor having a channel formed in the semiconductor fin that extends from the semiconductor substrate and between respective source/drains on/in the semiconductor fin, with respective gates disposed on and surrounding the channel of the semiconductor fin (i.e., the non-planar transistor is a fin field effect transistor (FinFET)). In some embodiments, the device substrate 102 includes a non-planar transistor having a channel formed in a semiconductor layer suspended above the semiconductor substrate and extending between respective sources/drains, with respective gates disposed on the channel and at least partially surrounding the channel (i.e., the non-planar transistor is a full-gate-all-around (GAA) transistor and/or a fork-slice transistor). The individual transistors of the device substrate 102 may be configured as planar or non-planar transistors, depending on design requirements.

The device substrate 102 may include various passive and active electronic devices such as resistors, capacitors, inductors, diodes, p-type FETs (PFETs), n-type FETs (NFETs), metal Oxide Semiconductor (MOS) FETs (MOSFETs), complementary MOS (CMOS) transistors, bipolar Junction Transistors (BJTs), laterally Diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. The individual electronic devices may be configured to provide functionally distinct regions of the IC, such as a logic region (i.e., core region), a memory region, an analog region, a peripheral region (e.g., input/output (I/O) region), a dummy region, other suitable regions, or a combination thereof. The logic region may be configured with standard cells, each of which may provide logic devices and/or logic functions, such as inverters, and gates, nand gates, or gates, nor gates, exclusive or gates, nor gates, other suitable logic devices, or combinations thereof. The memory region may be configured with memory cells, each of which may provide a memory device and/or storage function, such as flash memory, non-volatile random access memory (NVRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other volatile memory, other non-volatile memory, other suitable memory, or a combination thereof. In some embodiments, the memory cells and/or logic cells include transistors and interconnect structures that combine to provide memory devices/functions and logic devices/functions, respectively, of the chip.

A multi-layer interconnect (MLI) feature 110 is disposed over the side 104 of the device substrate 102. The MLI component 110 electrically connects individual devices (e.g., transistors) and/or components of the device substrate 102 and/or individual devices (e.g., memory devices disposed within the MLI component 110) and/or components of the MLI component 110 such that the individual devices and/or components may operate as specified by the design requirements. The MLI feature 110 includes a combination of dielectric and conductive layers (e.g., patterned metal layers) configured to form an interconnect (wiring) structure. The conductive layers form vertical interconnect structures (such as device level contacts and/or vias) and/or horizontal interconnect structures (such as conductive lines). The vertical interconnect typically connects horizontal interconnect structures in different layers/levels (or different planes) of the MLI component 110. During operation, the interconnect structures may route and/or distribute electrical signals (e.g., clock signals, voltage signals, ground signals, etc.) between devices and/or components of the device substrate 102 and/or the MLI component 110 to devices and/or device components of the device substrate 102 and/or the MLI component 110. Although the MLI component 110 is depicted as having a given number of dielectric and metal layers, the disclosed embodiments contemplate MLI components 110 having more or fewer dielectric and/or metal layers.

The MLI component 110 may include circuitry fabricated on and/or over the side 104 by back-end-of-line (BEOL) processing, and thus may also be referred to as a BEOL structure. The MLI component 110 includes n-level interconnect layers, (n+x) -level interconnect layers, and intermediate interconnect layers therebetween (i.e., (n+1) -level interconnect layers, (n+2) -level interconnect layers, and the like), where n is an integer greater than or equal to 1, and x is an integer greater than or equal to 1. Each of the n-level interconnect layers to the (n+x) -level interconnect layers includes a respective metallization layer and a respective via layer. For example, the n-level interconnect layers include respective n via layers (denoted as V _n) and respective n metallization layers (denoted as M _n) over the n via layers, the (n+1) level interconnect layers include respective (n+1) via layers (denoted as V _n+1) and respective (n+1) metallization layers (denoted as _Mn+1) over the (n+1) via layers, For intermediate to (n+x) level interconnect layers, and so on, the (n+x) level interconnect layers include respective (n+x) via layers (denoted V _n+x) and (n+x) metallization layers (denoted M _n+x) over the (n+x) via layers. In the depicted embodiment, n is equal to 1, x is equal to 9, and the MLI component 110 includes ten interconnect layers, such as a first level interconnect layer including a V ₁ layer and an M ₁ layer, a second level interconnect layer including a V ₂ layer and an M ₂ layer, and so on, up to a tenth level interconnect layer including the V ₁₀ layer and the M ₁₀ layer. Each via layer physically and/or electrically connects an underlying metallization layer and an overlying metallization layer, an underlying device level contact layer (e.g., a middle of line (MEOL) interconnect layer such as an M ₀ layer) and an overlying metallization layer, an underlying device component (e.g., a gate electrode of a gate or source/drain) and an overlying metallization layer or an underlying metallization layer and an overlying top contact layer. For example, V ₂ layers are located between the M ₁ layer and the M ₂ layer, physically and electrically connected to the M ₁ layer and the M ₂ layer. In another example, the V ₁ layer is located between the M ₁ layer and the underlying device-level contact layer and/or the underlying device component, physically and electrically connected to the M ₁ layer and the underlying device-level contact layer and/or the underlying device component. In some embodiments, the metallization layer and the via layer are further electrically connected to the device substrate 102. For example, a first combination of metallization layers and via layers is electrically connected to the gates of the transistors of the device substrate 102, and a second combination of metallization layers and via layers is electrically connected to the sources/drains of the transistors, such that voltages may be applied to the gates and/or the sources/drains.

The MLI component 110 includes an insulating layer 115 with metal lines 116, vias 118, other conductive components, or a combination thereof disposed in the insulating layer 115. Each of the M _n to M _n+x metallization layers includes a patterned metal layer (i.e., a set of metal lines 116 arranged in a desired pattern) in a corresponding portion of the insulating layer 115. Each of V _n through V _n+x via layers includes a patterned metal layer (i.e., a set of vias 118 arranged in a desired pattern) in a corresponding portion of insulating layer 115. Insulating layer 115 includes a dielectric material such as silicon oxide, tetraethyl orthosilicate (TEOS) oxide, phosphosilicate glass (PSG), boron doped silicate glass (BSG), boron doped PSG (BPSG), low-k dielectric materials having a dielectric constant, for example, less than that of silicon oxide (e.g., k < 3.9), other suitable dielectric materials, or combinations thereof. Exemplary low-k dielectric materials include fluorosilicate glass (FSG), carbon doped oxide, black(Applied materials of Santa Clara, calif.), xerogels, aerogels, amorphous carbon fluorides, parylene, benzocyclobutene (BCB), silk (Dow chemical company of Midland, michigan), polyimides, other low-k dielectric materials, or combinations thereof. In some embodiments, insulating layer 115 includes a low-k dielectric material (such as carbon doped oxide) or an extremely low-k dielectric material (e.g., k.ltoreq.2.5) (such as porous carbon doped oxide).

The insulating layer 115 has a multilayer structure. For example, insulating layer 115 may include at least one inter-layer dielectric (ILD) layer, at least one Contact Etch Stop Layer (CESL) disposed between respective ILD layers, and at least one CESL disposed between respective ILD layers and device substrate 102. In such embodiments, the material of the CESL is different from the material of the ILD layer. For example, where the ILD layer comprises a low-k dielectric material (which includes silicon and oxygen), the CESL may include silicon and nitrogen (e.g., silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof) or other suitable dielectric materials. The ILD layer and/or CESL may have a multi-layer structure (with multiple dielectric materials). In some embodiments, each of the n-level interconnect layers to the (n+x) -level interconnect layers includes a respective ILD layer and/or a respective CESL of insulating layers 115, and respective metal lines 116 and vias 118 are located in the respective ILD layer and/or the respective CESL. In some embodiments, each of the M _n to M _n+x layers includes a respective ILD layer and/or a respective CESL of insulating layer 115, with a respective metal line 116 located in the respective ILD layer and/or the respective CESL. In some embodiments, each of the V _n to V _n+x layers includes a respective ILD layer and/or a respective CESL of insulating layer 115, with a respective via 118 located in the respective ILD layer and/or the respective CESL.

A Top Contact (TC) layer is disposed over the MLI feature 110 and, in the depicted embodiment, over the topmost metallization layer (i.e., the M ₁₀ layer) of the MLI feature 110. The TC layer includes patterned metal layers (i.e., groups of contacts 120 and contacts 122 (e.g., contact layers) arranged in a desired pattern and groups of vias 124 (e.g., via layers) arranged in a desired pattern) in respective portions of the insulating layer 115. The via layer (e.g., via 124) physically and/or electrically connects the contact layers (e.g., contacts 120 and 122) to the MLI component 110 (e.g., metal line 116 of the M _n+x layer). The contacts 120 and/or 122 may facilitate electrical connection of the MLI component 110 and/or the device substrate 102 to external circuitry, and thus may be referred to as external contacts. In some embodiments, contacts 120 and/or contacts 122 are Under Bump Metallization (UBM) structures. In some embodiments, insulating layer 115 includes at least one passivation layer. For example, the insulating layer 115 may include a passivation layer disposed over a topmost metallization layer (such as an M ₁₀ layer) of the MLI component 110. In such an embodiment, the TC layer may include a passivation layer with the contacts 120, the contacts 122, and the vias 124 disposed in the passivation layer. The passivation layer comprises a material that is different from the dielectric material of the underlying ILD layer of the MLI feature 110. In some embodiments, the passivation layer comprises polyimide, undoped Silicate Glass (USG), silicon oxide, silicon nitride, other suitable passivation materials, or combinations thereof. In some embodiments, the dielectric material of the passivation layer has a dielectric constant that is greater than the dielectric constant of the topmost ILD layer of the MLI feature 110. The passivation layer may have a multi-layered structure (with various dielectric materials). For example, the passivation layer may include a silicon nitride layer and a USG layer.

The metal lines 116, vias 118, contacts 120, contacts 122, and vias 124 comprise a metallic material including, for example, aluminum, copper, titanium, tantalum, tungsten, ruthenium, cobalt, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, alloys thereof, silicides thereof, or combinations thereof. In some embodiments, metal line 116, via 118, contact 120, contact 122, via 124, or a combination thereof, includes a bulk metal layer (also referred to as a metal fill layer, conductive plug, metal plug, etc.). In some embodiments, metal line 116, via 118, contact 120, contact 122, via 124, or a combination thereof, includes a barrier layer, an adhesive layer, other suitable layer, or a combination thereof, disposed between the bulk metal layer and insulating layer 115. The barrier layer may include titanium, titanium alloy (e.g., tiN), tantalum alloy (e.g., taN), other suitable barrier material (e.g., a material that may prevent diffusion of metal components from metal lines 116, vias 118, contacts 120, contacts 122, vias 124, or combinations thereof into a surrounding dielectric such as insulating layer 115), or combinations thereof. In some embodiments, the metal lines 116, vias 118, contacts 120, contacts 122, vias 124, or combinations thereof comprise different metal materials. For example, the lower metal lines 116 and/or vias 118 of the MLI component 110 comprise tungsten, ruthenium, cobalt, or combinations thereof, while the upper metal lines 116 and/or vias 118 of the MLI component 110 comprise copper. In some embodiments, the metal lines 116, vias 118, contacts 120, contacts 122, vias 124, or combinations thereof comprise the same metal material.

Each metallization layer is a patterned metal layer having metal lines 116, wherein the patterned metal layers have corresponding pitches. Thus, the metallization layers of the MLI components 110 may be grouped according to their respective pitches. The pitch of the patterned metal layer generally refers to the sum of the width of the metal lines of the patterned metal layer (e.g., metal lines 116) and the spacing between immediately adjacent metal lines of the patterned metal layer (i.e., the lateral distance between the edges of immediately adjacent metal lines 116 of the patterned metal layer). In some embodiments, the pitch of the patterned metal layer is the lateral distance between the centers of immediately adjacent metal lines 116 of the patterned metal layer. In fig. 1, metallization layers having the same pitch are grouped together. For example, MLI component 110 has a group of metallization layers 110a (with pitch P1), a group of metallization layers 110b (with pitch P2), and a group of metallization layers 110c (with pitch P3). Group 110a includes M ₁ layers to M ₇ layers, group 110B includes M ₈ layers and M ₉ layers, and group 110c includes M ₁₀ layers. Pitch P1, pitch P2, and pitch P3 are different. In the depicted embodiment, pitch P1 is less than pitch P2, and pitch P2 is less than pitch P3. In such an embodiment, the spacing of the metallization layers of the MLI feature 110 increases as the distance between the metallization layers and the front side 104 of the device substrate 102 increases. In some embodiments, pitch P1 is greater than pitch P2, and pitch P2 is greater than pitch P3. In some embodiments, pitch P1 is greater than pitch P2 and less than pitch P3. In some embodiments, pitch P1 is less than pitch P2 and greater than pitch P3. The MLI component 110 may include any number of groups of metallization layers (groups) with different pitches, depending on the IC technology node and/or the generation of the IC (e.g., 20nm, 5nm, etc.). In some embodiments, the MLI component 110 includes three to six sets of metallization layers with different pitches.

A Through Substrate Via (TSV) 130 (also referred to as a through silicon via or a semiconductor via) is disposed in insulating layer 115. The TSVs 130 are physically and/or electrically connected to the TC layer (e.g., respective vias 124 physically and electrically connect the TSVs to contacts 122, contacts 122 being connected to guard rings 140). TSV 130 extends from contact 122 through insulating layer 115 and through device substrate 102. In fig. 1, TSV 130 extends from side 104 to side 106 of device substrate 102 such that TSV 130 extends completely through device substrate 102.TSV 130 has a dimension D _TSV, such as a width or diameter, along the x-direction. Dimension D _TSV may also be referred to as the Critical Dimension (CD) of TSV 130. In some embodiments, dimension D _TSV is about 1 μm to about 18 μm. In fig. 2, the TSV 130 has a circular shape in a top view, and a dimension D _TSV represents the diameter of the TSV 130. In such an embodiment, TSV 130 may be a cylindrical structure that extends through insulating layer 115. TSVs 130 may have different shapes in top view, such as square shapes, diamond shapes, trapezoidal shapes, hexagonal shapes, octagonal shapes, or other suitable shapes.

In some embodiments, the TSV 130 has a substantially vertical sidewall profile, and the dimension D _TSV is substantially the same along the thickness T (e.g., in the z-direction) of the TSV 130. In such an embodiment, dimension D _TSV at the top of TSV 130 (e.g., the portion thereof interfacing with contact 122), dimension D _TSV at the middle of TSV 130 (e.g., the portion thereof at the interface of insulating layer 115 and device substrate 102), and dimension D _TSV at the bottom of TSV 130 (e.g., the portion thereof at side 106 of device substrate 102). For example, the ratio of the top CD of the TSV 130 (i.e., dimension D _TSV at the top of the TSV 130) to the middle CD of the TSV 130 (i.e., dimension D _TSV at the middle of the TSV 130) to the bottom CD of the TSV 130 (i.e., dimension D _TSV at the bottom of the TSV 130) is about 1:1:1. In some embodiments, dimension D _TSV varies along thickness T. For example, in the depicted embodiment, the TSV 130 has a tapered sidewall profile (i.e., tapered sidewall), and the dimension D _TSV decreases from the top of the TSV 130 to the bottom of the TSV 130. In such embodiments, the ratio of top CD to middle CD to bottom CD (top CD: middle CD: bottom CD) may be about 1:1:1 to about 4:2:1. In some embodiments, TSV 130 has a tapered sidewall profile, and dimension D _TSV increases from the top of TSV 130 to the bottom of TSV 130. In such embodiments, the ratio of top CD to middle CD to bottom CD may be about 1:1:1 to about 1:2:4. In some embodiments, the top CD is greater or less than the bottom CD. In some embodiments, dimension D _TSV may be substantially uniform along thickness T at portions of TSV 130, such as in device substrate 102 or insulating layer 115. The disclosed embodiments contemplate TSV 130 having any varying dimension D _TSV along its thickness T, depending on its sidewall profile configuration.

The aspect ratio of TSV 130 is given by the ratio of thickness T to dimension D _TSV (e.g., thickness T/dimension D _TSV). In some embodiments, TSV 130 has an aspect ratio of about 1 to about 20. The angle θ is between the sidewalls of the TSV 130 and the top surface of the device substrate 102 (i.e., its side 104). In some embodiments, the angle θ is about 70 ° to about 95 °. In the depicted embodiment, the angle θ is about an x-axis that is substantially parallel to the top surface of the device substrate 102. If the angle θ is too small (e.g., less than 70 °), the width of the opening in which the TSV 130 is formed may be too narrow and cause pinch-off during gap filling (i.e., filling the opening with the body layer 134), which may result in void formation in the TSV 130. On the other hand, if the angle θ is too large (e.g., greater than 95 °), the spacing between the TSV 130 and the guard ring 140 may be too small, which may result in damage to the guard ring 140 during manufacture of the TSV 130. In some embodiments, if angle θ is too large, TSV 130 may increase the effective resistance and/or decrease the capacitance, which may reduce device performance. In some embodiments, if the angle θ is too large, the TSV 130 spans a larger region of the device substrate 102, which may undesirably reduce the region of the device component used to form the device substrate 102.

TSV 130 comprises a conductive material including, for example, aluminum, copper, titanium, tantalum, tungsten, ruthenium, cobalt, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, alloys thereof, silicides thereof, or combinations thereof. In fig. 1, the TSV 130 has a multilayer structure. For example, TSV 130 includes a barrier layer 132 and a body layer 134 (also referred to as a metal fill layer, a conductive plug, a metal plug, etc.). The barrier layer 132 wraps around the body layer 134, and because the TSV 130 is fabricated as described herein, the barrier layer 132 is disposed along the top (rather than the bottom) and sidewalls of the body layer 134 (and thus along the top/front side (rather than the bottom/back side) and sidewalls of the TSV 130). Further, a barrier layer 132 is disposed between the bulk layer 134 and the TC layer (e.g., via 124), the barrier layer 132 is disposed between the bulk layer 134 and the insulating layer 115, and the barrier layer 132 is disposed between the bulk layer 134 and the device substrate 102.

In fig. 1, barrier layer 132 includes a dielectric liner 136 and a barrier/seed liner 138. A dielectric liner 136 is disposed between the barrier/seed liner 138 and the TC layer (e.g., via 124), the dielectric liner 136 is disposed between the barrier/seed liner 138 and the insulating layer 115, and the dielectric liner 136 is disposed between the barrier/seed liner 138 and the device substrate 102. Dielectric liner 136 comprises a dielectric material such as silicon oxide, silicon nitride, other suitable dielectric material, or a combination thereof. In the depicted embodiment, the dielectric liner 136 includes oxygen and may be referred to as an oxide liner. The barrier/seed liner 138 may include titanium, titanium alloy (e.g., tiN and/or TiC), tantalum alloy (e.g., taN and/or TaC), aluminum alloy (e.g., alON and/or Al ₂O₃), silicon (e.g., siO ₂), other suitable barrier/seed material (e.g., a material that may prevent diffusion of metal components from the bulk layer 134 into the insulating layer 115 and/or a material that may promote growth and/or deposition of the bulk layer 134), or a combination thereof. The bulk layer 134 comprises a conductive material such as aluminum, copper, titanium, tantalum, tungsten, ruthenium, cobalt, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, alloys thereof, silicides thereof, or combinations thereof. In some embodiments, the body layer 134 comprises copper (i.e., the TSV 130 comprises a copper plug), tungsten (i.e., the TSV 130 comprises a tungsten plug), or polysilicon (i.e., the TSV 130 comprises a polysilicon plug). The bulk layer 134, dielectric liner 136, barrier/seed layer 138, or a combination thereof may have a multi-layer structure.

Guard ring 140 is disposed in insulating layer 115 and around TSV 130. The guard ring 140 extends from the TC layer through the insulating layer 115 to the side 104 of the device substrate 102. A space S (also referred to as a distance) is located between the guard ring 140 and the TSV 130 in the x-direction, and the insulating layer 115 fills the space S between the guard ring 140 and the TSV 130. The guard ring 140 has a dimension D _b, such as a width or diameter, in the x-direction. The ratio of dimension D _b to dimension D _TSV may be configured to optimize spacing S. In some embodiments, the ratio of dimension D _b to dimension D _TSV is greater than zero and less than about two (i.e., 2>D _b/D_TSV > 0). The guard ring 140 is a circular ring around the TSV 130 from a top view (fig. 2), and the guard ring 140 extends continuously around the TSV 130. In such an embodiment, dimension D _b represents the inner diameter of the protective ring 140. In some embodiments, the protective ring 140 has other shapes in a top view. For example, the protective ring 140 may be a square ring, a hexagonal ring, an octagonal ring, or other suitably shaped ring. In some embodiments, the protective ring 140 is discontinuous (e.g., a ring formed of discrete segments).

The guard ring 140 is physically and/or electrically connected to the TC layer (e.g., the via 124 physically and electrically connects the guard ring 140 to the contact 122). The guard ring 140 may be physically and/or electrically connected to the device substrate 102. For example, the MEOL layer (i.e., device level contacts and/or vias) may physically and/or electrically connect the guard ring 140 to the device substrate 102, such as to doped regions (e.g., n-wells and/or p-wells) in the device substrate 102. In some embodiments, guard ring 140 is electrically connected to a voltage. In some embodiments, the guard ring 140 is electrically connected to electrical ground. In some embodiments, the guard ring 140 is configured to electrically insulate the TSV 130 from the MLI component 110, the device substrate 102, other device components and/or device assemblies, or a combination thereof. In some embodiments, guard ring 140 absorbs thermal and/or mechanical stresses from TSV 130, within TSV 130, and/or around TSV 130. In some embodiments, guard ring 140 reduces thermal and/or mechanical stresses from TSV 130, within TSV 130, and/or around TSV 130. Such stress may be due to TSV 130, device substrate 102, and/or insulating layer 115 having different Coefficients of Thermal Expansion (CTE). Such stresses may be generated during and/or after the manufacture of TSV 130. In some embodiments, the guard ring 140 reduces or eliminates cracking at the interface of the TSV 130 and the device substrate 102 (e.g., at the metal/semiconductor interface), which may be caused by the stresses described herein. In some embodiments, the guard ring 140 provides structural support, integrity, reinforcement, or a combination thereof for the TSV 130.

The guard ring 140 is fabricated with the MLI component 110, and the guard ring 140 may be considered part of the MLI component 110. For example, the guard ring 140 includes a stack of interconnect structures, wherein the interconnect structures are vertically stacked along the z-direction (or along the thickness direction of the TSV 130). Each interconnect structure includes a respective metal line 116 and a respective via 118. In fig. 1, the stack of interconnect structures includes an a interconnect structure, (a+b) interconnect structure, and intermediate interconnect structures therebetween (i.e., (a+1) interconnect structure, (a+2) interconnect structure, and so on), where a is an integer greater than or equal to 1, and b is an integer greater than or equal to 1. In the depicted embodiment, a is equal to n (e.g., a=1), b is equal to x (e.g., b=9), and the guard ring 140 has an interconnect structure corresponding to each hierarchical interconnect layer of the MLI component 110. For example, an a interconnect structure forms a conductive ring around the TSVs 130 in an n-level interconnect layer, an (a+1) interconnect structure forms a conductive ring around the TSVs 130 in an (n+1) level interconnect layer, and so on for an intermediate interconnect structure, and an (a+b) interconnect structure forms a conductive ring around the TSVs 130 in an (n+x) level interconnect layer. The disclosed embodiments contemplate that the guard ring 140 has a greater or lesser number of interconnect structures than the number of levels of interconnect layers of the MLI component 110. For example, the guard ring 140 may extend from an (n+x) level interconnect layer to an (n+5) level interconnect layer of the MLI component 110.

The semiconductor structure 100 may be attached (bonded) to another semiconductor structure to form an IC package or portion thereof. For example, fig. 3 is a cross-sectional view of a portion or an entirety of a semiconductor arrangement including a via (such as TSV 130) in accordance with aspects of an embodiment of the present disclosure. In fig. 3, semiconductor structure 100 is attached to semiconductor structure 160, and semiconductor structure 160 may be similar to semiconductor structure 100. For example, the semiconductor structure 160 includes a respective device substrate 102, a respective MLI component 110 (having a respective insulating layer 115, a respective metal line 116, and a respective via 118) disposed over the side 104 of the respective device substrate 102, and a respective TC layer (having a respective contact 120) disposed over the respective MLI component 110. In such an embodiment, the side 106 (e.g., backside) of the device substrate 102 of the semiconductor structure 100 is attached to the insulating layer 115 of the semiconductor structure 160, and the TSVs 130 of the semiconductor structure 100 are connected to the respective contacts 122 of the TC layer of the semiconductor structure 160. TSV 130 electrically and/or physically connects semiconductor structure 100 and semiconductor structure 160. In some embodiments, the bonding layer is located in the insulating layer 115 of the semiconductor structure 160 and between the TSV 130 and the contact 122 of the TC layer of the semiconductor structure 160. Semiconductor structure 100 and semiconductor structure 160 may be attached by a dielectric-to-dielectric bond (e.g., an oxide-to-oxide bond), a metal-to-metal bond (e.g., a copper-to-copper bond), a metal-to-dielectric bond (e.g., a copper-to-oxide bond), other types of bonds, or combinations thereof. For clarity, fig. 3 has been simplified to better understand the inventive concepts of the disclosed embodiments. Additional components may be added to the semiconductor arrangement and/or components thereof, and in other embodiments of the semiconductor arrangement and/or components thereof, some of the components described below may be replaced, modified, or eliminated.

In some embodiments, semiconductor structure 100 and semiconductor structure 160 are chips that include at least one functional IC, such as an IC configured to implement logic functions, memory functions, digital functions, analog functions, mixed signal functions, radio Frequency (RF) functions, input/output (I/O) functions, communication functions, power management functions, other functions, or a combination thereof. In such embodiments, TSVs 130 may be vertically physically and/or electrically connected to the chip. In some embodiments, semiconductor structure 100 and semiconductor structure 160 are chips (e.g., central Processing Units (CPUs)) that provide the same functionality. In some embodiments, semiconductor structure 100 and semiconductor structure 160 are chips (e.g., a CPU and a Graphics Processing Unit (GPU), respectively) that provide different functions. In some embodiments, semiconductor structure 100 and/or semiconductor structure 160 is a system on a chip (SoC), which generally refers to a single chip or monolithic die having multiple functions. In such embodiments, TSVs 130 may be vertically physically and/or electrically connected to the SOC. In some embodiments, the SoC is a single chip on which the entire system (such as a computer system) is fabricated.

In some embodiments, the semiconductor structure 100 is part of a chip-on-substrate (CoWoS) package, an integrated fan-out (InFO) package, an integrated system-on-chip (SoIC) package, other three-dimensional integrated circuit (3 DIC) package, or a hybrid package that implements a combination of multi-chip packaging techniques. In some embodiments, TSVs 130 of semiconductor structure 100 are physically and/or electrically connected to a package substrate, interposer, redistribution layer (RDL), printed Circuit Board (PCB), printed wiring board, other package structure and/or substrate, or a combination thereof. In some embodiments, TSVs 130 of semiconductor structure 100 are physically and/or electrically connected to controlled collapse chip connections (C4 bonds) (e.g., solder bumps and/or solder balls) and/or micro bumps (also referred to as micro bonds, μbumps, and/or μbonds), which are physically and/or electrically connected to the package structure.

Fig. 4 is a partial or complete cross-sectional view of another semiconductor arrangement including vias, such as TSV 130, in accordance with aspects of the embodiments of the present disclosure. In fig. 4, the front side and the back side of a semiconductor structure, such as semiconductor structure 170, may be attached (bonded) to the respective semiconductor structure to form an IC package or portion thereof. Semiconductor structure 170 is similar to semiconductor structure 100. For example, the semiconductor structure 170 has a respective device substrate 102 (having sides 104 and 106), a respective MLI component 110 (having a respective insulating layer 115, a respective metal line 116, a respective via 118, and a respective guard ring 140) disposed over the sides 104 of the respective device substrate 102, a respective TSV 130 extending through the insulating layer 115 and the device substrate 102, and a respective TC layer (having a respective contact 120 and/or contact 122) disposed over the respective MLI component 110. The semiconductor structure 170 also includes a top/front side interconnect feature 172 disposed over its respective MLI feature 110. The top/front side interconnect 172 may have an insulating layer (e.g., insulating layer 115) and metal lines 174, vias 176, and bond structures 178 (e.g., a single bond layer and/or a combination of bond layers/structures, such as bond vias and bond metal lines) disposed in the insulating layer. In some embodiments, one or more of the metal lines 174 are metal pads, such as aluminum pads. In some embodiments, the insulating layer includes one or more passivation layers and/or respective dielectric layers. For clarity, fig. 4 has been simplified to better understand the inventive concepts of the disclosed embodiments. Additional components may be added to the semiconductor arrangement and/or components thereof, and in other embodiments of the semiconductor arrangement and/or components thereof, some of the components described below may be replaced, modified, or eliminated.

In such an embodiment, the back side of the semiconductor structure 170 is formed by the side 106 of the device substrate 102, and the front side of the semiconductor structure 170 is formed by the top/front side interconnect feature 172 (here, the bonding structure 178 and the insulating layer 115). In fig. 4, the front side of semiconductor structure 170 is attached to semiconductor structure 180, and semiconductor structure 180 may be similar to semiconductor structure 170. For example, the semiconductor structure 180 includes a respective device substrate 102, a respective MLI feature 110 (having a respective insulating layer 115, a respective metal line 116, and a respective via 118) disposed over a side 104 of the respective device substrate 102, a respective TC layer (having a respective contact 120) disposed over the respective MLI feature 110, and a respective top/front side interconnect feature 172 (having a respective metal line 174, a respective via 176, and a respective bonding structure 178), wherein the respective top/front side interconnect feature 172 forms a top/front side of the semiconductor structure 180. Thus, the front side of semiconductor structure 170 is attached to the front side of semiconductor structure 180, and semiconductor structure 170 and semiconductor structure 180 are physically and/or electrically connected by bonding structure 178. In addition, the TSVs 130 of the semiconductor structure 170 may be connected to the semiconductor structure 180 through the TC layer and the top/front side interconnect feature 172 of the semiconductor structure 170. Thus, the TSV 130 may be electrically connected to the semiconductor structure 180. In some embodiments, devices at side 104 of semiconductor structure 170 are electrically connected to devices at side 104 of semiconductor structure 180 through MLI feature 110 and/or top/front side interconnect feature 172 thereof. Semiconductor structure 170 and semiconductor structure 180 may be attached by a dielectric-to-dielectric bond (e.g., an oxide-to-oxide bond), a metal-to-metal bond (e.g., a copper-to-copper bond), a metal-to-dielectric bond (e.g., a copper-to-oxide bond), other types of bonds, or combinations thereof. In some embodiments, semiconductor structure 170 and semiconductor structure 180 are chips that include at least one functional IC. The chips may be of the same or different types. In some embodiments, semiconductor structure 170 and semiconductor structure 180 are logic chips.

In some embodiments, the semiconductor structure 170 further includes a bottom/backside interconnect feature 190 disposed over the side 106 of the device substrate 102. The bottom/backside interconnect feature 190 may include an insulating layer 192 (similar to insulating layer 115 and/or portions thereof forming the top/front side interconnect feature 172), metal lines 194, vias 196, and Under Bump Metallization (UBM) features 198 disposed in the insulating layer 192. In fig. 4, TSVs 130 of semiconductor structure 170 are physically and/or electrically connected to bottom/backside interconnect 190, which bottom/backside interconnect 190 may be connected to external circuitry. In some embodiments, the insulating layer 192 includes one or more passivation layers and/or respective dielectric layers. In some embodiments, one or more of the metal lines 194 are metal pads, such as aluminum pads. In some embodiments, UBM component 198 may provide a low resistance electrical connection to semiconductor structure 170. In some embodiments, UBM component 198 includes multiple layers of different metals, such as an adhesion layer (e.g., ti, cr, al, other metals, or combinations thereof), a diffusion barrier layer (e.g., crCu alloy and/or other suitable metals), a solderable layer, and an oxidation barrier layer (e.g., au and/or other suitable metals). The various layers of UBM feature 198 may be deposited by electroplating, sputtering, evaporation, other methods, or combinations thereof. In some embodiments, the bottom/backside interconnect features 190 are or form part of a redistribution layer (RDL) and/or redistribution structure that includes individual metal lines for redistributing the bond pads to different locations, such as from peripheral locations to locations uniformly distributed over the chip surface. In some embodiments, the RDL may couple the semiconductor structure 170 to a bond pad for connection to external circuitry and/or another semiconductor structure.

Fig. 5A-5O are partial or complete cross-sectional views of a workpiece 200 at various stages of manufacture in forming TSVs in accordance with various aspects of an embodiment of the present disclosure. Fig. 6A-6E are partial or complete cross-sectional views of a portion of a workpiece 200 at various stages of manufacture in forming a TSV trench (which may be implemented at the stages of manufacture associated with fig. 5E) in accordance with various aspects of an embodiment of the present disclosure. For ease of description and understanding, the following discussion of fig. 5A-5O and fig. 6A-6E is directed to fabricating the semiconductor structure 100 of fig. 1 and 2, the semiconductor structure 100 including the TSV 130 and the guard ring 140. Embodiments of the present disclosure contemplate embodiments that implement processes related to fig. 5A-5O and/or fig. 6A-6E to fabricate workpieces having differently configured TSVs 130 and/or guard rings 140, such as those described herein. For clarity, fig. 5A-5O and fig. 6A-6E have been simplified to better understand the inventive concepts of the disclosed embodiments. Additional components may be added to the workpiece 200, and in other embodiments of the workpiece 200, some of the components described below may be replaced, modified, or eliminated.

Referring to fig. 5A-5C, after the workpiece 200 has undergone FEOL processing and MEOL processing, the workpiece 200 undergoes BEOL processing to form the MLI feature 110 over the device region 202A and/or the device region 202B of the device substrate 102. The MLI component 110 may be physically and/or electrically connected to devices, such as a device 204A (e.g., a transistor) formed in the device region 202A and/or a device 204B (e.g., another transistor) formed in the device region 202B. The guard ring 140 may be formed over the intermediate region 202C of the device substrate 102 at the same time as the MLI feature 110 is formed. The guard ring 140 may be physically and/or electrically connected to a doped region, such as an n-well or a p-well, formed in the device substrate 102. The guard ring 140 is a conductive ring (e.g., a metal ring) having an inner dimension D _b that defines the dielectric region 210 of the insulating layer 115. As described further below, TSV 130 is formed to extend through dielectric region 210.

In fig. 5A, a first level interconnect layer (i.e., V ₁ layer and M ₁ layer) of the MLI feature 110 and a first interconnect structure (e.g., interconnect structure) of the guard ring 140 are formed over the device substrate 102. For example, a patterned via layer (i.e., via 118) is formed over the device substrate 102, and a patterned metal layer (i.e., metal line 116) is formed over the patterned via layer. In some embodiments, the patterned via layer is formed by: depositing a portion of insulating layer 115 over the MEOL layer; photolithography and etching processes are performed to form openings in portions of insulating layer 115 that expose underlying conductive features (e.g., contacts and/or vias, such as gates and/or source/drains, of MEOL layers or device features); filling the opening with a conductive material; and performing a planarization process that removes excess conductive material, wherein the remaining conductive material filling the opening provides a via 118. After the planarization process, the via 118 and portions of the insulating layer 115 may form a substantially planar common surface. In some embodiments, the patterned metal layer is formed by: depositing a portion of insulating layer 115 over the patterned via layer; photolithography and etching processes are performed to form openings (e.g., vias 118 of the first level interconnect layer and vias of the first interconnect structure) in portions of the insulating layer 115 that expose underlying conductive features; filling the opening with a conductive material; and performing a planarization process that removes excess conductive material, wherein the remaining conductive material filling the opening provides metal line 116. After the planarization process, portions of metal line 116 and insulating layer 115 may form a substantially planar common surface. In some embodiments, the via 118 and the metal line 116 are formed by respective single damascene processes (i.e., the via 118 is formed separately from its corresponding upper and/or lower metal line 116). In some embodiments, the via 118 and the metal line 116 are formed by a dual damascene process, as described further below.

In some embodiments, depositing portions of insulating layer 115 includes depositing an ILD layer. In some embodiments, depositing the portion of insulating layer 115 includes depositing a CESL prior to depositing the ILD layer such that the ILD layer is deposited over the CESL. Portions of insulating layer 115 (e.g., ILD layer and/or CESL) are formed by Chemical Vapor Deposition (CVD), plasma Enhanced CVD (PECVD), high Density Plasma CVD (HDPCVD), flowable CVD (FCVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), metal Organic Chemical Vapor Deposition (MOCVD), remote Plasma CVD (RPCVD), low Pressure CVD (LPCVD), atomic Layer CVD (ALCVD), atmospheric Pressure CVD (APCVD), other suitable deposition methods, or combinations thereof. A planarization process may be performed after depositing portions of insulating layer 115.

In some embodiments, the first level interconnect layer of the MLI feature 110 and/or the first interconnect structure of the guard ring 140 is formed by a dual damascene process, which may involve simultaneously depositing conductive material for the via/metal line pair. In such embodiments, the vias 118 and the metal lines 116 may share a barrier layer and a conductive plug, rather than each having a respective and distinct barrier layer and conductive plug (e.g., where the barrier layer of a respective metal line 116 separates the conductive plug of a respective metal line 116 from the conductive plug of its corresponding respective via 118). In some embodiments, the dual damascene process includes performing a patterning process to form interconnect openings extending through insulating layer 115 to expose underlying conductive features. The patterning process may include: a first photolithography step and a first etching step to form a trench opening of an interconnect opening (which corresponds to the metal line 116 and defines the metal line 116) in the insulating layer 115; and a second photolithography step and a second etching step to form via openings (which correspond to the vias 118 and define the vias 118) of the interconnect openings in the insulating layer 115. The first lithography/first etching step and the second lithography/second etching step may be performed in any order (e.g., trench-first-via or trench-first-via). The first etching step and the second etching step are each configured to selectively remove the insulating layer 115 with respect to the patterned mask layer. The first and second etching steps may be a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof.

After performing the patterning process, the dual damascene process may include: performing a first deposition process to form a barrier material over insulating layer 115 that partially fills the interconnect openings; and performing a second deposition process to form a body conductive material over the barrier material, wherein the body conductive material fills the remaining portion of the interconnect opening. In such an embodiment, the barrier material and the bulk conductive material are disposed in the interconnect opening and over the top surface of insulating layer 115. The first deposition process and the second deposition process may include CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, electroplating, electroless plating, other suitable deposition methods, or combinations thereof. A CMP process and/or other planarization process is then performed to remove excess bulk conductive material and barrier material from over the top surface of portions of insulating layer 115, resulting in a patterned via layer (e.g., via 118) and a patterned metal layer (e.g., metal line 116) of the first level interconnect layer of MLI feature 110 and a corresponding first interconnect structure of guard ring 140. The CMP process planarizes the top surfaces of insulating layer 115 and via 118 and/or metal line 116. The barrier material and the bulk conductive material may fill the trench openings and via openings of the interconnect openings without interruption, such that the barrier layer and the conductive plugs of the metal lines 116 and the vias 118 may each extend continuously from the metal lines 116 to the respective vias 118 without interruption.

In fig. 5B, the second-to sixth-level interconnect layers (i.e., (n+1) -to (n+5) -level interconnect layers) of the MLI component 110 are formed above the first-level interconnect layer. The second to sixth interconnect structures (i.e., (a+1) to (a+5) interconnect structures) of the guard ring 140 are formed simultaneously with the formation of the second to sixth level interconnect layers, respectively. Each of the second to sixth level interconnect layers of the MLI component 110 and the second to sixth interconnect structures of the guard ring 140 corresponding thereto may be formed as described above with reference to the fabrication of the first level interconnect layer of the MLI component 110 and the first interconnect structure of the guard ring 140.

In fig. 5C, seventh to tenth level interconnect layers (i.e., (n+6) to (n+x) level interconnect layers) of the MLI component 110 are formed over the sixth level interconnect layer. The seventh to tenth interconnect structures (i.e., (a+6) to (a+b) interconnect structures) of the guard ring 140 are formed simultaneously with the formation of the seventh to tenth interconnect layers, respectively. Each of the seventh to tenth level interconnect layers of the MLI component 110 and the seventh to tenth interconnect structures of the guard ring 140 corresponding thereto may be formed as described above with reference to fabrication of the first level interconnect layer of the MLI component 110 and the first interconnect structure of the guard ring 140. In fig. 5A-5C, for a given level of interconnect layer, the metal lines 116 and vias 118 of the interconnect structure of the guard ring 140 at the given level of interconnect layer may be formed simultaneously (e.g., by the same patterning process and deposition process), partially simultaneously (e.g., by the same patterning process but a different deposition process, and vice versa), or separately (e.g., by a different patterning process and a different deposition process), respectively, with the metal lines 116 and vias 118 of the given level of interconnect layer.

In fig. 5D, a trench 220 is formed in the dielectric region 210 of the insulating layer 115. Trenches 220 extend through insulating layer 115 to expose sides 104 of device substrate 102. The trench 220 has a width W ₁ in the x-direction that is less than the inner dimension D _b of the guard ring 140. The width W ₁ may be substantially the same as the desired width of the TSV 130. In some embodiments, width W ₁ is about dimension D _TSV. In some embodiments, forming trench 220 includes: forming a patterned mask layer 222 having an opening 224 therein exposing dielectric region 210 of insulating layer 115; and etching the insulating layer 115 using the patterned mask layer as an etching mask. The etching is a dry etching process, a wet etching process, other etching processes, or a combination thereof. The width of the opening 224 may be configured to provide a desired spacing between the guard ring 140 and the subsequently formed TSV 130. For example, the openings 224 are provided with a width approximately equal to a desired width and/or a desired diameter of the TSVs 130. In some embodiments, the ratio of the width of dimension D _b to opening 224 is substantially the same as the ratio of dimension D _b to dimension D _TSV. Controlling the spacing between the guard ring 140 and the trench 220 may reduce defects that may result from extending the trench 220 into the device substrate 102 (i.e., defects caused by the TSV drilling process).

Patterned mask layer 222 may be formed using a photolithographic process that may include resist coating (e.g., spin coating), pre-exposure bake (e.g., soft bake), mask alignment, exposure, post-exposure bake, developing resist, rinsing, drying (e.g., hard bake), other suitable process, or combinations thereof. In some embodiments, patterned masking layer 222 is a hard mask layer, such as a silicon nitride layer, a silicon oxynitride layer, or other suitable layer including a suitable hard mask material. In some embodiments, patterned masking layer 222 is a patterned resist layer. In some embodiments, the patterned mask layer 222 has a multi-layered structure, such as a resist layer and a hard mask layer. For example, a hard mask layer is deposited over insulating layer 115, a photolithography process is performed to form a patterned resist layer over the hard mask layer (e.g., spin-on, exposure, development, etc.), and an etching process removes the exposed portions of the hard mask layer to form a patterned hard mask layer, wherein the etching process may use the patterned resist layer as an etching mask.

In fig. 5E, the trench 220 is extended to a depth d in the device substrate 102 by a suitable process, such as an etching process. The depth d is less than the thickness of the device substrate 102 (e.g., the thickness of the device substrate 102 in the z-direction (i.e., from side 104 to side 106)). In some embodiments, the depth d is about 3 μm to about 10 μm. In some embodiments, trenches 220 extend at sides 104 beyond active devices, passive devices, and/or device components formed within and/or on device substrate 102 (e.g., trenches 220 extend farther in device substrate 102 than isolation structures formed therein). In some embodiments, the trenches 220 extend through the device substrate 102, such as from side 104 to side 106 (i.e., depth d is equal to the thickness of the device substrate 102). The etching process is a dry etching process, a wet etching process, other etching processes, or a combination thereof. In some embodiments, the etching process is a dry etching process, such as an isotropic dry etching (i.e., an etching process that will remove material in more than one direction, such as vertically in the z-direction and laterally in the x-direction). In some embodiments, the etching process is a plasma etching process. In some embodiments, the trenches 220 extend into the device substrate 102 by a laser drilling process. In some embodiments, the etching process uses the patterned mask layer 222 as an etching mask, and after the trenches 220 are extended into the device substrate 202 by a suitable process (such as a lift-off process, an ashing process, an etching process, or a combination thereof), the patterned mask layer 222 is removed. In some embodiments, patterned masking layer 222 is removed prior to extending trenches 220 into device substrate 202 by a suitable process.

In some embodiments, a Bosch (Bosch) process, such as depicted in fig. 6A-6E, is implemented to extend the trenches 220 into the device substrate 102. The bosch process is generally referred to as an high aspect ratio plasma etch process that involves alternating etch and deposition phases, wherein a cycle includes an etch phase and a deposition phase, and the cycle is repeated until trench 220 has a desired depth d. For example, the bosch process may include: a first gas (e.g., a fluorine-containing gas such as SF ₆) is introduced into the process chamber to etch the device substrate 102 (e.g., silicon) and extend the trenches 220 to a depth d ₁ (fig. 6A, etch stage) of the device substrate 102 that is less than depth d; stopping and/or reducing the first gas and introducing and/or adding a second gas (e.g., a fluorine-containing gas such as C ₄F₈) into the process chamber, which forms a protective layer 226 over the surfaces of the device substrate 102 where the trenches 220 are formed (fig. 6B, deposition phase); stopping and/or reducing the second gas and introducing and/or adding the first gas into the process chamber to further etch the device substrate 102 and extend the trenches 220 to a depth d2 of the device substrate 102 that is less than the depth d (fig. 6C, etch stage); stopping and/or reducing the first gas and introducing and/or adding the second gas into a process chamber that forms a protective layer 226 (also referred to as a polymer layer or passivation layer) over the exposed surfaces of the device substrate 102 that form the trenches 220 (fig. 6D, deposition phase); and repeating the cycle of the bosch process (i.e., the etch phase plus the polymer deposition phase) until the trenches 220 extend a depth d in the device substrate 102 (fig. 6E). Each etching stage may remove portions of the protective layer 226 that cover the surfaces of the device substrate 102 that form the bottom of the trench 220, but does not (or minimally) remove portions of the protective layer 226 that cover the surfaces of the device substrate 102 that form the sidewalls of the trench 220. The protective layer 226 may include fluorine and carbon (i.e., a fluorocarbon based layer). The bosch process may use the patterned mask layer 228 as an etch mask having openings therein that overlap with the trenches 220 in the insulating layer 115. In some embodiments, when forming the trench 220 in the insulating layer 115 in fig. 5D, a patterned mask layer 228 is formed that serves as an etch mask. In other words, patterned mask layer 228 may be patterned mask layer 222 in fig. 5D.

In fig. 6E, because the bosch process laterally etches (and vertically etches) the device substrate 102 during the etching phase, the trenches 220 may have scalloped sidewalls, wavy sidewalls, roughened sidewalls, or a combination thereof formed by the curved segments/surfaces 230 of the device substrate 102. The rough sidewalls may adversely affect the subsequently formed TSVs 130. For example, the TSVs 130 may delaminate from scalloped sidewalls of the device substrate 102. Thus, referring to fig. 5F, a smoothing process may be performed on the sidewalls of the trenches 220. Parameters of the smoothing process are adjusted to remove scalloped sidewalls, wavy sidewalls, rough sidewalls, or combinations thereof that form the trenches 220. For example, after the smoothing process, the trench 220 has substantially linear sidewalls and/or substantially planar sidewalls 232. In some embodiments, the smoothing process is an etching process that selectively removes semiconductor material (e.g., silicon portions of the device substrate 102) with minimal (to no) removal of dielectric material (e.g., the insulating layer 115). The etching process is a dry etching process, a wet etching process, other etching processes, or a combination thereof. In some embodiments, the smoothing process also removes the protective layer 226 from the trench 220. In some embodiments, the smoothing process may not be performed before continuing to form TSV 130 in trench 220, and protective layer 226 may be removed by a suitable process (such as an etching process). In some embodiments, the sidewalls of the trenches 220 are smoothed and the protective layer 226 is removed by a different process. Patterned masking layer 222 may be removed before or after the smoothing process.

In fig. 5F, the trench 220 has a depth D and a width W ₁. In some embodiments, the depth D is about 5 μm to about 100 μm. In some embodiments, the width W ₁ (in some embodiments, the diameter of the trench 220) is about 1 μm to about 18 μm. The trench 220 may have an aspect ratio. For example, the aspect ratio (i.e., the ratio of depth D to width W ₁) is greater than about 10. In some embodiments, the aspect ratio is about 5 to about 20. Typically, fabrication continues by depositing a conductive material (e.g., copper) filling trench 220 over insulating layer 115 (and thus over side 104 of device substrate 102), performing a planarization process that removes the conductive material from over the top surface of insulating layer 115, and thinning device substrate 102 from side 106 to expose the conductive material. Because trench 220 has a high aspect ratio and/or a large depth, the conductive material may fill or close portions of trench 220 before trench 220 is completely filled (i.e., pinch-off occurs during gap filling). This creates voids (seams) and/or keyholes in the conductive material. Voids and/or keyholes may reduce the electrical performance of TSV 130 and/or semiconductor structure 100, for example, by increasing resistance and/or inhibiting electrical communication between device components of the stacked ICs. In addition, because portions of the conductive material are often removed when thinning the device substrate 102, typical TSV fabrication techniques use more conductive material than is needed, thereby increasing fabrication costs. As described herein, the disclosed TSV fabrication techniques address these issues by reducing the aspect ratio and/or depth of the TSV opening (trench 220) prior to forming the TSV 130 therein and thinning the device substrate 102 prior to forming the TSV 130, which may minimize and/or prevent pinch-off (and thus inhibit void formation in the TSV 130) and eliminate conductive material wastage.

In fig. 5G, the fabrication continues with a TSV dielectric gap filling step that includes forming a dielectric layer 240 that fills trench 220 over insulating layer 115. Thus, the dielectric layer 240 is formed over the side 104 (e.g., front side) of the device substrate 102. Portions of dielectric layer 240 fill trenches 220 and extend through insulating layer 115 and to device substrate 102. The portion of dielectric layer 240 has a thickness T ₁ and a width W ₁, the thickness T ₁ being substantially the same as the depth D of trench 220. The composition of dielectric layer 240 is different from the composition of insulating layer 115 and the composition of device substrate 102 to achieve etch selectivity during subsequent processing. In other words, dielectric layer 240, insulating layer 115, and device substrate 102 comprise materials having different etch sensitivities to a given etchant, such that dielectric layer 240 may be selectively etched/removed with minimal (to no) etching/removal of insulating layer 115 and/or device substrate 102. In some embodiments, dielectric layer 240 includes an oxide material, such as a silicon oxide material. In some embodiments, the dielectric layer 240 comprises the same oxide material as the oxide material of the isolation structures (e.g., STI) in the device substrate 102. In some embodiments, the dielectric layer 240 includes a flowable oxide material, such as an oxide material formed by FCVD. In some embodiments, dielectric layer 240 includes a gap-fill oxide material, such as an oxide material formed by ALD. Dielectric layer 240 may be formed by CVD, PECVD, HDPCVD, FCVD, MOCVD, RPCVD, LPCVD, ALCVD, APCVD, other deposition processes, or a combination thereof. In some embodiments, a planarization process (e.g., CMP) is performed to remove dielectric layer 240 from over the top surface of insulating layer 115 and/or the top surface of the top patterned metal layer (such as the metal layer formed by top metal line 116). In such embodiments, the planarization process may stop when the insulating layer 115 and/or the top patterned metal layer are reached, and the planarization process may planarize the top surface of the insulating layer 115, the top surface of the top patterned metal layer, and the top surface of the remaining portion of the dielectric layer 240. Further, in such embodiments, the remaining portion of dielectric layer 240 (which fills trench 220) may be referred to as a dielectric plug.

In fig. 5H, a thinning process is performed on the device substrate 102 to expose the dielectric layer 240 such that the dielectric layer 240 extends through the device substrate 102. For example, after the thinning process, the dielectric layer 240 extends from the side 104 (e.g., front side) to the side 106 (e.g., back side) of the device substrate 102. The thinning process is a grinding process, a planarization process (e.g., CMP), an etching process, other suitable processes, or a combination thereof. A thinning process is applied to the side 106 of the device substrate 102. The dielectric layer 240 maintains the shape and/or profile of the trench 220 during the thinning process. In some embodiments, the workpiece 200 is attached to a carrier wafer (substrate) prior to performing the thinning process. For example, the dielectric layer 240 may be attached/bonded to the carrier wafer prior to the thinning process. In another example, such as where a planarization process is performed to expose insulating layer 115 prior to the thinning process, insulating layer 115, a top patterned metal layer (e.g., top metal line 116), dielectric layer 240, or a combination thereof may be attached/bonded to the carrier wafer prior to the thinning process.

The thinning process reduces the thickness of the device substrate 102 in the z-direction. For example, the thinning process removes the thickness t of the device substrate 102. In some embodiments, the thickness t is about 1 μm to about 95 μm. In some embodiments, the thickness t is greater than about 10 μm. In the depicted embodiment, the thinning process removes the portion of dielectric layer 240 that fills trench 220 such that the portion of dielectric layer 240 that fills trench 220 has a thickness T ₂ after the thinning process. Thickness T ₂ is less than thickness T ₁, and thickness T ₂ is substantially the same as the desired thickness (e.g., thickness T) of a subsequently formed TSV (e.g., TSV 130). Because the trench 220 is filled with the dielectric layer 240 instead of the TSV, the thickness of the device substrate 102 removed during the thinning process is greater than that which can be removed when the thinning process is performed after the TSV is formed in the trench 220. Accordingly, the aspect ratio of the trench 220 may be reduced before the TSV is formed therein, which may improve the gap filling. In some embodiments, the thinning process stops when the dielectric layer 240 is reached, such that the portion of the dielectric layer 240 filling the trench 220 has a thickness T ₁ after the thinning process. In such an embodiment, the thickness T ₁ is substantially the same as the desired thickness of the subsequently formed TSV.

In fig. 5I, dielectric layer 240 is removed from workpiece 200 to provide TSV opening 250 (which corresponds to trench 220 having a smaller aspect ratio). TSV opening 250 has a length L and a width W ₂. Before forming dielectric layer 240 therein, length L is less than depth D of trench 220 (and thus less than thickness T ₁ of dielectric layer 240), and length L is substantially the same as the desired thickness of TSV 130 (e.g., length l≡thickness T). Thus, prior to forming the dielectric layer 240 therein and performing the thinning process, the aspect ratio (i.e., the ratio of the length L to the width W ₂) of the TSV opening 250 is less than the aspect ratio (i.e., the ratio of the depth D to the width W ₁) of the trench 220. For example, the aspect ratio of TSV opening 250 is less than about 10, such as about 1.5 to about 10. In some embodiments, the aspect ratio of TSV opening 250 is about 1.5 to about 20. In some embodiments, the length L is about 3 μm to about 98 μm. Width W ₂ is substantially the same as the desired thickness of TSV 130 (e.g., width W ₂ ≡width W), and width W ₂ is greater than or equal to width W ₁. In some embodiments, the width W ₂ is about 1 μm to about 18 μm.

The etching process is configured to selectively remove dielectric layer 240 relative to insulating layer 115, metal lines 116, device substrate 102, or a combination thereof. For example, the etching process removes dielectric layer 240, but does not remove or negligibly remove insulating layer 115, metal lines 116, device substrate 102, or a combination thereof. For example, an etchant is selected for the etching process that etches the dielectric layer 240 (e.g., a dielectric material having a first composition) at a higher rate than the material of the insulating layer 115 (e.g., a dielectric material having a second composition different from the first composition), the metal lines 116 (e.g., a metal material), the device substrate 102 (e.g., a semiconductor material), or a combination thereof (i.e., the etchant has a high etch selectivity relative to the dielectric layer 240 (e.g., a dielectric material having a first composition). The etching process is a dry etching process, a wet etching process, other etching processes, or a combination thereof. In some embodiments, the etching process is a two-step process, such as a first etching process that uses a first etchant to selectively remove dielectric layer 240 relative to insulating layer 115, and a second etching process that uses a second etchant to selectively remove dielectric layer 240 relative to device substrate 102. In some embodiments, a single etchant selectively removes dielectric layer 240 relative to insulating layer 115 and device substrate 102. Various parameters (e.g., etchant type, etching time, etching pressure, etching temperature, etc.) may be adjusted to achieve selective etching of the dielectric layer 240. In some embodiments, a cleaning process and/or a surface treatment process (collectively referred to as a cleaning process) is performed after the etching process to remove defects, such as any native oxide, contaminants, residues of the dielectric layer 240, or combinations thereof, from the insulating layer 115 and/or the surfaces of the device substrate 102 defining/forming the TSV opening 250. In some embodiments, the etching process uses a patterned mask layer as an etching mask, wherein the patterned mask layer covers a top surface of insulating layer 115 and a top surface of a top patterned metal layer, the patterned mask layer exposes dielectric layer 240 (e.g., a dielectric plug), and the patterned mask layer is removed during and/or after removal of dielectric layer 240.

In fig. 5J-5N, fabrication continues with the formation of TSV 130 in TSV opening 250. In fig. 5J, a dielectric layer 136' is formed that partially fills TSV opening 250. In the depicted embodiment, prior to forming TSV 130, workpiece 200 is flipped such that device substrate 102 forms the top of workpiece 200 instead of insulating layer 115. Because the workpiece 200 is flipped over, the dielectric layer 136' is formed over and covers the side 106 of the device substrate 102, the sidewalls of the TSV opening 250 (here, formed by the insulating layer 115), and the top/bottom of the TSV opening 250 (here, formed in the insulating layer 115 and extending between the sidewalls of the TSV opening 250) and covering the side 106 of the device substrate 102, the sidewalls of the TSV opening 250, and the top/bottom of the TSV opening 250. Dielectric layer 136' has vertically oriented segments (i.e., portions of the sidewalls of liner TSV openings 250) and horizontally oriented segments (i.e., portions of the top/bottom of liner TSV openings 250) extending between the vertically oriented segments. Vertically oriented segments are disposed in insulating layer 115 and device substrate 102, while horizontally oriented segments are disposed in insulating layer 115. In some embodiments, the workpiece 200 is attached to a carrier wafer (substrate) 255 prior to forming the TSVs 130. For example, the insulating layer 115 and/or the top patterned metal layer (e.g., top metal line 116) may be attached/bonded to the carrier wafer 255 prior to forming the dielectric layer 136', and then the workpiece 200 may be flipped over. In such an embodiment, carrier wafer 255 forms the top/bottom of TSV opening 250, and dielectric layer 136' covers carrier wafer 255.

Dielectric layer 136' comprises a dielectric material that may include silicon, oxygen, carbon, nitrogen, other suitable dielectric components, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.). For example, dielectric layer 136' includes oxygen and is referred to as an oxide layer. In some embodiments, dielectric layer 136 'further comprises silicon, and dielectric layer 136' is a silicon oxide layer. In some embodiments, dielectric layer 136' is a TEOS oxide layer. In some embodiments, dielectric layer 136' is a silicon nitride layer. Dielectric layer 136' is formed by CVD (e.g., PECVD and/or LPCVD), thermal oxidation, chemical oxidation, other suitable deposition processes, or a combination thereof. In the depicted embodiment, the dielectric layer 136 'is conformally deposited over the workpiece 200 such that the dielectric layer 136' has a substantially uniform thickness.

In fig. 5K, a barrier/seed layer 138 'is formed over dielectric layer 136' that partially fills TSV opening 250. Because the workpiece 200 is flipped over, the barrier/seed layer 138 'is formed over the side 106 (e.g., backside) of the device substrate 102, and the barrier/seed layer 138' is disposed over the side 106 of the device substrate 102, the sidewalls of the TSV opening 250, and the top/bottom of the TSV opening 250. The barrier/seed layer 138' has vertically oriented segments (i.e., portions of the sidewalls of the liner TSV openings 250) and horizontally oriented segments (i.e., portions of the top/bottom of the liner TSV openings 250) extending between the vertically oriented segments. Vertically oriented segments are disposed in insulating layer 115 and device substrate 102, while horizontally oriented segments are disposed in insulating layer 115. The barrier/seed layer 138' is formed by PVD, CVD, ALD, other suitable deposition processes, or a combination thereof. In the depicted embodiment, the barrier/seed layer 138 'is conformally deposited over the workpiece 200 such that the barrier/seed layer 138' has a substantially uniform thickness.

The barrier/seed layer 138 'includes a material that may prevent diffusion of metal from a subsequently formed bulk layer into the insulating layer 115, promote growth and/or deposition of a subsequently formed bulk layer, promote adhesion of a subsequently formed bulk layer and a dielectric material (e.g., the dielectric layer 136' and/or the insulating layer 115), or a combination thereof. For example, the barrier/seed layer 138' includes titanium, a titanium alloy (e.g., tiN, tiSiN, tiC or a combination thereof), tantalum, a tantalum alloy (e.g., taN and/or TaC), tungsten, a tungsten alloy (e.g., WN), aluminum, an aluminum alloy (e.g., alON and/or Al ₂O₃), silicon (e.g., siO ₂), other suitable barrier/seed material, or a combination thereof. In some embodiments, the barrier/seed layer 138 'has a multi-layer structure, such as a barrier layer (e.g., comprising a material that can inhibit metal diffusion) over the dielectric layer 136' and a seed layer (e.g., comprising a material that can promote deposition and/or adhesion of a subsequently formed bulk layer) over the barrier layer. For example, the barrier/seed layer 138' may include a metal nitride barrier layer and a copper seed layer. In some embodiments, the barrier layer and/or the seed layer has a multilayer structure. For example, the barrier layer may include a metal nitride layer (e.g., a TaN layer or TiN layer) and a metal layer (e.g., a Ta layer or Ti layer).

In fig. 5L, a body layer 134 'is formed over the barrier/seed layer 138' filling the remainder of the TSV opening 250. Because the workpiece 200 is flipped, the bulk layer 134' is formed over the side 106 (e.g., backside) of the device substrate 102. In addition, because the aspect ratio of the TSV opening 250 is less than the aspect ratio of the trench 220, the body layer 134' fills the TSV opening 250 with minimal to no voids and/or keyholes formed therein. The bulk layer 134' comprises a conductive material such as aluminum, copper, titanium, tantalum, tungsten, ruthenium, cobalt, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, alloys thereof, silicides thereof, or combinations thereof. In some embodiments, bulk layer 134' includes copper. In some embodiments, bulk layer 134' comprises tungsten. In some embodiments, bulk layer 134' comprises polysilicon. In some embodiments, the bulk layer 134' has a multi-layer structure. The bulk layer 134' is formed by electrochemical plating (ECP), electroplating, electroless plating, PVD, CVD, other suitable deposition process, or combinations thereof. In the depicted embodiment, the bulk layer 134' is blanket deposited over the workpiece 200.

In fig. 5M, a planarization process (e.g., CMP) is performed on the workpiece 200. The planarization process removes TSV layers, such as bulk layer 134', barrier/seed layer 138', and dielectric layer 136', from over sides 106 of device substrate 102. The device substrate 102 may serve as a planarization stop layer and a planarization process may be performed until the device substrate 102 is reached and exposed. The remaining portion of the TSV layer forms a TSV 130 having a thickness T and a width W. For example, the remaining portion of dielectric layer 136' forms dielectric liner 136, the remaining portion of barrier/seed layer 138' forms barrier/seed liner 138, and the remaining portion of bulk layer 134' forms bulk layer 134 (also referred to as a conductive plug or TSV plug). The dielectric liner 136 and the barrier/seed liner 138 in combination form a barrier layer 132 of the TSV 130, the barrier layer 132 surrounding the bulk layer 134 of the TSV 130. Because the device substrate 210 is thinned prior to forming the TSV 130, portions of the TSV 130 are not removed when manufactured as described with reference to fig. 5A-5M, thereby reducing conductive material waste and/or reducing manufacturing costs. The planarization process may planarize the sides 106 of the device substrate 102 (i.e., the back/bottom surface thereof) and the surfaces of the TSVs 130 (i.e., the back/bottom surface thereof). In some embodiments, the sides 106 of the device substrate 102 and the surfaces of the TSVs 130 (i.e., their back/bottom surfaces) are substantially planar after the planarization process.

In fig. 5N, the workpiece 200 is flipped back so that the insulating layer 115 forms the top of the workpiece 200 instead of the device substrate 102. Thus, the workpiece 200 is reoriented such that the insulating layer 115 forms the top/front side of the workpiece 200 and the device substrate 102 (e.g., side 106 thereof) forms the bottom/back side of the workpiece 200. Because the TSV 130 extends through the insulating layer 115 and the device substrate 102, the top/front side of the TSV 130 also forms the top/front side of the workpiece 200, and the bottom/back side of the TSV 130 also forms the bottom/back side of the workpiece 200. In addition, because the TSV 130 is formed as described with reference to fig. 5A-5M, the top/front side of the TSV 130 is formed by the barrier layer 132 (e.g., dielectric liner 136) and the bottom/back side of the TSV 130 is formed by the body layer 134 and the barrier layer 132. Thus, horizontally oriented segments of barrier layer 132 are disposed in insulating layer 115, rather than device substrate 102. In some embodiments, dielectric liner 136 is omitted from TSV 130, barrier/seed layer 138 separates bulk layer 134 from insulating layer 115, barrier/seed layer 138 separates bulk layer 134 from device substrate 102, and the top/front side of TSV 130 is formed from barrier/seed layer 138. In embodiments where insulating layer 115 is attached to carrier wafer 255 during TSV formation, carrier wafer 255 is removed before or after the planarization process.

In fig. 5O, fabrication may continue with forming a TC layer over the MLI feature 110, TSV 130, and guard ring 140. In some embodiments, forming the TC layer includes: depositing a passivation layer over the workpiece 200; and patterning the passivation layer to have an opening therein exposing the metal lines 116 of the (n+x) -level interconnect layer of the MLI feature 110, the metal lines 116 of the (a+b) -interconnect structure of the TSV 130 and the guard ring 140 (i.e., the topmost metal feature). One of the openings in the patterned passivation layer may expose the TSV 130, the guard ring 140, and a portion of the insulating layer 115 between the TSV 130 and the guard ring 140. In some embodiments, forming the TC layer may include: depositing a conductive material over the workpiece 200 that fills the openings in the patterned passivation layer; and performing a planarization process that removes excess conductive material from over the top surface of the passivation layer, thereby forming contacts 120, 122, and vias 124 in the passivation layer.

Fig. 7 is a flow chart of a method 300 for fabricating a via, such as TSV 130, in accordance with aspects of an embodiment of the present disclosure. In block 310, the method 300 includes forming a trench (e.g., trench 220) extending through an insulating layer (e.g., insulating layer 115) and into a substrate (e.g., device substrate 102). The substrate has a first side (e.g., side 104 of device substrate 102) and a second side (e.g., side 106 of device substrate 102). The second side is opposite the first side, and an insulating layer is disposed over the first side of the substrate. In block 315, the method 300 includes filling the trench with a sacrificial material (e.g., the dielectric layer 240). In block 320, the method 300 includes performing a thinning process on a second side of the substrate. The thinning process exposes the sacrificial material. In some embodiments, the thinning process removes portions of the sacrificial material. In block 325, the method 300 includes: after a thinning process is performed and the sacrificial material is removed from the trench, a conductive structure is formed in the trench. The conductive structure extends through the substrate from the first side to the second side. The conductive structure may include a liner surrounding the conductive plug, and a portion of the liner covering the top and/or bottom of the conductive plug is disposed in the insulating layer. In some embodiments, the trench has a first aspect ratio before being filled with the sacrificial material and a second aspect ratio after the thinning process and removal of the sacrificial material. The second aspect ratio is less than the first aspect ratio. In some embodiments, the insulating layer and the substrate form a first semiconductor structure, which may be attached (bonded) to a second semiconductor structure. For example, a backside of the first semiconductor structure (e.g., formed by the second side of the substrate) is attached to the second semiconductor structure, and the conductive structure electrically and/or physically connects the first semiconductor structure and the second semiconductor structure. In another example, a front side of the semiconductor structure (e.g., a portion thereof formed and/or disposed over the insulating layer) is attached to the second semiconductor structure, and the conductive structure electrically and/or physically connects the first semiconductor structure and the second semiconductor structure. In yet another example, a back side of the first semiconductor structure is attached to the second semiconductor structure and a front side of the first semiconductor structure is attached to the third semiconductor structure. In such examples, the conductive structure electrically and/or physically connects the first semiconductor structure and the second semiconductor structure and/or the first semiconductor structure and the third semiconductor structure. For clarity, fig. 7 has been simplified to better understand the inventive concepts of the disclosed embodiments. Additional steps may be provided before, during, and after method 300, and some of the steps described may be moved, replaced, or eliminated for additional embodiments of method 300.

Fig. 8 is a partial schematic cross-sectional view of a portion or an entirety of a device substrate 102 in accordance with aspects of an embodiment of the present disclosure. In fig. 8, the device substrate 102 has a device region 202A, a device region 202B, and an intermediate region 202C. The device substrate 102 is depicted as having a semiconductor substrate 402 and various transistors, such as transistor 404A in device region 202A and transistor 404B in device region 202B. The transistors 404A and 404B each include a respective gate structure 410 (which may include gate spacers disposed along a gate stack (e.g., a gate electrode disposed over a gate dielectric)) disposed between respective source/drains 412 (e.g., epitaxial source/drains), the source/drains 412 being disposed on, in, and/or over the semiconductor substrate 402, with channels extending between the respective source/drains 412 in the semiconductor substrate 402. The device substrate 102 may also include isolation structures 414, such as shallow trench isolation features, that separate and/or electrically isolate transistors (such as transistor 404A and transistor 404B) and/or other devices of the device substrate 102 from each other. The device substrate 102 also includes a dielectric layer 420 and a dielectric layer 422, which are similar to and may be fabricated similar to the dielectric layers described herein (i.e., the dielectric layer 420 may include one or more ILD layers and/or one or more CESL). Gate contact 432 is disposed in dielectric layer 420 and dielectric layer 422, source/drain contact 434 is disposed in dielectric layer 420, and via 436 is disposed in dielectric layer 422. The gate contact 432 electrically and physically connects the gate structure 410 (particularly the gate electrode) to the MLI component 110, and the source/drain contact 434 and/or via 436 electrically and physically connects the source/drain 412 to the MLI component 110. In some embodiments, dielectric layer 420, dielectric layer 422, gate contact 432, source/drain contact 434, and via 436 form MEOL layer 440. In some embodiments, the gate contacts 432, source/drain contacts 434, vias 436, or a combination thereof are physically and/or electrically connected to the n-level interconnect layer of the MLI component 110. In some embodiments, the gate contacts 432 and/or vias 436 may form part of the V _n layers of the n-level interconnect layer, and the gate contacts 432 and/or vias 436 are physically and/or electrically connected to the M _n layers of the n-level interconnect layer. In some embodiments, dielectric layer 420 and/or dielectric layer 422 form part of insulating layer 115. In some embodiments, contacts are disposed in dielectric layer 420 over doped regions in semiconductor substrate 402 in interface region 202C, and vias are disposed in dielectric layer 422 over the contacts. Such contacts may be physically and/or electrically connected to the doped regions, and such vias may be vias 118 of the interconnect structure of guard ring 140, and disposed in the V _n layer of the n-level interconnect layer. In such embodiments, the guard ring 140 may be physically and/or electrically connected to doped regions in the semiconductor substrate 402. for clarity, fig. 8 has been simplified to better understand the inventive concepts of the disclosed embodiments. Additional components may be added to the device substrate 102, and in other embodiments of the device substrate 102, some of the components described below may be replaced, modified, or eliminated.

Disclosed herein are via structures and methods of making the same. The disclosed embodiments provide many different embodiments. An exemplary method of forming a through substrate via includes forming a trench extending through an insulating layer and into a substrate. The substrate has a first side and a second side, and the second side is opposite the first side. An insulating layer is disposed over the first side of the substrate. The method further comprises the steps of: filling the trench with a dielectric material; and performing a thinning process on the second side of the substrate. The thinning process exposes the dielectric material. After performing the thinning process and removing the dielectric material from the trench, the method further includes forming a conductive structure in the trench. The conductive structure extends through the substrate from the first side to the second side.

In some embodiments, the first side and the second side of the substrate are a front side and a back side, respectively. In some embodiments, the dielectric material filling the trench has a first thickness, and the thinning process removes portions of the dielectric material, thereby providing the dielectric material filling the trench with a second thickness that is less than the first thickness. In some embodiments, the trench has a first aspect ratio before being filled with the dielectric material, and after the thinning process and removing the dielectric material from the trench, the trench has a second aspect ratio that is less than the first aspect ratio, and the conductive structure fills the trench having the second aspect ratio.

In some embodiments, forming the conductive structure in the trench includes: forming a barrier layer in the trench, the barrier layer forming a top and sidewalls of the conductive structure; and forming a conductive layer over the barrier layer in the trench. The portion of the barrier layer forming the top of the conductive structure is disposed in the insulating layer. In some embodiments, forming the barrier layer includes: depositing a dielectric liner over a second side of the substrate; and depositing a metal-containing liner over the dielectric liner. The dielectric liner and the metal-containing liner partially fill the trench, and a conductive layer is formed over the metal-containing liner and fills the remainder of the trench. In some embodiments, a planarization process is performed to remove portions of the dielectric liner, metal-containing liner, conductive layer, or a combination thereof from the second side of the substrate. In some embodiments, the barrier layer includes a metal-containing liner, but does not include a dielectric liner.

In some embodiments, removing the dielectric material includes performing an etching process that selectively removes the dielectric material relative to the insulating layer and the substrate. In some embodiments, the insulating layer and the substrate form a semiconductor structure, and the method further comprises flipping the semiconductor structure such that forming the conductive structure in the trench comprises depositing a conductive material over the second side of the substrate. In some embodiments, the insulating layer and the substrate form a first semiconductor structure, and the method includes bonding the first semiconductor structure to a second semiconductor structure. The conductive structure connects the first semiconductor structure and the second semiconductor structure.

In some embodiments, after the thinning process and removal of dielectric material from the trench, the trench has a top critical dimension in the insulating layer, an intermediate critical dimension near the interface of the insulating layer and the first side of the substrate, and a bottom critical dimension in the substrate. In some embodiments, the ratio of the top critical dimension to the middle critical dimension to the bottom critical dimension is about 1:1:1 to about 4:2:1. In some embodiments, the ratio of the top critical dimension to the middle critical dimension to the bottom critical dimension is about 1:2:4 to about 1:1:1.

Another exemplary method includes receiving a workpiece having a device substrate and a multilayer interconnect (MLI) feature. The device substrate has a first thickness between its first and second sides. The MLI component is disposed over the first side. The method further includes forming a via opening extending through the insulating layer of the MLI feature and extending to a depth into the device substrate. The depth is less than the first thickness and the via opening has a first aspect ratio. The method further includes filling the via opening with a sacrificial material. The method further includes removing a portion of the device substrate to reduce the first thickness to a second thickness. When removing portions of the device substrate, portions of the sacrificial material are removed. The method further includes selectively removing the sacrificial material relative to the insulating layer and the device substrate. After selectively removing the sacrificial material, the via opening has a second aspect ratio that is less than the first aspect ratio. The method further includes forming a via in the via opening having the second aspect ratio. The via includes a barrier liner surrounding the conductive plug, and the barrier liner and the insulating layer form a top surface of the workpiece. In some embodiments, the first side is a front side of the device substrate and the second side is a back side of the device substrate.

In some embodiments, forming the via includes: forming a barrier layer over a second side of the device substrate; and forming a bulk layer over the barrier layer and the second side of the device substrate. The barrier layer partially fills the via opening and the body layer fills the remainder of the via opening. A planarization process may be performed to remove portions of the body layer and portions of the barrier layer from over the second side of the device substrate such that the remaining portions of the body layer form conductive plugs and the remaining portions of the barrier layer form barrier liners. In some embodiments, forming the barrier layer includes: forming a dielectric layer over a second side of the device substrate; and forming a barrier/seed layer over the dielectric layer. In such embodiments, the remaining portion of the dielectric layer forms a dielectric liner, the remaining portion of the barrier/seed layer forms a barrier/seed liner, and the barrier liner includes the dielectric liner and the barrier/seed liner. In some embodiments, forming the barrier layer includes forming a barrier/seed layer (i.e., omitting the dielectric liner).

In some embodiments, a cleaning process is performed prior to forming the via in the via opening. In some embodiments, the method further includes forming a patterned metal layer over the MLI feature and the via. The patterned metal layer includes a metal line over the via. The barrier liner of the via is located between the metal line of the patterned metal layer and the conductive plug of the via.

In some embodiments, a top of the workpiece is formed by the insulating layer of the MLI feature, a bottom of the workpiece is formed by the second side of the device substrate, and forming the via in the via opening includes flipping the workpiece before forming the via in the via opening. In some embodiments, the device substrate, the MLI component, and the via form part of a first chip, and the method further comprises bonding the first chip to a second chip. The via may provide an electrical connection between the first chip and the second chip.

An exemplary semiconductor structure includes a device substrate having a first side and a second side. An insulating layer is disposed over the first side of the device substrate. The via extends through the insulating layer and through the device substrate from the first side to the second side. The via includes a body layer disposed over the barrier layer. The barrier layer is located between the body layer and the device substrate. The barrier layer is located between the body layer and the insulating layer. The barrier layer has a first portion forming a first sidewall of the via, a second portion forming a second sidewall of the via, and a third portion extending between the first portion and the second portion. The third portion is disposed in the insulating layer. In some embodiments, the first side is a front side, the second side is a back side, and the third portion of the barrier layer forms a top of the via.

In some embodiments, the barrier layer includes a dielectric liner and a metal-containing liner, wherein the metal-containing liner is located between the body layer and the dielectric liner. In some embodiments, the barrier layer includes a metal-containing liner without a dielectric liner. In some embodiments, the semiconductor structure further includes an interconnect structure disposed in the insulating layer and on the via. A barrier layer is disposed between the interconnect structure and the body layer.

Some embodiments of the present application provide a method for forming a through substrate via, the method comprising: forming a trench extending through an insulating layer and into a substrate, wherein the substrate has a first side and a second side, the insulating layer is disposed over the first side of the substrate, and the second side is opposite the first side; filling the trench with a dielectric material; performing a thinning process on the second side of the substrate, wherein the thinning process exposes the dielectric material; and forming a conductive structure in the trench after performing the thinning process and removing the dielectric material from the trench, wherein the conductive structure extends through the substrate from the first side to the second side. In some embodiments, forming the conductive structure in the trench includes: forming a barrier layer in the trench, the barrier layer forming a top and sidewalls of the conductive structure; and forming a conductive layer over the barrier layer in the trench, wherein a portion of the barrier layer forming the top of the conductive structure is disposed in the insulating layer. In some embodiments, forming the barrier layer comprises: depositing a dielectric liner over the second side of the substrate, wherein the dielectric liner partially fills the trench; and depositing a metal-containing liner over the dielectric liner. In some embodiments, the dielectric material filling the trench has a first thickness; and the thinning process removes portions of the dielectric material, thereby providing a dielectric material filling the trench having a second thickness less than the first thickness. In some embodiments, removing the dielectric material includes performing an etching process that selectively removes the dielectric material relative to the insulating layer and the substrate. In some embodiments, the trench has a first aspect ratio; and after the thinning process and removing the dielectric material, the trench has a second aspect ratio that is less than the first aspect ratio. In some embodiments, the insulating layer and the substrate form a semiconductor structure; and the method further includes flipping the semiconductor structure such that forming the conductive structure in the trench includes depositing a conductive material over the second side of the substrate. In some embodiments, after the thinning process and removal of the dielectric material, a trench has a top critical dimension in the insulating layer, an intermediate critical dimension near an interface of the insulating layer and the first side of the substrate, and a bottom critical dimension in the substrate; and a ratio of the top critical dimension to the middle critical dimension to the bottom critical dimension is about 1:1:1 to about 4:2:1. In some embodiments, the insulating layer and the substrate form a first semiconductor structure, the method further comprising bonding the first semiconductor structure to a second semiconductor structure, wherein the conductive structure connects the first semiconductor structure and the second semiconductor structure.

Other embodiments of the present application provide a method of forming a semiconductor structure, comprising: receiving a workpiece having a device substrate and a multilayer interconnect (MLI) feature, wherein the device substrate has a first thickness between a first side and a second side thereof, and the multilayer interconnect feature is disposed over the first side; forming a via opening extending through the insulating layer of the multilayer interconnect component and into the device substrate to a depth, wherein the depth is less than the first thickness and the via opening has a first aspect ratio; filling the via opening with a sacrificial material; removing a portion of the device substrate to reduce the first thickness to a second thickness, wherein removing the portion of the device substrate further comprises removing a portion of the sacrificial material; Selectively removing the sacrificial material relative to the insulating layer and the device substrate, wherein the via opening has a second aspect ratio after selectively removing the sacrificial material, and the second aspect ratio is less than the first aspect ratio; and forming a via in the via opening having the second aspect ratio, wherein the via includes a barrier liner surrounding a conductive plug, and the barrier liner and the insulating layer form a top surface of the workpiece. In some embodiments, forming the via includes: forming a barrier layer over the second side of the device substrate, wherein the barrier layer partially fills the via opening; Forming a body layer over the barrier layer and the second side of the device substrate, wherein the body layer fills a remaining portion of the via opening; and performing a planarization process to remove portions of the body layer and portions of the barrier layer from over the second side of the device substrate, wherein a remaining portion of the body layer forms the conductive plug and a remaining portion of the barrier layer forms the barrier liner. In some embodiments, forming the barrier layer comprises: forming a dielectric layer over the second side of the device substrate; and forming a barrier/seed layer over the dielectric layer, wherein a remaining portion of the dielectric layer forms a dielectric liner, a remaining portion of the barrier/seed layer forms a barrier/seed liner, and the barrier liner comprises the dielectric liner and the barrier/seed liner. In some embodiments, a top of the workpiece is formed by the insulating layer of the multilayer interconnect feature, a bottom of the workpiece is formed by the second side of the device substrate, and forming the via in the via opening includes flipping the workpiece before forming the via in the via opening. In some embodiments, the first side is a front side of the device substrate and the second side is a back side of the device substrate. In some embodiments, the device substrate, the multilayer interconnect component, and the via form part of a first chip, the method further comprising bonding the first chip to a second chip, wherein the via provides an electrical connection between the first chip and the second chip. In some embodiments, the method further comprises: a patterned metal layer is formed over the multilayer interconnect feature and the via, wherein the patterned metal layer includes a metal line disposed over the via, and the barrier liner of the via is located between the metal line of the patterned metal layer and the conductive plug of the via.

Still further embodiments of the present application provide a semiconductor structure comprising: a device substrate having a first side and a second side; an insulating layer disposed over the first side of the device substrate; and a via extending through the insulating layer and through the device substrate from the first side to the second side, wherein: the via includes a body layer disposed over a barrier layer, the barrier layer being between the body layer and the device substrate, the barrier layer being between the body layer and the insulating layer, the barrier layer having a first portion forming a first sidewall of the via, a second portion forming a second sidewall of the via, and a third portion extending between the first portion and the second portion, and the third portion being disposed in the insulating layer. In some embodiments, the first side is a front side, the second side is a back side, and the third portion of the barrier layer forms a top of the via. In some embodiments, the barrier layer includes a dielectric liner and a metal-containing liner, wherein the metal-containing liner is located between the body layer and the dielectric liner. In some embodiments, the semiconductor structure further comprises: an interconnect structure disposed in the insulating layer and on the via, wherein the barrier layer is disposed between the interconnect structure and the body layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the embodiments of the present disclosure. Those skilled in the art will appreciate that they may readily use the presently disclosed embodiments as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments presented herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a through substrate via, the method comprising:

Forming a trench extending through an insulating layer and into a substrate, wherein the substrate has a first side and a second side, the insulating layer is disposed over the first side of the substrate, and the second side is opposite the first side;

filling the trench with a dielectric material;

performing a thinning process on the second side of the substrate, wherein the thinning process exposes the dielectric material; and

After performing the thinning process and removing the dielectric material from the trench, a conductive structure is formed in the trench, wherein the conductive structure extends through the substrate from the first side to the second side.

2. The method of claim 1, wherein forming the conductive structure in the trench comprises:

forming a barrier layer in the trench, the barrier layer forming a top and sidewalls of the conductive structure; and

A conductive layer is formed over the barrier layer in the trench, wherein a portion of the barrier layer forming the top of the conductive structure is disposed in the insulating layer.

3. The method of claim 2, wherein forming the barrier layer comprises:

depositing a dielectric liner over the second side of the substrate, wherein the dielectric liner partially fills the trench; and

A metal-containing liner is deposited over the dielectric liner.

4. The method according to claim 1, wherein:

The dielectric material filling the trench has a first thickness; and

The thinning process removes portions of the dielectric material, providing a dielectric material filling the trench having a second thickness less than the first thickness.

5. The method of claim 1, wherein removing the dielectric material comprises performing an etching process that selectively removes the dielectric material relative to the insulating layer and the substrate.

6. The method according to claim 1, wherein:

The trench has a first aspect ratio; and

After the thinning process and removing the dielectric material, the trench has a second aspect ratio that is less than the first aspect ratio.

7. The method according to claim 1, wherein:

the insulating layer and the substrate form a semiconductor structure; and

The method also includes flipping the semiconductor structure such that forming the conductive structure in the trench includes depositing a conductive material over the second side of the substrate.

8. The method of claim 1, wherein,

After the thinning process and removal of the dielectric material, a trench has a top critical dimension in the insulating layer, an intermediate critical dimension near an interface of the insulating layer and the first side of the substrate, and a bottom critical dimension in the substrate; and

The ratio of the top critical dimension to the intermediate critical dimension to the bottom critical dimension is from about 1:1:1 to about 4:2:1.

9.A method of forming a semiconductor structure, comprising:

Receiving a workpiece having a device substrate and a multilayer interconnect (MLI) feature, wherein the device substrate has a first thickness between a first side and a second side thereof, and the multilayer interconnect feature is disposed over the first side;

forming a via opening extending through the insulating layer of the multilayer interconnect component and into the device substrate to a depth, wherein the depth is less than the first thickness and the via opening has a first aspect ratio;

filling the via opening with a sacrificial material;

Removing a portion of the device substrate to reduce the first thickness to a second thickness, wherein removing the portion of the device substrate further comprises removing a portion of the sacrificial material;

Selectively removing the sacrificial material relative to the insulating layer and the device substrate, wherein the via opening has a second aspect ratio after selectively removing the sacrificial material, and the second aspect ratio is less than the first aspect ratio; and

Forming a via in the via opening having the second aspect ratio, wherein the via includes a barrier liner surrounding a conductive plug, and the barrier liner and the insulating layer form a top surface of the workpiece.

10. A semiconductor structure, comprising:

A device substrate having a first side and a second side;

An insulating layer disposed over the first side of the device substrate; and

A via extending through the insulating layer and through the device substrate from the first side to the second side, wherein:

the via includes a body layer disposed over a barrier layer,

The barrier layer is located between the bulk layer and the device substrate,

The barrier layer is located between the bulk layer and the insulating layer,

The barrier layer has a first portion forming a first sidewall of the via, a second portion forming a second sidewall of the via, and a third portion extending between the first portion and the second portion, and

The third portion is disposed in the insulating layer.