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CN118314936B - Memory, access method and electronic equipment - Google Patents

Memory, access method and electronic equipment Download PDF

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Publication number
CN118314936B
CN118314936B CN202410732614.2A CN202410732614A CN118314936B CN 118314936 B CN118314936 B CN 118314936B CN 202410732614 A CN202410732614 A CN 202410732614A CN 118314936 B CN118314936 B CN 118314936B
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China
Prior art keywords
word line
row
selection
line
substrate
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Chinese (zh)
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CN118314936A (en
Inventor
戴瑾
胡秀芝
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Beijing Superstring Academy of Memory Technology
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Beijing Superstring Academy of Memory Technology
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)

Abstract

The application discloses a memory, an access method and electronic equipment, and relates to the technical field of semiconductors. The memory includes: the memory cell comprises a plurality of memory cell layers stacked along a vertical substrate direction, and a plurality of word lines and a plurality of bit lines correspondingly connected with each memory cell in the memory cell layers; wherein the word lines extend in a first direction parallel to the substrate, one of the word lines connecting a row of the memory cells in the memory cell layer; the bit lines extend along the direction vertical to the substrate, and one bit line is connected with one column of the memory cells which are arranged along the direction vertical to the substrate in different memory cell layers; a word line selection circuit connected to each of the word lines extending in a first direction parallel to the substrate, and configured to: a layer selection signal and a row strobe signal are provided in response to an access request, and a target word line is strobed according to the layer selection signal and the row strobe signal. The circuit has simple structure and low cost.

Description

Memory, access method and electronic equipment
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a memory, an access method, and an electronic device.
Background
With the development of semiconductor technology, the types of memories manufactured by using semiconductor technology are increasing, and the memories include memory cell arrays for storing data. With the increasing demands of various electronic devices for integration level, storage capacity, and the like, three-dimensional (3 d) memory devices have been developed. The memory with the three-dimensional stacked structure can be realized by stacking a plurality of memory cell arrays for storing data, thereby improving the data capacity capable of being stored in the memory.
Disclosure of Invention
The disclosure provides a memory, an access method and electronic equipment, which can realize the selection of a target word line in a target memory cell array.
The present disclosure provides a memory including a plurality of memory cell layers stacked in a vertical substrate direction, and a plurality of word lines and a plurality of bit lines correspondingly connected to respective memory cells in the memory cell layers; wherein the word lines extend in a first direction parallel to the substrate, one of the word lines connecting a row of the memory cells in the memory cell layer; the bit lines extend along the direction vertical to the substrate, and one bit line is connected with one column of the memory cells which are arranged along the direction vertical to the substrate in different memory cell layers;
A word line selection circuit connected to each of the word lines, configured to: a layer selection signal and a row strobe signal are provided in response to an access request, and a target word line is strobed according to the layer selection signal and the row strobe signal.
In one embodiment, the word line selection circuit includes:
A layer selection circuit including a plurality of word line layer selection lines; the word line layer selection line is disposed corresponding to the memory cell layer and configured to: providing the layer selection signal to each of the word lines connected corresponding to the memory cell layer in response to the access request;
A row strobe circuit including a plurality of first row strobe circuits; the row strobe signal includes a first word line row strobe signal; the first row strobe circuit is correspondingly arranged with a row of word lines which are arranged in columns along the direction vertical to the substrate and are used for connecting corresponding memory cells in different memory cell layers, and is configured to: in response to the access request, the first word line row strobe signal is provided to each of the word lines of a corresponding column.
In one embodiment, the word line layer select lines extend in a second direction parallel to the substrate, the second direction intersecting the first direction;
The first row strobe circuit includes: a word line row selection line, and a plurality of first selection transistors arranged in columns along a vertical substrate direction and arranged in one-to-one correspondence with one column of the word lines; wherein,
The word line row selection line extends along the direction vertical to the substrate and is connected with the grid electrode of one column of the first selection transistors;
The first selection transistor is located at a first end corresponding to the word line, a first source drain electrode of the first selection transistor is connected with the first end, and a second source drain electrode of the first selection transistor is connected with the corresponding word line layer selection line.
In one embodiment, the row strobe circuit further comprises a plurality of second row strobe circuits; the row strobe signal further includes a second word line row strobe signal;
The second row strobe circuit is correspondingly arranged with a row of word lines which are arranged in a column along the direction vertical to the substrate and are used for connecting corresponding memory cells in different memory cell layers, and is configured to: in response to the access request, the second word line row strobe signal is provided to each of the word lines of the corresponding column.
In one embodiment, the first row strobe circuit and the second row strobe circuit connected to the same word line are respectively located at two ends of the word line, and the potentials of the first word line row strobe signal and the second word line row strobe signal are opposite.
In one embodiment, the second row strobe circuit includes: a word line row counter selection line, and a plurality of second selection transistors which are arranged in columns along the direction vertical to the substrate and are arranged in one-to-one correspondence with one column of the word lines; wherein,
The word line row counter selection line extends along the direction vertical to the substrate and is connected with the grid electrode of one column of the second selection transistors;
The second selection transistor is positioned at a second end corresponding to the word line, and the first end and the second end of the word line are opposite in the first direction; the first source-drain electrode of the second selection transistor is connected with the second end, and the second source-drain electrode of the second selection transistor is connected with the reference voltage end.
In one embodiment, the reference voltage terminal includes a reference voltage signal line extending in a direction perpendicular to the substrate; the second source and drain electrodes of the second selection transistors in the same second row gating circuit are connected to the same reference voltage signal line;
Or, the reference voltage terminal comprises a reference voltage conductive wall extending along the direction vertical to the substrate; and the second source and drain electrodes of the second selection transistors in different second row strobe circuits are connected to the reference voltage conducting wall.
In one embodiment, the layer selection circuit further comprises:
The layer leading-out structure is used for being connected with an external control circuit and comprises a plurality of layer leading-out wires; the layer outgoing line is correspondingly connected with the word line layer selection line and extends and is led out along the direction vertical to the substrate.
In one embodiment, the memory further comprises:
a bit line selection circuit, located at the top or bottom of the memory cell layers and connected to each bit line, configured to: a bit line strobe signal is provided in response to the access request, and a target bit line is strobed according to the bit line strobe signal.
An access method of a memory, the memory includes a plurality of memory cell layers stacked in a vertical substrate direction, and a plurality of word lines and a plurality of bit lines correspondingly connected to each memory cell in the memory cell layers; wherein the word lines extend in a first direction parallel to the substrate, one of the word lines connecting a row of the memory cells in the memory cell layer; the bit lines extend along the direction vertical to the substrate, and one bit line is connected with one column of the memory cells which are arranged along the direction vertical to the substrate in different memory cell layers;
The access method comprises the following steps:
In response to an access request, a layer selection signal and a row strobe signal are supplied to each of the word lines to which it is connected through a word line selection circuit, and a target word line is strobed according to the layer selection signal and the row strobe signal.
In one embodiment, the word line selection circuit includes a layer selection circuit and a row strobe circuit; the layer selection circuit comprises a plurality of word line layer selection lines which are arranged corresponding to the memory cell layers; the row strobe circuit includes a plurality of first row strobe circuits; the row strobe signal includes a first word line row strobe signal; the first row strobe circuit is correspondingly arranged with a row of word lines which are arranged in a column along the direction vertical to the substrate and are used for connecting corresponding memory cells in different memory cell layers; wherein the word line selection circuit provides a layer selection signal and a row strobe signal to each of the connected word lines in response to an access request, comprising:
providing the layer selection signal to each of the word lines connected to the corresponding memory cell layer through the word line layer selection line in response to the access request;
In response to the access request, the first word line row strobe signal is provided to each of the word lines of a corresponding column through the first row strobe circuit.
In one embodiment, the row strobe circuit further comprises a plurality of second row strobe circuits; the second row strobe circuits are correspondingly arranged with a row of word lines which are arranged in a column along the direction vertical to the substrate and are used for connecting corresponding memory cells in different memory cell layers; the row strobe signal further includes a second word line row strobe signal; wherein the word line selection circuit supplies a layer selection signal and a row strobe signal to each of the connected word lines in response to an access request, further comprising:
In response to the access request, the second word line row strobe signal is provided to each of the word lines of a corresponding column through the second row strobe circuit.
In one embodiment, the first row strobe circuit and the second row strobe circuit connected to the same word line are respectively located at two ends of the word line, and the potentials of the first word line row strobe signal and the second word line row strobe signal are opposite.
In one embodiment, the memory access method further includes:
in response to the access request, a bit line strobe signal is supplied to each of the bit lines connected thereto through a bit line selection circuit, and a target bit line is strobed in accordance with the bit line strobe signal.
The present disclosure also provides an electronic device comprising any one of the memories described above.
In the memory, the word lines extend along the first direction parallel to the substrate, one word line is connected with one row of the memory cells in the memory cell layer, the word line selection circuit is respectively connected with each word line, a layer selection signal and a row strobe signal are provided in response to an access request, a target word line is strobed according to the layer selection signal and the row strobe signal, and bit lines extending along the direction perpendicular to the substrate are connected with one column of the memory cells arranged along the direction perpendicular to the substrate in different memory cell layers, so that a bit line signal can be provided for a target memory cell in the determined target word line.
In the access method of the memory, the word line selection circuit is used for providing the layer selection signal and the row strobe signal for each connected word line in response to the access request, and the target word line is strobed according to the layer selection signal and the row strobe signal, and the bit line extending along the direction vertical to the substrate is connected with one column of the memory cells arranged along the direction vertical to the substrate in different memory cell layers, so that the bit line signal can be provided for the target memory cells in the determined target word line.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present application, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a schematic diagram of a circuit structure of a memory according to an embodiment;
FIG. 2 is a schematic three-dimensional structure of a memory according to an embodiment;
FIG. 3 is a flow chart illustrating a method for fabricating a three-dimensional memory according to an embodiment.
Reference numerals illustrate:
A first select transistor 102, a word line layer select line 104, a word line row select line 106, a word line 108, a second select transistor 110, a word line row counter select line 112, a reference voltage signal line 114, a reference voltage conductive wall 116, a layer out 118, a memory cell layer 202, a memory cell 204, a cell select transistor 206, and a bit line 208.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that the terms first, second, etc. as used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first select transistor may be referred to as a second select transistor, and similarly, a second select transistor may be referred to as a first select transistor, without departing from the scope of the application. Both the first select transistor and the second select transistor are select transistors, but they are not the same select transistor.
It is to be understood that in the following embodiments, "connected" is understood to mean "electrically connected", "communicatively connected", etc., if the connected circuits, modules, units, etc., have electrical or data transfer between them.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention; for example, the first doping type may be referred to as a second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques.
Fig. 1 is a schematic circuit diagram of a memory in an embodiment, fig. 2 is a schematic three-dimensional structure of the memory in an embodiment, an X direction may be a first direction in a plane parallel to a substrate shown in fig. 1, a Y direction may be a second direction in a plane parallel to a substrate shown in fig. 1, and a Z direction may be a third direction perpendicular to the substrate in fig. 1, as shown in fig. 1 and 2, in this embodiment, a memory is provided, including: a plurality of memory cell layers 202 stacked in a vertical substrate direction Z, and a plurality of word lines 108 and a plurality of bit lines 208 correspondingly connected to respective memory cells in the memory cell layers 202; wherein the word lines 108 extend in a first direction X parallel to the substrate, one of the word lines 108 connecting a row of the memory cells in the memory cell layer 202; the bit lines 208 extend along the direction perpendicular to the substrate, and one bit line is connected with one column of the memory cells arranged along the direction perpendicular to the substrate in different memory cell layers; a word line selection circuit connected to each of the word lines 108, and configured to: a layer selection signal and a row strobe signal are provided in response to an access request, and a target word line is strobed according to the layer selection signal and the row strobe signal.
In the memory, the word lines extend along the first direction parallel to the substrate, one word line is connected with one row of the memory cells in the memory cell layer, the word line selection circuit is respectively connected with each word line, a layer selection signal and a row strobe signal are provided in response to an access request, a target word line is strobed according to the layer selection signal and the row strobe signal, and bit lines extending along the direction perpendicular to the substrate are connected with one column of the memory cells arranged along the direction perpendicular to the substrate in different memory cell layers, so that a bit line signal can be provided for a target memory cell in the determined target word line.
In one embodiment, the word line selection circuit includes: a layer selection circuit and a row strobe circuit; the layer selection circuit includes a plurality of word line layer selection lines 104; the word line layer selection line 104 is disposed corresponding to the memory cell layer 202 and is configured to: in response to the access request, providing the layer selection signal to each of the word lines 108 connected to the corresponding memory cell layer 202; the row strobe circuit includes a plurality of first row strobe circuits; the row strobe signal includes a first word line row strobe signal; the first row strobe circuit is disposed corresponding to a column of the word lines 108 arranged in a column along the Z direction of the vertical substrate and used for connecting corresponding memory cells 204 in different memory cell layers 202, and is configured to: in response to the access request, the first word line row strobe signal is provided to each of the word lines 108 of the corresponding column.
Specifically, the layer selection signal provided by the word line layer selection line 104 determines the target memory cell layer where the target word line is located, one end of the word line 108 is suspended, the other end of the word line 108 is connected to a first row strobe circuit, the first row strobe circuit provides a first word line strobe signal to the word line according to an access request (a request corresponding to the layer selection signal and a request corresponding to a word line signal transmitted by the word line selection line), and the target row where the target word line is located can be determined according to the first word line strobe signal.
In some embodiments, the word line layer selection lines 104 and the memory cell layers 202 are disposed in a one-to-one correspondence, where the word line layer selection lines 104 provide the same layer selection signals to the plurality of word lines 108 in the memory cell layers 202 correspondingly connected thereto, and the layer selection signals provided by the word line layer selection lines 104 of different layers may be the same or different, and the target memory cell layer where the target word line is located may be selected by the layer selection signals.
In some embodiments, the word line layer select line 104 extends along a second direction Y parallel to the substrate, the second direction Y intersecting the first direction X; the first row strobe circuit includes: a word line row selection line 106 and a plurality of first selection transistors 102, wherein the plurality of first selection transistors 102 are arranged in columns along the Z direction of the vertical substrate and are arranged in one-to-one correspondence with a column of the word lines 108 arranged along the Z direction of the vertical substrate; wherein the word line row select line 106 extends in a direction perpendicular to the substrate and is connected to the gates of a column of the first select transistors 102; the first selection transistor 102 is located at a first end corresponding to the word line, a first source-drain electrode of the first selection transistor 102 is connected to the first end, and a second source-drain electrode of the first selection transistor 102 is connected to the corresponding word line layer selection line 104.
In some embodiments, the row strobe circuit further comprises a plurality of second row strobe circuits; the row strobe signal further includes a second word line row strobe signal; the second row strobe circuit is disposed corresponding to a column of the word lines 108 arranged in a vertical substrate direction and used for connecting corresponding memory cells 204 in different memory cell layers 202, and is configured to: in response to the access request, the second word line row strobe signal is provided to each of the word lines 108 of the corresponding column.
Specifically, the second row strobe circuit provides the second word line strobe signal to each of the word lines 108 of the corresponding column according to the access request (the request corresponding to the word line row signal transmitted by the word line counter selection line and the request corresponding to the reference signal of the reference voltage terminal), the same word line 108 receives the first word line strobe signal provided by the first row strobe circuit and the second word line strobe signal provided by the second row strobe circuit, and the target word line is strobed according to the first word line strobe signal and the second word line strobe signal, so that compared with the case of only using the first word line strobe signal and the layer strobe signal to strobe the target word line, the influence of external interference can be avoided, and the accurate address selection of the target word line is realized.
In some embodiments, the first row strobe circuit and the second row strobe circuit connected to the same word line 108 are located at two ends of the word line, respectively, and the first word line row strobe signal and the second word line row strobe signal are opposite in potential.
In some embodiments, the second row strobe circuit comprises: a word line row counter selection line 112, and a plurality of second selection transistors 110 arranged in columns along a vertical substrate direction and disposed in one-to-one correspondence with one column of the word lines 108; wherein the word line row counter selection line 112 extends in a direction perpendicular to the substrate and is connected to the gates of a column of the second selection transistors 110; the second selection transistor 110 is located at a second end corresponding to the word line 108, and the first end and the second end of the word line 108 are opposite in the first direction X; the first source-drain electrode of the second selection transistor 110 is connected to the second end, and the second source-drain electrode of the second selection transistor 110 is connected to the reference voltage end.
For example, the memory cell 204 includes a cell select transistor 206, and the gates of the cell select transistors 206 of the same row are connected to one word line 108; the word line 108 extends in a first direction X parallel to the substrate; a bit line 208 extending along a third direction Z perpendicular to the substrate and connected to the first source and drain electrodes of each of the cell selection transistors 206 arranged in the third direction Z in different memory cell layers 202; the first selection transistor 102 is located at a first end of the word line 108, and a first source-drain electrode of the first selection transistor 102 is connected with the first end of the word line 108; the word line layer selection line 104 extends along a second direction Y parallel to the substrate and is connected with a second source drain electrode of the first selection transistor 102, and the second direction Y is intersected with the first direction X; a word line row select line 106 extends along a third direction Z of the vertical substrate and is connected to the gate of the first select transistor 102.
As can be appreciated, the first selection transistors 102 in the plurality of first row gate circuits are arranged at intervals along the second direction Y, and are stacked along the third direction Z, and in the same plane parallel to the substrate, the gates of the first selection transistors 102 (the first selection transistors 102 in the different first row gate circuits) arranged at intervals along the second direction Y are respectively connected to the word line row selection lines 106 (the word line row selection lines 106 in the different first row gate circuits) extending along the third direction Z, the first source and drain electrodes of the first selection transistors 102 arranged at intervals along the second direction Y are respectively connected to the first ends of the word lines 108 extending along the first direction X, and the second source and drain electrodes of the first selection transistors 102 arranged at intervals along the second direction Y are respectively connected to the same word line layer selection line 104 extending along the second direction Y; the gates of the first selection transistors 102 stacked in the third direction Z are connected to the same word line row selection line extending in the third direction Z, and the second source and drain of the first selection transistors 102 stacked in the third direction Z are connected to the word line layer selection lines 104 stacked in the third direction Z. Compared with the word lines extending along the third direction Z, the word lines 108 extend along the first direction X, the bit lines extend along the third direction Z and are arranged at intervals along the first direction X and the second direction Y, so that parasitic capacitance among the bit lines can be reduced, and design difficulty is simplified. The target memory cell layer parallel to the substrate where the target word line is located can be selected by the respective word line layer selection lines 104 stacked in the third direction Z, and the target row where the target word line is located stacked in the third direction can be selected by the word line row selection lines 106 extending in the third direction Z and the plurality of first selection transistors 102 stacked in the third direction Z while the word lines located in the target memory cell layer and the target row are the target word lines. The word line row select lines 106 extend along a third direction Z perpendicular to the substrate, and no separate row lead lines are required to connect the external control circuit with the word line row select lines 106, which is simple in circuit structure and low in cost.
For example, the first selection transistor 102 and the word line layer selection line 104 in the same plane parallel to the substrate in the memory may be used as one word line selection sub-circuit, where each word line selection sub-circuit corresponds to each memory cell layer 202, and assuming that the first word line selection sub-circuit corresponds to the first memory cell layer 202, each first selection transistor 102 in the first word line selection sub-circuit corresponds to each row of memory cells 204 in the first memory cell layer 202, and the first end of the word line 108 connected to the gate of the cell selection transistor 206 in the same row is connected to the first source/drain of the first selection transistor 102 corresponding to the row of memory cells 204.
Illustratively, a second select transistor 110 is located at a second end of the word line 108; a first end and a second end of the word line 108 are oppositely arranged in the first direction X, and a first source-drain electrode of the second selection transistor 110 is connected with the second end of the word line 108; the word line row counter selection line 112 extends in a third direction Z perpendicular to the substrate and is connected to the gate of the second selection transistor 110.
It will be appreciated that the second select transistor 110, the word line layer counter select line 112, the first select transistor 102, and the word line layer select line 104 in the memory in the same plane parallel to the substrate may be used as a word line select sub-circuit, each corresponding to a respective memory cell layer 202, assuming that the first word line select sub-circuit corresponds to a first memory cell layer 202, each first select transistor 102 in the first word line select sub-circuit corresponds to a respective row of memory cells 204 in the first memory cell layer 202, and a first end of the word line 108 connected to the gate of the cell select transistor 206 in the same row is connected to a first source/drain of the first select transistor 102 corresponding to the row of memory cells 204; the second selection transistor 110 and the first selection transistor 102 are arranged in pairs, and in the first direction X, the second selection transistor 110 and the first selection transistor 102 are located at opposite ends of the same word line 108, and a second end of the word line 108 connected to the gate of the cell selection transistor 206 in the same row is connected to the first source-drain of the second selection transistor 110 corresponding to the memory cell 204 in the row.
As shown in fig. 1, in some embodiments, the reference voltage terminal includes a reference voltage signal line 114 extending in a direction perpendicular to the substrate; the second source and drain of each of the second selection transistors 110 in the same second row strobe circuit are connected to the same reference voltage signal line 114.
Specifically, the reference voltage terminal includes a reference voltage signal line 114 extending along a third direction Z, in the same plane parallel to the substrate, the second source and drain of each second selection transistor 110 are respectively connected to each reference voltage signal line 114, and in the third direction Z, the second source and drain of each second selection transistor 110 stacked and arranged are connected to the same reference voltage signal line 114.
As shown in fig. 2, in some embodiments, the reference voltage terminal includes a reference voltage conductive wall 116 extending in a direction perpendicular to the substrate; wherein the second source and drain of each of the second selection transistors 110 in the second row strobe circuits are connected to the reference voltage conductive wall 116.
Specifically, the reference voltage terminal includes a reference voltage conductive wall 116 extending along the third direction Z, and the second source and drain electrodes of the second selection transistors 110 stacked in the third direction Z and arranged in the same plane parallel to the substrate are connected to the same reference voltage conductive wall 116.
In one embodiment, the word line row select line 106 and the word line row counter select line 112, which correspond to the same word line 108, are used to transmit word line row signals of opposite potential, respectively. Illustratively, the word line row select line 106 transmits a word line row signal of high potential (e.g., 1) and the word line row counter select line 112 transmits a word line row signal of low potential (e.g., 0); or the word line row select line 106 transmits a low (e.g., 0) word line row signal and the word line row counter select line 112 transmits a high (e.g., 1) word line row signal. According to the word line row signal transmitted by the word line row selection line 106, the first gating transistor is controlled to be turned on or off, and the first word line row gating signal, namely, a layer selection signal, is provided for the word line; the second gate transistor is controlled to be turned on or off according to the word line row signal transmitted from the word line row counter selection line 112, and a voltage signal having a short reference voltage, which is the second word line row gate signal, is supplied to the word line.
As shown in fig. 2, in one embodiment, the layer selection circuit further includes: a layer extraction structure for connecting to an external control circuit, including a plurality of layer extraction lines 118; the layer lead-out lines 118 are connected to the word line layer selection lines 104, and extend in a direction perpendicular to the substrate.
Specifically, layer pinout 118 includes: the vertical portion and the horizontal portion of connection, the one end and the word line layer selection line 104 of horizontal portion are connected, the other end and the vertical portion of horizontal portion are connected, the horizontal portion extends along the direction (the direction in the plane that first direction X and second direction Y lie in) that is on a parallel with the substrate, the vertical portion extends along the direction that is perpendicular to the horizontal portion, lie in the through-hole that echelonment through-hole (staircase) technique formed, the through-hole that each layer lead-out wire 118 corresponds is arranged at intervals in the plane that is on a parallel with the substrate. Illustratively, the horizontal portion is integrally connected with the word line layer select line 104 and the vertical portion extends in the third direction Z. "integrally joined" may refer to a microstructure where there is no distinct fault or gap between a and B. Typically, the connected film layers are patterned on one film layer as one piece. For example, a and B use the same material to form a film and simultaneously form a structure with a connection relationship through the same patterning process.
As shown in fig. 1 and 2, in one embodiment, the memory cell 204 includes a cell selection transistor 206, and a memory module 210 connected to a second source and drain of the cell selection transistor 206, and a gate of the cell selection transistor 206 in the same row is connected to one word line 108. Illustratively, the memory module 210 includes one or more of a storage capacitor, a magnetic memory module, or a ferroelectric memory module. Compared with the plane parallel to the substrate, the parasitic capacitance between the bit lines 208 arranged along the third direction Z is lower, so that the design difficulty is simplified, and the reliability of the three-dimensional memory is improved. Memory cell 204 coupled to the target word line may be selected as the target memory cell via bit line 208 and a bit line signal may be provided to the target memory cell to effect storage or reading of data in the target memory cell.
In one embodiment, in the same memory cell layer 202, one bit line 208 may be shared by two adjacent cell selection transistors 206 in each two adjacent rows of the memory cells 204, so as to reduce the size of the three-dimensional memory and improve the integration level of the three-dimensional memory.
In one embodiment, the memory further comprises: bit line selection circuitry, located at the top or bottom of the memory array, coupled to the bit lines 208, configured to: a bit line strobe signal is provided in response to the access request. Any memory cell 204 connected to the target word line can be selected as the target memory cell by the bit line select circuit and bit line 208. The plane in which the top and bottom portions lie may be parallel to the substrate, at opposite ends of the memory array in a third direction Z.
In one embodiment, the bit line selection circuit comprises a plurality of bit line selection transistors arranged in an array in a plane parallel to the substrate, each bit line selection transistor is connected with each bit line respectively, and connection and disconnection between the bit lines and the read-write circuit are realized by controlling on and off of the bit line selection transistors.
In this embodiment, the same or corresponding parts as those of the embodiments in the memory are not described in detail, and as shown in fig. 1-2, the memory includes a plurality of memory cell layers stacked along a vertical substrate direction, and a plurality of word lines and a plurality of bit lines correspondingly connected to each memory cell in the memory cell layers; wherein the word lines extend in a first direction parallel to the substrate, one of the word lines connecting a row of the memory cells in the memory cell layer; the bit lines extend along the direction vertical to the substrate, and one bit line is connected with one column of the memory cells which are arranged along the direction vertical to the substrate in different memory cell layers; the access method of the memory comprises the following steps: in response to an access request, a layer selection signal and a row strobe signal are supplied to each of the word lines to which it is connected through a word line selection circuit, and a target word line is strobed according to the layer selection signal and the row strobe signal. In the access method of the memory, the word line selection circuit is used for providing the layer selection signal and the row strobe signal for each connected word line in response to the access request, and the target word line is strobed according to the layer selection signal and the row strobe signal, and the bit line extending along the direction vertical to the substrate is connected with one column of the memory cells arranged along the direction vertical to the substrate in different memory cell layers, so that the target memory cells in the target word line can be determined and the bit line signals can be provided.
In one embodiment, the word line selection circuit includes a layer selection circuit and a row strobe circuit; the layer selection circuit comprises a plurality of word line layer selection lines which are arranged corresponding to the memory cell layers; the row strobe circuit includes a plurality of first row strobe circuits; the row strobe signal includes a first word line row strobe signal; the first row strobe circuit is correspondingly arranged with a row of word lines which are arranged in a column along the direction vertical to the substrate and are used for connecting corresponding memory cells in different memory cell layers; wherein the word line selection circuit provides a layer selection signal and a row strobe signal to each of the connected word lines in response to an access request, comprising:
providing the layer selection signal to each of the word lines connected to the corresponding memory cell layer through the word line layer selection line in response to the access request;
In response to the access request, the first word line row strobe signal is provided to each of the word lines of a corresponding column through the first row strobe circuit.
In one embodiment, the row strobe circuit further comprises a plurality of second row strobe circuits; the second row strobe circuits are correspondingly arranged with a row of word lines which are arranged in a column along the direction vertical to the substrate and are used for connecting corresponding memory cells in different memory cell layers; the row strobe signal further includes a second word line row strobe signal; wherein the word line selection circuit supplies a layer selection signal and a row strobe signal to each of the connected word lines in response to an access request, further comprising:
In response to the access request, the second word line row strobe signal is provided to each of the word lines of a corresponding column through the second row strobe circuit.
In one embodiment, the first row strobe circuit and the second row strobe circuit connected to the same word line are respectively located at two ends of the word line, and the potentials of the first word line row strobe signal and the second word line row strobe signal are opposite.
In one embodiment, the memory access method further includes:
in response to the access request, a bit line strobe signal is supplied to each of the bit lines connected thereto through a bit line selection circuit, and a target bit line is strobed in accordance with the bit line strobe signal.
Illustratively, the memory cell 204 includes a cell select transistor 206, and the gates of the cell select transistors 206 of the same row are connected to one word line 108; the word line 108 extends in a first direction X parallel to the substrate; a bit line 208 extending along a third direction Z perpendicular to the substrate and connected to the first source and drain electrodes of each of the cell selection transistors 206 arranged in the third direction Z in different memory cell layers 202; a first select transistor 102 in a first row strobe circuit is located at a first end of a word line 108, a first source drain of the first select transistor 102 being connected to the first end of the word line 108; the word line layer selection line 104 extends along a second direction Y parallel to the substrate and is connected with a second source drain electrode of the first selection transistor 102, and the second direction Y is intersected with the first direction X; a word line row select line 106 in the first row strobe circuit extends along a third direction Z perpendicular to the substrate and is connected to the gate of the first select transistor 102. The layer selection signal having the same potential is supplied to the second source/drain of the first selection transistor 102 connected thereto and located in the same word line layer through the word line layer selection line 104. Illustratively, the target word line layer and the non-target word line layer correspond to opposite potentials of the transmitted layer selection signals, one of the target word line layer and the non-target word line layer transmits a layer selection signal of a high potential (e.g., 1) and the other transmits a layer selection signal of a low potential (e.g., 0). A first word line row signal of the same potential is supplied to the gate of the first selection transistor 102 connected thereto, which is stacked in the third direction Z (the same row of different layers), through the word line row selection line 106, wherein the potential of the first word line row signal correspondingly transmitted by the target row and the non-target row is opposite. Illustratively, one of the target row and the non-target row transmits a first word line row signal of high potential (e.g., 1) and the other transmits a first word line row signal of low potential (e.g., 0). Each first selection transistor 102 is turned on or off according to the received first word line row signal, and provides a layer selection signal, namely a first word line row strobe signal, for the word line, the other end of the word line is suspended, and a target word line is strobed according to the layer selection signal; the states of the first selection transistors 102 located at the target word line layer and the target word line row are opposite to those of the remaining first selection transistors 102, where the states include on and off, thereby confirming the target word line layer (target memory cell layer) and the target word line row where the target word line is located.
Illustratively, a word line row counter select line 112 in the second row strobe circuit extends along a third direction Z perpendicular to the substrate and is connected to the gate of the second select transistor 110 in the second row strobe circuit, the second select transistor 110 being located at a second end of the word line 108; the first and second ends of the word line 108 are disposed opposite each other in the first direction X; the first source-drain electrode of the second selection transistor 110 is connected to the second end of the word line 108, and the second source-drain electrode of the second selection transistor 110 is connected to a reference voltage end to obtain a reference signal. A second word line row signal having the same potential is supplied to the gates of the second selection transistors 110 connected thereto and stacked in the third direction Z (the same row of different layers) through the word line row counter selection line 112, and the second source-drain electrodes of the second selection transistors 110 are connected to the reference voltage terminal, wherein the potentials of the second word line row signals correspondingly transferred by the target row and the non-target row are opposite. The potential of the second word line row signal of the target row is opposite to the potential of the first word line row signal, and the potential of the second word line row signal of the non-target row is the same as the potential of the first word line row signal. Each second selection transistor 110 is turned on or off according to the received second word line row signal, and provides a reference signal, i.e., a second word line row strobe signal, to the word line, and gates the target word line according to the layer selection signal, the first word line row strobe signal, and the second word line row strobe signal; the states of the second selection transistors 110 located at the target word line layer and the target word line row are opposite to the states of the remaining second selection transistors 110, where the states include on and off, thereby confirming the target word line row where the target word line is located. Compared with the method for gating the target word line by only adopting the first word line row gating signal and the layer gating signal, the method can avoid the influence of external interference and realize accurate address selection of the target word line.
Illustratively, the layer select signal provided by the word line layer select line 104 of the middle target word line layer (target memory cell layer) and the first word line row signal provided by the word line row select line 106 of the target word line row are high, and the second word line row signal provided by the word line row counter select line 112 of the target word line row is low; the layer select signal provided by the word line layer select line 104 of the non-target word line layer and the first word line row signal provided by the word line row select line 106 of the non-target word line row are low, and the second word line row signal provided by the word line row counter select line 112 of the non-target word line row is high, thereby controlling the on and off of each first select transistor 102 and each second select transistor 110, gating the target word line. Illustratively, the reference signal is low.
The present disclosure also provides an electronic device comprising a memory as described above. The electronic device may include a smart phone, computer, tablet, artificial intelligence, wearable device, or intelligent mobile terminal. The embodiment of the application does not limit the specific form of the electronic device.
Fig. 3 is a schematic flow chart of a method for preparing a three-dimensional memory according to an embodiment, which is the same as or corresponding to the above embodiment, and will not be described in detail below. As shown in fig. 1,2 and 3, the present disclosure further provides a method for preparing a three-dimensional memory, including:
S302, providing a substrate.
S304, forming a storage array on the substrate.
The memory array includes a plurality of memory cell layers 202 stacked in a third direction Z perpendicular to the substrate; the memory cell layer 202 includes a plurality of rows of memory cells 204 arranged at intervals in a second direction Y parallel to the substrate, the memory cells 204 include cell select transistors 206, and gates of the cell select transistors 206 in the same row are connected to one word line 108, the word line 108 extends along a first direction X parallel to the substrate, and the first direction X intersects the second direction Y.
S306, forming a word line selection circuit of the memory according to any one of the above on the substrate, wherein the word line selection circuit of the memory is located at the periphery of the memory array and is connected with each word line.
In the method for manufacturing the three-dimensional memory, the word line selection circuit located at the periphery of the memory array is connected with the word lines, the word line layer selection lines of the word line selection circuit of the memory extend along the second direction and are connected with the second source drain electrodes of the first selection transistors of the same layer, the target memory cell layer where the target word line is located can be selected through the word line layer selection lines, the word line row selection lines extend along the third direction perpendicular to the substrate and are connected with the grid electrodes of the first selection transistors of a column arranged in the third direction, the target row where the target word line is located can be selected through the word line row selection lines, and the word lines connected with the grid electrodes of the unit selection transistors of the target row of the target memory cell layer are the target word lines. The word line row selection lines extend along a third direction perpendicular to the substrate, an independent row outgoing line is not required to be prepared to connect an external control circuit with the word line row selection lines, and the preparation method of the three-dimensional memory is simple and low in cost.
It should be understood that, although the steps in the flowchart of fig. 3 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in fig. 3 may include a plurality of steps or stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily sequential, but may be performed in rotation or alternatively with at least a portion of the steps or stages in other steps or other steps.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.

Claims (13)

1. A memory comprising a plurality of memory cell layers stacked in a vertical substrate direction, and a plurality of word lines and a plurality of bit lines correspondingly connected to each memory cell in the memory cell layers; wherein the word lines extend in a first direction parallel to the substrate, one of the word lines connecting a row of the memory cells in the memory cell layer; the bit lines extend along the direction vertical to the substrate, and one bit line is connected with one column of the memory cells which are arranged along the direction vertical to the substrate in different memory cell layers;
A word line selection circuit connected to each of the word lines, configured to: providing a layer selection signal and a row strobe signal in response to an access request, and gating a target word line according to the layer selection signal and the row strobe signal;
the word line selection circuit includes:
A layer selection circuit including a plurality of word line layer selection lines; the word line layer selection line is disposed corresponding to the memory cell layer and configured to: providing the layer selection signal to each of the word lines connected corresponding to the memory cell layer in response to the access request;
A row strobe circuit including a plurality of first row strobe circuits; the row strobe signal includes a first word line row strobe signal; the first row strobe circuit is correspondingly arranged with a row of word lines which are arranged in columns along the direction vertical to the substrate and are used for connecting corresponding memory cells in different memory cell layers, and is configured to: providing the first word line row strobe signal to each of the word lines of a corresponding column in response to the access request;
the word line layer select lines extend along a second direction parallel to the substrate, the second direction intersecting the first direction;
The first row strobe circuit includes: a word line row selection line, and a plurality of first selection transistors arranged in columns along a vertical substrate direction and arranged in one-to-one correspondence with one column of the word lines; wherein,
The word line row selection line extends along the direction vertical to the substrate and is connected with the grid electrode of one column of the first selection transistors;
The first selection transistor is located at a first end corresponding to the word line, a first source drain electrode of the first selection transistor is connected with the first end, and a second source drain electrode of the first selection transistor is connected with the corresponding word line layer selection line.
2. The memory of claim 1, wherein the row strobe circuit further comprises a plurality of second row strobe circuits; the row strobe signal further includes a second word line row strobe signal;
The second row strobe circuit is correspondingly arranged with a row of word lines which are arranged in a column along the direction vertical to the substrate and are used for connecting corresponding memory cells in different memory cell layers, and is configured to: in response to the access request, the second word line row strobe signal is provided to each of the word lines of the corresponding column.
3. The memory according to claim 2, wherein the first row strobe circuit and the second row strobe circuit connected to the same word line are respectively located at both ends of the word line, and potentials of the first word line row strobe signal and the second word line row strobe signal are opposite.
4. The memory of claim 2, wherein the second row strobe circuit comprises: a word line row counter selection line, and a plurality of second selection transistors which are arranged in columns along the direction vertical to the substrate and are arranged in one-to-one correspondence with one column of the word lines; wherein,
The word line row counter selection line extends along the direction vertical to the substrate and is connected with the grid electrode of one column of the second selection transistors;
The second selection transistor is positioned at a second end corresponding to the word line, and the first end and the second end of the word line are opposite in the first direction; the first source-drain electrode of the second selection transistor is connected with the second end, and the second source-drain electrode of the second selection transistor is connected with the reference voltage end.
5. The memory of claim 4, wherein the reference voltage terminal comprises a reference voltage signal line extending in a direction perpendicular to the substrate; the second source and drain electrodes of the second selection transistors in the same second row gating circuit are connected to the same reference voltage signal line;
Or, the reference voltage terminal comprises a reference voltage conductive wall extending along the direction vertical to the substrate; and the second source and drain electrodes of the second selection transistors in different second row strobe circuits are connected to the reference voltage conducting wall.
6. The memory of claim 1, wherein the layer selection circuit further comprises:
The layer leading-out structure is used for being connected with an external control circuit and comprises a plurality of layer leading-out wires; the layer outgoing line is correspondingly connected with the word line layer selection line and extends and is led out along the direction vertical to the substrate.
7. The memory according to any one of claims 1 to 6, further comprising:
a bit line selection circuit, located at the top or bottom of the memory cell layers and connected to each bit line, configured to: a bit line strobe signal is provided in response to the access request, and a target bit line is strobed according to the bit line strobe signal.
8. A memory access method, applied to the memory of any one of claims 1 to 7, comprising a plurality of memory cell layers stacked in a vertical substrate direction, and a plurality of word lines and a plurality of bit lines correspondingly connected to each memory cell in the memory cell layers; wherein the word lines extend in a first direction parallel to the substrate, one of the word lines connecting a row of the memory cells in the memory cell layer; the bit lines extend along the direction vertical to the substrate, and one bit line is connected with one column of the memory cells which are arranged along the direction vertical to the substrate in different memory cell layers;
The access method comprises the following steps:
In response to an access request, a layer selection signal and a row strobe signal are supplied to each of the word lines to which it is connected through a word line selection circuit, and a target word line is strobed according to the layer selection signal and the row strobe signal.
9. The method of accessing a memory according to claim 8, wherein the word line selection circuit comprises a layer selection circuit and a row strobe circuit; the layer selection circuit comprises a plurality of word line layer selection lines which are arranged corresponding to the memory cell layers; the row strobe circuit includes a plurality of first row strobe circuits; the row strobe signal includes a first word line row strobe signal; the first row strobe circuit is correspondingly arranged with a row of word lines which are arranged in a column along the direction vertical to the substrate and are used for connecting corresponding memory cells in different memory cell layers; wherein the word line selection circuit provides a layer selection signal and a row strobe signal to each of the connected word lines in response to an access request, comprising:
providing the layer selection signal to each of the word lines connected to the corresponding memory cell layer through the word line layer selection line in response to the access request;
In response to the access request, the first word line row strobe signal is provided to each of the word lines of a corresponding column through the first row strobe circuit.
10. The method of accessing a memory according to claim 9, wherein the row strobe circuit further comprises a plurality of second row strobe circuits; the second row strobe circuits are correspondingly arranged with a row of word lines which are arranged in a column along the direction vertical to the substrate and are used for connecting corresponding memory cells in different memory cell layers; the row strobe signal further includes a second word line row strobe signal; wherein the word line selection circuit supplies a layer selection signal and a row strobe signal to each of the connected word lines in response to an access request, further comprising:
In response to the access request, the second word line row strobe signal is provided to each of the word lines of a corresponding column through the second row strobe circuit.
11. The method according to claim 10, wherein the first row strobe circuit and the second row strobe circuit connected to the same word line are respectively located at both ends of the word line, and potentials of the first word line row strobe signal and the second word line row strobe signal are opposite.
12. The access method of a memory according to any one of claims 8 to 11, characterized in that the access method further comprises:
in response to the access request, a bit line strobe signal is supplied to each of the bit lines connected thereto through a bit line selection circuit, and a target bit line is strobed in accordance with the bit line strobe signal.
13. An electronic device comprising a memory as claimed in any one of claims 1 to 7.
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