CN118312110B

CN118312110B - Flash memory data processing method, device, computer equipment and storage medium

Info

Publication number: CN118312110B
Application number: CN202410734695.XA
Authority: CN
Inventors: 郭晓琳; 杨勇军; 王琨; 王瑞
Original assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Current assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority date: 2024-06-07
Filing date: 2024-06-07
Publication date: 2024-11-22
Anticipated expiration: 2044-06-07
Also published as: CN118312110A

Abstract

The present invention relates to the field of flash memory technology, and discloses a flash memory data processing method, device, computer equipment and storage medium, wherein the method comprises: obtaining application data, and storing the application data in a target data block in a data block of the flash memory; when it is detected that the number of reads for the application data exceeds the read threshold of the target data block, determining a migration position for the application data in the flash memory; encoding the application data based on a first encoding method corresponding to a data block matching the migration position, and storing the encoded application data in the migration position. The present invention can flexibly adopt a corresponding encoding method when processing application data through a corresponding data block, thereby improving the reliability of pages in the flash memory unit, thereby improving the performance of the flash memory, and increasing the service life of the flash memory.

Description

Flash memory data processing method, device, computer equipment and storage medium

Technical Field

The present invention relates to the field of flash memory technologies, and in particular, to a flash memory data processing method, apparatus, computer device, and storage medium.

Background

In QLC (Triple-LEVEL CELL, quad-level cell) flash memory, a flash read can distinguish whether a cell is above/below a certain voltage, so reading secondary data from such a cell typically involves multiple flash reads. For widely used flash data gray code encoding, the minimum flash read times for different pages can be used to represent a particular gray code selection. Based on this, in the related flash data processing scheme, a corresponding gray code is generally set for the flash data to encode the stored data according to the gray code.

However, there is a certain difference in read-write performance and reliability between different gray codes, and at the same time, the adoption of the fixed gray code coding mode can further deteriorate the reliability of part of pages in the flash memory unit, and the deterioration of the reliability can cause the increase of the number of times of data re-reading and writing in the flash memory, so that the performance of the flash memory is affected, and the service life of the flash memory is also affected.

Disclosure of Invention

In view of the above, the present invention provides a method, apparatus, computer device and storage medium for processing flash memory data, so as to solve the problem that the reliability of part of pages in a flash memory unit is further degraded by adopting a fixed gray code coding method.

In a first aspect, the present invention provides a flash memory data processing method, including:

Acquiring application program data, and storing the application program data into a target data block in a data block of a flash memory, wherein the data block in the flash memory comprises: a read data block related to read-only data and/or a write data block related to write data, wherein the read data block and the write data block are coded in different corresponding modes;

Determining a migration position for the application program data in the flash memory when the reading times of the application program data exceeds the reading threshold of the target data block, wherein the reading times are used for indicating the reading times of a preset page in the target data block;

And encoding the application program data based on a first encoding mode corresponding to the data block matched with the migration position, and storing the encoded application program data into the migration position.

In an alternative embodiment, storing the application data into a target data block of the data blocks of the flash memory includes:

Searching a second coding mode corresponding to the target data block based on mapping information, wherein the mapping information is used for representing the corresponding relation between the data block and the coding mode;

And coding the application program data according to the Gray code corresponding to the second coding mode, and storing the coded application program data into the target data block.

In the embodiment of the disclosure, the second coding mode corresponding to the target data block can be searched based on the mapping information in the DRAM, so that the arbitration of the Gray code coding mode based on the characteristics of the application program data is realized, and the reading performance and the writing performance of the flash memory are improved.

In an alternative embodiment, the target data block includes: writing a data block;

the step of encoding the application program data according to the balance gray code corresponding to the second encoding mode and storing the encoded application program data into the target data block comprises the following steps:

Performing coarse coding on a first page of the application program data based on the balanced gray code and the coarse coding steps of the second coding mode to obtain coarse coding data, wherein the first page comprises: most significant bits and high significant bits;

Performing fine coding on a second page of the coarse coded data based on the balanced gray code and the fine coding steps of the second coding mode to obtain coded data, and storing the coded data into the target data block, wherein the second page comprises: middle significant bit and low significant bit.

In the embodiment of the present disclosure, it is known from the above that the write data block is generally related to the write data in the flash memory, so the unbalanced coding modes TSP (4, 16) with better write performance and the corresponding gray codes GC (1,2,6,6) can be adopted in the write data block, thereby improving the write performance of the flash memory.

In an alternative embodiment, the flash memory includes: four-layer unit flash memory;

the method further comprises the steps of:

the method comprises the steps of obtaining Gray codes to be allocated corresponding to the four-layer unit flash memory, and respectively determining first mapping relations between various Gray codes and corresponding coding modes;

And respectively establishing second mapping relations between the read data block and the write data block and the corresponding Gray codes, and determining mapping information according to the first mapping relation and the second mapping relation.

In the embodiment of the disclosure, mapping relations can be respectively established for the BGC blocks and the UGC blocks, the corresponding gray codes with better read-write performance and the coding modes, so as to determine mapping information according to the mapping relations, thereby providing a technical basis for implementing gray code arbitration based on the characteristics of application program data.

In an alternative embodiment, when the target data block includes a read data block, the preset page includes: most significant bits, high significant bits, intermediate significant bits, and low significant bits; when the target data block includes a write data block, the preset page includes: most significant bits and high significant bits.

In the embodiment of the disclosure, corresponding reading thresholds can be set for each page according to the reading delays and weights of different page types in the QLC flash memory, so that granularity in setting the reading thresholds is thinned, and the reliability of the flash memory is further improved.

In an alternative embodiment, the determining manner of the read threshold of the target data block includes:

Acquiring a re-read-write operand in the flash memory, and determining a storage state corresponding to the flash memory according to the re-read-write operand;

And acquiring a preset threshold value matched with the storage state of the target data block, and determining the reading threshold value according to the preset threshold value.

In the embodiment of the present disclosure, due to the fact that the above UGC blocks and BGC blocks are different in reading reliability, corresponding preset thresholds may be set for the UGC blocks and BGC blocks, so that the reliability of the UGC blocks and the BGC blocks is ensured, and the overall reliability of the flash memory is improved.

In an alternative embodiment, the method further comprises:

Setting corresponding re-reading and writing operand intervals for the reading data block and the writing data block respectively based on re-reading and writing operands in the flash memory;

Setting corresponding storage states according to each re-read-write operand interval, and setting corresponding preset thresholds for each storage state.

In an alternative embodiment, the storage state of the flash memory includes: the storage device comprises a first storage state, a second storage state and a third storage state, wherein the re-read-write operands in the flash memory corresponding to the first storage state, the second storage state and the third storage state are sequentially increased;

the storing the application program data into the target data block in the data block of the flash memory further comprises:

When the flash memory is in a first storage state, determining an empty data block in the flash memory as the target data block, and storing the application program data into the empty data block; or alternatively

When the flash memory is in a second storage state, determining a write data block in the flash memory as the target data block, and storing the application program data into the write data block according to a coding mode corresponding to the write data block; or alternatively

And when the flash memory is in a third storage state, determining a read data block in the flash memory as the target data block, and storing the application program data into the read data block according to a coding mode corresponding to the read data block.

In the embodiment of the disclosure, considering that the number of times of the data re-reading and writing operation in the flash memory is gradually increased along with the decrease of the reliability of the flash memory, the flash memory can be divided into different storage stages according to the number of times of the data re-reading and writing operation in the flash memory, and different application program storage strategies are set for the different storage stages, so that the reliability of the flash memory in the different storage stages is improved.

In an alternative embodiment, the method further comprises:

Before the fact that the reading times of the application program data exceed the reading threshold value of the target data block is monitored, a preset threshold value of the read data block is determined based on the original bit error rate of the data read in the read data block.

In the embodiment of the present disclosure, when the preset threshold TBR corresponding to the BGC block is set, the value of the TBR may not be too large or too small, and if the value is too small, data migration may occur frequently, and if the value is too large, the reading performance may be affected. Therefore, the preset threshold value of the BGC block in each storage state of the flash memory can be set during setting, so that the applicability of the method for the different storage states of the flash memory is improved.

In an alternative embodiment, determining the preset threshold of the read data block based on the original bit error rate of the read secondary data in the read data block comprises:

decoding the data in the read data block based on the threshold sequence to be confirmed to obtain a decoded data sequence;

acquiring original data corresponding to the data in the read data block, and respectively determining an original bit error rate of each decoded data in a decoded data sequence and the original data;

and determining a threshold to be confirmed, which corresponds to the original bit error rate in the threshold sequence to be confirmed and meets the error rate condition, as the preset threshold.

In an alternative embodiment, decoding the data in the read data block based on the threshold sequence to be confirmed to obtain a decoded data sequence includes:

acquiring the simulation times of the threshold sequence to be confirmed, and determining whether the simulation times do not exceed the number of elements in the threshold sequence to be confirmed;

if yes, decoding the data in the read data block based on a decoding mode corresponding to the read data block to obtain a decoded data sequence;

And if not, decoding the data in the read data block based on the decoding mode corresponding to the write data block to obtain a decoded data sequence.

In the embodiment of the disclosure, the decoding mode can be adopted according to the comparison result of the simulation times of the Monte Carlo method and the number of elements in the threshold sequence to be confirmed, so that the accuracy of decoded data obtained by decoding is improved, and the accuracy of the determined preset threshold is further improved.

In an alternative embodiment, determining a migration location in the flash memory for the application data includes:

Determining a migration location for the application data in the read data block when the target data block comprises a write data block; or alternatively

Determining a migration location based on a target page of the write data block when the target data block includes a read data block, wherein the target page includes: middle significant bit and low significant bit.

In the embodiment of the disclosure, granularity of data migration between data blocks in the flash memory can be refined to a page level, so that the reliability of the flash memory is further improved.

In a second aspect, the present invention provides a flash memory data processing apparatus, the apparatus comprising:

the system comprises an acquisition module, a storage module and a storage module, wherein the acquisition module is used for acquiring application program data and storing the application program data into a target data block in a data block of a flash memory, wherein the data block in the flash memory comprises: reading and/or writing data blocks;

The determining module is used for determining a migration position for the application program data in the flash memory when the reading times of the application program data exceeds the reading threshold value of the target data block, wherein the reading times are used for indicating the reading times of a preset page in the target data block;

And the encoding module is used for encoding the application program data based on a first encoding mode corresponding to the data block matched with the migration position and storing the encoded application program data into the migration position.

In a third aspect, the present invention provides a computer device comprising: the flash memory data processing system comprises a memory and a processor, wherein the memory and the processor are in communication connection, the memory stores computer instructions, and the processor executes the computer instructions, so that the flash memory data processing method of the first aspect or any corresponding implementation mode is executed.

In a fourth aspect, the present invention provides a computer readable storage medium having stored thereon computer instructions for causing a computer to execute the flash memory data processing method of the first aspect or any of its corresponding embodiments.

In a fifth aspect, the present invention provides a computer program product comprising computer instructions for causing a computer to perform the flash memory data processing method of the first aspect or any of its corresponding embodiments.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram showing threshold voltage distribution of flash memory cells in QLC flash memory;

FIG. 2 is a flow chart of a flash data processing method according to an embodiment of the present invention;

FIG. 3 is a flow chart of another flash data processing method according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of encoding application data based on unbalanced encoding;

FIG. 5 is a flow chart of yet another flash data processing method according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a data storage manner between data blocks in different storage states in a flash memory;

FIG. 7 is a flow chart of encoding and decoding data in a flash memory;

FIG. 8 is a block diagram of a flash data processing system according to an embodiment of the present invention;

FIG. 9 is a block diagram of a flash data device according to an embodiment of the present invention;

fig. 10 is a schematic diagram of a hardware structure of a computer device according to an embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The application scenario is described herein in connection with an application scenario on which execution of a flash data processing method depends.

For example, as shown in fig. 1, the threshold voltage distribution of the flash memory cells in the QLC flash memory is shown, and the gray code commonly used in the QLC flash memory includes: GC (1, 2,4, 8), GC (1,2,6,6), GC (1,4,5,5) and GC (3, 4), wherein GC (1, 2,4, 8), GC (1,2,6,6) and GC (1,4,5,5) have better writing performance and GC (3, 4) have better reading performance. However, after the fixed gray code is set for the flash memory data, the read-write performance cannot be considered, and the reliability of a part of pages in the flash memory unit is further deteriorated.

Based on the above, the invention provides a flash memory data processing method, which comprises the following steps: acquiring application program data, and storing the application program data into a target data block in a data block of a flash memory, wherein the data block in the flash memory comprises: and the read data block related to the read-only data and/or the write data block related to the write data, and meanwhile, the coding mode of the read data block corresponding to the write data block is different. When the reading times of the application program data exceeds the reading threshold value of the target data block, determining a migration position for the application program data in the flash memory, wherein the reading times are used for indicating the reading times of preset pages in the target data block. Then, the application data may be encoded based on a first encoding scheme corresponding to the data block that matches the migration location, and the encoded application data may be stored in the migration location. The invention can partition the data blocks of the flash memory, and the Gray codes and the coding modes corresponding to different data blocks are different, so that the corresponding coding modes can be flexibly adopted when the application program data is processed through the corresponding data blocks, the reliability of pages in the flash memory unit is improved, the performance of the flash memory is further improved, and the service life of the flash memory is prolonged.

In accordance with an embodiment of the present invention, there is provided a flash memory data processing method embodiment, it being noted that the steps shown in the flowchart of the figures may be performed in a computer system such as a set of computer executable instructions, and, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in an order other than that shown or described herein.

In this embodiment, a flash data processing method is provided, which may be used in the QLC flash memory described above, and fig. 2 is a flowchart of a flash data processing method according to an embodiment of the present invention, as shown in fig. 2, where the flowchart includes the following steps:

step S201, acquiring application program data, and storing the application program data into a target data block in a data block of a flash memory, wherein the data block in the flash memory includes: and the read data block related to the read-only data and/or the write data block related to the write data are coded in different modes corresponding to the write data block.

In the embodiment of the disclosure, the read data block may be a BGC (balanced Gray Code ) block, and the write data block may be a UGC (Unbalanced Gray Code ) block. Here, the read data block and the write data block are both determined by a blank data block in the flash memory, and specifically, the blank data block stored with the read-only data may be determined as the read data block, and the blank data block stored with the write data may be determined as the write data block.

It should be understood that the encoding mode corresponding to the BGC block may be a balanced encoding mode, and the corresponding gray code may be GC (3, 4). Here, the balanced coding scheme may be TSP (16, 16), in which TSP is two steps of coding the flash word line based on gray code, the number of coding steps of the first step coarse coding is 16, and the number of coding steps of the second step fine coding is 16.

In addition, the encoding mode corresponding to the UGC block may be an unbalanced encoding mode, and the corresponding gray code may be GC (1,2,6,6). Here, the unbalanced coding scheme may be TSP (4, 16), in which the number of coding steps of the first coarse coding is 4 and the number of coding steps of the second fine coding is 16. Here, the balanced encoding scheme TSP (16, 16) has a good read performance, and the unbalanced encoding scheme TSP (4, 16) has a good write performance.

Considering that the characteristics of the application program data are generally unknown before execution, that is, the application program data cannot be determined to be read-only data, write data or read-write interleaved access data, the application program data can be stored in the BGC block or the blank data block according to the encoding mode corresponding to the BGC block, so that the stored data have better reading performance, and the reliability of the data read in the flash memory in the follow-up process is improved.

And then, continuously detecting the characteristics of the application program data, and determining a target data block corresponding to the application program data based on the detected characteristics, thereby realizing arbitration of the used Gray code coding mode. For example, if it is detected that the application data is characterized as read-only data, the BGC block may be determined as a target data block to continue storing the application data in the BGC block. If the subsequent application data is detected to be write data, the UGC block can be determined to be a target data block, so that the subsequent application data is stored in the UGC block. If the application program data is the read-write interleaved access data, a corresponding target data block can be selected based on the read-write proportion in the application program data, for example, when the read proportion is high, the BGC block is determined to be the target data block, and when the write proportion is high, the UGC block is determined to be the target data block.

In step S202, when it is detected that the number of times of reading the application data exceeds the reading threshold of the target data block, determining a migration position for the application data in the flash memory, where the number of times of reading is used to indicate the number of times of reading the preset page in the target data block.

In the embodiment of the disclosure, considering that the flash memory unit gradually generates bad blocks with the increase of the usage time, for example, if the flash memory unit has a write frequency limitation, frequent read operations are usually accompanied by erase and write operations, and when a certain write frequency is reached, the memory unit may fail due to wear and tear, and be converted into bad blocks.

Based on the above, the number of read operations for the application data in the flash memory, that is, the number of read operations, can be detected, so that the application data is migrated at an appropriate time, and bad blocks are avoided, thereby improving the reliability of the flash memory.

Specifically, considering that there is a certain difference in read-write performance and reliability between different gray codes, this results in a difference in read-write reliability of the flash memory cell page between different data blocks. For example, in the above QLC flash memory, the flash cell page may include: LSB (LEAST SIGNIFICANT Bit, low significant Bit), CSB (CENTRAL SIGNIFICANT Bit, middle significant Bit), MSB (Most Significant Bit, high significant Bit), and TSB (Top Significant Bit, most significant Bit).

In the QLC flash memory, the read reliability of the LSB and MSB pages in the UGC block is higher than that of the CSB and TSB pages, and in the BGC block, the read reliability of each page is balanced. Therefore, corresponding read thresholds can be set for the UGC blocks and the BGC blocks respectively, so that the reliability of the flash memory is ensured.

When the above read threshold is set, the granularity may be as fine as the page in the flash memory unit, for example, corresponding read thresholds are set for different pages in the UGC block and the BGC block, respectively.

Step S203, the application data is encoded based on the first encoding mode corresponding to the data block matched with the migration position, and the encoded application data is stored in the migration position.

In the embodiment of the present disclosure, the first encoding mode may be determined according to an encoding mode corresponding to a data block that matches the migration position, for example, if the data block corresponding to the migration position is the UGC, the first encoding mode may be the unbalanced encoding mode TSP (4, 16).

Considering that when data migration is performed, the migration position often spans data blocks, and therefore, application data needs to be recoded according to the coding mode of the data block corresponding to the migration position.

Specifically, the granularity of data migration may be as fine as a page unit, for example, when the TSB of the UGC block and the data in the CSB page are migrated into the BGC block, application data to be migrated may be cached in DRAM (Dynamic Random Access Memory ), and data to be written into the LSB and MSB pages of the BGC block are waited for, so that the data to be migrated and the data to be written into the BGC block are combined and written together, thereby reducing the data writing frequency.

As can be seen from the above description, in the embodiment of the present disclosure, the application program data is acquired and stored into a target data block in a data block of a flash memory, where the data block in the flash memory includes: and the read data block related to the read-only data and/or the write data block related to the write data, and meanwhile, the coding mode of the read data block corresponding to the write data block is different. When the reading times of the application program data exceeds the reading threshold value of the target data block, determining a migration position for the application program data in the flash memory, wherein the reading times are used for indicating the reading times of preset pages in the target data block. Then, the application data may be encoded based on a first encoding scheme corresponding to the data block that matches the migration location, and the encoded application data may be stored in the migration location. The invention can partition the data blocks of the flash memory, and the Gray codes and the coding modes corresponding to different data blocks are different, so that the corresponding coding modes can be flexibly adopted when the application program data is processed through the corresponding data blocks, the reliability of pages in the flash memory unit is improved, the performance of the flash memory is further improved, and the service life of the flash memory is prolonged.

In this embodiment, another method for processing flash data is provided, which may be used for the QLC flash memory, and fig. 3 is a flowchart of a method for processing flash data according to an embodiment of the present invention, as shown in fig. 3, where the flowchart includes the following steps:

step S301, acquiring application program data, and storing the application program data into a target data block in a data block of a flash memory, wherein the data block in the flash memory includes: and the read data block related to the read-only data and/or the write data block related to the write data are coded in different modes corresponding to the write data block.

Specifically, the step S301 includes:

Step S3011, searching for a second coding mode corresponding to the target data block based on mapping information, where the mapping information is used to characterize a correspondence between the data block and the coding mode.

Step S3012, the application program data is encoded according to the Gray code corresponding to the second encoding mode, and the encoded application program data is stored in the target data block.

In the embodiment of the present disclosure, a mapping relationship may be established in advance based on a data block in a flash memory and a corresponding coding manner, and mapping information may be determined according to the mapping relationship, where the mapping information may include GCB (Gray Code Bitmap) corresponding to the coding manner of each data block.

Here, the mapping information may be cached in the DRAM to invoke the DRAM to implement tracking of which gray code coding mode is selected for each data block, so as to select different gray code coding modes for application program data with different features. For example, the read performance is improved by adopting a Gray code coding mode with better read performance, and the write performance is improved by adopting a Gray code coding mode with better programming performance, so that Gray code arbitration is performed based on the characteristics of the application program data.

It should be appreciated that since the target data block and the data block corresponding to the migration position are generally different, the second encoding scheme is also generally different from the first encoding scheme.

In step S302, when it is detected that the number of times of reading the application data exceeds the reading threshold of the target data block, determining a migration position for the application data in the flash memory, where the number of times of reading is used to indicate the number of times of reading the preset page in the target data block. Please refer to step S202 in the embodiment shown in fig. 2, which is not described herein.

Step S303, the application program data is encoded based on the first encoding mode corresponding to the data block matched with the migration position, and the encoded application program data is stored in the migration position. Please refer to step S203 in the embodiment shown in fig. 2 in detail, which is not described herein.

In some alternative embodiments, the target data block includes: writing the data block, the step S3012 includes:

step a1, performing coarse coding on a first page of application program data based on a balance gray code and a coarse coding step number of a second coding mode to obtain coarse coding data, wherein the first page comprises: most significant bits and high significant bits.

Step a2, performing fine coding on a second page of coarse coded data based on the balance gray code and the fine coding steps of a second coding mode to obtain coded data, and storing the coded data into a target data block, wherein the second page comprises: middle significant bit and low significant bit.

In the embodiment of the disclosure, when the target data block is the UGC block, the second encoding mode may be an unbalanced encoding mode TSP (4, 16) in the form of TSP (M, N), and the gray code corresponding to the encoding mode may be the GC (1,2,6,6), where M is used to indicate a coarse encoding step number and N is used to indicate a fine encoding step number. Here, the TSP (4, 16) has a coarse encoding step number of 4 and a fine encoding step number of 16.

Fig. 4 is a schematic diagram of encoding application data based on the unbalanced encoding mode, wherein the first step is to instruct to perform coarse programming on a first page to obtain coarse encoded data, where the first page is the MSB and the TSB. In addition, the second step is used for indicating to perform fine programming on a second page of the coarse coded data to obtain the coded data, wherein the second page is the LSB and CSB.

In some optional embodiments, the flash memory includes: four-layer unit flash memory, namely the QLC flash memory unit, wherein the target data block comprises: writing the data block, the step S301 includes:

And b1, acquiring Gray codes to be allocated corresponding to the four-layer unit flash memory, and respectively determining a first mapping relation between various Gray codes and corresponding coding modes.

And b2, respectively establishing second mapping relations between the read data block and the write data block and the corresponding Gray codes, and determining mapping information according to the first mapping relation and the second mapping relation.

In the embodiment of the present disclosure, after the gray codes to be allocated are obtained, a coding mode with the best programming effect corresponding to each gray code to be allocated may be allocated to establish a first mapping relationship between each gray code and the corresponding coding mode, and the mode of determining the coding mode with the best programming effect specifically may be implemented, which is not limited in this disclosure.

Specifically, in the above QLC flash memory, the gray code to be allocated may include: GC (1, 2,4, 8), GC (1,2,6,6), GC (1,4,5,5) and GC (3, 4), wherein a first mapping relationship between Gray codes GC (1, 2,4, 8), GC (1,2,6,6), GC (1,4,5,5) and the coding modes TSP (4, 16) and a first mapping relationship between Gray codes GC (3, 4) and the coding modes TSP (16, 16) can be established.

Then, a second mapping relation between the BGC block and the gray code with better reading performance can be established, and a second mapping relation between the UGC block and the gray code with better writing performance can be established.

Specifically, a second mapping relationship between the BGC block and the balance gray code may be established, for example, a second mapping relationship between the BGC block and the balance gray code GC (3, 4). In addition, a second mapping relationship between the UGC blocks and the unbalanced gray codes described above, for example, a second mapping relationship between the UGC blocks and the unbalanced gray codes GC (1, 2,4, 8), GC (1,2,6,6), and GC (1,4,5,5) described above, may be established.

In some alternative embodiments, when the target data block includes a read data block, the preset page includes: most significant bits, high significant bits, intermediate significant bits, and low significant bits; when the target data block includes a write data block, the preset page includes: most significant bits and high significant bits.

In the embodiments of the present disclosure, in the above QLC flash memory, it is considered that there is a difference in both read delay and reliability among different types of flash pages. Specifically, LSB (low significant bit) pages have the smallest read delay and the best reliability, while TSB (most significant bit) pages have the largest read delay and the worst reliability, with a delay difference between LSB page and TSB page up to 20 times.

The above-described flash pages can be classified into three types according to asymmetric read latency: type one, the TSB and MSB of the UGC blocks tend to have higher read latency; type two, all pages in the BGC block, with read latency in the mid-range; type three, LSB (low significant bit) and CSB (intermediate significant bit) pages in the UGC blocks have relatively low read latency.

In addition, in the above UGC block, MSB represents the bit with the greatest weight in binary coding, and its variation has the greatest effect on the whole value. In gray codes, MSBs are typically used to represent the most important information bits. Second, TSB and LSB represent the least weighted bit and the next least weighted bit, respectively, whose variation in binary encoding has relatively little effect on the overall value. In gray codes, these two bits are typically used to represent less important information bits. Finally, CSB is a bit between MSB and LSB, with its weight and impact between the two.

In particular, when reading the data of these different bits, their contribution to the whole value is also different, due to their different weights in the encoding. In practical applications this may mean that different bit variations may cause different degrees of influence when processing signals or data. For example, a change in MSB and TSB may result in a significant change in the overall value, while a change in CSB and LSB may result in only a minor change.

Based on this, in the above UGC block, the TSB and MSB pages may be set as preset pages based on consideration of read delay and weight. Meanwhile, in the BGC block, all pages (TSB, MSB, LSB and CSB) in the BGC block are set as preset pages.

In this embodiment, there is provided another flash data processing method, which may be used in the above QLC flash memory, and fig. 5 is a flowchart of another flash data processing method according to an embodiment of the present invention, as shown in fig. 5, where the flowchart includes the following steps:

Step S501, acquiring application program data, and storing the application program data into a target data block in a data block of a flash memory, where the data block in the flash memory includes: and the read data block related to the read-only data and/or the write data block related to the write data are coded in different modes corresponding to the write data block. Please refer to step S201 in the embodiment shown in fig. 2 in detail, which is not described herein.

In step S502, when it is detected that the number of times of reading the application data exceeds the reading threshold of the target data block, determining a migration position for the application data in the flash memory, where the number of times of reading is used to indicate the number of times of reading the preset page in the target data block.

Specifically, in the above step S502, the determination method of the read threshold of the target data block includes:

Step S5021, obtaining the re-read-write operand in the flash memory, and determining the storage state corresponding to the flash memory according to the re-read-write operand.

Step S5022, a preset threshold value of matching the target data block with the storage state is obtained, and a reading threshold value is determined according to the preset threshold value.

Step S503, encoding the application program data based on the first encoding mode corresponding to the data block matched with the migration position, and storing the encoded application program data in the migration position. Please refer to step S203 in the embodiment shown in fig. 2 in detail, which is not described herein.

In the embodiments of the present disclosure, the reliability of the flash memory may gradually decrease with the increase of the usage period, for example, the memory cells may undergo multiple program and erase operations with the usage of the flash memory, which may cause physical wear. Particularly QLC type flash memories, have reduced service life due to the need to traverse a thinner silicon dioxide layer to store more bits, which makes the oxide layer more easily thinner. In addition, over time, even if a write operation is not performed, the charge stored in the flash memory cell may gradually decrease due to leakage, which may also affect the reliability of the data.

With the decrease of the reliability of the flash memory, the number of times of the data re-reading and writing operations in the flash memory gradually increases, so that the preset threshold corresponding to each data block in different storage states of the flash memory can be preset, the storage state corresponding to the flash memory is determined based on the re-reading and writing operation number in the flash memory, and the preset threshold corresponding to the data block which is not decocted is searched according to the storage state.

Specifically, the setting mode of the preset threshold value includes:

And c1, setting corresponding re-reading and writing operand intervals for the reading data block and the writing data block respectively based on re-reading and writing operands in the flash memory.

And c2, setting a corresponding storage state according to each re-read-write operand interval, and setting a corresponding preset threshold value for each storage state.

In the embodiment of the present disclosure, based on the re-read/write operands in the flash memory, corresponding re-read/write operand intervals are set for the read data block and the write data block, respectively, and a corresponding storage state is set according to each re-read/write operand interval, which is not described herein.

When setting the corresponding preset threshold for the storage state of the data block, the preset threshold TUR (Threshold Update Read ) corresponding to the UGC block may be set first, for example, the TUR may be set to 1 fixedly regardless of the storage state of the flash memory, that is, when the data is read at the TSB or MSB of the UGC block, the read threshold may be considered to be exceeded, so that the application data is migrated to the BGC block.

In addition, when the preset threshold value TBR corresponding to the BGC block is set, the value of the TBR may not be too large or too small, and if the value TBR is too small, data migration may occur frequently, and if the value TBR is too large, the reading performance may be affected. Therefore, the preset threshold value of the BGC block in each storage state of the flash memory may be set during the setting, so as to improve the applicability of the present disclosure to different storage states of the flash memory, and the specific setting process is described below, which is not repeated here.

In some alternative embodiments, the storage state of the flash memory includes: a first storage state, a second storage state, and a third storage state, wherein, the re-read/write operands in the flash memory corresponding to the first storage state, the second storage state and the third storage state are sequentially increased, the step S201 further includes the following steps:

mode one: the flash memory is in a first storage state.

And determining the empty data block in the flash memory as a target data block, and storing the application program data into the empty data block.

In the disclosed embodiments, no additional rereading and re-writing operations occur during the first storage phase. It should be understood that the counter may be configured to count the number of times that the different pages in the UGC block and the BGC block are rewritten, so as to determine the storage state of the flash memory according to the number of times of the rewriting. Here, the more the number of times of reading the data, the higher the reading heat, and thus, the storage state of the flash memory may be determined based on the number of times of re-reading, and the specific storage state determining manner is not limited in the present disclosure.

FIG. 6 shows a data storage manner among data blocks in different storage states in a flash memory, wherein in the first storage state, UGC flash memory blocks are UGC blocks, and idle data blocks are empty data blocks.

In the UGC blocks, data A-H are written for the first time, and in the subsequent process, data A, C, F, G is updated and rewritten into the UGC blocks to obtain updated pages. The page of data A, C, F, G in the original location may then be determined to be an updated invalid page. Next, the application data may be written into the empty data blocks of the flash memory.

Mode two: the flash memory is in a second storage state, a write data block in the flash memory is determined to be a target data block, and application program data is stored in the write data block according to a coding mode corresponding to the write data block.

In the disclosed embodiments, the TSB and MSB pages of UGC may introduce a reread operation during the second storage phase. At this time, the BGC block may be used as a default data block, so that the gray code corresponding to the BGC block may be determined as a default gray code. Specifically, after the acquired application data is updated into the UGC block, the application data with the number of times of reading in TSB and MSB pages in the UGC block exceeding the TUR may be updated into the BGC block.

Specifically, as shown in fig. 6, in the second storage state (i.e., stage two in the figure), in storing the application data A, C, F, G in the UGC block, the number of reads of A, C, F, G may be detected, and F, G, in which the number of reads exceeds the TUR, may be determined as thermal read data. Then F, G may be updated into the CSB and LSB pages of the BGC block (the BGC flash block in fig. 6, i.e., the BGC block), and the CSB and LSB pages in the BGC block may be determined as hot pages in which hot read data is stored.

Mode three: the flash memory is in a third storage state, a read data block in the flash memory is determined to be a target data block, and application program data is stored in the read data block according to a coding mode corresponding to the read data block.

In the embodiment of the disclosure, during the second storage phase, the page of the BGC is also reread. At this time, bad blocks appear in the TSB and MSB pages in the UGC blocks, and the encoding mode corresponding to the UGC is not reliable any more.

Thus, application data A, C, F, G may be stored in the BGC block and the number of reads of all data A-H and A, C, F, G in the BGC block may be detected. When B, D is detected to have read times exceeding the above TBR, hot read data B, D can be stored in CSB and LSB pages of UGC.

In some alternative embodiments, before it is detected that the number of reads for the application data exceeds the read threshold for the target data block, the embodiment corresponding to fig. 2 above further includes the following process:

A preset threshold value of the read data block is determined based on an original bit error rate of the data read in the read data block.

In the embodiment of the present disclosure, it is known from the above that the read threshold TUR of the UGC block is generally set to a fixed value, and when the preset threshold TBR corresponding to the BGC block is set, the value of the TBR may not be too large or too small, and if too small, data migration may occur frequently, and if too large, the read performance may be affected. Therefore, a preset threshold value of the BGC block in each storage state of the flash memory can be set at the time of setting.

Specifically, determining the preset threshold of the read data block includes:

and S11, decoding the data in the read data block based on the threshold sequence to be confirmed to obtain a decoded data sequence.

Step S12, obtaining the original data corresponding to the data in the read data block, and respectively determining the original bit error rate of each decoded data in the decoded data sequence corresponding to the original data.

And S13, determining a to-be-confirmed threshold value, corresponding to the original bit error rate in the to-be-confirmed threshold value sequence, meeting the error rate condition as a preset threshold value.

In the embodiment of the present disclosure, a plurality of thresholds to be confirmed may be preset to obtain a sequence of thresholds to be confirmed xi (i=1, 2, …, m), and the influence of different thresholds to be confirmed on the reliability of the flash memory is analyzed by adopting a monte carlo method, so as to obtain a preset threshold.

Fig. 7 is a schematic flow chart of encoding and decoding data in a flash memory, wherein first, various encoding can be performed on original transmission data Sn according to an encoding mode in a BGC block to obtain original data S 'n, and then, the signal Rn can be obtained by transmitting the S' n through a channel according to any to-be-confirmed threshold xi in a to-be-confirmed threshold sequence. Where No represents flash channel noise, which is used to represent the integration of additive noise such as program or erase disturb, intercell disturb, endurance disturb, random telegraph noise, etc.

Next, the target signal R 'n may be obtained by performing channel detection on Rn, and the target signal R' n may be decoded by a source to obtain Yn, so as to calculate the original bit error rate RBERi based on Yn and the original data Sn.

It should be appreciated that the original bit error rate corresponding to each to-be-confirmed threshold in the to-be-confirmed threshold sequence xi may be calculated by the above manner of calculating the original bit error rate, so as to obtain an error rate matrix [ RBER1, RBER2, …, RBERm-1, rberm ]. Then, the original bit error rate RBERmin with the minimum error rate can be determined through the error rate condition, so that the threshold to be confirmed corresponding to RBERmin is determined as a preset threshold.

In some alternative embodiments, the step S11 includes:

And acquiring the simulation times of the threshold sequence to be confirmed, and determining whether the simulation times do not exceed the number of elements in the threshold sequence to be confirmed.

Specifically, if so, decoding the data in the read data block based on a decoding mode corresponding to the read data block to obtain a decoded data sequence;

If not, decoding the data in the read data block based on the decoding mode corresponding to the write data block to obtain a decoded data sequence.

In the embodiment of the present disclosure, it is known from the above that the monte carlo method may be used to analyze the influence of different thresholds to be confirmed on the reliability of the flash memory, so as to obtain the preset threshold. Therefore, when the target signal is decoded by the source to obtain the decoded data Yn, it can be determined whether the simulation number N of the monte carlo method does not exceed the element number i in the threshold sequence to be confirmed.

Specifically, if N is greater than or equal to i, R 'N is decoded according to Gray codes GC (3, 4) corresponding to BGC to obtain Yn, and if N is less than i, R' N is decoded according to Gray codes GC (1,2,6,6) corresponding to UGC to obtain Yn.

In this embodiment, a further method for processing flash data is provided, which may be used in the QLC flash memory described above, where the process includes the following steps:

Step S801, acquiring application program data, and storing the application program data into a target data block in a data block of a flash memory, wherein the data block in the flash memory includes: and the read data block related to the read-only data and/or the write data block related to the write data are coded in different modes corresponding to the write data block. Please refer to step S201 in the embodiment shown in fig. 2 in detail, which is not described herein.

In step S802, when it is detected that the number of times of reading the application data exceeds the reading threshold of the target data block, determining a migration position for the application data in the flash memory, where the number of times of reading is used to indicate the number of times of reading the preset page in the target data block. Please refer to step S202 in the embodiment shown in fig. 2, which is not described herein.

Step S803, the application data is encoded based on the first encoding mode corresponding to the data block matched with the migration position, and the encoded application data is stored in the migration position.

Specifically, the step S803 includes:

Determining a migration location for the application data in the read data block when the target data block comprises the write data block; or determining a migration position based on a target page of the write data block when the target data block comprises the read data block, wherein the target page comprises: middle significant bit and low significant bit.

In the embodiment of the present disclosure, considering that the reliability of the MSB and TSB pages in the UGC block is poor, the preset pages in the UGC block are the MSB and TSB pages, and the reliability of the pages in the BGC block is relatively balanced, so that the preset pages in the BGC block are all the pages, that is, LSB, CSB, MSB and TSB.

Therefore, when data in the UGC is migrated into the BGC, any page in the BGC can be used as a migration position, and when data in the BGC is migrated into the UGC, the LSB and CSB pages with higher reliability in the UGC can be used as target pages, so that the migration position is determined according to the target pages.

There is also provided in this embodiment a flash data processing system, which may be used in the QLC flash memory described above, and fig. 8 is a frame diagram of a flash data processing system according to an embodiment of the present invention, where the flash data processing system includes: SSD (Solid STATE DRIVE, solid state disk) controller, FTL (Flash Translation Layer ) and flash memory, wherein;

and the SSD controller is used for connecting the flash memory interface and the host interface, regulating data read-write among the flash memory chips, ensuring the loss balance of the flash memory chips, controlling garbage collection in the flash memory, and simultaneously carrying out coding error correction in the flash memory.

FTL, configured to perform arbitration of the gray code encoding method in the embodiment corresponding to fig. 2, where the DRAM is configured to store the mapping information GCB, so as to perform implementation of determining the target data block in the embodiment corresponding to fig. 3.

In the embodiment of the disclosure, the initial gray code arbitration, that is, the implementation of determining the target data block corresponding to the application program and storing the application program data into the target data block corresponding to the step S201. The hot data gray code arbitration, that is, the step S203, is an embodiment of encoding the application data based on the first encoding method corresponding to the data block matched with the migration position, and storing the encoded application data in the migration position. In the gray code arbitration perceived in the reliability phase, the reliability phase includes the first storage state to the third storage state, and the gray code arbitration in the present phase is the embodiment corresponding to the step S201.

And the flash memory is used for providing read-write operation for the application program data.

In the embodiment of the present disclosure, the UGC block and the BGC block are included, so that the obtained application data is stored in the UGC block or the BGC block by the controller, and a specific data storage process is not specifically limited in the present disclosure. Meanwhile, an encoding part encoding the application data and a decoding part decoding the application data are provided to encode or decode the application data in response to a read-write operation for the application data.

The embodiment also provides a flash memory data processing device, which is used for implementing the above embodiment and the preferred implementation, and is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

The present embodiment provides a flash memory data processing apparatus, as shown in fig. 9, including:

an acquiring module 901, configured to acquire application program data and store the application program data into a target data block in a data block of a flash memory, where the data block in the flash memory includes: reading and/or writing data blocks;

A determining module 902, configured to determine a migration position for application data in the flash memory when it is detected that the number of times of reading the application data exceeds a reading threshold of a target data block, where the number of times of reading is used to indicate the number of times of reading a preset page in the target data block;

The encoding module 903 is configured to encode application data based on a first encoding mode corresponding to a data block that matches the migration location, and store the encoded application data in the migration location.

In some alternative embodiments, the acquiring module 901 includes:

the searching unit is used for searching a second coding mode corresponding to the target data block based on mapping information, wherein the mapping information is used for representing the corresponding relation between the data block and the coding mode;

And the coding unit is used for coding the application program data according to the Gray code corresponding to the second coding mode and storing the coded application program data into the target data block.

In some alternative embodiments, the target data block comprises: writing a data block; the encoding unit includes:

The coarse coding subunit is configured to perform coarse coding on a first page of application program data based on the balanced gray code and the coarse coding step number of the second coding mode to obtain coarse coded data, where the first page includes: most significant bits and high significant bits;

The fine coding subunit is configured to perform fine coding on a second page of the coarse coded data based on the balanced gray code and the number of fine coding steps in the second coding mode, to obtain coded data, and store the coded data into a target data block, where the second page includes: middle significant bit and low significant bit.

In some alternative embodiments, the flash memory includes: four-layer unit flash memory; the acquisition module 901 further includes:

The first determining unit is used for obtaining the Gray codes to be allocated corresponding to the four-layer unit flash memory and respectively determining a first mapping relation between various Gray codes and corresponding coding modes;

And the second determining unit is used for respectively establishing a second mapping relation between the read data block and the write data block and the corresponding Gray codes and determining mapping information according to the first mapping relation and the second mapping relation.

In some alternative embodiments, the determining module 902 includes:

the third determining unit is used for obtaining the re-read-write operand in the flash memory and determining the storage state corresponding to the flash memory according to the re-read-write operand;

and the fourth determining unit is used for acquiring a preset threshold value matched with the storage state of the target data block and determining a reading threshold value according to the preset threshold value.

In some alternative embodiments, the determining module 902 further comprises:

The first setting unit is used for setting corresponding re-reading operand intervals for the read data block and the write data block respectively based on re-reading operands in the flash memory;

the second setting unit is used for setting corresponding storage states according to each re-read-write operand interval and setting corresponding preset thresholds for each storage state.

In some alternative embodiments, the storage state of the flash memory includes: the flash memory comprises a first storage state, a second storage state and a third storage state, wherein the number of re-read-write operands in the flash memory corresponding to the first storage state, the second storage state and the third storage state is sequentially increased; the acquisition module 901 further includes:

A fifth determining unit, configured to determine, when the flash memory is in the first storage state, an empty data block in the flash memory as a target data block, and store the application program data into the empty data block; or when the flash memory is in the second storage state, determining a write data block in the flash memory as a target data block, and storing the application program data into the write data block according to the coding mode corresponding to the write data block; or when the flash memory is in the third storage state, determining the read data block in the flash memory as a target data block, and storing the application program data into the read data block according to the coding mode corresponding to the read data block.

In some alternative embodiments, the apparatus further comprises:

And a sixth determining unit for determining a preset threshold value of the read data block based on an original bit error rate of the data read in the read data block before it is monitored that the number of times of reading the application data exceeds the read threshold value of the target data block.

In some alternative embodiments, the sixth determining unit includes:

the decoding subunit is used for decoding the data in the read data block based on the threshold sequence to be confirmed to obtain a decoded data sequence;

the first determining subunit is used for acquiring original data corresponding to the data in the read data block and respectively determining an original bit error rate corresponding to each decoded data in the decoded data sequence and the original data;

And the second determining subunit is used for determining the to-be-confirmed threshold value, which is corresponding to the original bit error rate in the to-be-confirmed threshold value sequence and meets the error rate condition, as a preset threshold value.

In some alternative embodiments, the decoding subunit is further configured to:

In some alternative embodiments, the encoding module 903 includes:

a seventh determining unit configured to determine a migration position for the application data in the read data block when the target data block includes the write data block; or alternatively

An eighth determining unit configured to determine a migration position based on a target page of the write data block when the target data block includes the read data block, wherein the target page includes: middle significant bit and low significant bit.

Further functional descriptions of the above respective modules and units are the same as those of the above corresponding embodiments, and are not repeated here.

The flash memory data processing device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application SPECIFIC INTEGRATED Circuit) Circuit, a processor and a memory that execute one or more software or firmware programs, and/or other devices that can provide the above-described functions.

The embodiment of the invention also provides computer equipment, which is provided with the flash memory data processing device shown in the figure 9.

Referring to fig. 10, fig. 10 is a schematic structural diagram of a computer device according to an alternative embodiment of the present invention, as shown in fig. 10, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the computer device, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display device coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple computer devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 10 is illustrated in fig. 10.

The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.

Wherein the memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform the methods shown in implementing the above embodiments.

The memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 20 may optionally include memory located remotely from processor 10, which may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

Memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; the memory 20 may also comprise a combination of the above types of memories.

The computer device also includes a communication interface 30 for the computer device to communicate with other devices or communication networks.

The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.

Portions of the present invention may be implemented as a computer program product, such as computer program instructions, which when executed by a computer, may invoke or provide methods and/or aspects in accordance with the present invention by way of operation of the computer. Those skilled in the art will appreciate that the form of computer program instructions present in a computer readable medium includes, but is not limited to, source files, executable files, installation package files, etc., and accordingly, the manner in which the computer program instructions are executed by a computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Herein, a computer-readable medium may be any available computer-readable storage medium or communication medium that can be accessed by a computer.

Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.

Claims

1. A method for processing flash data, the method comprising:

Acquiring a to-be-confirmed threshold sequence corresponding to the read data block, and decoding data in the read data block to obtain a decoded data sequence;

determining a threshold to be confirmed, which is corresponding to the original bit error rate in the threshold sequence to be confirmed and meets the error rate condition, as a preset threshold;

Determining a read threshold of the read data block according to the preset threshold;

determining a migration position for the application program data in the flash memory when the reading times of the application program data exceeds the reading threshold value of the target data block, wherein the reading times are used for indicating the times of reading operations on a preset page in the target data block;

2. The method of claim 1, wherein storing the application data into a target one of the data blocks of the flash memory comprises:

3. The method of claim 2, wherein the target data block comprises: writing a data block;

4. The method of claim 2, wherein the flash memory comprises: four-layer unit flash memory;

the method further comprises the steps of:

5. The method of claim 1, wherein when the target data block comprises a read data block, the preset page comprises: most significant bits, high significant bits, intermediate significant bits, and low significant bits; when the target data block includes a write data block, the preset page includes: most significant bits and high significant bits.

6. The method according to claim 1, wherein the determining the read threshold of the target data block comprises:

7. The method of claim 6, wherein the method further comprises:

8. The method of claim 1, wherein the memory state of the flash memory comprises: the storage device comprises a first storage state, a second storage state and a third storage state, wherein the re-read-write operands in the flash memory corresponding to the first storage state, the second storage state and the third storage state are sequentially increased;

9. The method according to claim 1, wherein the method further comprises:

Before the fact that the reading times of the application program data exceed the reading threshold value of the target data block is detected, the preset threshold value of the read data block is determined based on the original bit error rate of the data read in the read data block.

10. The method of claim 9, wherein the determining the preset threshold for the read data block based on the original bit error rate of the read secondary data in the read data block comprises:

11. The method of claim 10, wherein decoding the data in the read data block based on the sequence of thresholds to be confirmed to obtain a decoded data sequence, comprising:

12. The method of claim 1, wherein said determining a migration location in said flash memory for said application data comprises:

13. A flash memory data processing apparatus, the apparatus comprising:

The system comprises an acquisition module, a storage module and a storage module, wherein the acquisition module is used for acquiring application program data and storing the application program data into a target data block in a data block of a flash memory, wherein the data block in the flash memory comprises: reading a data block and/or writing a data block, obtaining a threshold sequence to be confirmed corresponding to the data block, and decoding data in the data block to obtain a decoded data sequence; acquiring original data corresponding to the data in the read data block, and respectively determining an original bit error rate of each decoded data in a decoded data sequence and the original data; determining a threshold to be confirmed, which is corresponding to the original bit error rate in the threshold sequence to be confirmed and meets the error rate condition, as a preset threshold; determining a read threshold of the read data block according to the preset threshold;

a determining module, configured to determine a migration position for the application program data in the flash memory when it is monitored that a number of times of reading the application program data exceeds a reading threshold of the target data block, where the number of times of reading is used to indicate a number of times of reading operations on a preset page in the target data block;

14. A computer device, comprising:

A memory and a processor in communication with each other, the memory having stored therein computer instructions, the processor executing the computer instructions to perform the flash memory data processing method of any of claims 1 to 12.

15. A computer-readable storage medium having stored thereon computer instructions for causing a computer to perform the flash memory data processing method of any one of claims 1 to 12.

16. A computer program product comprising computer instructions for causing a computer to perform the flash data processing method of any one of claims 1 to 12.