CN118300603A - Self-bias phase-locked loop system and electronic equipment - Google Patents

Abstract

The application provides a self-bias phase-locked loop system and electronic equipment.A first input end of a phase frequency detector is used for accessing a reference clock signal, a second input end of the phase frequency detector is connected with an output end of a frequency divider, and the output end of the phase frequency detector is respectively connected with an input end of a charge pump and an input end of a lock detector; the output end of the charge pump is connected with the input end of the bias controller, the first output end of the bias controller is connected with the first input end of the voltage-controlled oscillator, the second output end of the bias controller is connected with the second input end of the voltage-controlled oscillator, and the first output end of the bias controller is also connected with the regulating end of the lock detector; the filter is connected between the charge pump and the bias controller; the output end of the voltage-controlled oscillator is connected with the input end of the frequency divider. The self-bias phase-locked loop system pair verification width can be flexibly set according to the bias controller pair output, and has the advantages of shorter locking time, higher flexibility and wide frequency working range.

Description

Self-bias phase-locked loop system and electronic equipment

Technical Field

The present application relates to the field of circuits, and in particular, to a self-biased phase-locked loop system and an electronic device.

Background

Self-biasing phase-locked loop systems are one of the basic building blocks in modern electronic systems, being widely used in communications, multimedia, and other applications. For example, frequency synthesizers, FM demodulators, clock recovery circuits, modems, and audio decoders are all applications related to self-biasing phase-locked loop systems.

During operation, the self-biased phase-locked loop system will adjust its value based on the reference signal and the feedback signal until it is in a locked state. How to shorten the locking time as much as possible under the condition of ensuring the precision becomes a problem which is focused on by the person skilled in the art.

Disclosure of Invention

It is therefore an object of the present application to provide a self-biasing phase locked loop system and an electronic device, which at least partially ameliorate the above problems.

In order to achieve the above object, the technical scheme adopted by the embodiment of the application is as follows:

In a first aspect, an embodiment of the present application provides a self-biased phase-locked loop system, including: the device comprises a phase frequency detector, a charge pump, a filter, a bias controller, a voltage controlled oscillator, a frequency divider and a lock detector;

the first input end of the phase frequency detector is used for accessing a reference clock signal, the second input end of the phase frequency detector is connected with the output end of the frequency divider, and the output end of the phase frequency detector is respectively connected with the input end of the charge pump and the input end of the lock detector;

the output end of the charge pump is connected with the input end of the bias controller, the first output end of the bias controller is connected with the first input end of the voltage-controlled oscillator, the second output end of the bias controller is connected with the second input end of the voltage-controlled oscillator, and the first output end of the bias controller is also connected with the regulating end of the lock detector;

The filter is connected between the charge pump and the bias controller;

The output end of the voltage-controlled oscillator is connected with the input end of the frequency divider.

In a second aspect, an embodiment of the present application provides an electronic device, including the self-biased phase-locked loop system described above.

Compared with the prior art, the self-bias phase-locked loop system and the electronic device provided by the embodiment of the application comprise: the device comprises a phase frequency detector, a charge pump, a filter, a bias controller, a voltage controlled oscillator, a frequency divider and a lock detector; the first input end of the phase frequency detector is used for accessing a reference clock signal, the second input end of the phase frequency detector is connected with the output end of the frequency divider, and the output end of the phase frequency detector is respectively connected with the input end of the charge pump and the input end of the lock detector; the output end of the charge pump is connected with the input end of the bias controller, the first output end of the bias controller is connected with the first input end of the voltage-controlled oscillator, the second output end of the bias controller is connected with the second input end of the voltage-controlled oscillator, and the first output end of the bias controller is also connected with the regulating end of the lock detector; the filter is connected between the charge pump and the bias controller; the output end of the voltage-controlled oscillator is connected with the input end of the frequency divider. The self-bias phase-locked loop system pair verification width can be flexibly set according to the bias controller pair output, and has the advantages of shorter locking time, higher flexibility and wide frequency working range.

In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a self-biased pll system according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a lock detector according to an embodiment of the present application;

FIG. 3 is a second schematic diagram of a lock detector according to an embodiment of the present application;

FIG. 4 is a second schematic diagram of a self-biased PLL system according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a voltage-controlled oscillator according to an embodiment of the present application.

In the figure: a 10-lock detector; 20-bias controller; 30-a voltage controlled oscillator; 40-a charge pump; a 50-filter; a 60-frequency divider; 70-phase frequency detector; 301-standard differential pairs; 302-a second unit.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

In the description of the present application, it should be noted that, directions or positional relationships indicated by terms such as "upper", "lower", "inner", "outer", etc., are directions or positional relationships based on those shown in the drawings, or those conventionally put in use in the application, are merely for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application.

In the description of the present application, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed", "connected" and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.

Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.

The purpose of the self-biasing phase-locked loop system is to align the clock on the circuit with some external clock (e.g., the clock corresponding to the reference clock signal, as described below) to achieve phase synchronization.

Referring to fig. 1, fig. 1 is a schematic diagram of a self-biased pll system according to an embodiment of the application. As shown in fig. 1, the self-biasing phase-locked loop system includes: a phase frequency detector 70 (Phase Frequency Detector, PFD), a Charge pump 40 (Charge pump), a filter 50 (LPF, low PASS FILTER), a Bias controller 20 (Bias Gen), a voltage controlled oscillator 30 (Voltage Controlled Oscillator, VCO), a frequency Divider 60 (Divider 1/N), and a Lock-in detector 10 (lock_det).

The first input end of the phase frequency detector 70 is used for accessing a reference clock signal (Fref), the second input end of the phase frequency detector 70 is connected to the output end of the frequency divider 60, and is used for receiving a feedback signal (Fdb) transmitted by the frequency divider 60, and the output end of the phase frequency detector 70 is respectively connected with the input end of the charge pump 40 and the input end of the lock detector 10.

The output of the charge pump 40 is connected to the input of the bias controller 20, the first output of the bias controller 20 is connected to the first input of the voltage controlled oscillator 30, the second output of the bias controller 20 is connected to the second input of the voltage controlled oscillator 30, and the first output of the bias controller 20 is also connected to the adjustment terminal of the lock detector 10.

The filter 50 is connected between the charge pump 40 and the bias controller 20.

The output of the voltage controlled oscillator 30 is connected to the input of the frequency divider 60.

Optionally, the phase frequency detector 70 is configured to generate a corresponding phase pulse error signal (UP or DN, also referred to as UPDN) according to the reference clock signal and the feedback signal transmitted by the frequency divider 60, and transmit the phase pulse error signal to the charge pump 40 and the lock detector 10.

The charge pump 40 is used for generating a corresponding charge signal according to the phase pulse error signal.

It should be noted that, the charge pump 40 generates a corresponding charge signal under the control of the phase pulse error signal, so as to charge or discharge the capacitor in the filter 50, and the corresponding current has the magnitude of I _cp. The wider the pulse width at which the phase pulse error signal remains high, the greater the current I _cp.

The filter 50 is used to filter out high frequency components on the path between the charge pump 40 to the bias controller 20.

Alternatively, the filter 50 may be a low pass filter.

The bias controller 20 is configured to generate a first bias signal and a second bias signal based on the filtered charge signal, transmit the first bias signal and the second bias signal to the voltage controlled oscillator 30, and transmit the first bias signal to the lock detector 10.

The voltage controlled oscillator 30 is used to adjust the output signal frequency according to the first bias signal and the second bias signal.

The voltage controlled oscillator 30 output signal frequency decreases when the bias Voltage (VBP) corresponding to the first bias signal increases, and the voltage controlled oscillator 30 output signal frequency increases when the bias Voltage (VBP) corresponding to the first bias signal decreases.

The frequency divider 60 is configured to divide the output signal of the voltage-controlled oscillator 30 to obtain a feedback signal, and transmit the feedback signal to the phase frequency detector 70.

It should be noted that, the frequency of the feedback signal output by the frequency divider 60 may be 1/N, n+.2 of the frequency of the output signal of the voltage-controlled oscillator 30. The phase frequency detector 70, the charge pump 40, the filter 50, the bias controller 20, the voltage-controlled oscillator 30 and the frequency divider 60 form a self-correction loop, and the reference clock signal and the feedback signal (i.e. the frequency-divided signal of the output signal of the voltage-controlled oscillator 30) output by the frequency divider 60 can be aligned by multiple self-corrections, or the phase deviation is smaller than a preset value, i.e. the self-biased phase-locked loop system achieves locking.

The lock detector 10 is configured to adjust a verification width (also referred to as RC delay width) according to the first bias signal and determine whether to lock according to the phase pulse error signal and the verification width.

When the width of the phase pulse error signal is smaller than the verification width, it means that the clock is stable, the lock signal outputted from the lock detector 10 is the high level signal 1, and otherwise, the lock signal is the low level signal 0.

Optionally, the smaller the bias voltage of the first bias signal, the smaller the verification width, the greater the bias current of the first bias signal; the smaller the bias current of the first bias signal, the larger the bias voltage of the first bias signal, and the larger the verification width.

The higher the output signal frequency of the voltage-controlled oscillator 30, the higher the frequency of the feedback signal, and at this time, the larger the bias current (Ibias) corresponding to the first bias signal output by the bias controller 20, the smaller the verification width, and the higher the lock detection accuracy of the self-biased phase-locked loop system (lock detector 10); when the frequency of the output signal of the voltage-controlled oscillator 30 is lower, the frequency of the feedback signal is also lower, and at this time, the smaller the bias current (Ibias) corresponding to the first bias signal output by the bias controller 20 is, the larger the verification width is, the lock detection accuracy of the self-biased phase-locked loop system (lock detector 10) is lowered, and the lock time can be shortened. The lower the frequency, the lower the jitter required for digital timing and application, and in order to reduce the lock time, the lock detection accuracy may be reduced.

In the self-bias phase-locked loop system provided by the scheme of the application, the verification width can be flexibly set, and the self-bias phase-locked loop system has the advantages of shorter locking time, higher flexibility and wide frequency working range.

A fixed verification width is employed with respect to the lock detector 10 to ensure that the self-biased phase-locked loop system (pll_clk_out) at different output frequencies and processes meets jitter (jitter) requirements, i.e., the design value of jitter (jitter) meets application requirements, as described below. Because the low frequency Phase Locked Loop (PLL) has poorer stability and large accumulated phase error in each period, under the same precision, the lock signal (lock signal) is more difficult to set to 1, that is, PLL locking is more difficult, but the low frequency output timing requirement is more relaxed in application, so the jitter requirement can be reduced, that is, the filtering width of the lock detection circuit can be increased. The high frequency output Phase Locked Loop (PLL) requirements are reversed, and the jitter is small because the timing requirements are strict, so the lock detection circuit requires a small filter width. Therefore, the invention provides a lock detection circuit adapting to different frequency outputs.

Referring to fig. 2, fig. 2 is a schematic diagram of a lock detector according to an embodiment of the application.

As shown in fig. 2, the lock detector 10 includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a first capacitor C1, and a second capacitor C2.

The gate of the first PMOS transistor P1 is connected to a first output terminal (VBP) of the bias controller 20 as an adjustment terminal of the lock detector 10.

It should be noted that, when VBP changes, the resistance value of the equivalent resistor R corresponding to the first PMOS transistor P1 also changes, so that the verification width may be changed.

The source of the first PMOS tube P1 is connected to a power supply (VCC), the drain of the first PMOS tube P1 is connected to the source of the second PMOS tube P2, and the source of the first NMOS tube N1 is connected to ground (VSS).

A connection terminal is led out from the connection position between the gate of the second PMOS transistor P2 and the gate of the first NMOS transistor N1, and is used as an input end of the lock detector 10, connected to an output end of the phase frequency detector 70, and receives a phase pulse error signal (UP or DN, also referred to as UPDN).

A connection terminal is led out from the connection position of the drain electrode of the second PMOS transistor P2 and the drain electrode of the first NMOS transistor N1, and is used as an output end of the lock detector 10 for outputting a lock signal.

One end of the first capacitor C1 is connected to the power source, and the other end of the first capacitor C1 is connected to the output end of the lock detector 10.

One end of the second capacitor C2 is connected to the ground, and the other end of the second capacitor C2 is connected to the output terminal of the lock detector 10.

Referring to fig. 3, fig. 3 is a second schematic diagram of a lock detector according to an embodiment of the application.

As shown in fig. 3, the lock detector 10 includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a third PMOS transistor P3, and a second NMOS transistor N2.

The third PMOS transistor P3 and the second NMOS transistor N2 serve as equivalent capacitors, which satisfies the production process.

The gate of the first PMOS transistor P1 is connected to a first output terminal (VBP) of the bias controller 20 as an adjustment terminal of the lock detector 10.

The source electrode of the first PMOS tube P1 is connected to a power supply, the drain electrode of the first PMOS tube P1 is connected to the source electrode of the second PMOS tube P2, and the source electrode of the first NMOS tube N1 is connected to the ground.

A connection terminal is led out from the connection position of the grid electrode of the second PMOS tube P2 and the grid electrode of the first NMOS tube N1, and is used as the input end of the lock detector 10 and is connected to the output end of the phase frequency detector 70.

A connecting terminal is led out from the connection part of the drain electrode of the second PMOS tube P2 and the drain electrode of the first NMOS tube N1 and is used as the output end of the lock detector 10.

The drain electrode and the source electrode of the third PMOS tube P3 are connected to a power supply, and the grid electrode of the third PMOS tube P3 is connected to the output end of the lock detector 10.

The drain and source of the second NMOS transistor N2 are connected to ground, and the gate of the second NMOS transistor N2 is connected to the output terminal of the lock detector 10.

Alternatively, the verification width in the scheme of the present application may be the product of the resistance R (or equivalent resistance) and the capacitance C (equivalent capacitance) in the lock detector 10, where the verification width varies with the resistance R, and the larger the resistance R, the larger the verification width, and the larger the width that can be filtered.

Referring to fig. 4, fig. 4 is a second schematic diagram of a self-biased pll system according to an embodiment of the application.

The bias controller 20 includes a first operational amplifier U1 and a third NMOS transistor N3.

The first end of the first op-amp U1 is used as an input end of the bias controller 20, connected to an output end of the charge pump 40, and has a corresponding voltage vc_int, and the first end of the first op-amp U1 is an inverting input end. When the loop is stable, vc_int is equal to VBP.

The second end of the first op-amp U1 is connected to the drain of the third NMOS transistor N3, and a connection terminal is led out at the junction of the second end and the drain as the first output end (VBP) of the bias controller 20, where the second end of the first op-amp U1 is the in-phase input end.

The output end of the first operational amplifier U1 is connected to the gate of the third NMOS transistor N3, and a connection terminal is led out at the connection position of the first operational amplifier U1 and the third NMOS transistor N as the second output end (VBN) of the bias controller 20.

The source of the third NMOS transistor N3 is connected to ground.

With continued reference to fig. 4, the charge pump 40 includes a fourth PMOS transistor P4, a fifth PMOS transistor P5, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, and a seventh NMOS transistor N7.

The source electrode of the fourth PMOS tube P4 and the source electrode of the fifth PMOS tube P5 are both connected to a power supply, the grid electrode of the fourth PMOS tube P4 is connected to the grid electrode of the fifth PMOS tube P5, and the grid electrode of the fourth PMOS tube P4 is connected to the drain electrode of the fourth PMOS tube P4.

The drain electrode of the fourth PMOS tube P4 is connected with the drain electrode of the fourth NMOS tube N4, the source electrode of the fourth NMOS tube N4 is connected with the drain electrode of the sixth NMOS tube N6, and the source electrode of the sixth NMOS tube N6 is connected with the ground.

The gate of the fourth NMOS transistor N4 is connected to the first output (UP) of the phase frequency detector 70 as the first input of the charge pump 40.

The drain electrode of the fifth PMOS transistor P5 is connected to the drain electrode of the fifth NMOS transistor N5, and a connection terminal is led out at the connection position of the drain electrode and the drain electrode as an output end of the charge pump 40, and is connected to the input end of the bias controller 20.

The source of the fifth NMOS transistor N5 is connected to the drain of the seventh NMOS transistor N7, and the source of the seventh NMOS transistor N7 is connected to ground.

The gate of the fifth NMOS transistor N5 is connected to the second output terminal (DN) of the phase frequency detector 70 as the second input terminal of the charge pump 40.

The gates of the sixth NMOS transistor N6 and the seventh NMOS transistor N7 are both connected to the second output terminal (VBN) of the bias controller 20.

With continued reference to fig. 4, the filter 50 includes a third capacitor C3, a sixth PMOS transistor P6, and a seventh PMOS transistor P7.

One end of the third capacitor C3 is connected to the power supply, and the other end of the third capacitor C3 is connected between the charge pump 40 and the bias controller 20 (vc_int).

The source of the sixth PMOS transistor P6 is connected to the power supply, the drain of the sixth PMOS transistor P6 is connected to the gate of the seventh PMOS transistor P7, and the gate of the sixth PMOS transistor P6 is connected between the charge pump 40 and the bias controller 20.

The source electrode of the seventh PMOS transistor P7 is connected to the power supply, the gate electrode of the seventh PMOS transistor P7 is connected to the drain electrode of the seventh PMOS transistor P7, and the drain electrode of the seventh PMOS transistor P7 is connected to the first output terminal (VBP) of the bias controller 20.

Referring to fig. 5, fig. 5 is a schematic structural diagram of a voltage-controlled oscillator according to an embodiment of the application. As shown in fig. 5, the voltage controlled oscillator 30 includes a standard differential pair 301 and K second cells 302, where K may be, but is not limited to, 3.

The ith second unit 302 includes an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, an eleventh PMOS transistor P11, an eighth NMOS transistor N8, a ninth NMOS transistor N9, and a tenth NMOS transistor N10.

The source of the eighth PMOS transistor P8, the source of the ninth PMOS transistor P9, the source of the tenth PMOS transistor P10, and the source of the eleventh PMOS transistor P11 are all connected to a power supply.

A connection terminal is led out from the connection position between the gate of the eighth PMOS transistor P8 and the gate of the eleventh PMOS transistor P11, and is used as the first input terminal (VBP) of the voltage-controlled oscillator 30.

The drain electrode of the eighth PMOS transistor P8 is connected to the gate electrode of the ninth PMOS transistor P9, the gate electrode of the ninth PMOS transistor P9 is connected to the drain electrode of the ninth PMOS transistor P9, the drain electrode of the ninth PMOS transistor P9 is connected to the drain electrode of the eighth NMOS transistor N8, and a connection terminal is led out at the junction of the drain electrode and the drain electrode as the first output end OUTPi of the ith second unit 302.

The drain electrode of the eleventh PMOS transistor P11 is connected to the gate electrode of the tenth PMOS transistor P10, the gate electrode of the tenth PMOS transistor P10 is connected to the drain electrode of the tenth PMOS transistor P10, the drain electrode of the tenth PMOS transistor P10 is connected to the drain electrode of the ninth NMOS transistor N9, and a connection terminal is led out at the junction of the drain electrode and the drain electrode as the second output end OUTNi of the ith second unit 302.

The gate of the eighth NMOS transistor N8 serves as the first control terminal INPi of the ith second unit 302, where when i=1, the first control terminal of the 1 st second unit 302 is connected to the first output terminal of the kth second unit 302, and when i > 1, the first control terminal of the ith second unit 302 is connected to the first output terminal of the i-1 st second unit 302.

The gate of the ninth NMOS transistor N9 serves as the second control terminal INNi of the ith second unit 302, where when i=1, the second control terminal of the 1 st second unit 302 is connected to the second output terminal of the kth second unit 302, and when i > 1, the second control terminal of the ith second unit 302 is connected to the second output terminal of the i-1 st second unit 302.

The source of the eighth NMOS transistor N8 and the source of the ninth NMOS transistor N9 are both connected to the drain of the tenth NMOS transistor N10, the source of the tenth NMOS transistor N10 is connected to ground, and the gate of the tenth NMOS transistor N10 serves as the second input terminal (VBN) of the voltage-controlled oscillator 30.

The first output OUTPK and the second output OUTNK of the kth second unit 302 are connected to the standard differential pair 301, and the output of the standard differential pair 301 is used as the output of the voltage-controlled oscillator 30.

Wherein i is more than or equal to 1 and less than or equal to K, and K is an odd number which is more than or equal to 3.

The operation principle of the above components is partially described as follows:

the Bias controller 20 (Bias Gen) outputs a Bias current (Ibias) corresponding to the first Bias signal and provides Bias voltages VBP and VBN. The output signal frequency of the voltage-controlled oscillator 30 is different, the bias current (Ibias) corresponding to the first bias signal is different, the higher the output signal frequency of the voltage-controlled oscillator 30 is, the larger the bias current (Ibias) corresponding to the first bias signal output by the bias controller 20 is, and when the output signal frequency of the voltage-controlled oscillator 30 is lower, the smaller the bias current (Ibias) corresponding to the first bias signal output by the bias controller 20 is.

The frequency of the output signal of the voltage controlled oscillator 30 is denoted fosc, which is proportional to mu _p*C_ox*(W/L)*(VDD-VBP-|V_TH |)/Cl, which represents the total capacitance to ground for each output pole of the voltage controlled oscillator 30. When the bias Voltage (VBP) corresponding to the first bias signal becomes smaller and fosc becomes larger, the PMOS transistor in the voltage-controlled oscillator 30 works in the saturation region, and the bias current (Ibias) is determined by the IV curve equation:

Ibias＝1/2*[μ_p×C_ox×(W/L)×(VDD-VBP-|V_TH|)²]。

Mu _p is the mobility of P-type carriers, W and L are the width and length of the first PMOS tube P1 respectively, C _ox is the capacitance of the oxide layer, and V _TH is the threshold voltage of the first PMOS tube P1.

Gm is the transconductance of the diode connection of the first PMOS transistor P1, and 1/gm is the resistance of the equivalent pull-up resistor in the first PMOS transistor P1 in the lock detector 10.

It should be noted that, the larger the bias current (Ibias), the smaller the bias voltage VBP, the larger the gm=up×c _ox*W/L*(VDD-VBP-|V_TH |), the smaller the equivalent resistance (for example, the equivalent pull-UP resistance of the first PMOS transistor) in the Lock detector 10 (lock_det), the smaller the corresponding verification width, the higher the Lock detection accuracy, the narrower the width requirement of the phase pulse error signal (UP or DN, also referred to as UPDN) required to be output by the phase frequency detector 70, that is, the smaller the phase difference requirement of the self-biased phase-locked loop system, the smaller the jitter of the self-biased phase-locked loop system, and the longer the Lock time of the self-biased phase-locked loop system. Conversely, the larger the bias current (Ibias), the smaller the bias voltage VBP, and the smaller gm=up×c _ox*W/L*(VDD-VBP-|V_TH |), the larger the equivalent resistance (for example, the equivalent pull-up resistance of the first PMOS transistor) in the Lock detector 10 (lock_det), the larger the corresponding verification width, the larger the filterable width, and the circuit can be locked even in the case of the larger phase pulse error signal width, that is, the Lock detection accuracy is reduced and the Lock duration is shortened at the VCO low frequency. At this time, the frequency is lower, the jitter of time sequence and application requirement can be larger, the application requirement is still satisfied, and the locking frequency time of the circuit can be greatly shortened.

The embodiment of the application also provides electronic equipment which comprises the self-bias phase-locked loop system. The electronic device can be a system on a chip, a mobile phone, a computer, a server, intelligent wearable equipment and the like.

In summary, the embodiment of the present application provides a self-biased phase-locked loop system and an electronic device, where the self-biased phase-locked loop system includes: the device comprises a phase frequency detector, a charge pump, a filter, a bias controller, a voltage controlled oscillator, a frequency divider and a lock detector; the first input end of the phase frequency detector is used for accessing a reference clock signal, the second input end of the phase frequency detector is connected with the output end of the frequency divider, and the output end of the phase frequency detector is respectively connected with the input end of the charge pump and the input end of the lock detector; the output end of the charge pump is connected with the input end of the bias controller, the first output end of the bias controller is connected with the first input end of the voltage-controlled oscillator, the second output end of the bias controller is connected with the second input end of the voltage-controlled oscillator, and the first output end of the bias controller is also connected with the regulating end of the lock detector; the filter is connected between the charge pump and the bias controller; the output end of the voltage-controlled oscillator is connected with the input end of the frequency divider. The self-bias phase-locked loop system pair verification width can be flexibly set according to the bias controller pair output, and has the advantages of shorter locking time, higher flexibility and wide frequency working range.

The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

It will be evident to those skilled in the art that the application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims (10)

1. A self-biasing phase-locked loop system, the self-biasing phase-locked loop system comprising: the device comprises a phase frequency detector, a charge pump, a filter, a bias controller, a voltage controlled oscillator, a frequency divider and a lock detector;

the first input end of the phase frequency detector is used for accessing a reference clock signal, the second input end of the phase frequency detector is connected with the output end of the frequency divider, and the output end of the phase frequency detector is respectively connected with the input end of the charge pump and the input end of the lock detector;

the output end of the charge pump is connected with the input end of the bias controller, the first output end of the bias controller is connected with the first input end of the voltage-controlled oscillator, the second output end of the bias controller is connected with the second input end of the voltage-controlled oscillator, and the first output end of the bias controller is also connected with the regulating end of the lock detector;

The filter is connected between the charge pump and the bias controller;

The output end of the voltage-controlled oscillator is connected with the input end of the frequency divider.

2. A self-biasing phase-locked loop system as defined in claim 1, wherein,

The phase frequency detector is used for generating a corresponding phase pulse error signal according to the reference clock signal and the feedback signal transmitted by the frequency divider, and transmitting the phase pulse error signal to the charge pump and the lock detector;

the charge pump is used for generating a corresponding charge signal according to the phase pulse error signal;

the filter is used for filtering out high-frequency components on a path from the charge pump to the bias controller;

The bias controller is configured to generate a first bias signal and a second bias signal based on the filtered charge signal, transmit the first bias signal and the second bias signal to the voltage controlled oscillator, and transmit the first bias signal to the lock detector;

The voltage-controlled oscillator is used for adjusting the frequency of an output signal according to the first bias signal and the second bias signal;

The frequency divider is used for performing frequency division processing on the output signal of the voltage-controlled oscillator to obtain the feedback signal, and transmitting the feedback signal to the phase frequency detector;

the lock detector is used for adjusting the verification width according to the first bias signal and determining whether the lock is locked according to the phase pulse error signal and the verification width.

3. The self-biasing phase-locked loop system of claim 2, wherein the lock detector comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a first capacitor, and a second capacitor;

the grid electrode of the first PMOS tube is used as an adjusting end of the locking detector and is connected with the first output end of the bias controller;

The source electrode of the first PMOS tube is connected with a power supply, the drain electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube, and the source electrode of the first NMOS tube is connected with the ground;

A wiring terminal is led out of the connection part of the grid electrode of the second PMOS tube and the grid electrode of the first NMOS tube and is used as the input end of the locking detector and is connected with the output end of the phase frequency detector;

a wiring terminal is led out of the connection part of the drain electrode of the second PMOS tube and the drain electrode of the first NMOS tube and is used as the output end of the locking detector;

One end of the first capacitor is connected with a power supply, and the other end of the first capacitor is connected with the output end of the lock detector;

One end of the second capacitor is connected to the ground, and the other end of the second capacitor is connected to the output end of the lock detector.

4. The self-biasing phase-locked loop system of claim 2, wherein the lock detector comprises a first PMOS tube, a second PMOS tube, a first NMOS tube, a third PMOS tube, and a second NMOS tube;

the grid electrode of the first PMOS tube is used as an adjusting end of the locking detector and is connected with the first output end of the bias controller;

The source electrode of the first PMOS tube is connected with a power supply, the drain electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube, and the source electrode of the first NMOS tube is connected with the ground;

A wiring terminal is led out of the connection part of the grid electrode of the second PMOS tube and the grid electrode of the first NMOS tube and is used as the input end of the locking detector and is connected with the output end of the phase frequency detector;

a wiring terminal is led out of the connection part of the drain electrode of the second PMOS tube and the drain electrode of the first NMOS tube and is used as the output end of the locking detector;

the drain electrode and the source electrode of the third PMOS tube are connected to a power supply, and the grid electrode of the third PMOS tube is connected to the output end of the lock detector;

The drain electrode and the source electrode of the second NMOS tube are connected to the ground, and the grid electrode of the second NMOS tube is connected to the output end of the locking detector.

5. The self-biasing phase-locked loop system of claim 2, wherein the bias controller comprises a first op-amp and a third NMOS transistor;

the first end of the first operational amplifier is used as the input end of the bias controller and is connected with the output end of the charge pump;

The second end of the first operational amplifier is connected with the drain electrode of the third NMOS tube, and a connecting terminal is led out from the junction of the second end and the drain electrode of the third NMOS tube and is used as a first output end of the bias controller;

the output end of the first operational amplifier is connected with the grid electrode of the third NMOS tube, and a connecting terminal is led out from the joint of the first operational amplifier and the third operational amplifier and is used as the second output end of the bias controller;

and the source electrode of the third NMOS tube is connected with the ground.

6. The self-biasing phase-locked loop system of claim 5, wherein the charge pump comprises a fourth PMOS transistor, a fifth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor;

The source electrode of the fourth PMOS tube and the source electrode of the fifth PMOS tube are both connected with a power supply, the grid electrode of the fourth PMOS tube is connected with the grid electrode of the fifth PMOS tube, and the grid electrode of the fourth PMOS tube is connected with the drain electrode of the fourth PMOS tube;

The drain electrode of the fourth PMOS tube is connected with the drain electrode of the fourth NMOS tube, the source electrode of the fourth NMOS tube is connected with the drain electrode of the sixth NMOS tube, and the source electrode of the sixth NMOS tube is connected with the ground;

the grid electrode of the fourth NMOS tube is used as a first input end of the charge pump and is connected with a first output end of the phase frequency detector;

The drain electrode of the fifth PMOS tube is connected with the drain electrode of the fifth NMOS tube, and a wiring terminal is led out from the junction of the drain electrode of the fifth PMOS tube and the drain electrode as the output end of the charge pump and is connected with the input end of the bias controller;

the source electrode of the fifth NMOS tube is connected with the drain electrode of the seventh NMOS tube, and the source electrode of the seventh NMOS tube is connected with the ground;

the grid electrode of the fifth NMOS tube is used as a second input end of the charge pump and is connected with a second output end of the phase frequency detector;

and the grid electrode of the sixth NMOS tube and the grid electrode of the seventh NMOS tube are connected to the second output end of the bias controller.

7. The self-biasing phase-locked loop system of claim 6, wherein the filter comprises a third capacitor, a sixth PMOS transistor, and a seventh PMOS transistor;

one end of the third capacitor is connected with a power supply, and the other end of the third capacitor is connected between the charge pump and the bias controller;

The source electrode of the sixth PMOS tube is connected with a power supply, the drain electrode of the sixth PMOS tube is connected with the grid electrode of the seventh PMOS tube, and the grid electrode of the sixth PMOS tube is connected between the charge pump and the bias controller;

The source electrode of the seventh PMOS tube is connected to a power supply, the grid electrode of the seventh PMOS tube is connected to the drain electrode of the seventh PMOS tube, and the drain electrode of the seventh PMOS tube is connected to the first output end of the bias controller.

8. The self-biasing phase-locked loop system of claim 2, wherein the voltage-controlled oscillator comprises a standard differential pair and K second units, an ith of the second units comprising an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor;

The source electrode of the eighth PMOS tube, the source electrode of the ninth PMOS tube, the source electrode of the tenth PMOS tube and the source electrode of the eleventh PMOS tube are all connected with a power supply;

A connecting terminal is led out from the joint of the grid electrode of the eighth PMOS tube and the grid electrode of the eleventh PMOS tube and is used as a first input end of the voltage-controlled oscillator;

The drain electrode of the eighth PMOS tube is connected with the grid electrode of the ninth PMOS tube, the grid electrode of the ninth PMOS tube is connected with the drain electrode of the ninth PMOS tube, the drain electrode of the ninth PMOS tube is connected with the drain electrode of the eighth NMOS tube, and a connecting terminal is led out at the joint of the drain electrode of the eighth PMOS tube and the drain electrode of the eighth NMOS tube and is used as a first output end of the ith second unit;

The drain electrode of the eleventh PMOS tube is connected with the grid electrode of the tenth PMOS tube, the grid electrode of the tenth PMOS tube is connected with the drain electrode of the tenth PMOS tube, the drain electrode of the tenth PMOS tube is connected with the drain electrode of the ninth NMOS tube, and a connecting terminal is led out at the joint of the drain electrode of the tenth PMOS tube and the drain electrode of the ninth NMOS tube and is used as the second output end of the ith second unit;

The grid electrode of the eighth NMOS tube is used as a first control end of an ith second unit, when i=1, the first control end of the 1 st second unit is connected with the first output end of the K th second unit, and when i is more than 1, the first control end of the ith second unit is connected with the first output end of the i-1 th second unit;

The grid electrode of the ninth NMOS tube is used as a second control end of the ith second unit, when i=1, the second control end of the 1 st second unit is connected with the second output end of the K th second unit, and when i is more than 1, the second control end of the ith second unit is connected with the second output end of the i-1 th second unit;

The source electrode of the eighth NMOS tube and the source electrode of the ninth NMOS tube are both connected to the drain electrode of the tenth NMOS tube, the source electrode of the tenth NMOS tube is connected to the ground, and the grid electrode of the tenth NMOS tube is used as the second input end of the voltage-controlled oscillator;

The first output end and the second output end of the Kth second unit are both connected to the standard differential pair, and the output end of the standard differential pair is used as the output end of the voltage-controlled oscillator;

wherein i is more than or equal to 1 and K is more than or equal to K.

9. A self-biasing phase-locked loop system as defined in claim 2, wherein,

The smaller the bias voltage of the first bias signal, the smaller the verification width, when the bias current of the first bias signal is larger;

the larger the bias voltage of the first bias signal, the larger the verification width, as the bias current of the first bias signal is smaller.

10. An electronic device comprising the self-biasing phase-locked loop system of any one of claims 1-9.