CN118300540A - Signal equalizer, adjustable amplifier, buffer and photoelectric receiver - Google Patents
Signal equalizer, adjustable amplifier, buffer and photoelectric receiver Download PDFInfo
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- CN118300540A CN118300540A CN202410725920.3A CN202410725920A CN118300540A CN 118300540 A CN118300540 A CN 118300540A CN 202410725920 A CN202410725920 A CN 202410725920A CN 118300540 A CN118300540 A CN 118300540A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
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Abstract
The application provides a signal equalizer, an adjustable amplifier, a buffer and an optoelectronic receiver, wherein the signal equalizer comprises: the input end of the main path differential amplifying circuit and the input end of the auxiliary path differential amplifying circuit are respectively connected to the differential voltage input end, and one output end of the main path differential amplifying circuit is connected with one output end of the auxiliary path differential amplifying circuit and then connected to the differential voltage output module; the other output end of the main path differential amplifying circuit is connected to the first bias circuit, and the other output end of the auxiliary path differential amplifying circuit is connected to the second bias circuit; the first bias circuit is also connected to a bias voltage source, and the bias voltage source is also connected to the second bias circuit through a high-frequency component emphasis controller.
Description
Technical Field
The present application relates to the field of signal amplification technologies, and in particular, to a signal equalizer, an adjustable amplifier, a buffer, and an optoelectronic receiver.
Background
The adjustable amplifier mainly comprises a main path differential amplifier and a sub path differential amplifier which are connected in parallel in the traditional scheme, wherein the main path differential amplifier realizes the full flux (including high-frequency signals and low-frequency signals) gain of an input voltage signal, the sub path differential amplifier realizes the gain of the low-frequency signals in the input voltage signal, and the two paths differential amplifiers realize the gain control of respective signals by using corresponding adjustable varistors.
However, the disadvantage of using an adjustable varistor to realize signal gain control is that the minimum gain of the differential amplifier of the secondary path is limited, and it is difficult to realize control of the relative gain between the primary path and the secondary path, thereby affecting the emphasis of the high-frequency component or the amplitude of the gain, so that the amplifier loses the emphasis effect of the high-frequency component when the gain is smaller, and the spectrum equalization effect is poor.
Disclosure of Invention
In view of the above, the present application is directed to at least one signal equalizer, an adjustable amplifier, a buffer and an optoelectronic receiver, which are capable of increasing the amplitude of the emphasis or gain of the high frequency component and improving the subsequent spectrum equalizing effect on the signal by introducing a bias circuit with controllable bias current into the low frequency differential amplifier path.
The application mainly comprises the following aspects:
In a first aspect, an embodiment of the present application provides a signal equalizer, where the signal equalizer includes a main path differential amplifying circuit and a first bias circuit corresponding to the main path differential amplifying circuit, a sub path differential amplifying circuit and a second bias circuit corresponding to the sub path differential amplifying circuit, a high frequency component emphasis controller, and a differential voltage output module, where an input end of the main path differential amplifying circuit and an input end of the sub path differential amplifying circuit are connected to differential voltage input ends respectively, and an output end of the main path differential amplifying circuit and an output end of the sub path differential amplifying circuit are connected to the differential voltage output module; the other output end of the main path differential amplifying circuit is connected to the first bias circuit, and the other output end of the auxiliary path differential amplifying circuit is connected to the second bias circuit; the first bias circuit is also connected to a bias voltage source, which is also connected to the second bias circuit through a high frequency component emphasis controller.
In one possible implementation, the differential voltage input terminal includes a differential positive voltage input terminal and a differential negative voltage input terminal, and the main path differential amplifying circuit includes a first triode, a second triode, a first resistor and a second resistor, wherein a base of the first triode is connected to the differential positive voltage input terminal and the sub-path differential amplifying circuit, and a base of the second triode is connected to the differential negative voltage input terminal and the sub-path differential amplifying circuit, respectively; the collector of the first triode and the collector of the second triode are connected with the auxiliary channel differential amplifying circuit and then connected with the differential voltage output module; the emission set of the first triode is connected to one end of a first resistor, the other end of the first resistor is connected to one end of a second resistor and the first bias circuit respectively, and the other end of the second resistor is connected to the emitter of the second triode.
In one possible implementation manner, the differential voltage output module comprises a first output resistor, a second output resistor, a differential positive voltage output end and a differential negative voltage output end, the secondary path differential amplifying circuit comprises a first low-pass filter circuit, a second low-pass filter circuit, a third triode, a fourth triode, a third resistor and a fourth resistor, wherein the input end of the first low-pass filter circuit is respectively connected with the differential negative voltage input end and the base electrode of the second triode, the output end of the first low-pass filter circuit is connected with the base electrode of the third triode, the input end of the second low-pass filter circuit is respectively connected with the differential positive voltage input end and the base electrode of the first triode, and the output end of the first low-pass filter circuit is connected with the base electrode of the fourth triode; the collector of the third triode is respectively connected to the collector of the first triode, the differential negative voltage output end and one end of the first output resistor, the collector of the fourth triode is respectively connected to the collector of the second triode, the differential positive voltage output end and one end of the second output resistor, and the other end of the first output resistor and the other end of the second output resistor are respectively connected to a power supply; the emitter of the third triode is connected to one end of the third resistor, the other end of the third resistor is connected to one end of the fourth resistor and the second bias circuit respectively, and the other end of the fourth resistor is connected to the emitter of the fourth triode.
In one possible implementation manner, the first low-pass filter circuit comprises a fifth resistor and a first adjustable capacitor, the second low-pass filter circuit comprises a sixth resistor and a second adjustable capacitor, one end of the fifth resistor is respectively connected to the base electrode of the second triode and the differential negative voltage input end, the other end of the fifth resistor is respectively connected to one end of the first adjustable capacitor and the base electrode of the third triode, and the other end of the first adjustable capacitor is grounded; one end of the sixth resistor is connected to the base electrode of the first triode and the differential positive voltage input end respectively, the other end of the sixth resistor is connected to one end of the second adjustable capacitor and the base electrode of the fourth triode respectively, and the other end of the second adjustable capacitor is grounded.
In one possible implementation manner, the first bias circuit includes a first operational amplifier, a fifth triode and a seventh resistor, wherein a positive input end of the first operational amplifier is connected to a bias voltage source, a negative input end of the first operational amplifier is respectively connected to one end of the seventh resistor and an emitter of the fifth triode, the other end of the seventh resistor is grounded, an output end of the first operational amplifier is connected to a base of the fifth triode, and a collector of the fifth triode is respectively connected to the other end of the first resistor and one end of the second resistor, wherein bias current provided by the bias voltage source is proportional to absolute temperature.
In one possible implementation manner, the second bias circuit includes a second operational amplifier, a sixth triode and an eighth resistor, wherein the bias voltage source is connected to the positive input end of the second operational amplifier through the high-frequency component weighting controller, the negative input end of the second operational amplifier is respectively connected to one end of the eighth resistor and the emitter of the sixth triode, the other end of the eighth resistor is grounded, the output end of the second operational amplifier is connected to the base of the sixth triode, and the collector of the sixth triode is respectively connected to the other end of the third resistor and one end of the fourth resistor.
In a second aspect, an embodiment of the present application further provides an adjustable amplifier, where the adjustable amplifier includes a gain control circuit and a signal equalizer provided in any one of the embodiments above, where an input end of the gain control circuit is connected to an upper computer to obtain an amplified gain signal sent by the upper computer, and another input end of the gain control circuit is connected to an output end of the main path differential amplifying circuit and an output end of the sub path differential amplifying circuit, respectively; the output end of the gain control circuit is connected to the differential voltage output module.
In one possible implementation manner, the gain control circuit comprises a first current rudder, a second current rudder, a seventh triode, an eighth triode, a third operational amplifier and a current source, wherein the input end of the current source is connected to the upper computer, the first output end of the current source is connected to the positive input end of the third operational amplifier, the second output end of the current source is connected to the negative input end of the third operational amplifier, the positive output end of the third operational amplifier is respectively connected to the base electrode of the seventh triode, the first input end of the first current rudder and the first input end of the second current rudder, and the negative output end of the third operational amplifier is respectively connected to the base electrode of the eighth triode, the second input end of the first current rudder and the second input end of the second current rudder; the collector of the seventh triode and the collector of the eighth triode are respectively connected to a power supply, the emitter of the seventh triode is connected to the negative input end of the third operational amplifier, and the emitter of the eighth triode is connected to the positive input end of the third operational amplifier; the first output end of the first current rudder is respectively connected to the collector electrode of the first triode in the main path differential amplifying circuit and the collector electrode of the third triode in the auxiliary path differential amplifying circuit, and the second output end of the first current rudder is connected to one end of the first output resistor in the differential voltage output module and the differential negative voltage output end; the first output end of the second current rudder is respectively connected to the collector electrode of the fourth triode in the auxiliary path differential amplifying circuit and the collector electrode of the second triode in the main path differential amplifying circuit, and the second output end of the second current rudder is connected to one end of the second output resistor in the differential voltage output module and the differential positive voltage output end.
In one possible implementation manner, the first current rudder comprises a ninth triode and a thirteenth triode, the second current rudder comprises an eleventh triode and a twelfth triode, wherein a base electrode of the ninth triode is connected with a base electrode of the twelfth triode and then connected with a negative output end of the third operational amplifier, and a base electrode of the thirteenth triode is connected with a base electrode of the eleventh triode and then connected with a positive output end of the third operational amplifier; the collector of the ninth triode is connected to the differential negative voltage output end and one end of the first output resistor, the collector of the thirteenth triode and the collector of the eleventh triode are respectively connected to a power supply, and the collector of the twelfth triode is connected to the differential positive voltage output end and one end of the second output resistor; the emitter of the ninth triode is connected with the emitter of the thirteenth triode and then connected with the collector of the first triode and the collector of the third triode, and the emitter of the eleventh triode is connected with the emitter of the twelfth triode and then connected with the collector of the second triode and the collector of the fourth triode.
In a third aspect, an embodiment of the present application further provides a buffer, where the buffer includes a third current rudder and the signal equalizer provided in any one of the foregoing embodiments, where a first input end of the third current rudder is connected to the host computer, and a second input end of the third current rudder is connected to the main path differential amplifying circuit and the auxiliary path differential amplifying circuit respectively; the output end of the third current rudder is connected to the differential voltage output module.
In one possible implementation manner, the third current rudder includes a thirteenth triode and a fourteenth triode, wherein after the base electrode of the thirteenth triode is connected to the base electrode of the fourteenth triode, the base electrode of the thirteenth triode is connected to the differential negative voltage output end in the differential voltage output module and one end of the first output resistor, the emitter electrode of the thirteenth triode is respectively connected to the collector electrode of the first triode in the main path differential amplification circuit and the collector electrode of the third triode in the auxiliary path differential amplification circuit, the collector electrode of the fourteenth triode is connected to the differential positive voltage output end in the differential voltage output module and one end of the second output resistor, and the emitter electrode of the fourteenth triode is respectively connected to the collector electrode of the second triode in the main path differential amplification circuit and the collector electrode of the fourth triode in the auxiliary path differential amplification circuit.
In a fourth aspect, an embodiment of the present application further provides an optoelectronic receiver, including: the photodiode is used for converting the received optical signal into a current signal and transmitting the current signal to the transimpedance amplifier; the transimpedance amplifier is used for converting the current signal into a differential voltage signal and transmitting the differential voltage signal to the adjustable amplifier; the adjustable amplifier is used for amplifying the differential voltage signal and then transmitting the differential voltage signal to the buffer; and the buffer is used for outputting the target voltage signal after carrying out signal attenuation processing on the amplified differential voltage signal, wherein the adjustable amplifier and/or the buffer comprises the signal equalizer provided by any embodiment.
The embodiment of the application provides a signal equalizer, an adjustable amplifier, a buffer and an optoelectronic receiver, which comprises the following components: the input end of the main path differential amplifying circuit and the input end of the auxiliary path differential amplifying circuit are respectively connected to the differential voltage input end, and one output end of the main path differential amplifying circuit is connected with one output end of the auxiliary path differential amplifying circuit and then connected to the differential voltage output module; the other output end of the main path differential amplifying circuit is connected to the first bias circuit, and the other output end of the auxiliary path differential amplifying circuit is connected to the second bias circuit; the first bias circuit is also connected to a bias voltage source, and the bias voltage source is also connected to the second bias circuit through a high-frequency component emphasis controller.
The application has the advantages that:
(1) The adjustable amplifier provided by the application realizes complete decoupling between the high-low frequency relative gain control required by equalization and the integral absolute gain control of the adjustable amplifier through the gain control circuit and the bias circuit, namely, the absolute gain and the high-frequency emphasis of the adjustable amplifier are completely independently controlled without mutual dependence and influence, thus being more convenient for users to respectively control according to actual demands and reducing the control difficulty.
(2) The relative relation between the main channel bias current and the auxiliary channel bias current which influence the high-low frequency relative gain in the adjustable amplifier relates to the realization of control adjustment by a high-frequency component emphasis controller, and the gain of the auxiliary channel differential amplifying circuit can be ensured to be changed along with the relative change of the main channel differential amplifying circuit while realizing the emphasis adjustment of high-frequency signals.
(3) The gain control circuit can adjust the current distribution proportion between the triodes in the current rudder of the adjustable amplifier according to the proportion relation of the two adjustable current sources, so as to adjust the absolute gain of the adjustable amplifier, specifically, if a voltage control signal which is in direct proportion to the absolute gain is directly applied to the base electrode of the triodes in the current rudder, the absolute gain is nonlinear due to the exponential characteristic of the collector current of the triodes to the base electrode voltage, the nonlinear relation is unfavorable for the subsequent control of the absolute gain, and the gain control circuit introduced in the application has the advantages that the linear control of the absolute gain can be realized, in addition, the differential operational amplifier in the gain control circuit has extremely low output impedance, can provide enough bias current for the base electrode of the triodes in the current rudder, and the ultra-large direct current gain of the differential operational amplifier can ensure that the absolute gain control has good linearity.
(4) The transconductance of the main path differential amplifying circuit and the auxiliary path differential amplifying circuit is kept constant because the corresponding bias current is in direct proportion to the absolute temperature, so that the gain of the adjustable amplifier is ensured not to change along with the temperature.
In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an existing adjustable amplifier according to an embodiment of the present application;
fig. 2 shows one of the structural diagrams of a signal equalizer according to an embodiment of the present application;
fig. 3 shows a second schematic diagram of a signal equalizer according to an embodiment of the present application;
FIG. 4 shows one of the schematic structural diagrams of an adjustable amplifier according to an embodiment of the present application;
FIG. 5 shows a second schematic diagram of an adjustable amplifier according to an embodiment of the application;
FIG. 6 shows a third schematic diagram of an adjustable amplifier according to an embodiment of the application;
FIG. 7 is a schematic diagram of a buffer according to an embodiment of the present application;
FIG. 8 is a diagram showing a second embodiment of a buffer structure
Fig. 9 shows a schematic structural diagram of an optoelectronic receiver according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application, and it should be understood that the drawings in the present application are for the purpose of illustration and description only and are not intended to limit the scope of the present application. In addition, it should be understood that the schematic drawings are not drawn to scale. A flowchart, as used in this disclosure, illustrates operations implemented according to some embodiments of the present application. It should be appreciated that the operations of the flow diagrams may be implemented out of order and that steps without logical context may be performed in reverse order or concurrently. Moreover, one or more other operations may be added to or removed from the flow diagrams by those skilled in the art under the direction of the present disclosure.
In addition, the described embodiments are only some, but not all, embodiments of the application. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by a person skilled in the art based on embodiments of the application without making any inventive effort, fall within the scope of the application.
Referring to fig. 1, fig. 1 is a schematic diagram of a conventional adjustable amplifier according to an embodiment of the application. As shown in fig. 1, the adjustable amplifier provided in the conventional manner includes a main path differential amplifier formed by triodes Q1 and Q2 and resistors R1", R2", and R3", and a sub path differential amplifier formed by triodes Q3 and Q4 and resistors R4", R5", and R6", VIP "is a differential input positive voltage, VIN" is a differential input negative voltage, an output current of the main path differential amplifier is added to a load resistor R9 "to form a negative output voltage VON", an output current of the sub path differential amplifier is added to a load resistor R10 "to form a positive output voltage VOP", gains of the main path differential amplifier and the sub path differential amplifier are controlled by resistors R3 "and R6", a low-pass filter circuit corresponding to each other is formed between the resistor R7 "and the adjustable capacitor C1", the main path differential amplifier can realize the adjustment of zero point of the input voltage signal (including high-frequency and low-frequency differential amplifier) and the low-frequency differential amplifier, that is the gain of the low-frequency differential amplifier in the low-frequency differential amplifier is actually amplified, and the gain of the low-frequency differential amplifier is partially amplified, and the gain amplifier is actually amplified, and the gain of the low-frequency differential amplifier is compared with the low-frequency differential amplifier.
As shown in fig. 1, the conventional scheme has a disadvantage in that the minimum gain of the sub-path differential amplifier needs to be realized when the resistor R6 "is turned off, and at this time, the gain of the sub-path differential amplifier is determined by R4", Q3 and R9", since R4" is a fixed resistor in the conventional scheme, the gain of the sub-path amplifier cannot be adjusted to 0, and thus, since the minimum gain of the sub-path differential amplifier is limited, it is difficult to realize control of the relative gain between the main and sub-paths, thereby affecting the amplitude of the emphasis of the high frequency component, causing the amplifier to lose the effect of the emphasis of the high frequency component when the gain is small, and resulting in deterioration of the spectrum equalizing effect.
Even if R4 "is replaced with a variable resistor and R4" is allowed to be adjusted to open, it is extremely difficult to achieve a variable main path gain while keeping the sub-path gain track of the main path differential gain to maintain a constant relative gain and also to ensure that the relative gain is user adjustable, which is not a function required by the user in the prior art solutions disclosed.
Based on this, the embodiment of the application provides an adjustable amplifier and an optoelectronic receiver, which increase the amplitude of the emphasis or gain of a high-frequency component and improve the subsequent spectrum equalization effect on signals by introducing a bias circuit with controllable bias current into a low-frequency differential amplifier channel, and specifically comprises the following steps:
referring to fig. 2, fig. 2 shows a schematic diagram of a signal equalizer according to an embodiment of the application. As shown in fig. 2, the signal equalizer provided by the embodiment of the application includes a main path differential amplifying circuit 1 and a corresponding first bias circuit 2, a sub path differential amplifying circuit 3 and a corresponding second bias circuit 4, a high frequency component emphasis controller 5 and a differential voltage output module 6.
In a preferred embodiment, the input terminal of the main path differential amplifying circuit 1 and the input terminal of the sub path differential amplifying circuit 3 are respectively connected to the differential voltage input terminal VI, and after one output terminal of the main path differential amplifying circuit 1 and one output terminal of the sub path differential amplifying circuit 3 are connected, the differential voltage output module 6 is connected, the other output terminal of the main path differential amplifying circuit 1 is connected to the first bias circuit 2, the other output terminal of the sub path differential amplifying circuit 3 is connected to the second bias circuit 4, the first bias circuit 2 is further connected to the bias voltage source Vref, and the bias voltage source Vref is further connected to the second bias circuit 4 through the high frequency component weighting controller 5.
In particular embodiments, a bias voltage source Vref is applied to the first bias circuit 2 to provide a main path bias current to the main path differential amplifying circuit 1 via the first bias circuit 2A bias voltage source Vref is applied to the second bias circuit 4 through a high frequency component emphasis controller 5 to provide a sub-path bias current to the sub-path differential amplifying circuit 3 through the second bias circuit 4Wherein the high-frequency component emphasis controller 5 is controlled by an upper computer to realize gain of the bias voltage source Vref input into the second bias circuit 4For example, if the upper computer is set up=0, The bias voltage source Vref received by the second bias circuit 4 is 0, i.e. atWhen=0, the sub-path differential amplifying circuit 3 loses the gain effect on the low-frequency voltage signal in the input differential voltage, that is, after the low-frequency voltage signal loses the gain effect, the frequency response of the whole signal equalizer is equal to the frequency response of the main path, that is, there is no high-frequency emphasis, and the larger the gain of the low-frequency signal, the more the low-frequency signal subtracted from the main path signal, the more the high-frequency part is emphasized.
Referring to fig. 3, fig. 3 shows a second schematic diagram of a signal equalizer according to an embodiment of the application. As shown in fig. 3, the differential voltage input terminal includes a differential positive voltage input terminal VIP and a differential negative voltage input terminal VIN, the main path differential amplifying circuit 1 includes a first transistor T1, a second transistor T2, a first resistor R1 and a second resistor R2, the sub path differential amplifying circuit 3 includes a first low pass filter circuit 31, a second low pass filter circuit 32, a third transistor T3, a fourth transistor T4, a third resistor R3 and a fourth resistor R4, and the differential voltage output module 6 includes a first output resistor 61, a second output resistor 62, a differential positive voltage output terminal VOP and a differential negative voltage output terminal VON.
Preferably, as shown in fig. 3, the base of the first triode T1 is connected to the differential positive voltage input terminal VIP and the input terminal of the second low-pass filter circuit 32, the base of the second triode T2 is connected to the differential negative voltage input terminal VIN and the input terminal of the first low-pass filter circuit 31, respectively, after the collector of the first triode T1 and the collector of the third triode T3 are connected, one end of the first output resistor 61 and the differential negative voltage output terminal VON are connected, the emitter of the first triode T1 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to one end of the second resistor R2 and the first bias circuit 2, respectively, the other end of the second resistor R2 is connected to the emitter of the second triode T2, and the other end of the first output resistor 61 and the other end of the second output resistor 62 are connected to the power supply VCC, respectively.
After the collector of the second triode T2 is connected with the collector of the fourth triode T4, one end of the second output resistor 62 and the differential positive voltage output terminal VOP are connected, the output terminal of the first low-pass filter circuit 31 is connected to the base of the third triode T3, and the output terminal of the second low-pass filter circuit 32 is connected to the base of the fourth triode T4.
The emitter of the third triode T3 is connected to one end of a third resistor R3, the other end of the third resistor R3 is connected to one end of a fourth resistor R4 and the second bias circuit 4 respectively, and the other end of the fourth resistor R4 is connected to the emitter of the fourth triode T4.
As shown in fig. 3, the first low-pass filter circuit 31 includes a fifth resistor R5 and a first adjustable capacitor C1, the second low-pass filter circuit 32 includes a sixth resistor R6 and a second adjustable capacitor C2, wherein one end of the fifth resistor R5 is used as an input end of the first low-pass filter circuit 31 and is respectively connected to the base of the second triode T2 and the differential negative voltage input end VIN, the other end of the fifth resistor R5 is respectively connected to one end of the first adjustable capacitor C1 and the base of the third triode T3, the other end of the first adjustable capacitor C1 is grounded, one end of the sixth resistor R6 is used as an input end of the second low-pass filter circuit 32 and is respectively connected to the base of the first triode T1 and the differential positive voltage input end VIP, the other end of the sixth resistor R6 is respectively connected to one end of the second adjustable capacitor C1 and the base of the fourth triode T4, and the other end of the second adjustable capacitor C2 is grounded.
In a preferred embodiment, as shown in fig. 3, the first bias circuit 2 includes a first operational amplifier OpAmp1, a fifth transistor T5, and a seventh resistor R7, and the second bias circuit 4 includes a second operational amplifier OpAmp2, a sixth transistor T6, and an eighth resistor R8, and specifically, the first operational amplifier OpAmp1 and the second operational amplifier OpAmp2 are single-ended output operational amplifiers.
The positive input end of the first operational amplifier OpAmp1 is connected to the bias voltage source Vref, the negative input end of the first operational amplifier OpAmp1 is respectively connected to one end of the seventh resistor R7 and the emitter of the fifth triode T5, the other end of the seventh resistor R7 is grounded, the output end of the first operational amplifier OpAmp1 is connected to the base of the fifth triode T5, and the collector of the fifth triode T5 is respectively connected to the other end of the first resistor R1 and one end of the second resistor R2.
The bias voltage source Vref is connected to the positive input terminal of the second operational amplifier OpAmp2 through the high frequency component emphasis controller 5, the negative input terminal of the second operational amplifier OpAmp2 is connected to one end of the eighth resistor R8 and the emitter of the sixth transistor T6, respectively, the other end of the eighth resistor R8 is grounded, the output terminal of the second operational amplifier OpAmp2 is connected to the base of the sixth transistor T6, and the collector of the sixth transistor T6 is connected to the other end of the third resistor R3 and one end of the fourth resistor R4, respectively.
In a specific embodiment of the present application, in the signal equalizer as shown in fig. 3 provided by the present application, a first operational amplifier OpAmp1, a seventh resistor R7 and a fifth triode T5 form a first bias circuit, and the bias voltage source Vref provides a main path bias current for the main path differential amplifying circuit through the first bias circuitMain path bias current。
The second operational amplifier OpAmp2, the eighth resistor R8 and the sixth triode T6 form a second bias circuit 4, and the high-frequency component emphasis controller 5 is introduced to regulate the input voltage signal at the positive input end of the second operational amplifier OpAmp2, and the application can write the corresponding emphasis gain into the high-frequency component emphasis controller 5 through the upper computer in advance according to the actual emphasis requirement of the high-frequency signal in the input differential voltage signal by a userThe high frequency component emphasis controller 5 determines the emphasis gainAfter that, the control and adjustment of the voltage signal output by the bias voltage source Vref to the positive input end of the second operational amplifier OpAmp2 can be realized, in the application, the emphasis degree and emphasis gain of the high-frequency signalIn direct proportion, specifically, the bias voltage source Vref provides a secondary path bias current for the secondary path differential amplifying circuit through the high-frequency component emphasis controller 5 and the second bias circuitSecondary path bias current。
In the main path differential amplifying circuit, a first triode T1, a first resistor R1 and a first biasing circuit 2 are used for realizing gain amplification processing of a full flux signal in a differential positive voltage signal input into the adjustable amplifier, and a second triode T2, a second resistor R2 and the first biasing circuit 2 are used for realizing gain amplification processing of a full flux signal in a differential negative voltage signal input into the adjustable amplifier.
In the differential amplifying circuit of the secondary path, after the differential positive voltage signal passes through the first low-pass filter 31, part of low-frequency signals in the differential positive voltage signal are screened out, namely the emphasis frequency of the high-frequency components in the input differential voltage in the whole adjustable amplifier is determined by the low-pass filter, wherein feq represents the emphasis frequency of the high-frequency components in the input differential voltage signal, namely the first low-pass filter passes signals lower than feq and blocks signals higher than feq, the signals higher than feq are high-frequency components for emphasis processing, the specific value of feq is determined by a variable capacitor, the variable capacitor is further connected to an upper computer (not shown in the figure), and the variable capacitor is particularly determined by a register in an I2C interface of the upper computer, in the application, the third triode T3 and the second bias circuit 4 together realize gain amplification processing of the low-frequency signals lower than feq in the differential positive voltage signal, and the differential negative voltage signal passes through the second low-pass filter, the fourth triode T4 and the second bias circuit 4 realize gain amplification of the low-frequency signals lower than feq in the differential positive voltage signal.
Referring to fig. 3, at the common collector of the first transistor T1 and the third transistor T3, the current signal output at the collector of the first transistor T1 and the current signal output at the collector of the third transistor T3 are added to complete the emphasis processing of the high frequency component in the differential negative voltage, and similarly, the emphasis processing of the high frequency component in the differential positive voltage is completed at the common collector of the second transistor T2 and the fourth transistor T4, and the emphasis processing is similar to that described above, and details of the emphasis amplitude of the high frequency component are related to the main path bias current and the sub path bias current, and the emphasis processing can be performed by the gain coefficientTo control.
In another preferred embodiment, referring to fig. 4, fig. 4 shows one of the structural diagrams of an adjustable amplifier according to an embodiment of the present application. As shown in fig. 4, the adjustable amplifier includes a gain control circuit 7 and a signal equalizer, wherein one input end of the gain control circuit 7 is connected to a host computer (not shown in the figure) to obtain an amplified gain signal sent by the host computer, the other input end of the gain control circuit 7 is connected to an output end of the main path differential amplifying circuit 1 and an output end of the sub path differential amplifying circuit 3, respectively, and an output end of the gain control circuit 7 is connected to the differential voltage output module 6.
The gain control circuit 7 is configured to amplify the input differential voltage by the entire adjustable amplifier according to the amplified gain signal received from the host computer.
In practice it is controlled that the emphasis amplitude of the high frequency component in the input differential voltage signal relative to the low frequency component in the overall differential voltage output signal, i.e. the relative gain of the high frequency component relative to the low frequency component, is such thatWhen the low-frequency gain corresponding to the differential amplifying circuit of the secondary path is reduced to 0, the emphasis amplitude of the high-frequency component relative to the low-frequency component in the differential voltage output signal corresponding to the adjustable gain amplifier is reduced to 0, and the differential voltage output signal can be regarded as having no equalization effect, namely if the emphasis of the high-frequency signal in the differential input voltage is required to be realized in the application, the differential voltage output signal is directly changedThe value of (2) can be realized, so that the operation flow can be simplified, and the efficiency is improved.
In another preferred embodiment, referring to fig. 5, fig. 5 shows a second schematic diagram of an adjustable amplifier according to an embodiment of the application. As shown in fig. 5, the gain control circuit 7 includes a first current rudder 71, a second current rudder 72, a seventh transistor T7, an eighth transistor T8, a third operational amplifier OpAmp3, and a current source 73.
The input end of the current source 73 is connected to an upper computer (not shown in the figure), the first output end of the current source 73 is connected to the positive input end of the third operational amplifier OpAmp3, the second output end of the current source 73 is connected to the negative input end of the third operational amplifier OpAmp3, the positive output end of the third operational amplifier OpAmp3 is connected to the base of the seventh triode T7, the first input end of the first current rudder 71 and the first input end of the second current rudder 72 are connected, the negative output end of the third operational amplifier OpAmp3 is connected to the base of the eighth triode T8, the second input end of the first current rudder 71 and the second input end of the second current rudder 72, and the second input end of the first current rudder 71 is connected.
The collector of the seventh triode T7 and the collector of the eighth triode T8 are respectively connected to a power supply VCC, the emitter of the seventh triode T7 is connected to the negative input terminal of the third operational amplifier OpAmp3, and the emitter of the eighth triode T8 is connected to the positive input terminal of the third operational amplifier OpAmp 3.
The first output end of the first current rudder 71 is connected to the collector of the first triode T1 and the collector of the third triode T3, respectively, the second output end of the first current rudder 71 is connected to one end of the first output resistor 61 and the differential negative voltage output end VON, the first output end of the second current rudder 72 is connected to the collector of the fourth triode T4 and the collector of the second triode T2, respectively, the second output end of the second current rudder 72 is connected to one end of the second output resistor 62 and the differential positive voltage output end VOP, and the other end of the first output resistor 61 and the other end of the second output resistor 62 are connected to the power supply VCC, respectively.
In a preferred embodiment, referring to fig. 6, fig. 6 shows a third schematic diagram of an adjustable amplifier according to an embodiment of the application. As shown in fig. 6, the first current rudder 71 includes a ninth transistor T9 and a tenth transistor T10, and the second current rudder 72 includes an eleventh transistor T11 and a twelfth transistor T12.
The base of the ninth triode T9 is connected with the base of the twelfth triode T12 and then connected with the negative output end of the third operational amplifier OpAmp3, the base of the thirteenth triode T10 is connected with the base of the eleventh triode T11 and then connected with the positive output end of the third operational amplifier OpAmp3, the collector of the ninth triode T9 is connected with the differential negative voltage output end VON and one end of the first output resistor 61, the collector of the thirteenth triode T10 and the collector of the eleventh triode T11 are respectively connected with the power supply VCC, the collector of the twelfth triode T12 is connected with the differential positive voltage output end VOP and one end of the second output resistor 62, the emitter of the ninth triode T9 is connected with the emitter of the thirteenth triode T10 and then connected with the collector of the first triode T1 and the collector of the third triode T3, the emitter of the eleventh triode T11 is connected with the emitter of the twelfth triode T12 and then connected with the collector of the second triode T2 and one end of the fourth triode T4, and the emitter of the third triode T3 is a dual-output operational amplifier input.
In the adjustable amplifier provided by the application, the gain control circuit 7 adjusts the absolute gain of the whole differential input voltage, preferably, the first current rudder realizes the absolute gain of the whole differential positive input voltage, the second current rudder realizes the absolute gain of the differential negative input voltage, the first current rudder formed by the ninth triode T9 and the tenth triode T10 leads the current signal output by the common collector of the first triode T1 and the third triode T3 to the first output resistor 61 or the power supply VCC, the current proportion between the ninth triode T9 and the thirteenth triode T10 determines the amplification degree of the input current signal input by the emitter of the ninth triode T9 and the thirteenth triode T10, and when the first current rudder leads the received input current signal to the first output resistor 61, the gain of the adjustable amplifier for the input differential voltage signal reaches the maximum value, namely the differential negative output voltage reaches the maximum value.
And a second current rudder formed by an eleventh triode T11 and a tenth diode T12, wherein the current signal output by the second triode T2 and the current signal output by the fourth triode T4 are led to a second output resistor 62 or a power supply VCC, and when the second current rudder leads all received input current signals to the second output resistor 62, the gain of the adjustable amplifier to the input differential voltage signal reaches the maximum value, and the differential positive output voltage reaches the maximum value.
Specifically, in the gain control circuit 7, the current source 73 includes a first current source 730 and a second current source 732, where the current output by the first current source 730 isThe second current source 732 outputs a current ofIn the present application, the sum of the currents corresponding to the first current source 730 and the second current source 732 isCurrent source 73 is connected to the host computer, KGAIN represents the total amplification gain of the entire adjustable amplifier to the input differential voltage signal,Occupying the area ofAfter the upper computer determines KGAIN according to the actual requirement of the user, the current source 73 reads KGAIN from the upper computer, and automatically adjusts the output current of the first current source 730 according to KGAINAnd a second current source 732 outputs a currentFurther, the method comprises, further,Proportional to KGAIN, controlled according to the target KGAINAs a specific example: assuming that target KGAIN =2, then setSet I set =1Let KGAIN =1.
Then, a third operational amplifier OpAmp3 is at the inputAndUnder the action, the output voltage of the positive output end controls the current ratio between the eleventh triode T11 and the twelfth triode T12, the output voltage of the negative output end of the third operational amplifier OpAmp3 controls the current ratio between the ninth triode T9 and the thirteenth triode T10, and the current ratio between the ninth triode T9 and the thirteenth triode T10 or the current ratio between the eleventh triode T11 and the twelfth triode T12 can be considered to be equal to。
In a preferred embodiment of the present application, the bias voltage source Vref can be designed to be proportional to absolute temperature, so that the transconductance of the first transistor T1 and the second transistor T2, and the third transistor T3 and the fourth transistor T4 is kept constant with respect to temperature, and the gain of the adjustable amplifier is kept constant with respect to temperature.
Referring to fig. 7, fig. 7 shows one of the schematic structural diagrams of a buffer according to an embodiment of the application. As shown in fig. 7, the buffer includes a signal equalizer R and a third current rudder 8, wherein a first input terminal of the third current rudder 8 is connected to a host computer (not shown in the figure), a second input terminal of the third current rudder 8 is connected to a main path differential amplifying circuit 1 and a sub path differential amplifying circuit 3 in the signal equalizer, respectively, and an output terminal of the third current rudder 8 is connected to a differential voltage output module 6.
In another preferred embodiment, please refer to fig. 8, fig. 8 shows a second schematic diagram of a buffer according to an embodiment of the present application. As shown in fig. 8, the third current rudder 8 includes a thirteenth triode T13 and a fourteenth triode T14, where after the base of the thirteenth triode T13 is connected to the base of the fourteenth triode T14, the thirteenth triode is connected to the upper computer to receive the VCAS signal provided by the upper computer, the collector of the thirteenth triode T13 is connected to the differential negative voltage output terminal VON and one end of the first output resistor 61, the emitter of the thirteenth triode T13 is connected to the collector of the first triode T1 in the main path differential amplifying circuit and the collector of the third triode T3 in the sub path differential amplifying circuit, the collector of the fourteenth triode T14 is connected to the differential positive voltage output terminal VOP in the differential voltage output module and one end of the second output resistor, and the emitter of the fourteenth triode T14 is connected to the collector of the second triode T2 in the main path differential amplifying circuit and the collector of the fourth triode T4 in the sub path differential amplifying circuit, respectively.
Referring to fig. 9, fig. 9 is a schematic structural diagram of an optical receiver according to an embodiment of the present application. As shown in fig. 9, the photo receiver includes a photodiode PD, a transimpedance amplifier A1, an adjustable amplifier A2 provided in the above-described embodiment, and a buffer A3 connected in this order.
In the present application, the differential voltage input terminal of the signal equalizer section in the adjustable amplifier A2 is connected to the output terminal of the transimpedance amplifier A1, the differential voltage output terminal (including the differential positive voltage output terminal and the differential negative voltage output terminal) of the signal equalizer section in the adjustable amplifier A2 is connected to the differential voltage input terminal of the signal equalizer section in the buffer A3, and the differential voltage signal finally output by the differential voltage output terminal of the signal equalizer section in the buffer A3 is taken as the target voltage signal output by the whole photoelectric receiver.
Preferably, the photodiode PD converts the received optical signal into a current signal and then transmits the current signal to the transimpedance amplifier A1, the transimpedance amplifier A1 converts the current signal into a differential voltage signal and then transmits the differential voltage signal to the adjustable amplifier A2, the adjustable amplifier A2 amplifies the differential voltage signal and then transmits the differential voltage signal to the buffer A3, and the buffer A3 outputs the target voltage signal after performing signal attenuation processing on the amplified differential voltage signal.
In the present application, a set of signal processing structures is formed by the adjustable amplifier A2 and the buffer A3 connected in series, and for the whole photoelectric receiver, a plurality of sets of signal processing structures connected in parallel may be included, and the plurality of signal processing structures are used for processing differential signals of different frequencies output by the transimpedance amplifier A1.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described system and apparatus may refer to corresponding procedures in the foregoing method embodiments, which are not described herein again. In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a non-volatile computer readable storage medium executable by a processor. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily appreciate variations or alternatives within the scope of the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.
Claims (12)
1. A signal equalizer is characterized in that the signal equalizer comprises a main path differential amplifying circuit and a first bias circuit corresponding to the main path differential amplifying circuit, a sub path differential amplifying circuit and a second bias circuit corresponding to the sub path differential amplifying circuit, a high-frequency component emphasis controller and a differential voltage output module,
The input end of the main path differential amplifying circuit and the input end of the auxiliary path differential amplifying circuit are respectively connected to the differential voltage input end, and one output end of the main path differential amplifying circuit is connected with one output end of the auxiliary path differential amplifying circuit and then connected to the differential voltage output module;
The other output end of the main path differential amplifying circuit is connected to the first bias circuit, and the other output end of the auxiliary path differential amplifying circuit is connected to the second bias circuit;
The first bias circuit is further connected to a bias voltage source, which is further connected to the second bias circuit through the high frequency component emphasis controller.
2. The signal equalizer of claim 1, wherein the differential voltage input comprises a differential positive voltage input and a differential negative voltage input, the main path differential amplifying circuit comprises a first transistor, a second transistor, a first resistor and a second resistor,
The base electrode of the first triode is connected to the differential positive voltage input end and the auxiliary channel differential amplifying circuit, and the base electrode of the second triode is respectively connected to the differential negative voltage input end and the auxiliary channel differential amplifying circuit;
The collector electrode of the first triode and the collector electrode of the second triode are connected with the auxiliary channel differential amplifying circuit and then connected with the differential voltage output module;
The emission set of the first triode is connected to one end of the first resistor, the other end of the first resistor is connected to one end of the second resistor and the first bias circuit respectively, and the other end of the second resistor is connected to the emitter of the second triode.
3. The signal equalizer of claim 2, wherein the differential voltage output module comprises a first output resistor, a second output resistor, a differential positive voltage output terminal, and a differential negative voltage output terminal, the sub-path differential amplification circuit comprises a first low pass filter circuit, a second low pass filter circuit, a third triode, a fourth triode, a third resistor, and a fourth resistor,
The input end of the first low-pass filter circuit is respectively connected to the differential negative voltage input end and the base electrode of the second triode, the output end of the first low-pass filter circuit is connected to the base electrode of the third triode, the input end of the second low-pass filter circuit is respectively connected to the differential positive voltage input end and the base electrode of the first triode, and the output end of the first low-pass filter circuit is connected to the base electrode of the fourth triode;
The collector of the third triode is respectively connected to the collector of the first triode, the differential negative voltage output end and one end of the first output resistor, the collector of the fourth triode is respectively connected to the collector of the second triode, the differential positive voltage output end and one end of the second output resistor, and the other end of the first output resistor and the other end of the second output resistor are respectively connected to a power supply;
The emitter of the third triode is connected to one end of the third resistor, the other end of the third resistor is connected to one end of the fourth resistor and the second bias circuit respectively, and the other end of the fourth resistor is connected to the emitter of the fourth triode.
4. The signal equalizer of claim 3, wherein the first low pass filter circuit comprises a fifth resistor and a first adjustable capacitor, wherein the second low pass filter circuit comprises a sixth resistor, a second adjustable capacitor,
One end of the fifth resistor is respectively connected to the base electrode of the second triode and the differential negative voltage input end, the other end of the fifth resistor is respectively connected to one end of the first adjustable capacitor and the base electrode of the third triode, and the other end of the first adjustable capacitor is grounded;
one end of the sixth resistor is connected to the base electrode of the first triode and the differential positive voltage input end respectively, the other end of the sixth resistor is connected to one end of the second adjustable capacitor and the base electrode of the fourth triode respectively, and the other end of the second adjustable capacitor is grounded.
5. The signal equalizer of claim 2, wherein the first bias circuit comprises a first operational amplifier, a fifth transistor, and a seventh resistor,
The positive input end of the first operational amplifier is connected to the bias voltage source, the negative input end of the first operational amplifier is connected to one end of the seventh resistor and the emitter of the fifth triode respectively, the other end of the seventh resistor is grounded, the output end of the first operational amplifier is connected to the base of the fifth triode, and the collector of the fifth triode is connected to the other end of the first resistor and one end of the second resistor respectively, wherein bias current provided by the bias voltage source is proportional to absolute temperature.
6. The signal equalizer of claim 3, wherein the second bias circuit comprises a second operational amplifier, a sixth transistor, and an eighth resistor,
The bias voltage source is connected to the positive input end of the second operational amplifier through the high-frequency component weighting controller, the negative input end of the second operational amplifier is respectively connected to one end of the eighth resistor and the emitter of the sixth triode, the other end of the eighth resistor is grounded, the output end of the second operational amplifier is connected to the base electrode of the sixth triode, and the collector electrode of the sixth triode is respectively connected to the other end of the third resistor and one end of the fourth resistor.
7. An adjustable amplifier comprising a gain control circuit and a signal equalizer as claimed in any one of claims 1-6,
One input end of the gain control circuit is connected to the upper computer so as to acquire an amplified gain signal sent by the upper computer, and the other input end of the gain control circuit is respectively connected to one output end of the main path differential amplifying circuit and one output end of the auxiliary path differential amplifying circuit;
The output end of the gain control circuit is connected to the differential voltage output module.
8. The adjustable amplifier of claim 7 wherein the gain control circuit comprises a first current rudder, a second current rudder, a seventh transistor, an eighth transistor, a third operational amplifier, and a current source,
The input end of the current source is connected to the upper computer, the first output end of the current source is connected to the positive input end of the third operational amplifier, the second output end of the current source is connected to the negative input end of the third operational amplifier, the positive output end of the third operational amplifier is respectively connected to the base electrode of the seventh triode, the first input end of the first current rudder and the first input end of the second current rudder, and the negative output end of the third operational amplifier is respectively connected to the base electrode of the eighth triode, the second input end of the first current rudder and the second input end of the second current rudder;
The collector of the seventh triode and the collector of the eighth triode are respectively connected to a power supply, the emitter of the seventh triode is connected to the negative input end of the third operational amplifier, and the emitter of the eighth triode is connected to the positive input end of the third operational amplifier;
The first output end of the first current rudder is respectively connected to the collector electrode of the first triode in the main path differential amplifying circuit and the collector electrode of the third triode in the auxiliary path differential amplifying circuit, and the second output end of the first current rudder is connected to one end of the first output resistor in the differential voltage output module and the differential negative voltage output end;
The first output end of the second current rudder is respectively connected to the collector electrode of the fourth triode in the auxiliary path differential amplifying circuit and the collector electrode of the second triode in the main path differential amplifying circuit, and the second output end of the second current rudder is connected to one end of the second output resistor in the differential voltage output module and the differential positive voltage output end.
9. The adjustable amplifier of claim 8 wherein the first current rudder comprises a ninth transistor and a thirteenth transistor, the second current rudder comprises an eleventh transistor and a twelfth transistor,
The base electrode of the thirteenth triode is connected with the base electrode of the eleventh triode and then connected with the positive output end of the third operational amplifier;
The collector of the ninth triode is connected to the differential negative voltage output end and one end of the first output resistor, the collector of the thirteenth triode and the collector of the eleventh triode are respectively connected to a power supply, and the collector of the twelfth triode is connected to the differential positive voltage output end and one end of the second output resistor;
The emitter of the ninth triode is connected with the emitter of the thirteenth triode and then connected with the collector of the first triode and the collector of the third triode, and the emitter of the eleventh triode is connected with the emitter of the twelfth triode and then connected with the collector of the second triode and the collector of the fourth triode.
10. A buffer comprising a third current rudder and a signal equalizer as claimed in any one of claims 1 to 6,
The first input end of the third current rudder is connected to an upper computer, and the second input end of the third current rudder is respectively connected to the main path differential amplifying circuit and the auxiliary path differential amplifying circuit;
The output end of the third current rudder is connected to the differential voltage output module.
11. The buffer of claim 10 wherein the third current rudder comprises a thirteenth transistor and a fourteenth transistor,
The base electrode of the thirteenth triode is connected with the base electrode of the fourteenth triode and then is connected with the upper computer, the collector electrode of the thirteenth triode is connected to the differential negative voltage output end in the differential voltage output module and one end of the first output resistor, and the emitter electrode of the thirteenth triode is respectively connected to the collector electrode of the first triode in the main path differential amplifying circuit and the collector electrode of the third triode in the auxiliary path differential amplifying circuit;
and the collector electrode of the fourteenth triode is connected to the differential positive voltage output end of the differential voltage output module and one end of the second output resistor, and the emitter electrode of the fourteenth triode is respectively connected to the collector electrode of the second triode in the main path differential amplifying circuit and the collector electrode of the fourth triode in the auxiliary path differential amplifying circuit.
12. An optoelectronic receiver, the optoelectronic receiver comprising:
the photodiode is used for converting the received optical signal into a current signal and transmitting the current signal to the transimpedance amplifier;
The transimpedance amplifier is used for converting the current signal into a differential voltage signal and then transmitting the differential voltage signal to the adjustable amplifier;
the adjustable amplifier is used for amplifying the differential voltage signal and then transmitting the differential voltage signal to the buffer;
the buffer is used for outputting a target voltage signal after carrying out signal attenuation processing on the amplified differential voltage signal,
Wherein the adjustable amplifier and/or the buffer comprises a signal equalizer as claimed in any one of claims 1-6.
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Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6486735B1 (en) * | 2000-05-12 | 2002-11-26 | National Semiconductor Corporation | Adaptive equalizer filter with variable gain control |
| US20030174023A1 (en) * | 2002-03-12 | 2003-09-18 | Tokio Miyasita | Analog summing and differencing circuit, optical receiving circuit, optical transmitting circuit, automatic gain control amplifier, automatic frequency compensation amplifier, and limiting amplifier |
| US20060066395A1 (en) * | 2004-09-29 | 2006-03-30 | Mostafa Elmala | Variable gain amplifier with direct current offset correction |
| CN1957527A (en) * | 2004-03-31 | 2007-05-02 | 模拟设备股份有限公司 | Differential stage voltage offset trimming circuit |
| US7254173B1 (en) * | 2003-03-21 | 2007-08-07 | Applied Micro Circuits Corporation | Digitally adjusted high speed analog equalizer |
| CN108183696A (en) * | 2018-03-06 | 2018-06-19 | 厦门优迅高速芯片有限公司 | A kind of low-voltage high speed may be programmed equalizing circuit |
| CN109546987A (en) * | 2018-11-16 | 2019-03-29 | 西安电子科技大学 | Broadband active phase shifter |
| KR20200115805A (en) * | 2019-03-26 | 2020-10-08 | 삼성전자주식회사 | Receiver for compensating common mode offset |
| CN112272061A (en) * | 2020-10-22 | 2021-01-26 | 联合微电子中心有限责任公司 | Analog front-end circuit of optical receiver |
| CN116545399A (en) * | 2023-05-30 | 2023-08-04 | 深圳市傲科光电子有限公司 | Variable gain amplifier and communication circuit |
| CN116962125A (en) * | 2023-02-13 | 2023-10-27 | 北京大学 | A feedforward equalizer circuit with adjustable tap frequency response |
-
2024
- 2024-06-06 CN CN202410725920.3A patent/CN118300540B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6486735B1 (en) * | 2000-05-12 | 2002-11-26 | National Semiconductor Corporation | Adaptive equalizer filter with variable gain control |
| US20030174023A1 (en) * | 2002-03-12 | 2003-09-18 | Tokio Miyasita | Analog summing and differencing circuit, optical receiving circuit, optical transmitting circuit, automatic gain control amplifier, automatic frequency compensation amplifier, and limiting amplifier |
| US7254173B1 (en) * | 2003-03-21 | 2007-08-07 | Applied Micro Circuits Corporation | Digitally adjusted high speed analog equalizer |
| CN1957527A (en) * | 2004-03-31 | 2007-05-02 | 模拟设备股份有限公司 | Differential stage voltage offset trimming circuit |
| US20060066395A1 (en) * | 2004-09-29 | 2006-03-30 | Mostafa Elmala | Variable gain amplifier with direct current offset correction |
| CN108183696A (en) * | 2018-03-06 | 2018-06-19 | 厦门优迅高速芯片有限公司 | A kind of low-voltage high speed may be programmed equalizing circuit |
| CN109546987A (en) * | 2018-11-16 | 2019-03-29 | 西安电子科技大学 | Broadband active phase shifter |
| KR20200115805A (en) * | 2019-03-26 | 2020-10-08 | 삼성전자주식회사 | Receiver for compensating common mode offset |
| CN112272061A (en) * | 2020-10-22 | 2021-01-26 | 联合微电子中心有限责任公司 | Analog front-end circuit of optical receiver |
| CN116962125A (en) * | 2023-02-13 | 2023-10-27 | 北京大学 | A feedforward equalizer circuit with adjustable tap frequency response |
| CN116545399A (en) * | 2023-05-30 | 2023-08-04 | 深圳市傲科光电子有限公司 | Variable gain amplifier and communication circuit |
Non-Patent Citations (2)
| Title |
|---|
| "一种宽带电调均衡器的设计", 《电子信息对抗技术》, 31 December 2021 (2021-12-31), pages 79 - 82 * |
| JONATHAN E. PROESEL: "A 20-Gb/s, 0.66-pJ/bit serial receiver with 2-stage continuous-time linear equalizer and 1-tap decision feedback equalizer in 45nm SOI CMOS", 《2011 SYMPOSIUM ON VLSI CIRCUITS - DIGEST OF TECHNICAL PAPERS》, 31 December 2011 (2011-12-31), pages 1 - 4 * |
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