CN118282369A - High-precision digital pulse modulator and switch converter - Google Patents
High-precision digital pulse modulator and switch converter Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/22—Conversion of DC power input into DC power output with intermediate conversion into AC
- H02M3/24—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
- H02M3/28—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
- H02M3/325—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
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Abstract
The application discloses a high-precision digital pulse modulator and a switching converter, a coarse adjustment module obtains a first pulse signal according to a sampling clock signal and coarse adjustment parameters, a clock generation module obtains N-phase clock signals through an oscillator, N is a positive integer greater than or equal to 2, the N-phase clock signals are sequentially misplaced, the time interval of two adjacent clock signals is the cycle time of a standard clock signal divided by N, a fine adjustment module comprises a trigger chain, the fine adjustment module receives the first pulse signal, the N-phase clock signals and fine adjustment parameters so as to output a second pulse signal with accurate fine adjustment according to the first pulse signal, the N-phase clock signals clock-control the clock input end of the trigger chain, and the fine adjustment module can dynamically and automatically reset under the condition of accurately carrying out fine adjustment on the pulse signals, so that a calibration circuit is not needed, the cost can be saved, and the whole volume of a device can be reduced.
Description
Technical Field
The present invention relates to the field of electronic circuits, and more particularly, to a high-precision digital pulse modulator and a switching converter.
Background
A digital pulse width modulator (Digital Pulse Width Modulator, DPWM), commonly used in digitally controlled switching converters such as DC-DC converters, converts a digital signal transmitted by a pre-stage circuit into a pulse width signal output corresponding to a duty cycle, the pulse width signal of the duty cycle characterizing the magnitude of a duty cycle of a switching cycle for controlling the switching state of a switching tube of the switching converter. The pulse width signal generated by the DPWM can directly influence the on period and time of the switch of the DC-DC converter, and further influence the ripple of the output voltage. Therefore, the adjustment accuracy of the DPWM needs to be high enough, and the adjustment step needs to be thin enough, otherwise, the voltage stability is directly output.
In order to improve the accuracy of DPWM adjustment, the DPWM is generally required to be divided into a coarse adjustment and a fine adjustment, as shown in fig. 1, which is a DPWM adjustment scheme in the prior art patent CN 102832914A, and includes a coarse adjustment module and a fine adjustment module: the coarse adjustment module counts according to a preset sampling clock period by the digital counter, then outputs a coarse adjustment pulse signal when the coarse adjustment count threshold (namely coarse adjustment parameter) is reached by comparison of the comparator, the fine adjustment module receives the coarse adjustment pulse signal, shifts out signals of 32 phases in one period through delay lines such as delay action of a plurality of buffers D0 to D31, selects a needed corresponding phase signal as a reset signal of the trigger according to the fine adjustment parameter, and further accurately adjusts the falling edge position of the output pulse signal, and the setting signal of the trigger is determined according to the period of the clock signal. The delay line characteristics of the structure are greatly influenced by processes, voltages and temperatures, and an additional calibration circuit such as a logic control module in fig. 1 is needed, so that the complexity of the whole module is large, and the area of the delay line is large, so that the cost of a chip is greatly increased.
The existing solutions cannot meet the control requirements of simple control and low cost, and therefore, it is necessary to provide an improved technical solution to overcome the above technical problems existing in the prior art.
Disclosure of Invention
In view of the above, the present invention is directed to a high-precision digital pulse modulator and a switching converter, which are used for solving the technical problems of complicated control and high cost in the digital pulse modulator in the prior art.
The utility model provides a high accuracy digital pulse modulator for receiving the digital signal of input, convert to pulse signal output, including coarse adjustment module, fine adjustment module and clock generation module, coarse adjustment module is according to sampling clock signal and coarse adjustment parameter obtain first pulse signal, coarse adjustment parameter characteristic the high order part of digital signal, the clock generation module passes through the oscillator and obtains N looks clock signal, the clock cycle of N looks clock signal is the same and marks as the cycle of standard clock signal, N is the positive integer more than or equal to 2, wherein, N looks clock signal misplaces in proper order, and the time interval of adjacent two looks clock signal is the cycle time of standard clock signal divided by N, fine adjustment module includes the trigger chain, N looks clock signal carries out clock control to the clock input of trigger chain, fine adjustment module receives first pulse signal, N looks clock signal and fine adjustment parameter to the second pulse signal of accurate fine adjustment is based on this output, fine adjustment parameter characteristic the low order part of digital signal.
Preferably, a zeroth phase clock signal of the N-phase clock signals is used as the sampling clock signal.
Preferably, the clock generating module comprises N-way oscillators, and N-phase oscillators are connected in series to uniformly phase-shift the zeroth phase clock signal to obtain an N-phase clock signal output.
Preferably, the clock generation module comprises N/2 paths of differential oscillators, and the N/2 paths of differential oscillators are connected in series so as to uniformly phase shift the zero-phase clock signal and obtain N-phase clock signal output.
Preferably, the fine adjustment module includes a signal adjustment circuit, a trigger chain, a signal selection module and a PWM signal generation module, where the signal adjustment circuit receives the first pulse signal to obtain a third pulse signal and a selection signal, the trigger chain receives the N-phase clock signal and the third pulse signal to trigger the third pulse signal to perform phase shift processing according to the N-phase clock signal in sequence to obtain an N-phase pulse signal, the signal selection module receives the fine adjustment parameter and the N-phase pulse signal to select one phase of the N-phase pulse signal according to the fine adjustment parameter, and the PWM signal generation module receives the selection signal and an output signal of the signal selection module to obtain the second pulse signal.
Preferably, the signal adjustment circuit includes an exclusive-or logic circuit that receives the first pulse signal and the zeroth phase clock signal to output a first trigger signal, and a first flip-flop that receives the first pulse signal and the first output signal to obtain a third pulse signal, a second flip-flop that receives the first trigger signal and the zeroth phase clock signal to generate a second trigger signal, and a third flip-flop that receives the second trigger signal and the zeroth phase clock signal to generate the selection signal.
Preferably, the flip-flop chain includes N flip-flops, the D input end and the reset end of the next flip-flop in the N flip-flops are connected to the output end of the previous flip-flop, the clock input ends of the N flip-flops correspondingly receive the N-phase clock signal, the first flip-flop in the flip-flop chain receives the third pulse signal and the zeroth phase clock signal to generate a first-phase pulse signal, and the second flip-flop to the nth flip-flop in the flip-flop chain sequentially receive the output signals of the previous flip-flop to obtain second-phase pulse signals to nth-phase pulse signals.
Preferably, the signal selection module includes a multiplexer, and the multiplexer receives the fine tuning parameter and the first phase pulse signal to the nth phase pulse signal, so as to select one phase of the N phase pulse signal according to the fine tuning parameter.
Preferably, the multiplexer includes two ways, the two ways of multiplexers each receive the first phase pulse signal to the nth phase pulse signal, the fine adjustment parameters include a rising edge fine adjustment parameter and a falling edge fine adjustment parameter, one way of the two ways of multiplexers receives the rising edge fine adjustment parameter, the other way of the two ways of multiplexers receives the falling edge fine adjustment parameter, and the two ways of multiplexers select one phase of the first phase pulse signal to the nth phase pulse signal to output according to the received fine adjustment parameter.
Preferably, the PWM signal generating module includes an and circuit and a flip-flop, the and circuit receives the selection signal and an output signal of the multiplexer, the output signal is transmitted to a reset terminal of the flip-flop, and a set terminal of the flip-flop receives an input clock signal of the system to obtain the second pulse signal output.
Preferably, the selection signal includes a first selection signal and a second selection signal, the PWM signal generating module includes a first and gate circuit and a trigger, and a second and gate circuit and a trigger, the first and gate circuit receives the selection signal and an output signal of the multiplexer to output a first logic signal, the second and gate circuit receives the selection signal and another output signal of the multiplexer to output a second logic signal, wherein the first logic signal generated according to a rising edge fine adjustment parameter is transmitted to a set end of the trigger, the second logic signal generated according to a falling edge fine adjustment parameter is transmitted to a reset end of the trigger, and the trigger obtains the second pulse signal to output.
Preferably, the coarse adjustment module includes a counter that receives the sampling clock signal to count, and a comparator that compares the counted signal with the coarse adjustment parameter to generate the first pulse signal.
In a second aspect, a switching converter is provided, including a power stage circuit and a control module, where the control module includes an analog-to-digital converter, a proportional adjustment circuit and the high-precision digital pulse modulator, where the analog-to-digital converter receives an output signal of the power stage circuit and a reference signal to output a digital error signal, the proportional adjustment circuit receives the digital error signal to output an adjusted signal after proportional adjustment, and the digital pulse modulator controls the digital pulse modulator to receive the adjusted signal output by the proportional adjustment circuit as an input digital signal, and modulates the adjusted signal to obtain a pulse signal with a corresponding duty ratio, where the pulse signal is used to control a switching state of a power switch tube in the power stage circuit.
The high-precision digital pulse modulator and the switching converter comprise a clock generation module, a coarse adjustment module and a fine adjustment module, wherein the coarse adjustment module obtains a first pulse signal according to a sampling clock signal and coarse adjustment parameters, the clock generation module obtains N-phase clock signals through an oscillator, N is a positive integer greater than or equal to 2, the N-phase clock signals are sequentially misplaced, the time interval of each two adjacent phase clock signals is the period time of a standard clock signal divided by N, the fine adjustment module comprises a trigger chain, the fine adjustment module receives the first pulse signal, the N-phase clock signals and fine adjustment parameters so as to output a second pulse signal which is accurately and finely adjusted according to the first pulse signal, the N-phase clock signals clock the clock input end of the trigger chain, and the fine adjustment module can dynamically and self-reset under the condition of accurately carrying out the fine adjustment of the pulse signals, so that a calibration circuit is not needed, the cost can be saved, the whole size of a device is simple and reliable to control.
Drawings
FIG. 1 is a block diagram of a prior art switching power supply with a digital pulse modulator;
FIG. 2 is a circuit block diagram of a switching converter according to the present invention;
FIG. 3 is a first circuit diagram of a high-precision digital pulse modulator according to the present invention;
FIG. 4 is a circuit diagram of one manner of implementing the fine-tuning circuit according to FIG. 3;
FIG. 5 is a circuit diagram of one implementation of the signal conditioning circuit according to FIG. 4;
FIG. 6 is a circuit diagram of one implementation of the flip-flop chain according to FIG. 4;
fig. 7 is a circuit diagram of one implementation of the signal selection module and PWM signal generation module according to fig. 4.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but the present invention is not limited to these embodiments only. The invention is intended to cover any alternatives, modifications, equivalents, and variations that fall within the spirit and scope of the invention.
In the following description of preferred embodiments of the invention, specific details are set forth in order to provide a thorough understanding of the invention, and the invention will be fully understood to those skilled in the art without such details.
The invention is more particularly described by way of example in the following paragraphs with reference to the drawings. It should be noted that the drawings are in a simplified form and are not to scale precisely, but rather are merely intended to facilitate and clearly illustrate the embodiments of the present invention.
Referring to fig. 2, a circuit diagram of a switching converter according to the present application, fig. 3, a circuit diagram of a high-precision digital pulse modulator according to the present application, and fig. 4, a circuit diagram of a manner of implementing the fine-tuning circuit according to fig. 3 are shown. The application relates to a high-precision digital pulse modulator, which is used for receiving an input digital signal, converting the input digital signal into a pulse signal to be output and applying the pulse signal to a switch converter, as shown in fig. 2, wherein the switch converter comprises a power stage circuit, such as a Buck circuit, but is not limited to the Buck circuit, a control module of the switch converter comprises an analog-to-digital converter A/D, a proportion regulating circuit PID and a high-precision digital pulse modulator DPWM of the embodiment, wherein the analog-to-digital converter receives an output signal Vout and a reference signal Vref of the power stage circuit to output a digital error signal Ek, the proportion regulating circuit receives the digital error signal Ek to output a regulated signal Duty after the proportion regulating circuit is used as the input digital signal, the digital pulse modulator controls the regulated signal of the proportion regulating circuit to be modulated to obtain a pulse signal with a corresponding Duty ratio, the pulse signal is used for controlling the switching state of a power switching tube in the power stage circuit, and the power switching tube comprises a main power switching tube Q1 and a freewheel switching tube Q2.
Referring to fig. 3, the high-precision digital pulse modulator includes a coarse adjustment module, a fine adjustment module and a clock generation module, where the coarse adjustment module obtains a first pulse signal PWM1 according to a sampling clock signal and a coarse adjustment parameter, the coarse adjustment parameter characterizes a high-order part of the digital signal, the clock generation module obtains an N-phase clock signal, such as N is 8 or 16, where the N-phase clock signal is clk0-clk7, N is a positive integer greater than or equal to 2, the N-phase clock signal is sequentially misplaced, a clock period of the N-phase clock signal is set to a time period of the standard clock signal, a time interval of each adjacent two phases is set to a time period of one standard clock signal divided by N, a zero-th phase clock signal is used as the sampling clock signal, the fine adjustment module includes a trigger chain, and the N-phase clock signal clocks a clock input end of the trigger chain to receive the first pulse signal, the N-phase clock signal and the fine adjustment parameter, so that the fine adjustment signal is a high-order part of the digital pulse signal, and the fine adjustment parameter is set according to a predetermined pulse signal, and the fine adjustment parameter is set in advance, and the fine adjustment parameter is a high-order part of the digital pulse signal is defined according to the predetermined pulse signal, and the fine adjustment parameter is set in advance, and the fine adjustment parameter is set to a high-order part of the digital pulse signal is determined; the low order part is used as a fine tuning coefficient to determine the fine tuning of the pulse width further on the coarse tuning module, and the coarse tuning coefficient and the fine tuning coefficient jointly determine the pulse width of the final output pulse signal.
In one embodiment, the N-phase clock signals are uniformly phase-staggered in sequence, and each phase is shifted backward by 1/N period relative to its previous adjacent clock signal, for example, including N-phase oscillators connected in series to obtain N-phase clock signal output through N-way oscillators. In this embodiment, the clock generating module uses a mode of multiplexing the frequency-locking ring, and the output of the last oscillator is connected with the input of the first oscillator, so that the overall frequency is constant, and therefore, a standard period is divided into eight fine-tuning phases with minimum power consumption and area cost, and due to the effect of the frequency-locking ring, the eight-phase clock can resist the change of PVT, and accurate clock phase separation is realized. In another embodiment, the clock generating module includes N/2 differential oscillators, the N/2 differential oscillators are connected in series, and an output of a last oscillator is connected with an input of a first oscillator in a cross manner, so as to uniformly phase shift a zero-th phase clock signal to obtain first to nth phase clock signals.
Referring to fig. 4, a circuit diagram of one implementation of a fine tuning circuit is shown, where the fine tuning module includes a signal adjusting circuit, a trigger chain, a signal selecting module, and a PWM signal generating module, specifically, the signal adjusting circuit receives the first pulse signal PWM1 to obtain a third pulse signal PWM3 and a selection signal, the trigger chain receives the N-phase clock signal and the third pulse signal to sequentially trigger phase shifting processing of the third pulse signal according to the N-phase clock signal to obtain N-phase pulse signals sr0-sr7, the signal selecting module receives the fine tuning parameter and the N-phase pulse signals sr0-sr7 to select one phase of the N-phase pulse signals according to the fine tuning parameter, for example, srx, and the PWM signal generating module receives the selection signal and an output signal srx of the signal selecting module to obtain the second pulse signal PWM2. As the fine-tuning circuit provided by the scheme of the application has no calibration circuit for calibrating the pulse signals, a large circuit area and control complexity can be saved.
Specifically, referring to fig. 5, in one implementation manner of the signal adjustment circuit, the signal adjustment circuit includes an exclusive-or logic circuit and a first flip-flop, a second flip-flop and a third flip-flop, where the first flip-flop receives the first pulse signal and the zeroth phase clock signal to output a first trigger signal, the exclusive-or logic circuit receives the first pulse signal and the first output signal to obtain a third pulse signal PWM3, the second flip-flop receives the first trigger signal and the zeroth phase clock signal to generate a second trigger signal, and the third flip-flop receives the second trigger signal and the zeroth phase clock signal to generate the selection signal, where the selection signal may include a first selection signal vsel_1 and a second selection signal vsel_1 for signal selection control of a rising edge and signal selection control of a falling edge of a subsequent stage, respectively.
Specifically, referring to fig. 6, a circuit diagram is implemented in one manner of a flip-flop chain, where the flip-flop chain includes N flip-flops, a D input terminal and a reset terminal of a next flip-flop in the N flip-flops are connected to an output terminal of a previous flip-flop, clock input terminals of the N flip-flops correspondingly receive the N-phase clock signal, a first flip-flop in the flip-flop chain receives the third pulse signal and the zero-phase clock signal to generate a first-phase pulse signal sr0, and second flip-flops in the flip-flop chain sequentially receive output signals of previous flip-flops to obtain second-phase pulse signals sr1 to N-phase pulse signals sr7. Through the control of the trigger chain, each stage of trigger is effective only in the period that the input signal is high level, so that unnecessary power consumption caused by invalid inversion of internal circuits of the trigger such as a clock is avoided, in addition, the output signal of the trigger chain with dynamic self-reset is a combination signal sr 0-sr 7 with rising edge and falling edge, the width of the high level can be gradually reduced due to the effect of dynamic self-reset, and the last phase pulse signal only has a width with fine adjustment interval, but the trigger itself has delay from a reset end to an output end, the delay can be accumulated step by step, the pulse width of each phase pulse signal sr 0-sr 7 can be supplemented, and the problem that a subsequent circuit cannot be triggered due to too narrow pulse width is avoided.
Specifically, referring to fig. 7, a circuit diagram is implemented in one manner of the signal selection module and the PWM signal generation circuit, in one example, the signal selection module includes a multiplexer MUX, where, for example, a multiplexer receives the fine tuning parameter and the first phase pulse signal to the nth phase pulse signal, so as to select one phase srx of the N phase pulse signals according to the fine tuning parameter. The PWM signal generating module includes an and circuit that receives the selection signal such as vsel_2 and the output signal of the multiplexer, the output signal being transmitted to the reset terminal of the flip-flop, and the set terminal of the flip-flop receiving an input clock signal (not shown in fig. 6) of the system to obtain the second pulse signal PWM2 output. Here, the selection signal is a falling edge selection signal, and by the above-described structure, the falling edge position of the output pulse signal can be accurately adjusted, so that the width of the pulse signal can be accurately adjusted.
Still further, referring to fig. 7, the multiplexers include two ways, each of the two ways receives the first phase pulse signal to the nth phase pulse signal sr0-sr7, the fine adjustment parameters include a rising edge fine adjustment parameter 1 and a falling edge fine adjustment parameter 2, one of the two ways receives the rising edge fine adjustment parameter, the other receives the falling edge fine adjustment parameter, the two ways select one of the first phase pulse signal to the nth phase pulse signal to output according to the received fine adjustment parameter, and the output signals of the two ways may be the same or different. With continued reference to fig. 6, in this embodiment, the selection signal includes a first selection signal vsel_1 and a second selection signal vsel_2, the PWM signal generating module includes a first and a second and gates, the first and gate receives the selection signal such as vsel_1 and the output signal of the multiplexer to output a first logic signal set, the second and gate receives the selection signal and the output signal of the other multiplexer to output a second logic signal rst, wherein the first logic signal generated according to the rising edge fine adjustment parameter is transmitted to the set end of the flip-flop, the second logic signal generated according to the falling edge fine adjustment parameter is transmitted to the reset end of the flip-flop, and the flip-flop obtains the second pulse signal PWM2 to output. Thus, through the structure, the rising edge and the falling edge of the first pulse signal can be further adjusted at the same time, and a more accurate pulse signal is obtained.
Preferably, the coarse adjustment module includes a counter that receives the sampling clock signal to count, and a comparator that compares the counted signal with the coarse adjustment parameter to generate the first pulse signal.
The digital pulse modulator can be applied to a switch converter with any proper topological structure, is not limited to a buck converter in the embodiment, and according to the high-precision digital pulse modulator and the switch converter, the clock input end of the trigger chain is controlled by the N-phase clock signal, so that a fine adjustment module can perform dynamic self-resetting without extra calibration under the condition of precisely performing fine adjustment on the pulse signal, the precision is insensitive to PVT, the PVT is easy to transplant, the low-power-consumption and miniature advantages are realized, the cost can be saved, the whole volume of a device can be reduced, the rising edge and the falling edge can be adjusted at the same time with high precision, and the application range is wide.
It should be noted that the detailed description and the corresponding drawings are merely illustrative of one way of implementing the method of the invention and are not limiting of the specific structure of the embodiments of the invention, and many changes or modifications may be made to these embodiments without departing from the principles and spirit of the invention, but these changes and modifications fall within the scope of the invention.
Although the embodiments have been described and illustrated separately above, and with respect to a partially common technique, it will be apparent to those skilled in the art that alternate and integration may be made between embodiments, with reference to one embodiment not explicitly described, and reference may be made to another embodiment described.
The above-described embodiments do not limit the scope of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the above embodiments should be included in the scope of the present invention.
Claims (13)
1.A high-precision digital pulse modulator is used for receiving an input digital signal and converting the digital signal into a pulse signal to be output, and is characterized by comprising a coarse adjustment module, a fine adjustment module and a clock generation module,
The coarse tuning module obtains a first pulse signal based on a sampling clock signal and a coarse tuning parameter, the coarse tuning parameter characterizing a high order portion of the digital signal,
The clock generation module obtains N-phase clock signals through an oscillator, the clock periods of the N-phase clock signals are the same and recorded as the periods of the standard clock signals, N is a positive integer greater than or equal to 2, wherein the N-phase clock signals are sequentially staggered, the time interval of two adjacent phase clock signals is the period time of the standard clock signals divided by N,
The fine adjustment module comprises a trigger chain, the N-phase clock signal is used for carrying out clock control on the clock input end of the trigger chain, the fine adjustment module is used for receiving the first pulse signal, the N-phase clock signal and fine adjustment parameters so as to output a second precisely fine-adjusted pulse signal according to the first pulse signal, the N-phase clock signal and the fine adjustment parameters, and the fine adjustment parameters represent low-order parts of the digital signals.
2. The high precision digital pulse modulator of claim 1, wherein a zeroth phase clock signal of the N-phase clock signals is used as the sampling clock signal.
3. The high-precision digital pulse modulator of claim 2, wherein the clock generation module comprises N-way oscillators, the N-phase oscillators being connected in series to uniformly phase shift the zeroth phase clock signal to obtain the N-phase clock signal output.
4. The high-precision digital pulse modulator according to claim 2, wherein the clock generation module comprises N/2-way differential oscillators, and the N/2-way differential oscillators are connected in series to uniformly phase-shift the zeroth phase clock signal to obtain the N-phase clock signal output.
5. The high-precision digital pulse modulator according to claim 1, wherein the fine adjustment module comprises a signal adjustment circuit, a flip-flop chain, a signal selection module, and a PWM signal generation module,
The signal adjusting circuit receives the first pulse signal to obtain a third pulse signal and a selection signal,
The trigger chain receives the N-phase clock signal and the third pulse signal to trigger the third pulse signal to be subjected to phase shift processing according to the N-phase clock signal in sequence to obtain the N-phase pulse signal,
The signal selection module receives the fine tuning parameter and the N-phase pulse signal to select one phase of the N-phase pulse signal according to the fine tuning parameter,
The PWM signal generating module receives the selection signal and an output signal of the signal selecting module to obtain the second pulse signal.
6. The high precision digital pulse modulator according to claim 5, wherein the signal conditioning circuit comprises an exclusive OR logic circuit and first, second and third flip-flops,
The first trigger receives the first pulse signal and the zero-phase clock signal to output a first trigger signal,
The exclusive-or logic circuit receives the first pulse signal and the first output signal to obtain a third pulse signal,
The second trigger receives the first trigger signal and the zero-phase clock signal to generate a second trigger signal,
The third flip-flop receives the second trigger signal and the zero-phase clock signal to generate the selection signal.
7. The high-precision digital pulse modulator according to claim 5, wherein the flip-flop chain comprises N flip-flops, the D input terminal and the reset terminal of the next flip-flop in the N flip-flops are connected with the output terminal of the last flip-flop, the clock input terminals of the N flip-flops correspondingly receive the N-phase clock signal,
A first flip-flop in the chain of flip-flops receives the third pulse signal and the zero-phase clock signal to generate a first phase pulse signal,
And the second to nth triggers in the trigger chain sequentially receive the output signals of the previous stage trigger to obtain second to nth phase pulse signals.
8. The high precision digital pulse modulator according to claim 5, wherein said signal selection module comprises a multiplexer,
The multiplexer receives the fine tuning parameter and the first phase pulse signal to the N phase pulse signal to select one phase of the N phase pulse signal according to the fine tuning parameter.
9. The high precision digital pulse modulator according to claim 8, wherein the multiplexer comprises two ways,
The two multiplexers each receive the first phase pulse signal to the N phase pulse signal,
The fine tuning parameters comprise rising edge fine tuning parameters and falling edge fine tuning parameters, one of the two multiplexers receives the rising edge fine tuning parameters, the other multiplexer receives the falling edge fine tuning parameters,
And the two multiplexers select one phase of the first phase pulse signal to the N phase pulse signal to output according to the received fine tuning parameters.
10. The high-precision digital pulse modulator according to claim 8, wherein the PWM signal generation module comprises an AND gate circuit and a flip-flop,
The AND gate circuit receives the selection signal and the output signal of the multiplexer, the output signal is transmitted to the reset end of the trigger,
And the trigger setting end receives an input clock signal of the system to obtain the second pulse signal output.
11. The high precision digital pulse modulator according to claim 9, wherein the selection signal comprises a first selection signal and a second selection signal,
The PWM signal generating module comprises a first path of AND gate circuit, a trigger, a second path of AND gate circuit and a trigger,
The first path AND gate circuit receives the selection signal and the output signal of the multiplexer to output a first logic signal, the second path AND gate circuit receives the selection signal and the output signal of the other path of multiplexer to output a second logic signal,
The first logic signal generated according to the rising edge fine adjustment parameter is transmitted to the set end of the trigger, the second logic signal generated according to the falling edge fine adjustment parameter is transmitted to the reset end of the trigger, and the trigger obtains the second pulse signal output.
12. The high precision digital pulse modulator of claim 1, wherein the coarse tuning module comprises a counter and a comparator,
The counter receives the sampling clock signal for counting, and the comparator compares the counted signal with the rough adjustment parameter to generate the first pulse signal.
13. A switching converter comprising a power stage circuit and a control module, wherein the control module comprises an analog-to-digital converter, a proportional adjustment circuit and a high precision digital pulse modulator according to any of claims 1-12,
The analog-to-digital converter receives the output signal of the power stage circuit and a reference signal to output a digital error signal,
The proportion adjusting circuit receives the digital error signal to output an adjusting signal after proportion adjustment,
The digital pulse modulator is used for controlling and receiving the regulating signal output by the proportion regulating circuit as an input digital signal, modulating the digital signal to obtain a pulse signal with a corresponding duty ratio, and controlling the switching state of a power switch tube in the power stage circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410711083.9A CN118282369B (en) | 2024-06-03 | 2024-06-03 | High-precision digital pulse modulator and switch converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410711083.9A CN118282369B (en) | 2024-06-03 | 2024-06-03 | High-precision digital pulse modulator and switch converter |
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