CN118264223A - Digital filter circuit and digital filter - Google Patents

Abstract

The present invention discloses a digital filter circuit and a digital filter, which relate to the technical field of integrated circuits. The digital filter circuit includes a first input circuit, which includes: a first variable resistor, one end of which inputs a first electrical signal; a first switch, the input end of which is connected to the other end of the first variable resistor, the output end of which serves as the output end of the first input circuit, and the output end of which outputs the filtered first electrical signal. The present application can directly process analog signals, improve computing power, and reduce delay.

Description

A digital filter circuit and a digital filter

Technical Field

The present invention relates to the technical field of integrated circuits, and in particular to a digital filtering circuit and a digital filter.

Background technique

Traditional filter designs are divided into analog filters and digital filters based on the signals they process. Analog filters are mainly built using components such as resistors, capacitors, and inductors. When the parameters of the filter change, the original components need to be replaced, which is very troublesome. Digital filters process discrete-time signals and can be implemented through software. Compared with analog filters, they have the advantages of easy parameter modification, high accuracy, and good reliability.

However, classic digital signal processing still has limitations. First, the received analog signal must be converted from digital to analog, which limits the speed of the signal processing system. At the same time, quantization errors are difficult to avoid during the conversion process, which affects the accuracy of the signal processing system. Secondly, in actual digital signal processing systems, it is often the case that parameter changes cannot be completed by sending signals to the system, and part of the system needs to be removed, reprogrammed, and then reinstalled.

Summary of the invention

The purpose of the present invention is to provide a digital filtering circuit and a digital filter, which can directly process analog signals, improve computing power and reduce delay.

In order to solve the above technical problems, the present invention adopts the following technical solutions:

A first aspect of an embodiment of the present invention provides a digital filter circuit, which includes a first input circuit, wherein the first input circuit includes: a first variable resistor, one end of which inputs a first electrical signal; a first switch, the input end of the first switch is connected to the other end of the first variable resistor, the output end of the first switch serves as the output end of the first input circuit, and the output end of the first switch outputs the filtered first electrical signal.

In some embodiments, the digital filter circuit further includes a second input circuit, and an output end of the first input circuit and an output end of the second input circuit are connected to each other and serve as an output end of the digital filter circuit.

In some embodiments, the second input circuit includes a second switch and a second variable resistor, one end of the second variable resistor inputs the second electrical signal, the input end of the second switch is connected to the other end of the second variable resistor, the output end of the second switch serves as the output end of the second input circuit, and the output end of the second switch outputs the filtered second electrical signal.

In some embodiments, both the first switch and the second switch are NMOS transistors.

In some embodiments, the first input circuit has a positive conductance and the second input circuit has a negative conductance.

In some embodiments, both the first variable resistor and the second variable resistor are memristors.

In some embodiments, the difference between the first variable resistor and the second variable resistor is a filter coefficient.

In some embodiments, one end of the first variable resistor and the second variable resistor are both connected to a first decoder, and the first decoder outputs a first electrical signal and a second electrical signal to the first variable resistor and the second variable resistor, respectively.

In some embodiments, the control ends of the first switch and the second switch are both connected to a second decoder, and the second decoder outputs a first control signal and a second control signal to the control ends of the first switch and the second switch, respectively.

A first aspect of an embodiment of the present invention provides a digital filter, wherein the digital filter comprises at least two digital filter circuits as described above, and output ends of each of the digital filter circuits are connected to each other.

A digital filtering circuit and a digital filter according to an embodiment of the present invention have at least the following beneficial effects: the present application can be used for processing EEG signals, can directly process input analog signals, and parallel computing in the form of a crosspoint array is also feasible. The present application uses a memristor RRAM array for parallel computing, which can greatly improve computing power and reduce latency.

It is to be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

FIG. 1 is a circuit diagram of a digital filter according to an embodiment.

Detailed ways

The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

The terms "first", "second", and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", and "third" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these example embodiments are provided so that the description of the present disclosure will be more comprehensive and complete and the concepts of the example embodiments will be fully conveyed to those skilled in the art. The accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

The technical solution of the embodiment of the present application is briefly described below:

According to some embodiments, as shown in FIG. 1 , the present application provides a digital filtering circuit, wherein the digital filtering circuit 10 includes a first input circuit 1, and the first input circuit 1 includes:

A first variable resistor R1, one end of which is input with a first electrical signal BL _UP 0;

The first switch Q1 has an input end connected to the other end of the first variable resistor R1 , an output end of the first switch Q1 serves as an output end of the first input circuit 1 , and the output end of the first switch Q1 outputs a filtered first electrical signal BL _UP 0 .

The preferred embodiment of the present disclosure is further described in detail below in conjunction with FIG1 of the present specification.

According to some embodiments, the digital filter circuit 10 further includes a second input circuit 2 , and an output end of the first input circuit 1 and an output end of the second input circuit 2 are connected to each other and serve as an output end of the digital filter circuit 10 .

Based on the above embodiment, as shown in FIG. 1 , the output end of the first input circuit 1 and the output end of the second input circuit 2 are connected to each other, and the output end of the first input circuit 1 and the output end of the second input circuit 2 both serve as the output end of the digital filter circuit 10 .

Further, the second input circuit 2 includes a second switch Q2 and a second variable resistor R2, one end of the second variable resistor R2 inputs the second electrical signal BL _dn 0, the input end of the second switch Q2 is connected to the other end of the second variable resistor R2, the output end of the second switch Q2 serves as the output end of the second input circuit 2, and the output end of the second switch Q2 outputs the filtered second electrical signal BL _dn 0.

Based on the above embodiment, the filtered second electrical signal BL _dn 0 and the filtered first electrical signal BL _UP 0 are combined to generate the output signal of the digital filter circuit 10 .

According to some embodiments, both the first switch Q1 and the second switch Q2 are NMOS transistors.

According to some embodiments, the first input circuit 1 is used as a positive conductance, and the second input circuit 2 is used as a negative conductance.

According to some embodiments, both the first variable resistor R1 and the second variable resistor R2 are memristors RRAM.

Based on the above embodiments, memristor RRAM has great potential in filter design. Replacing resistors in basic analog filter circuits can make the filter produce new characteristics. Various analog filters based on memristor RRAM designed according to the properties of memristor RRAM have adaptive or programmable characteristics. The core idea is to change the characteristics of the filter by changing the resistance value of the memristor RRAM.

According to some embodiments, a difference between the first variable resistor R1 and the second variable resistor R2 is a filter coefficient.

According to some embodiments, one end of the first variable resistor R1 and the second variable resistor R2 are both connected to a first decoder, and the first decoder outputs a first electrical signal BL _UP 0 and a second electrical signal BL _dn 0 to the first variable resistor R1 and the second variable resistor R2 , respectively.

Based on the above embodiment, as shown in Fig. 1, one end of the first variable resistor R1 and one end of the second variable resistor R2 are both connected to the BL decoder, or one end of the first variable resistor R1 and one end of the second variable resistor R2 are both connected to the SL decoder. The BL decoder or the SL decoder uses the first input circuit 1 as a positive conductance and the second input circuit 2 as a negative conductance.

According to some embodiments, the control ends of the first switch Q1 and the second switch Q2 are both connected to a second decoder, and the second decoder outputs a first control signal WL _UP 0 and a second control signal WL _dn 0 to the control ends of the first switch Q1 and the second switch Q2, respectively.

Based on the above embodiment, as shown in FIG1 , the control end of the first switch Q1 and the control end of the second switch Q2 are both connected to the WL decoder, so that the WL decoder controls the first switch Q1 and the second switch Q2 to turn on or off.

According to some embodiments, as shown in FIG. 1 , the present application provides a digital filter, wherein the digital filter 100 includes at least two digital filter circuits 10 as described above, and the output ends of each of the digital filter circuits 10 are connected to each other.

The digital filter 100 can be mathematically represented as:

Where x represents the input signal. k and K are the filter coefficient index and filter order, respectively. n is the index of the time step. h represents the impulse response of the filter, whose mode determines the characteristics of the filter. y represents the filtered signal.

To implement the filter bank in a memristor RRAM array, the above formula is rewritten as follows:

_yn ＝ _xnH

Where _xn and _yn are the input and output signal row vectors in the nth time step, respectively. The matrix H represents the filter coefficients, which are represented by the device conductance in the memristor RRAM array for hardware implementation. The filter coefficients can have positive and negative values; to address this issue, we set two 1T1Rs for one weight, one for positive conductance and the other for negative conductance. The conductance values of the two 1T1Rs are denoted as Sp and Sn, respectively. In this way, the implementation of the filter in the memristor RRAM array can be expressed as:

Where V is the input voltage vector, (Sp(k)-Sn(k)) represents the mapping element of the kth row of the filter coefficient matrix H. I is the output current vector of the filter.

For the 1T1R differential topology, the upper part represents Sp and the lower part represents Sn. When WLup and WLdn are both high, the two transistors are turned on at the same time. BLup and BLdn are added with the voltage values Vsl+Vi and Vsl-Vi, respectively, and the current value flowing to SL is Vi/R1-Vi/R2 by changing the positive and negative 1T1R conductance. The coefficients of the designed filter are first mapped onto the memristor RRAM array as device conductance values. We set the filter order to n. Therefore, 2(n+1) memristor RRAM devices are used to represent a filter with (n+1) coefficients. The analog voltage signal is then applied to the memristor RRAM array. The sum of the output currents is the filtering result of the filter at each time step.

The present application can be used for processing EEG signals, can directly process input analog signals, and parallel computing in the form of a crosspoint array is also feasible. The present application uses a memristor RRAM array for parallel computing, which can greatly improve computing power and reduce latency.

In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

Although the present disclosure has been described with reference to several typical embodiments, it should be understood that the terms used are illustrative and exemplary, rather than restrictive. Since the present disclosure can be implemented in a variety of forms without departing from the spirit or essence of the present application, it should be understood that the above-mentioned embodiments are not limited to any of the foregoing details, but should be widely interpreted within the spirit and scope defined by the appended claims, so all changes and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims (10)

1. A digital filter circuit, characterized in that the digital filter circuit comprises a first input circuit, wherein the first input circuit comprises: a first variable resistor, a first electrical signal being input into one end of the first variable resistor; A first switch, wherein an input end of the first switch is connected to the other end of the first variable resistor, an output end of the first switch serves as an output end of the first input circuit, and the output end of the first switch outputs a filtered first electrical signal. 2. The digital filter circuit according to claim 1 is characterized in that the digital filter circuit also includes a second input circuit, and the output end of the first input circuit and the output end of the second input circuit are connected to each other and serve as the output end of the digital filter circuit. 3. The digital filter circuit according to claim 2 is characterized in that the second input circuit includes a second switch and a second variable resistor, one end of the second variable resistor inputs the second electrical signal, the input end of the second switch is connected to the other end of the second variable resistor, the output end of the second switch serves as the output end of the second input circuit, and the output end of the second switch outputs the filtered second electrical signal. 4 . The digital filter circuit according to claim 3 , wherein both the first switch and the second switch are NMOS tubes. 5 . The digital filter circuit according to claim 3 , wherein the first input circuit has positive conductance and the second input circuit has negative conductance. 6 . The digital filter circuit according to claim 3 , wherein the first variable resistor and the second variable resistor are both memristors. 7 . The digital filter circuit according to claim 3 , wherein a difference between the first variable resistor and the second variable resistor is a filter coefficient. 8. The digital filter circuit according to claim 3 is characterized in that one end of the first variable resistor and one end of the second variable resistor are both connected to a first decoder, and the first decoder outputs a first electrical signal and a second electrical signal to the first variable resistor and the second variable resistor respectively. 9. The digital filter circuit according to claim 8, characterized in that the control ends of the first switch and the second switch are both connected to a second decoder, and the second decoder outputs a first control signal and a second control signal to the control ends of the first switch and the second switch respectively. 10. A digital filter, characterized in that the digital filter comprises at least two digital filter circuits according to any one of claims 2 to 9, and the output ends of each of the digital filter circuits are connected to each other.