CN118251002A - Manufacturing method of split gate flash memory - Google Patents
Manufacturing method of split gate flash memory Download PDFInfo
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- CN118251002A CN118251002A CN202410182296.7A CN202410182296A CN118251002A CN 118251002 A CN118251002 A CN 118251002A CN 202410182296 A CN202410182296 A CN 202410182296A CN 118251002 A CN118251002 A CN 118251002A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 94
- 229920005591 polysilicon Polymers 0.000 claims abstract description 91
- 238000005530 etching Methods 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 150000004767 nitrides Chemical class 0.000 claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 11
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 11
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 37
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 230000009286 beneficial effect Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 7
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910001260 Pt alloy Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000009740 moulding (composite fabrication) Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- PCLURTMBFDTLSK-UHFFFAOYSA-N nickel platinum Chemical compound [Ni].[Pt] PCLURTMBFDTLSK-UHFFFAOYSA-N 0.000 description 1
- 229910052755 nonmetal Inorganic materials 0.000 description 1
- 150000002843 nonmetals Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- VCZQFJFZMMALHB-UHFFFAOYSA-N tetraethylsilane Chemical compound CC[Si](CC)(CC)CC VCZQFJFZMMALHB-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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Abstract
The invention provides a manufacturing method of a split gate flash memory, which comprises the steps of providing a substrate, and forming a gate oxide layer, a floating gate polycrystalline silicon layer and a hard mask layer which are sequentially stacked from bottom to top on the substrate; patterning the hard mask layer to define the opening size of the floating gate polysilicon layer, and then forming an ONO layer on the hard mask layer and the floating gate polysilicon layer, wherein the ONO layer consists of a first oxide layer, a nitride layer and a second oxide layer which are stacked in sequence from bottom to top; forming an erasing gate polysilicon layer on the ONO layer, forming a first side wall positioned on the erasing gate polysilicon layer at the opening, and etching the erasing gate polysilicon layer by taking the first side wall as a mask, so that the erasing gate polysilicon layer and the second oxide layer outside the first side wall are removed, and the removed erasing gate polysilicon layer and the nitride layer below the second oxide layer are exposed; and forming metal silicide on the needed erasing gate polysilicon layer. The control gate polysilicon layer is directly connected through the metal silicide, which is beneficial to reducing resistance-capacitance delay.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a split gate flash memory.
Background
In the split gate flash memory in the prior art, the control gate is formed before the deposition of the floating gate silicon nitride, and the control gate in the memory cell is difficult to connect.
In the prior art, LVT CELL (low threshold voltage memory CELL), the voltage on the floating gate is obtained by coupling Source line junction (source line junction) with the overlapped part of the floating gate during programming, so that in order to ensure the programming efficiency, the floating gate needs to be ensured to be long enough.
In order to solve the above-mentioned problems, a new method for manufacturing a split gate flash memory is needed.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for manufacturing a split-gate flash memory, which is used for solving the problem that the control gate in the memory cell is difficult to be connected out and the size of the memory cell needs to be reduced in the prior art.
To achieve the above and other related objects, the present invention provides a method for manufacturing a split gate flash memory, comprising:
step one, providing a substrate, and forming a gate oxide layer, a floating gate polycrystalline silicon layer and a hard mask layer which are stacked in sequence from bottom to top on the substrate;
patterning the hard mask layer to define the opening size of the floating gate polysilicon layer, and then forming an ONO layer on the hard mask layer and the floating gate polysilicon layer, wherein the ONO layer consists of a first oxide layer, a nitride layer and a second oxide layer which are stacked in sequence from bottom to top;
Forming an erasing gate polysilicon layer on the ONO layer, forming a first side wall positioned on the erasing gate polysilicon layer at the opening, and etching the erasing gate polysilicon layer by taking the first side wall as a mask, so that the erasing gate polysilicon layer and the second oxide layer except the first side wall are removed, and the removed nitride layers below the erasing gate polysilicon layer and the second oxide layer are exposed;
Forming metal silicide on the erasure gate polysilicon layer exposed between the first side wall and the second oxide layer;
Step five, etching to remove the exposed nitride layer, so that the first oxide layer and the floating gate polysilicon layer below the nitride layer are exposed, and removing the exposed first oxide layer on the opening;
Forming a second side wall on the exposed floating gate polysilicon, wherein the top of the second side wall extends to the first side wall, and then etching the exposed floating gate polysilicon layer and the gate oxide layer below the exposed floating gate polysilicon layer by taking the second side wall as a mask so as to expose the substrate below the exposed floating gate polysilicon layer and form a Vss end on the exposed substrate by utilizing ion implantation;
step seven, forming a third side wall on the exposed substrate, wherein the top of the third side wall extends to the second side wall;
step eight, forming a select gate polysilicon layer filling the trench and a select gate oxide layer located on the select gate polysilicon layer;
step nine, removing the hard mask layer and the first oxide layer on the hard mask layer to expose the floating gate polysilicon layer below the hard mask layer, and etching to remove the exposed floating gate polysilicon layer to form a laminated structure;
And step ten, forming a fourth side wall on the side wall of the laminated structure, then forming word line polysilicon on the fourth side wall by deposition and etching, and forming doped regions on two sides of the word line polysilicon by ion implantation.
Preferably, the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.
Preferably, the material of the hard mask layer in the first step is silicon nitride.
Preferably, the etching method in the third step is dry etching.
Preferably, in the third step, the material of the first side wall is silicon dioxide.
Preferably, the etching method in the fifth step is wet etching.
Preferably, in the sixth step, the material of the second sidewall is silicon dioxide.
Preferably, the etching method in the step six is dry etching.
Preferably, in the seventh step, the material of the third sidewall is silicon dioxide.
Preferably, in step nine, the hard mask layer and the first oxide layer thereon are removed by using a wet etching method.
Preferably, the etching method in the step nine is dry etching.
Preferably, in the step ten, the material of the fourth side wall is silicon dioxide.
As described above, the manufacturing method of split gate flash memory of the present invention has the following advantages:
Compared with LVT cells (low threshold voltage memory cells), the invention adds an erase gate polysilicon layer (EG, ERASE GATE) on the floating gate polysilicon layer. The erasure of electrons in the floating gate is realized by high voltage (for example, 12V) on the erasure gate polysilicon layer; the introduction of the erasing gate polysilicon layer in the cell structure can make up for the coupling of Source linejunction (source line junction) to the floating gate, greatly reduce the length of the floating gate polysilicon layer and greatly reduce the cell structure area; the control gate polysilicon layer is directly connected through the metal silicide, which is beneficial to reducing resistance capacitance delay.
Drawings
FIG. 1 is a schematic illustration of the process flow of the present invention;
FIG. 2 is a schematic diagram showing the formation of a gate oxide layer, a floating gate polysilicon layer and a hard mask layer stacked in sequence from bottom to top in accordance with the present invention;
FIG. 3 is a schematic diagram showing the patterning of a hard mask layer to define the opening size of a floating gate polysilicon layer according to the present invention;
FIG. 4 is a schematic diagram of forming an ONO layer according to the invention;
FIG. 5 is a schematic diagram of an erase gate polysilicon layer formed over an ONO layer in accordance with the invention;
FIG. 6 is a schematic view of forming a first side wall according to the present invention;
FIG. 7 is a schematic diagram of the first sidewall mask etching according to the present invention;
FIG. 8 is a schematic diagram of the formation of metal silicide in accordance with the present invention;
FIG. 9 is a schematic diagram of the etching to remove exposed nitride layer according to the present invention;
FIG. 10 is a schematic view of forming a second sidewall according to the present invention;
FIG. 11 is a schematic view of the formation of VSS in accordance with the present invention;
FIG. 12 is a schematic view showing the formation of a third sidewall according to the present invention;
FIG. 13 is a schematic view showing the formation of a select gate polysilicon layer and a select gate oxide layer according to the present invention
FIG. 14 is a schematic diagram of a hard mask layer removal process according to the present invention;
FIG. 15 is a schematic view of the removal of exposed floating gate polysilicon layer of the present invention;
FIG. 16 is a schematic view showing the formation of a fourth sidewall according to the present invention;
FIG. 17 is a schematic diagram of polysilicon forming deposited word lines in accordance with the present invention;
FIG. 18 is a schematic diagram of etched word line polysilicon according to the present invention;
fig. 19 is a schematic view showing the formation of doped regions according to the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Referring to fig. 1, the present invention provides a method for manufacturing a split gate flash memory, which includes:
Step one, providing a substrate 100, and forming a gate oxide layer 101, a floating gate polysilicon layer 102 and a hard mask layer 103 which are sequentially stacked from bottom to top on the substrate 100 to form a structure shown in fig. 2;
In some embodiments, the substrate 100 in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer under a thin semiconductor layer that is an active layer of the SOI substrate. The semiconductor and bulk semiconductor of the active layer typically comprise crystalline semiconductor material silicon, but may also comprise one or more other semiconductor materials such as germanium, silicon germanium alloys, compound semiconductors (e.g., gaAs, alAs, inAs, gaN, alN, etc.) or alloys thereof (e.g., gaxAl1-xAs, gaxAl1-xN, inxGa1-xAs, etc.), oxide semiconductors (e.g., znO, snO2, tiO2, ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.
In some embodiments, the material of the hard mask layer 103 in the first step is silicon nitride.
Patterning the hard mask layer 103 to define the opening size of the floating gate polysilicon layer 102, and forming a structure shown in fig. 3, namely forming a photoresist layer on the hard mask layer 103, photoetching the photoresist layer to define the opening size of the floating gate polysilicon layer 102, forming an opening on the hard mask layer 103 by etching, removing the photoresist layer by ashing process, wet cleaning and other methods, and then forming an ONO layer on the hard mask layer 103 and the floating gate polysilicon layer 102 to form a structure shown in fig. 4, wherein the ONO layer is composed of a first oxide layer 104, a nitride layer 105 and a second oxide layer 106 which are sequentially stacked from bottom to top;
Step three, forming an erase gate polysilicon layer 107 on the ONO layer, forming a structure as shown in fig. 5, forming a first side wall 108 positioned on the erase gate polysilicon layer 107 at the opening, forming a structure as shown in fig. 6, etching the erase gate polysilicon layer 107 by taking the first side wall 108 as a mask, removing the erase gate polysilicon layer 107 and the second oxide layer 106 except the first side wall 108, exposing the removed erase gate polysilicon layer 107 and the nitride layer 105 below the second oxide layer 106, and forming a structure as shown in fig. 7;
in some embodiments, the method of etching in step three is dry etching.
In some embodiments, the material of the first sidewall 108 in step three is silicon dioxide. The first sidewall 108 may be formed by deposition, etching back.
Step four, forming a metal silicide 109 on the exposed erasing gate polysilicon layer 107 between the first side wall 108 and the second oxide layer 106 to form a structure shown in fig. 8;
To obtain high-resistance active region resistance, high-resistance polysilicon resistance, and high-performance ESD devices, it is desirable to form regions of higher-resistance Non-metal silicide 109, which are commonly referred to as Non-Salicide regions, and those devices not forming metal silicide 109 are referred to as Non-Salicide devices. To form a Non-Salicide device, it is desirable to use the feature that the metal only reacts with the polysilicon and active region silicon, but not with the dielectric layer, and the material of the metal may be cobalt, titanium, nickel or nickel-platinum alloy. A dielectric layer is deposited to cover the Non-Salicide regions before the Salicide process flow is performed to prevent the Salicide from forming in these regions, a technique called Self-Aligned Block-SAB (Self-Aligned Block-SAB) for forming Non-Salicide devices, and may also be called resistive protection oxide (Resist Protection Oxide-RPO). The material of the SAB film includes silicon-rich oxide SRO (Silicon Rich Oxide), siO2, siON, and Si3N4. Wherein the silicon content of the SRO film is larger than that of the conventional silicon oxide film, the SRO is prepared in the same way as the conventional silicon oxide film, and the SRO film can be deposited by PECVD, and the gas sources are SiH4, O2 and Ar. Wherein the ratio of SiH4 to O2 is set to be higher than that used for forming conventional silicon oxide, si2H6 and TEOS (tetraethylsilane) may be used instead of SiH4, or N2O or O3 may be used instead of O2. SiON depositing gas sources are SiH4, N2O and Ar, and Si3N4 depositing gas sources are SiH4, N3H and Ar.
Step five, etching to remove the exposed nitride layer 105, so that the first oxide layer 104 and the floating gate polysilicon layer 102 below the exposed nitride layer are exposed, and removing the exposed first oxide layer 104 on the opening to form the structure shown in fig. 9;
in some embodiments, the method of etching in step five is wet etching.
Step six, forming a second side wall 110 on the exposed floating gate polysilicon, wherein the top of the second side wall 110 extends to the first side wall 108 to form a structure shown in fig. 10, and then etching to remove the exposed floating gate polysilicon layer 102 and the gate oxide layer 101 below the exposed floating gate polysilicon layer by using the second side wall 110 as a mask, so that the substrate 100 below the exposed floating gate polysilicon layer is exposed, and forming a VSS111 end on the exposed substrate 100 by utilizing ion implantation to form the structure shown in fig. 11;
In some embodiments, the material of the second sidewall 110 in the sixth step is silicon dioxide.
In some embodiments, the method of etching in step six is dry etching.
Step seven, forming a third side wall 112 on the exposed substrate 100, wherein the top of the third side wall 112 extends to the second side wall 110 to form a structure as shown in fig. 12;
in some embodiments, the material of the third sidewall 112 in the seventh step is silicon dioxide.
Step eight, forming a select gate polysilicon layer 113 filling the trench and a select gate oxide layer 114 on the select gate polysilicon layer 113, forming the structure shown in fig. 13;
Step nine, removing the hard mask layer 103 and the first oxide layer 104 thereon to expose the floating gate polysilicon layer 102 below the hard mask layer to form a structure shown in fig. 14, and etching to remove the exposed floating gate polysilicon layer 102 to form a laminated structure to form a structure shown in fig. 15;
in some embodiments, the hard mask layer 103 and the first oxide layer 104 thereon are removed in step nine by a wet etching method.
In some embodiments, the method of etching in step nine is dry etching.
Step ten, forming a fourth side wall 115 on the side wall of the laminated structure to form a structure shown in fig. 16, then forming a word line polysilicon 116 on the fourth side wall 115 by deposition and etching, sequentially forming the structures shown in fig. 17 and 18, and forming doped regions 117 on two sides of the word line polysilicon 116 by ion implantation to form the structure shown in fig. 19.
In some embodiments, the material of the fourth sidewall 115 in step ten is silicon dioxide.
An erase gate poly layer 107 (EG, ERASE GATE) is added over the floating gate poly layer 102 as compared to LVT cells (low threshold voltage memory cells). The erasure of electrons inside the floating gate is achieved by applying a high voltage (e.g., 12V) to the erase gate polysilicon layer 107.
The introduction of the erasing gate polysilicon layer 107 in the cell structure can make up for the coupling of Source linejunction (source line junction) to the floating gate, greatly reduce the length of the floating gate polysilicon layer 102, and greatly reduce the cell structure area.
Compared with the prior art, the control gate polysilicon layer is directly connected out through the metal silicide 109, which is beneficial to reducing resistance capacitance delay.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In summary, compared with LVT cells (low threshold voltage memory cells), the present invention adds an erase gate poly layer (EG, ERASE GATE) over the floating gate poly layer. The erasure of electrons in the floating gate is realized by high voltage (for example, 12V) on the erasure gate polysilicon layer; the introduction of the erasing gate polysilicon layer in the cell structure can make up for the coupling of Source linejunction (source line junction) to the floating gate, greatly reduce the length of the floating gate polysilicon layer and greatly reduce the cell structure area; the control gate polysilicon layer is directly connected through the metal silicide, which is beneficial to reducing resistance capacitance delay. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (12)
1. A method for manufacturing a split gate flash memory, comprising:
step one, providing a substrate, and forming a gate oxide layer, a floating gate polycrystalline silicon layer and a hard mask layer which are stacked in sequence from bottom to top on the substrate;
patterning the hard mask layer to define the opening size of the floating gate polysilicon layer, and then forming an ONO layer on the hard mask layer and the floating gate polysilicon layer, wherein the ONO layer consists of a first oxide layer, a nitride layer and a second oxide layer which are stacked in sequence from bottom to top;
Forming an erasing gate polysilicon layer on the ONO layer, forming a first side wall positioned on the erasing gate polysilicon layer at the opening, and etching the erasing gate polysilicon layer by taking the first side wall as a mask, so that the erasing gate polysilicon layer and the second oxide layer except the first side wall are removed, and the removed nitride layers below the erasing gate polysilicon layer and the second oxide layer are exposed;
Forming metal silicide on the erasure gate polysilicon layer exposed between the first side wall and the second oxide layer;
Step five, etching to remove the exposed nitride layer, so that the first oxide layer and the floating gate polysilicon layer below the nitride layer are exposed, and removing the exposed first oxide layer on the opening;
Forming a second side wall on the exposed floating gate polysilicon, wherein the top of the second side wall extends to the first side wall, and then etching the exposed floating gate polysilicon layer and the gate oxide layer below the exposed floating gate polysilicon layer by taking the second side wall as a mask so as to expose the substrate below the exposed floating gate polysilicon layer and form a Vss end on the exposed substrate by utilizing ion implantation;
step seven, forming a third side wall on the exposed substrate, wherein the top of the third side wall extends to the second side wall;
step eight, forming a select gate polysilicon layer filling the trench and a select gate oxide layer located on the select gate polysilicon layer;
step nine, removing the hard mask layer and the first oxide layer on the hard mask layer to expose the floating gate polysilicon layer below the hard mask layer, and etching to remove the exposed floating gate polysilicon layer to form a laminated structure;
And step ten, forming a fourth side wall on the side wall of the laminated structure, then forming word line polysilicon on the fourth side wall by deposition and etching, and forming doped regions on two sides of the word line polysilicon by ion implantation.
2. The method for manufacturing the split-gate flash memory according to claim 1, wherein: the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.
3. The method for manufacturing the split-gate flash memory according to claim 1, wherein: the material of the hard mask layer in the first step is silicon nitride.
4. The method for manufacturing the split-gate flash memory according to claim 1, wherein: and step three, the etching method is dry etching.
5. The method for manufacturing the split-gate flash memory according to claim 1, wherein: and in the third step, the material of the first side wall is silicon dioxide.
6. The method for manufacturing the split-gate flash memory according to claim 1, wherein: and step five, the etching method is wet etching.
7. The method for manufacturing the split-gate flash memory according to claim 1, wherein: and step six, the material of the second side wall is silicon dioxide.
8. The method for manufacturing the split-gate flash memory according to claim 1, wherein: and step six, the etching method is dry etching.
9. The method for manufacturing the split-gate flash memory according to claim 1, wherein: and in the seventh step, the material of the third side wall is silicon dioxide.
10. The method for manufacturing the split-gate flash memory according to claim 1, wherein: and step nine, removing the hard mask layer and the first oxide layer thereon by using a wet etching method.
11. The method for manufacturing the split-gate flash memory according to claim 1, wherein: the etching method in the step nine is dry etching.
12. The method for manufacturing the split-gate flash memory according to claim 1, wherein: and in the step ten, the material of the fourth side wall is silicon dioxide.
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