CN118249797B - Capacitor bias diode circuit with voltage stabilizing charge pump and reference voltage generating circuit - Google Patents
Capacitor bias diode circuit with voltage stabilizing charge pump and reference voltage generating circuit Download PDFInfo
- Publication number
- CN118249797B CN118249797B CN202410685120.3A CN202410685120A CN118249797B CN 118249797 B CN118249797 B CN 118249797B CN 202410685120 A CN202410685120 A CN 202410685120A CN 118249797 B CN118249797 B CN 118249797B
- Authority
- CN
- China
- Prior art keywords
- circuit
- diode
- capacitor
- branch
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/74—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of diodes
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
The invention discloses a capacitor bias diode circuit with a voltage stabilizing charge pump and a reference voltage generating circuit, and belongs to the technical field of integrated circuit design. The capacitor bias diode circuit with the voltage stabilizing charge pump comprises a charge pump circuit and a capacitor bias diode circuit, wherein one end of the charge pump circuit is connected with an input voltage, the other end of the charge pump circuit is connected with the capacitor bias diode circuit, and the input voltage is lower than 1V; the capacitor bias diode circuit comprises a capacitor branch and a diode branch, the charge pump circuit is used for increasing the input voltage to a charging voltage, the charging voltage is used for charging the capacitor branch, the capacitor branch discharges through the diode branch, and the diode branch generates an output voltage. The capacitor bias diode circuit can greatly reduce external power supply voltage, has a simple structure, and the charge pump circuit is additionally provided with the voltage stabilizing circuit, so that the generated charging voltage is further ensured to be irrelevant to the external power supply voltage, and the robustness of the capacitor bias diode to the external power supply voltage fluctuation is improved.
Description
Technical Field
The invention belongs to the technical field of integrated circuit design, and particularly relates to a capacitor bias diode circuit with a voltage stabilizing charge pump and a reference voltage generating circuit.
Background
As integrated circuit processes develop, standard digital power supply for advanced CMOS (Complementary Metal Oxide Semiconductor ) process nodes is reduced, e.g., 180nm nanometer standard power supply is 1.8V, while 22nm standard power supply is 0.9V. Considering a voltage fluctuation of + -10%, at least 0.8V supply is required for the circuit to be compatible with a 22nm CMOS process. The low voltage presents great difficulties for analog circuit design, particularly for analog modules used in conjunction with digital circuits, such as temperature sensors used to detect temperature changes in digital circuits. These analog modules require the same supply voltage to be compatible with digital circuits to reduce design costs. Conventional analog circuit structures have failed to accommodate the low voltage requirements of advanced process nodes.
Disclosure of Invention
The invention aims to: the invention aims to solve the technical problem of providing a capacitor bias diode circuit with a voltage stabilizing charge pump and a reference voltage generating circuit aiming at the defects of the prior art.
In order to solve the technical problems, in a first aspect, a capacitor bias diode circuit with a voltage stabilizing charge pump is disclosed, which comprises a charge pump circuit and a capacitor bias diode circuit, wherein one end of the charge pump circuit is connected with an input voltage, and the other end of the charge pump circuit is connected with the capacitor bias diode circuit, and the input voltage is lower than 1V; the capacitor bias diode circuit comprises a capacitor branch and a diode branch, the charge pump circuit is used for increasing the input voltage to a charging voltage, the charging voltage is used for charging the capacitor branch, the capacitor branch discharges through the diode branch, and the diode branch generates an output voltage.
Further, the charge pump circuit comprises a first NMOS tube, a second NMOS tube, a first capacitor, a second capacitor, a first node and a second node, wherein the first node is connected with the first capacitor and is used for receiving an inverted signal of an input signal, and the input signal is a square wave signal from 0 to the input voltage; the second node is connected with a second capacitor and is used for receiving the input signal; the first NMOS tube and the second NMOS tube are connected in a cross coupling configuration, the first NMOS tube is coupled between the input voltage and a first node, and the second NMOS tube is coupled between the input voltage and a second node; the second node is connected to the capacitance bias diode circuit. Even if the input voltage of the charge pump is smaller than 1V, the actual charging voltage on the capacitor branch can be boosted after the structure is adopted, and the implementation mode is concise.
Further, the charge pump circuit further comprises a voltage stabilizing circuit, wherein the voltage stabilizing circuit is used for stabilizing charging voltage, is connected with the capacitor bias diode circuit in parallel and is also connected with an inverse signal of the input signal. The voltage stabilizing circuit is added to further ensure that the generated charging voltage is irrelevant to the external power supply voltage, so that the robustness of the capacitor bias diode to the external power supply voltage fluctuation is improved.
Further, the voltage stabilizing circuit comprises a switch circuit and a diode load circuit, wherein the switch circuit is connected with an inverted signal of the input signal and is coupled between the second node and the diode load circuit. When the input signal is high, the initial value of the voltage at the second node is higher than the input voltage, the switch circuit is conducted, charges on the second capacitor and the capacitor branch are discharged through the diode load circuit, so that the whole voltage at the second node is reduced and is irrelevant to the input voltage, the capacitor bias diode is ensured to leave enough discharge voltage allowance, and the robustness of the capacitor bias diode to external power supply voltage fluctuation is further improved.
Further, the diode load circuit comprises a plurality of diode loads connected in series, wherein the diode loads are diodes, triodes using diode connection or transistors using diode connection. The triode with the diode connection method can realize better diode performance, and the transistor with the diode connection method can further reduce the power supply voltage; the series connection of a plurality of diode loads can improve the signal amplitude.
Further, the capacitor branch comprises more than one capacitor connected in parallel, the diode branch comprises more than one diode connected in parallel, the capacitor bias diode circuit further comprises a first switch and a second switch, one end of the first switch is connected with a second node, the other end of the first switch is respectively connected with one end of the capacitor branch and one end of the second switch, and the other end of the capacitor branch is grounded; the other end of the second switch is connected with one end of a diode branch, and the other end of the diode branch is grounded; the control timing of the first switch is controlled by the input signal, and the control timing of the second switch is controlled by an inverted signal of the input signal. The implementation can avoid additional control time sequence circuits and reduce circuit overhead.
Further, the diode load circuit includes a third transistor and a second diode using diode connection, the third transistor being coupled between the switching circuit and the second diode, one end of the second diode being grounded. When the input signal is high, the initial value of the voltage at the second node is higher than the input voltage, the switch circuit is turned on, the charges on the second capacitor and the capacitor branch are discharged through the diode load circuit, so that the overall voltage at the second node is reduced to V BE+VGS, wherein V BE represents the voltage between the emitter and the base of the second diode, and V GS represents the gate-source voltage difference of the third transistor; at this time, V BE+VGS is independent of the input voltage, and it is ensured that the capacitor bias diode has enough discharge voltage margin V GS, so that the robustness of the capacitor bias diode to external power supply voltage fluctuation is further improved.
Further, the switching circuit is a fourth transistor coupled between the second node and the third transistor, and a gate is connected to an inverted signal of the input signal.
Further, the charge pump circuit further comprises a first inverter and a second inverter, wherein the input end of the first inverter is connected with the input signal, and the output end of the first inverter is respectively connected with the grid electrodes of the first capacitor and the fourth transistor and the input end of the second inverter; the output end of the second inverter is connected with a second capacitor.
In a second aspect, a reference voltage generating circuit is disclosed, including a V CTAT generating circuit and a V PTAT generating circuit, where the V PTAT generating circuit includes a first generating circuit and a second generating circuit, the V CTAT generating circuit, the first generating circuit and the second generating circuit are all capacitance bias diode circuits with voltage stabilizing charge pump, the V CTAT is an output voltage generated by a diode branch in the V CTAT generating circuit, and the V CTAT becomes lower as the temperature becomes higher; v PTAT is the difference between the output voltage generated by the diode branch in the first generating circuit and the output voltage generated by the diode branch in the second generating circuit, and V PTAT is increased as the temperature is increased by adjusting the diode sizes of the diode branch in the first generating circuit and the diode branch in the second generating circuit, or the capacitance sizes of the capacitance branch in the first generating circuit and the capacitance branch in the second generating circuit; the reference voltages are additive combinations of V PTAT and V CTAT, and the additive combinations of V PTAT and V CTAT make the reference voltages independent of temperature.
The beneficial effects are that: according to the capacitor bias diode circuit with the voltage stabilizing charge pump, the charge pump is added to the capacitor bias diode circuit, so that the required external power supply voltage can be greatly reduced; the proposed charge pump only needs to supply power to a single capacitor in the capacitor bias diode circuit, and has a simple structure; the charge pump added voltage stabilizing circuit can further ensure that the generated charging voltage is irrelevant to the external power supply voltage, and the robustness of the capacitor bias diode to the external power supply voltage fluctuation is improved. The reference voltage in the reference voltage generating circuit provided by the application does not change along with temperature, has high precision, and can greatly reduce the power supply requirement of a system, so that the digital circuit is compatible with the same power supply voltage, and the design cost is reduced.
Drawings
The foregoing and/or other advantages of the invention will become more apparent from the following detailed description of the invention when taken in conjunction with the accompanying drawings and detailed description.
Fig. 1 is a V BE generation circuit of a conventional diode circuit.
Fig. 2 is a conventional capacitively biased diode circuit.
Fig. 3 is a schematic diagram of a capacitor bias diode with a voltage stabilizing charge pump according to a first embodiment of the present application.
Fig. 4 is a schematic diagram of a capacitor bias diode circuit with a voltage stabilizing charge pump according to a first embodiment of the present application.
Fig. 5 is a schematic diagram of a voltage stabilizing circuit added to a capacitor bias diode circuit with a voltage stabilizing charge pump according to a first embodiment of the present application.
Fig. 6 is a schematic diagram of a reference voltage generating circuit according to a second embodiment of the present application.
Fig. 7 is a schematic diagram of a V PTAT generation circuit in a reference voltage generation circuit according to a second embodiment of the present application.
Detailed Description
Embodiments of the present invention will be described below with reference to the accompanying drawings.
The triode with diode or diode connection method is used for generating voltage signal V BE which is inversely related to temperature, is a common analog circuit module and is commonly used for constructing circuits such as an on-chip temperature sensor, a band gap reference source and the like. Conventional implementations as shown in fig. 1, this structure uses a static current source to bias the diode, and the voltage drop V BE across the diode decreases with increasing temperature. At low temperatures (e.g., -40 ℃), V BE is a relatively large value, about 800mV. Since the current source itself also requires a voltage drop of several hundred mV, the conventional structure cannot operate at low voltages below 1V.
To reduce the static voltage drop across the current source, the current source may also be replaced with a capacitor that is pre-charged to the supply voltage, and the capacitor then discharged through a diode, as shown in fig. 2. By adopting the scheme, the prior art scheme can realize 0.95V supply voltage within a wide temperature range of-55 DEG to 125 deg. But still cannot be compatible with lower supply voltages due to the limitations of the diode voltage drop itself.
As shown in fig. 3, in order to be compatible with lower voltage, a first embodiment of the present application discloses a capacitor bias diode circuit with a voltage stabilizing charge pump, which comprises a charge pump circuit and a capacitor bias diode circuit, wherein one end of the charge pump circuit is connected with an input voltage VDD, and the other end of the charge pump circuit is connected with the capacitor bias diode circuit, and the input voltage VDD is lower than 1V; the charge pump circuit is used for increasing the input voltage VDD to a charging voltage, and the charging voltage takes the value range of VDD to VDDH, and VDDH is more than VDD; the charging voltage is used for charging the capacitor branch, the capacitor branch discharges through the diode branch, and the diode branch generates an output voltage V BE. The input voltage VDD can be raised to a higher voltage by an additional charge pump circuit for capacitor leg charging. Because only the capacitor branch components of higher voltage are needed by the capacitor bias diode structure, the load of the charge pump is very compact. Compared with the traditional structure of fig. 1, the charge pump does not need to continuously work all the time, and the implementation is more convenient.
The charge pump circuit comprises a first NMOS tube M N1, a second NMOS tube M N2, a first capacitor C 1, a second capacitor C 2, a first node N and a second node A, wherein the first node N is connected with the first capacitor C 1 and is used for receiving an inverted signal of an input signal rst, and the input signal rst is a square wave signal from 0 to the input voltage VDD; the second node A is connected with a second capacitor C 2 and used for receiving the input signal rst; the first NMOS transistor M N1 and the second NMOS transistor M N2 are connected in a cross-coupled configuration, the first NMOS transistor M N1 is coupled between the input voltage VDD and the first node N, and the second NMOS transistor M N2 is coupled between the input voltage VDD and the second node a; the second node a is connected to a capacitively biased diode circuit.
The capacitor branch circuit comprises more than one capacitor connected in parallel, the diode branch circuit comprises more than one diode connected in parallel, the capacitor bias diode circuit further comprises a first switch S W1 and a second switch S W2, one end of the first switch S W1 is connected with a second node, the other end of the first switch S W1 is respectively connected with one end of the capacitor branch circuit and one end of the second switch S W2, and the other end of the capacitor branch circuit is grounded; the other end of the second switch S W2 is connected with one end of a diode branch, and the other end of the diode branch is grounded; the control timing of the first switch S W1 is controlled by the input signal, and the control timing of the second switch S W2 is controlled by the inverted signal of the input signal.
Fig. 4 is a specific implementation manner of the present embodiment: the drain electrode of the first NMOS tube M N1 is connected with the drain electrode of the second NMOS tube M N2, and both are connected to the input voltage VDD; the source electrode of the first NMOS tube M N1 is connected to the first node N and is respectively connected with the grid electrodes of the first capacitor C 1 and the second NMOS tube M N2; The source of the second NMOS transistor M N2 is connected to the second node a, and is connected to the second capacitor C 2 and the gate of the first NMOS transistor M N1, respectively. the charge pump circuit further comprises a first inverter U 1 and a second inverter U 2, wherein the input end of the first inverter U 1 is connected with the input signal rst, and the output end of the first inverter U 1 is respectively connected with the input ends of a first capacitor C 1 and the second inverter U 2; The output terminal B of the second inverter U 2 is connected to the second capacitor C 2. The capacitor branch comprises a third capacitor C 3, the diode branch comprises a first diode D 1, one end of the first switch S W1 is connected with the second node A, the other end is respectively connected with one end of the third capacitor C 3 and one end of the second switch S W2, the other end of the third capacitor C 3 is grounded; The other end of the second switch S W2 is connected with one end of a first diode D 1, and the other end of the first diode D 1 is grounded; the control timing of the first switch S W1 is controlled by the input signal rst, and the control timing of the second switch S W2 is controlled by the inverted signal of the input signal rst.
A VDD to VDDH boost circuit may be generated at the first node a. When the second capacitance C 2 is much larger than the load capacitance third capacitance C 3, VDDH is ideally 2VDD. However, considering that the third capacitor C 3 is present, VDDH is slightly lower, and the specific value is related to the voltage value and the capacitance value at the end of the period on the third capacitor C 3, if the initial voltage of the third capacitor C 3 is negligible, the actual voltage of VDDH is about:
VDDH=2VDD*C2/(C2+C3)
Therefore, even if the input voltage VDD is less than 1V, the actual charging voltage VDDH on the third capacitor C 3 can be boosted with the structure shown in fig. 4, and the implementation is simple.
Although the above structure can solve the low voltage power supply problem, the actual charging voltage VDDH of the first diode D 1 is proportional to the input voltage VDD, and when the input voltage VDD is changed, the final output voltage V BE generated by the first diode D 1 still has a small amount of follow the input voltage VDD.
In order to solve the above problem, the charge pump circuit further includes a voltage stabilizing circuit, where the voltage stabilizing circuit is used for stabilizing the charging voltage, is connected in parallel with the capacitor bias diode circuit, and is also connected with the inverse signal of the input signal rst.
The voltage stabilizing circuit comprises a switch circuit and a diode load circuit, wherein the switch circuit is connected with an inverted signal of the input signal rst and is coupled between the second node A and the diode load circuit.
The diode load circuit comprises a plurality of diode loads connected in series, wherein the diode loads are diodes, triodes using diode connection or transistors using diode connection.
The diode load circuit includes a third transistor M N3 and a second diode D 2 using diode connection, the third transistor M N3 is coupled between the switching circuit and the second diode D 2, and one end of the second diode D 2 is grounded. The third transistor M N3 may be a PMOS transistor or an NMOS transistor.
The switch circuit is a fourth transistor M P1, the fourth transistor M P1 is coupled between the second node a and the third transistor M N3, and the gate is connected to the inverted signal of the input signal rst. The fourth transistor M P1 may be a PMOS transistor or an NMOS transistor.
Fig. 5 shows a further implementation of the present embodiment, in which the fourth transistor M P1 is a PMOS transistor, the third transistor M N3 is an NMOS transistor, the gate of the fourth transistor M P1 is connected to the output terminal of the first inverter U 1, The source of the fourth transistor M P1 is connected to the second node A, and the drain is connected to the drain and the gate of the third transistor M N3, respectively; The drain and gate of the third transistor M N3 are shorted, and the source is connected to the second diode D 2. The first diode D 1 and the second diode D 2 may be identical. On the basis of fig. 4, a fourth transistor M P1 and a second diode D 2 of a switching tube and a third transistor M N3 of a diode-connected MOS tube are added, and after the three transistors are connected in series, the switching tube is connected in parallel with a capacitor bias diode circuit. When the input signal rst is high, the initial value of the voltage at the point A of the second node is VDDH, and at this time, the fourth transistor M P1 is turned on, The charge on the second capacitor C 2 and the third capacitor C 3 is discharged through the third transistor M N3 and the second diode D 2, The overall voltage at the second node a is V BE+VGS, where V BE represents the voltage between the emitter and base of the second diode D 2 and V GS represents the gate-source voltage difference of the third transistor M N3. At this time, V BE+VGS is independent of the initial input voltage VDD, and ensures that the capacitor-biased diode first diode D 1 has enough discharge voltage margin V GS, thereby further improving the robustness of the capacitor-biased diode first diode D 1 to external power supply voltage fluctuations.
A second embodiment of the present application discloses a reference voltage generating circuit, as shown in figure 6, The circuit comprises a V CTAT generating circuit (a capacitor bias diode with a voltage stabilizing charge pump V CTAT generating circuit) and a V PTAT generating circuit (a capacitor bias diode with a voltage stabilizing charge pump V PTAT generating circuit). As shown in fig. 7, the V PTAT generating circuit includes a first generating circuit 100 and a second generating circuit 200, the V CTAT generating circuit, the first generating circuit 100 and the second generating circuit 200 are all the aforementioned capacitor biased diode circuits with voltage stabilizing charge pump, V CTAT is the output voltage generated by the diode branch in the V CTAT generating circuit, V CTAT becomes lower as the temperature becomes higher; V PTAT is the difference between the output voltage generated by the diode branch in the first generating circuit and the output voltage generated by the diode branch in the second generating circuit, and V PTAT is increased as the temperature is increased by adjusting the diode sizes of the diode branch in the first generating circuit and the diode branch in the second generating circuit, or the capacitance sizes of the capacitance branch in the first generating circuit and the capacitance branch in the second generating circuit; the reference voltages are additive combinations of V PTAT and V CTAT, and the additive combinations of V PTAT and V CTAT make the reference voltages independent of temperature.
Fig. 7 is a specific implementation of the V PTAT generating circuit in this embodiment, where the capacitor bias diode circuit in the first generating circuit 100 has the same structure as the capacitor bias diode circuit shown in fig. 4, the capacitor branch of the capacitor bias diode circuit in the second generating circuit 200 includes a fourth capacitor C 4, the diode branch includes a plurality of third diodes D 3 connected in parallel, The capacitor bias diode circuit also comprises a third switch S W3 and a fourth switch S W4, one end of the third switch S W3 is connected with the charge pump circuit, the other end is respectively connected with one end of a fourth capacitor C 4 and one end of a fourth switch S W4, The other end of the fourth capacitor C 4 is grounded; the other end of the fourth switch S W4 is connected with one end of a plurality of third diodes D 3 which are connected in parallel, and the other ends of the third diodes D 3 which are connected in parallel are grounded; the control timing of the third switch S W3 is controlled by the input signal rst, and the control timing of the fourth switch S W4 is controlled by the inverted signal of the input signal rst. The first diode D 1 and the third diode D 3 may employ diodes having different areas, or the third capacitor C 3 and the fourth capacitor C 4 may employ capacitors having different sizes, The difference between the output voltage generated by the first diode D 1 and the output voltage generated by the third diodes D 3 connected in parallel in the V PTAT generating circuit can realize the voltage V PTAT with positive temperature coefficient; The reference voltages are additive combinations of V PTAT and V CTAT, V PTAT and V CTAT, such that the reference voltages are independent of temperature, Including V PTAT and V CTAT, to counteract the temperature characteristics of V PTAT and V CTAT, a temperature independent reference voltage is achieved.
The reference voltage generating circuit is an application circuit of a capacitance bias diode circuit with a voltage stabilizing charge pump, and the capacitance bias diode circuit with the voltage stabilizing charge pump can be also applied to other circuits, such as a low-voltage high-precision temperature sensor and the like.
The invention provides a capacitor bias diode circuit with a voltage stabilizing charge pump and a reference voltage generating circuit, and the method and the way for realizing the technical scheme are numerous, the above description is only a preferred embodiment of the invention, and it should be pointed out that a plurality of improvements and modifications can be made to those skilled in the art without departing from the principle of the invention, and the improvements and modifications are also regarded as the protection scope of the invention. The components not explicitly described in this embodiment can be implemented by using the prior art.
Claims (9)
1. The capacitor bias diode circuit with the voltage stabilizing charge pump is characterized by comprising a charge pump circuit and a capacitor bias diode circuit, wherein the capacitor bias diode circuit comprises a capacitor branch, a diode branch, a first switch and a second switch, one end of the charge pump circuit is connected with an input voltage, the other end of the charge pump circuit is connected with one end of the first switch, and the input voltage is lower than 1V; the other end of the first switch is connected with one end of the capacitor branch and one end of the second switch respectively, and the other end of the second switch is connected with one end of the diode branch; the control time sequence of the first switch is controlled by an input signal, the control time sequence of the second switch is controlled by an inverted signal of the input signal, and the input signal is a square wave signal; the charge pump circuit is used for increasing the input voltage to a charging voltage when the input signal is at a high level, and the charging voltage is used for charging the capacitor branch; when the input signal is in a low level, the charge pump circuit is disconnected, the capacitor branch is discharged through the diode branch, and the diode branch generates output voltage;
the charge pump circuit comprises a first NMOS tube, a second NMOS tube, a first capacitor, a second capacitor, a first node and a second node, wherein the first node is connected with the first capacitor and is used for receiving an inverted signal of an input signal, and the input signal is a square wave signal from 0 to the input voltage; the second node is connected with a second capacitor and is used for receiving the input signal; the first NMOS tube and the second NMOS tube are connected in a cross coupling configuration, the first NMOS tube is coupled between the input voltage and a first node, and the second NMOS tube is coupled between the input voltage and a second node; the second node is connected to the capacitance bias diode circuit.
2. The capacitor-biased diode circuit with a regulated charge pump of claim 1, wherein said charge pump circuit further comprises a voltage regulator circuit for stabilizing a charging voltage, in parallel with said capacitor-biased diode circuit and in signal connection with an inverse of said input signal.
3. The capacitor-biased diode circuit with a regulated charge pump of claim 2, wherein the regulated circuit includes a switching circuit and a diode load circuit, the switching circuit being coupled between the second node and the diode load circuit in conjunction with an inverted signal of the input signal.
4.A capacitance-biased diode circuit with a regulated charge pump as claimed in claim 3, wherein the diode load circuit comprises a plurality of diode loads in series, the diode loads being diodes, diode-connected transistors or diode-connected transistors.
5. The capacitor-biased diode circuit of claim 4, wherein the capacitor branch comprises more than one capacitor in parallel, the diode branch comprises more than one diode in parallel, one end of the first switch is connected with the second node, the other end of the capacitor branch is grounded, and the other end of the diode branch is grounded.
6. The capacitor-biased diode circuit of claim 5, wherein the diode-load circuit includes a third transistor and a second diode using diode-coupling, the third transistor being coupled between the switching circuit and the second diode, the second diode having an end connected to ground.
7. The capacitor-biased diode circuit of claim 6, wherein the switching circuit is a fourth transistor coupled between the second node and the third transistor, and the gate is connected to an inverse of the input signal.
8. The capacitor-biased diode circuit with the regulated charge pump of claim 7, wherein the charge pump circuit further comprises a first inverter and a second inverter, the input terminal of the first inverter is connected with the input signal, and the output terminal is respectively connected with the gates of the first capacitor and the fourth transistor and the input terminal of the second inverter; the output end of the second inverter is connected with a second capacitor.
9. The reference voltage generating circuit is characterized by comprising a V CTAT generating circuit and a V PTAT generating circuit, wherein the V PTAT generating circuit comprises a first generating circuit and a second generating circuit, the V CTAT generating circuit, the first generating circuit and the second generating circuit are all the capacitance bias diode circuits with the voltage stabilizing charge pump according to any one of claims 1 to 8, V CTAT is the output voltage generated by a diode branch in the V CTAT generating circuit, and V CTAT becomes lower as the temperature becomes higher; v PTAT is the difference between the output voltage generated by the diode branch in the first generating circuit and the output voltage generated by the diode branch in the second generating circuit, and V PTAT is increased as the temperature is increased by adjusting the diode sizes of the diode branch in the first generating circuit and the diode branch in the second generating circuit, or the capacitance sizes of the capacitance branch in the first generating circuit and the capacitance branch in the second generating circuit; the reference voltages are additive combinations of V PTAT and V CTAT, and the additive combinations of V PTAT and V CTAT make the reference voltages independent of temperature.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410685120.3A CN118249797B (en) | 2024-05-30 | 2024-05-30 | Capacitor bias diode circuit with voltage stabilizing charge pump and reference voltage generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410685120.3A CN118249797B (en) | 2024-05-30 | 2024-05-30 | Capacitor bias diode circuit with voltage stabilizing charge pump and reference voltage generating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118249797A CN118249797A (en) | 2024-06-25 |
| CN118249797B true CN118249797B (en) | 2024-08-09 |
Family
ID=91557073
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410685120.3A Active CN118249797B (en) | 2024-05-30 | 2024-05-30 | Capacitor bias diode circuit with voltage stabilizing charge pump and reference voltage generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118249797B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108448891A (en) * | 2018-04-23 | 2018-08-24 | 电子科技大学 | A Voltage Stabilizer Circuit Based on Charge Pump Structure |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100909837B1 (en) * | 2007-08-14 | 2009-07-28 | 창원대학교 산학협력단 | Unit charge pump |
| KR20090071860A (en) * | 2007-12-28 | 2009-07-02 | 창원대학교 산학협력단 | High voltage generator for low voltage Dram with cross coupled charge pump |
| CN103647449B (en) * | 2013-12-18 | 2016-08-17 | 嘉兴中润微电子有限公司 | A kind of boost-type charge pump circuit |
| CN104022776B (en) * | 2014-06-27 | 2017-01-25 | 东南大学 | Bootstrapping diode artificial circuit in half-bridge driving circuit |
| CN106100321B (en) * | 2016-07-18 | 2018-06-15 | 东南大学 | A kind of complementary feedback formula gate switch charge pump circuit |
| CN106787693A (en) * | 2017-02-14 | 2017-05-31 | 上海华虹宏力半导体制造有限公司 | A kind of charge pump circuit of belt switch |
| US11081955B2 (en) * | 2017-04-10 | 2021-08-03 | Texas Instruments Incorporated | Unidirectional ring mitigation in a voltage converter |
| CN113377145B (en) * | 2021-08-03 | 2022-05-06 | 南京慧感电子科技有限公司 | Band gap reference trimming circuit suitable for low voltage |
| CN219740344U (en) * | 2023-04-21 | 2023-09-22 | 石家庄泽润科技有限公司 | Driving circuit taking NMOS as ideal diode |
-
2024
- 2024-05-30 CN CN202410685120.3A patent/CN118249797B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108448891A (en) * | 2018-04-23 | 2018-08-24 | 电子科技大学 | A Voltage Stabilizer Circuit Based on Charge Pump Structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118249797A (en) | 2024-06-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6603346B2 (en) | Semiconductor booster circuit having cascaded MOS transistors | |
| US6249169B1 (en) | Transistor output circuit | |
| US20070115041A1 (en) | Level conversion circuit | |
| US10811960B2 (en) | Voltage multiplier circuit with a common bulk and configured for positive and negative voltage generation | |
| US4390803A (en) | Semiconductor driver circuit | |
| EP0174694B1 (en) | Circuit for generating a substrate bias | |
| US7368969B2 (en) | Level shift circuit and semiconductor device | |
| US6980194B2 (en) | Amplitude conversion circuit for converting signal amplitude | |
| US20030214347A1 (en) | Basic stage for a charge pump circuit | |
| US6975161B2 (en) | Charge pump and voltage doubler using the same | |
| US6380792B1 (en) | Semiconductor integrated circuit | |
| US7315196B2 (en) | Voltage generating circuit that produces internal supply voltage from external supply voltage | |
| CN118249797B (en) | Capacitor bias diode circuit with voltage stabilizing charge pump and reference voltage generating circuit | |
| US6437637B2 (en) | Charge-pump circuit and control method thereof | |
| US7612605B2 (en) | Bootstrap voltage generating circuits | |
| US7002400B2 (en) | Input circuits including boosted voltage and related methods | |
| US6472924B1 (en) | Integrated semiconductor circuit having analog and logic circuits | |
| Racape et al. | A PMOS-switch based charge pump, allowing lost cost implementation on a CMOS standard process | |
| CN110266186B (en) | Low leakage current charge pump circuit | |
| KR20010004448A (en) | An Invertor for outputting a high voltage | |
| US20200292587A1 (en) | Current sensing circuit | |
| US11683010B2 (en) | Oscillation circuit | |
| CN117277783B (en) | LDO circuit applied to AC-DC power supply driving chip starting circuit | |
| US11690221B2 (en) | Charge pump circuit capable of generating voltages in erasing operation, program operation and read operation | |
| CN111313879B (en) | Time delay circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |