CN118245311B - Chip detection method and chip detection device - Google Patents
Chip detection method and chip detection device Download PDFInfo
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits
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Abstract
The invention relates to the technical field of chip detection, and discloses a chip detection method and a chip detection device, wherein the chip detection method is realized based on a fault detection program written into a chip to be detected; the chip detection method comprises the following steps: performing fault detection on a communication serial port of a chip to be detected; when the communication serial port has no fault, performing fault detection on the GPIO pin of the chip to be detected; performing fault detection on an ADC pin of a chip to be detected; and performing fault detection on other serial ports of the chip to be detected. The invention performs point detection test on each hardware function and each peripheral function on the chip to be detected, thereby achieving the purpose of rapidly positioning the fault position of the chip.
Description
Technical Field
The invention relates to the technical field of chip detection, in particular to a chip detection method and a chip detection device.
Background
The chip is provided with abundant peripheral equipment and pins, the test items are more, and the selection of reasonable test items and test methods is very necessary. For the production line, if the chip is damaged but no corresponding testing method exists, the product has a fault problem after being attached to the PCB; not only greatly affects the efficiency of production and troubleshooting, but also indirectly affects the satisfaction of the user using the product.
Therefore, a chip detection method is needed to perform point detection test on each hardware function and each peripheral function on a chip, so as to achieve the purpose of rapidly positioning the fault position of the chip.
Disclosure of Invention
In view of the above, the present invention provides a chip detection method and a chip detection device, so as to solve the problem that the existing test method cannot detect the damage of the chip, resulting in the failure of the product containing the chip, and affecting the efficiency of product production and failure detection.
In a first aspect, the present invention provides a chip detection method implemented based on a fault detection program written to a chip to be detected, the method comprising:
performing fault detection on the communication serial port of the chip to be detected;
When the communication serial port has no fault, performing fault detection on a GPIO pin of the chip to be detected;
performing fault detection on the ADC pins of the chip to be detected;
And performing fault detection on other serial ports of the chip to be detected.
According to the chip detection method provided by the invention, fault detection is carried out on the communication serial port of the chip to be detected; when the communication serial port has no fault, performing fault detection on the GPIO pin of the chip to be detected; and fault detection is carried out on the ADC pins and other serial ports of the chip to be detected, so that point detection test can be carried out on the hardware function and each peripheral function of the chip to be detected, the purpose of rapidly positioning the fault position of the chip is achieved, and the normal operation of the chip is ensured.
In an optional implementation manner, performing fault detection on the communication serial port of the chip to be detected includes:
Transmitting a request data frame to the singlechip through the communication serial port; the singlechip is used for judging whether the request data frame is received in a first preset time, and if the request data frame is not received in the first preset time, the singlechip sends the communication serial port fault data frame; if the singlechip receives the request data frame within the first preset time, sending a pin state data frame corresponding to the request data frame to the chip to be detected;
Judging whether the pin state data frame is received in a second preset time; if the pin state data frame is not received within the second preset time, the communication serial port fault data frame is sent; and if the pin state data frame is received within the second preset time, sending the communication serial port safety data frame.
In an alternative embodiment, the fault detection on the GPIO pin of the chip to be detected includes:
Pulling up the level value of a target GPIO pin in the chip to be detected, and sending a request data frame of a pin state to the singlechip through the communication serial port; the target GPIO pin is at least one of all GPIO pins; the singlechip is used for determining the pin states of all the GPIO pins according to the received request data frame, and sending a pin state data frame containing the pin states of all the GPIO pins to the chip to be detected through the communication serial port;
after the pin state data frame is received, comparing the pin states of all the GPIO pins with preset pin states, if the states are consistent, determining that the target GPIO pin has no fault, and if the states are inconsistent, determining that the target GPIO pin has fault.
In an alternative embodiment, the fault detection on the ADC pin of the chip to be detected includes:
Pulling down the level value of the ADC control pin of the chip to be detected;
When the ADC control pin is at a low level, judging whether a first voltage value corresponding to a first ADC pin, a second voltage value corresponding to a second ADC pin and a third voltage value corresponding to a third ADC pin are the same;
if the ADC pins are different, determining that faults exist in the ADC pins of the chip to be detected;
if the two values are the same, the level value of the ADC control pin of the chip to be detected is pulled up;
when the ADC control pin is at a high level, judging whether the first voltage value is in a first voltage range, whether the second voltage value is in a second voltage range and whether the third voltage value is in a third voltage range;
and if the first voltage value is in a first voltage range, the second voltage value is in a second voltage range and the third voltage value is in a third voltage range, determining that the ADC pin of the chip to be detected has no fault.
In an optional implementation manner, the other serial ports include a first serial port and a second serial port, and fault detection is performed on the other serial ports of the chip to be detected, including:
Transmitting a first preset data frame containing first fixed information to the second serial port through the first serial port;
Analyzing the first preset data frame received by the second serial port to obtain second fixed information; if the second fixed information is the same as the first fixed information, a second preset data frame containing the second fixed information is sent to the first serial port through the second serial port;
analyzing the second preset data frame received by the first serial port to obtain third fixed information; and if the third fixed information is the same as the first fixed information, determining that the first serial port and the second serial port have no faults.
In a second aspect, the invention provides a chip detection device, which comprises a chip clamp, a communication interface connected with the chip clamp, and a singlechip connected with the chip clamp;
the chip clamp is used for loading a chip to be detected and is respectively connected with each pin to be detected of the chip to be detected;
the communication interface is used for connecting an upper computer; the upper computer is used for brushing a fault detection program into the chip to be detected;
The singlechip is used for detecting faults of GPIO pins of the chip to be detected; the singlechip is connected with the GPIO pin of the chip to be detected through the chip clamp.
The chip detection device provided by the invention is used for being connected with the upper computer through the communication interface, brushing the fault detection program into the chip to be detected, and carrying out fault detection on the GPIO pins of the chip to be detected through the singlechip, so that the point detection test on each GPIO pin on the chip can be carried out, and the purpose of rapidly positioning the fault position of the chip is achieved.
In an alternative embodiment, the chip detection device further comprises an ADC detection circuit, and the ADC detection circuit is connected to an ADC pin of the chip to be detected through the chip holder;
the ADC detection circuit is used for detecting faults of the ADC pins of the chip to be detected.
In an alternative embodiment, the ADC detection circuit includes a power supply, a first resistor, a second resistor, a third resistor, a fourth resistor, and a ground terminal connected in sequence with the power supply;
The first node of the ADC detection circuit is connected with a first ADC pin of the chip to be detected, the second node is connected with a second ADC pin of the chip to be detected, the third node is connected with a third ADC pin of the chip to be detected, and the fourth node is connected with the ADC control pin of the chip to be detected through a fifth resistor;
the first node is located between the first resistor and the second resistor, the second node is located between the second resistor and the third resistor, the third node is located between the third resistor and the fourth resistor, and the fourth node is located between the fourth resistor and the ground terminal.
In an optional implementation manner, the singlechip is connected with the communication serial port of the chip to be detected through the chip clamp; the singlechip is also used for detecting faults of the communication serial port of the chip to be detected.
In an optional implementation manner, the chip to be detected further includes other serial ports, where the other serial ports include a first serial port and a second serial port; the first serial port is connected with the second serial port through the chip clamp.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for chip testing according to an embodiment of the invention;
FIG. 2 is a flow chart of another method for chip testing according to an embodiment of the invention;
FIG. 3 is a flow chart of another method for detecting a chip according to an embodiment of the invention;
FIG. 4 is a flow chart of another method for detecting a chip according to an embodiment of the invention;
FIG. 5 is a flow chart of GPIO pin detection in accordance with an embodiment of the present invention;
FIG. 6 is a flow chart of another method for chip testing according to an embodiment of the invention;
FIG. 7 is a flow chart of another method for chip testing according to an embodiment of the invention;
FIG. 8 is a flow chart of another method for chip testing according to an embodiment of the invention;
FIG. 9 is a schematic diagram of a chip inspection apparatus according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of another chip inspection apparatus according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of an ADC detection circuit according to an embodiment of the present invention;
Fig. 12 is a schematic structural view of another chip inspection apparatus according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The Quan Zhi T3 core board is a four-core ARM Cortex-A7 processor with high performance, not only provides stronger computing capacity and multitasking processing capacity, but also comprises a plurality of common peripheral interfaces such as a CAN bus, USB, HDMI, ethernet and the like, is convenient to connect with other devices or expansion modules, and meets the requirements of different application scenes. Based on the T3 chip, the method has the advantages of advanced low-power design, 100% localization, high cost performance, support of an open source operating system and the like, and is widely applied to various industries including smart grids, industrial controls and vehicle-standard products. Because the full-log T3 core board has abundant peripheral equipment and pins, more test items and reasonable test items and test methods are very necessary to select. For the production line of the company, if the core board is damaged but no corresponding testing method exists, the functions of the product after being attached to the PCB board are as problematic, so that the production efficiency and the fault detection efficiency are greatly affected, and the benefit of the company and the satisfaction degree of customers on the company product are indirectly affected.
Therefore, at present, a chip detection method is urgently needed to perform point detection test on the hardware function and each peripheral function of the T3 chip, and quickly locate the fault position of the chip.
In this embodiment, a method for detecting a chip is provided, the method is implemented based on a fault detection program that is written into a chip to be detected, fig. 1 is a flowchart of a method for detecting a chip according to an embodiment of the present invention, and as shown in fig. 1, the flowchart includes the following steps:
step S101, performing fault detection on the communication serial port of the chip to be detected.
Specifically, the chip to be detected may be the Quan Zhi T3 core board described above; the purpose of fault detection of the communication serial ports (such as two paths of serial ports) of the chip to be detected can be achieved through the combined action of the fault detection program in the chip to be detected and the singlechip of the chip detection device.
As shown in fig. 2, the step S101 further includes steps S1011 to S1012:
Step S1011, transmitting a request data frame to the singlechip through a communication serial port; the singlechip is used for judging whether a request data frame is received in a first preset time, and if the singlechip does not receive the request data frame in the first preset time, the singlechip sends a communication serial port fault data frame; and if the singlechip receives the request data frame within the first preset time, sending a pin state data frame corresponding to the request data frame to the chip to be detected.
Specifically, the first preset time may be set according to actual situations, which is not specifically limited herein.
Step S1012, judging whether a pin state data frame is received in a second preset time; if the pin state data frame is not received within the second preset time, transmitting a communication serial port fault data frame; and if the pin state data frame is received within the second preset time, transmitting the communication serial port safety data frame.
Specifically, the second preset time may be set according to actual situations, which is not specifically limited herein.
In the steps S1011 to S1012, the chip to be detected has four serial ports, and the single chip microcomputer of the chip detection device has only two serial ports, so that fault detection can be performed on two of the serial ports through the single chip microcomputer, and the specific fault detection flow is as follows:
the level value of a target GPIO pin in a chip to be detected is pulled down, and the chip to be detected is controlled by a fault detection program to send a request message (namely a request data frame for requesting the pin state) to a singlechip through a communication serial port (which can be any one of two serial ports, such as serial port 1); when the singlechip does not receive a request data frame sent by the chip to be detected within a first preset time, the transmitting end of the serial port 1 can be determined to be in a fault state; when the singlechip receives a request data frame in a first preset time, reading a corresponding pin connected with a chip to be detected to obtain a pin state; then the pin state is sent to a chip to be detected; however, if the chip to be detected does not receive the pin state data frame returned by the singlechip within the second preset time, the receiving end of the serial port 1 can be determined to be in a fault state; and when the singlechip receives the request data frame within the first preset time and the chip to be detected receives the pin state data frame returned by the singlechip within the second preset time, determining that the transmitting end and the receiving end of the serial port 1 are both in a safe state. Similarly, the serial port 2 can also detect whether the fault state exists in the above manner.
Step S102, when the communication serial port has no fault, fault detection is carried out on the GPIO pin of the chip to be detected.
As shown in fig. 3, the step S102 further includes steps S1021 to S1022:
Step S1021, pulling up the level value of a target GPIO pin in the chip to be detected, and sending a request data frame of a pin state to the singlechip through the communication serial port; the singlechip is used for determining the pin states of all the GPIO pins according to the received request data frame, and sending a pin state data frame containing the pin states of all the GPIO pins to the chip to be detected through the communication serial port.
Specifically, before step S1021, the level of all GPIO pins needs to be pulled low before the GPIO pins are detected, so that all GPIO pins are in a low level state.
More specifically, the target GPIO pin is at least one of all GPIO pins, for example, when the chip to be detected has 10 GPIO pins, fault detection needs to be performed on each GPIO pin separately, that is: when the first GPIO pin is detected, the level of the first GPIO pin needs to be pulled up to be in a high level, other GPIO pins keep in a low level state, and a request data frame of a corresponding pin state is sent to the singlechip; after receiving the request data frame, the singlechip analyzes the request data frame to determine the pin states of all GPIO pins, for example: 1-0-0-0-0-0-0-0-0; wherein "1" indicates that the first GPIO pin is at a high level and "0" indicates that the other GPIO pins are all at a low level; and then returning the pin state data frame containing all the pin states to the chip to be detected.
Step S1022, after receiving the pin status data frame, compares the pin status of all the GPIO pins with a preset pin status, if the status is consistent, determines that the target GPIO pin has no fault, and if the status is inconsistent, determines that the target GPIO pin has a fault.
Specifically, after the chip to be detected receives the pin state data frame, the state of all the GPIO pins is analyzed to be 1-0-0-0-0-0-0-0-0, and the level state of all the GPIO pins is the same as that when the first GPIO pin is pulled up, so that the first GPIO pin can be determined to have no fault. Wherein, the preset pin state is determined according to the currently detected target GPIO pins, for example, there are 10 GPIO pins in total, and when the target GPIO pin is the 3 rd GPIO pin, the preset pin state is "0-0-1-0-0-0-0-0-0"; when the target GPIO pin is the 6 th GPIO pin, the preset pin state is '0-0-0-0-0-1-0-0-0-0'. The target GPIO pin may be set as each GPIO pin, and the fault detection may be performed for each GPIO pin through the above steps S1021 to S1022, respectively.
In a preferred embodiment, as shown in fig. 4, the steps S101 and S102 further include steps S401 to S405:
Step S401, the level values of all GPIO pins of the chip to be detected are pulled down, and a request data frame of the pin state is sent to the singlechip through a communication serial port; the singlechip is used for judging whether the request data frame can be received within a first preset time; if the singlechip can receive the request data frame within a first preset time, determining that no fault exists at the transmitting end of the communication serial port; if the singlechip cannot receive the request data frame within the first preset time, determining that a fault exists at the transmitting end of the communication serial port.
Step S402, when the singlechip receives the request data frame within a first preset time, the singlechip sends a pin state data frame corresponding to the request data frame to the chip to be detected through the communication serial port.
Step S403, judging whether the chip to be detected receives the pin state data frame in a second preset time; if the chip to be detected does not receive the pin state data frame within the second preset time, determining that a fault exists at the receiving end of the communication serial port; and if the chip to be detected receives the pin state data frame within the second preset time, determining that the receiving end of the communication serial port has no fault.
Step S404, when no fault exists in the receiving end and the transmitting end of the communication serial port, the level value of the target GPIO pin of the chip to be detected is pulled up, and a request data frame of the pin state is sent to the singlechip through the communication serial port; the target GPIO pin is any one of all GPIO pins; the singlechip is used for determining the pin states of all the GPIO pins according to the received request data frame, and sending a pin state data frame containing the pin states of all the GPIO pins to the chip to be detected through the communication serial port;
And step S405, after the chip to be detected receives the pin state data frame, comparing the pin states of all the GPIO pins with preset pin states, if the states are consistent, determining that the target GPIO pin has no fault, and if the states are inconsistent, determining that the target GPIO pin has a fault.
More specifically, as shown in fig. 5, the pin driver needs to be turned on before all GPIO pins are pulled down, and the serial port driver needs to be turned on before the chip to be detected sends the request data frame to the singlechip, and the request data frame is sent and the pin state data frame is received through the serial port; after judging that the status information of the pins is compared with the program value (i.e. the preset pin status), error information or success information can be displayed through liquid crystal.
Step S103, fault detection is carried out on the ADC pins of the chip to be detected.
Specifically, the fault detection of the ADC pins of the chip to be detected is implemented based on an ADC detection circuit, and the specific circuit structure of the ADC detection circuit can be seen below.
As shown in fig. 6, the step S103 further includes steps S1031 to S1035:
step S1031, pulling down the level value of the ADC control pin of the chip to be detected.
Step S1032, when the ADC control pin is at the low level, determines whether the first voltage value corresponding to the first ADC pin, the second voltage value corresponding to the second ADC pin, and the third voltage value corresponding to the third ADC pin are the same.
Specifically, the first voltage value, the second voltage value and the third voltage value are determined according to the power supply voltage of the ADC detection circuit, for example, when the power supply voltage is 3.3v, it is determined whether the ADC control pin is at a low level, and the first voltage value, the second voltage value and the third voltage value are all 3.3v.
Step S1033, if not, determining that the ADC pins of the chip to be detected have faults; and if the two voltage values are the same, pulling up the level value of the ADC control pin of the chip to be detected.
In step S1034, when the ADC control pin is at a high level, it is determined whether the first voltage value is within a first voltage range, the second voltage value is within a second voltage range, and the third voltage value is within a third voltage range.
Step S1035, if the first voltage value is within a first voltage range, the second voltage value is within a second voltage range, and the third voltage value is within a third voltage range, determining that there is no fault in the ADC pin of the chip to be detected.
In the above steps S1031 to S1035, the first voltage range may be set to 0.8-1.2v, the second voltage range may be set to 1.8-2.2v, and the third voltage range may be set to 2.8-3.2v. And if the first voltage value is not in the first voltage range, the second voltage value is in the second voltage range and the third voltage value is in the third voltage range, determining that the ADC pin of the chip to be detected has no fault.
More specifically, as shown in fig. 11, three ADC pins (ADCHK 1, ADCHK, and ADCHK 3) are connected in series by resistors, and detection is judged by acquiring three sampled values by control of ADCHK _ctrl: when ADCHK _CTRL is set to low level, whether program acquisition values of the three ADC pins are 3.3v or not is judged by pulling up, whether sampling values of the three ADC pins are 1v,2v and 3v respectively is judged by circulating execution, timeout time is set, errors are reported, and the result is printed into a liquid crystal display.
Step S104, fault detection is carried out on other serial ports of the chip to be detected.
Specifically, the chip to be detected has four serial ports, wherein two serial ports are subjected to serial port fault detection by the singlechip and the chip to be detected; the other two serial ports are subjected to fault detection by the chip to be detected. The other serial ports of the chip to be detected comprise a first serial port and a second serial port, and the first serial port is connected with the second serial port.
As shown in fig. 7, the step S104 further includes steps S1041 to S1043:
step S1041, sending, through the first serial port, a first preset data frame including first fixed information to the second serial port.
Specifically, a transmitting line of a first serial port of a chip to be detected is connected with a receiving line of a second serial port in advance through a chip clamp, and the receiving line of the first serial port of the chip to be detected is connected with the transmitting line of the second serial port; when the first serial port and the second serial port of the chip to be detected are subjected to fault detection, a first preset data frame containing first fixed information can be sent to the second serial port through the transmitting line of the first serial port; the first fixed information is preset, and is not particularly limited herein.
Step S1042, analyzing the first preset data frame received by the second serial port to obtain second fixed information; and if the second fixed information is the same as the first fixed information, sending a second preset data frame containing the second fixed information to the first serial port through the second serial port.
Step S1043, analyzing the second preset data frame received by the first serial port to obtain third fixed information; and if the third fixed information is the same as the first fixed information, determining that the first serial port and the second serial port have no faults.
In step S1041 to step S1043, if the second serial port receives and parses the second fixed information and the first fixed information are consistent, it may be determined that there is no fault between the transmitting line of the first serial port and the receiving line of the second serial port; if the first serial port receives and analyzes the third fixed information and the second fixed information are the same, it can be determined that the receiving line of the first serial port and the transmitting line of the second serial port have no faults.
More specifically, for a core board applied to an electricity consumption information acquisition terminal, multiple serial ports are needed to realize different functions, serial ports connected with the coprocessor (i.e. a singlechip) in the coprocessor are limited, a self-receiving function is realized on the device aiming at the serial ports with more core boards, a fixed message is sent by the serial port 1, when the serial port 2 detects a matched message, the fixed message is returned to the serial port 1, the serial port 1 receives and judges again, and the verification is calculated to be successful only when two received frames are verified without errors.
In some optional embodiments, three kinds of fault detection of the GPIO pin, the ADC pin and other serial ports of the chip to be detected are independent of each other, and the three kinds of fault detection cannot be performed simultaneously without affecting the overall technical scheme of the present invention no matter which kind of fault detection is performed first.
In some alternative embodiments, the method further comprises: judging whether an electrified erasable programmable read-only memory (EEPROM) of a chip to be detected is qualified, judging whether a chip (ESAM) for safety authentication and data encryption is qualified, and judging whether a network port is qualified or not, wherein the method comprises the following steps of:
Judging whether an electrified erasable programmable read-only memory (EEPROM) of a chip to be detected is qualified or not, comprising: connecting the EEPROM with an I2C pin (the I2C pin comprises two signal lines, namely SCL (clock line) and SDA (data line)) of the detection chip, and detecting whether the two signal lines in the I2C pin are connected correctly and stably; if the two signal lines in the I2C pin are correct and stable, judging whether a chip to be detected has a corresponding file system or not; judging whether a newly generated file name exists in a file path appointed in a file system; if present, represents that the physical connection is free of faults; and finally judging whether the read address is consistent with the write address through the write data and the read data, and if so, qualifying the charged erasable programmable read-only memory (EEPROM) of the chip to be detected.
Determining whether a chip (ESAM) for security authentication and data encryption is acceptable includes:
The ESAM is a chip for safety authentication and data encryption, and is communicated with the core board through an SPI interface, so that the ESAM acquires a serial number for judgment and detection;
Judging whether the network port is qualified or not, comprising:
A udhcpc command is run on the core board that lets udhcpc attempt to request IP addresses and other configuration information from the DHCP server. udhcpc will scan all enabled portals and attempt to send requests to the DHCP server. If the DHCP server responds successfully, udhcpc automatically obtains the IP address and other configuration information and applies it to the corresponding portal. udhcpc can only make DHCP requests on an already enabled portal. If the network port is not enabled or there are problems such as hardware failure, udhcpc will not work properly. Therefore, before udhcpc is used, it is necessary to ensure that the portal is properly configured and can function properly.
In some alternative embodiments, as shown in fig. 8, in the process of detecting a chip to be detected by using the chip detection device, the fixture is opened, the core board is fixed, the power supply is powered, the boot pin is manually pressed, the switch of the power supply module is turned on, a program to be burnt is selected on the pc upper computer, when the upper computer recognizes the core board, the upper computer performs brushing, after the brushing is successful, the core board detection program is waited for starting, and the following detection processes are sequentially executed: judging whether the GPIO is qualified, the ESAM is qualified, the EEPROM is qualified, the ADC is qualified, the network port is qualified, and the serial port is qualified, then printing successful or failure information on the liquid crystal, checking specific information by a tester through the liquid crystal, and turning pages of the liquid crystal through up and down keys on the device. If the test functions are all qualified, the test flows into the next working procedure, otherwise, the test needs to be marked for maintenance.
The invention also provides a chip detection device, which consists of a core plate clamp, USB, RS232, liquid crystal, keys, a network port, a program programming and debugging port, a coprocessor (single chip microcomputer) and other devices, wherein the core plate is loaded by the clamp, pins of the core plate are contacted with clamp ejector pins, and fault detection of each function of the core plate is carried out through a peripheral circuit. The core board program is written by an upper computer (the process of writing the program into a chip), and the specific conditions of each test item can be rapidly displayed on the liquid crystal after the downloading is finished, so that the production detection of the core board is realized. The technical scheme is that the basic peripheral equipment of the core board is as follows: the network ports, the liquid crystal, the plurality of serial ports and the like are detected, so that the normal operation of the functions of the core board can be ensured. Therefore, the fault problem of the core plate T3 chip is detected, and the chip detection device has simple structure and low cost. And the firmware downloading, the device control and the function test are combined together, so that the automatic detection of the production line is realized, and the production cost and time are saved.
In this embodiment, there is provided a chip detection apparatus, as shown in fig. 9, including: the chip fixture 901, a communication interface 902 connected with the chip fixture 901, and a singlechip 903 connected with the chip fixture 901;
The chip clamp 901 is used for loading chips to be detected, and the chip clamp 901 is respectively connected with each pin to be detected of the chips to be detected. Specifically, the chip to be detected may be a full-lineage T3 core board; the chip to be detected comprises a plurality of pins. The chip clamp comprises a plurality of clamp ejector pins, and each clamp ejector pin is contacted with a corresponding pin of the chip to be detected.
The communication interface 902 is used for connecting with an upper computer; the upper computer is used for brushing the fault detection program into the chip to be detected.
The singlechip 903 is used for performing fault detection on the GPIO pin of the chip to be detected; the singlechip 903 is connected with the GPIO pin of the chip to be detected through the chip clamp.
Specifically, the GPIO pin (General-purpose input/output), also called General input/output, has a pin level of 0V-3.3V, and a part of the pins can tolerate 5V; output mode: the controllable port outputs high and low levels for driving the LED, controlling the buzzer, simulating the output time sequence of the communication protocol and the like; input mode: the high-low level or voltage of the port can be read and is used for reading key input, external module level signal input, ADC voltage acquisition, analog communication protocol receiving data and the like.
In some alternative embodiments, as shown in fig. 10, the chip detection device further includes an ADC detection circuit 1004, where the ADC detection circuit 1004 is connected to an ADC pin of the chip to be detected through the chip fixture 1001; the ADC detection circuit 4 is configured to perform fault detection on an ADC pin of the chip to be detected. In fig. 10, 1002 denotes a communication interface, and 1003 denotes a single-chip microcomputer.
Specifically, for a chip (such as a core board) applied to the electricity consumption information acquisition terminal, not only can control a common pin be ensured, but also various peripheral devices need to perform function detection. The battery voltage of the power utilization acquisition terminal needs to be sampled, and the core board is provided with a sampling interface of the ADC.
More specifically, as shown in fig. 11, the ADC detection circuit includes a power supply 1101, a first resistor 1101, a second resistor 1102, a third resistor 1103, a fourth resistor 1104, and a ground 1105 connected in this order to the power supply;
The first node of the ADC detection circuit is connected to the first ADC pin ADCHK1 of the chip to be detected, the second node is connected to the second ADC pin ADCHK2 of the chip to be detected, the third node is connected to the third ADC pin ADCHK3 of the chip to be detected, and the fourth node is connected to the ADC control pin adc_ctrl of the chip to be detected through the fifth resistor 1107;
The first node is located between the first resistor 1102 and the second resistor 1103, the second node is located between the second resistor 1103 and the third resistor 1104, the third node is located between the third resistor 1104 and the fourth resistor 1105, and the fourth node is located between the fourth resistor 1105 and the ground 1106.
Wherein the voltage value of the power supply 1101 may be 3.3v; the first resistor 1102 may be set to 1 kilo-ohm, the second resistor 1103 may be set to 3.3 kilo-ohm, the third resistor 1104 may be set to 3.3 kilo-ohm, and the fourth resistor 1105 may be set to 3.3 kilo-ohm.
In some optional embodiments, the single chip microcomputer is connected with the chip to be detected through the chip clamp; the singlechip is also used for detecting faults of the communication serial port of the chip to be detected.
In some optional embodiments, the chip to be detected further includes other serial ports, where the other serial ports include a first serial port and a second serial port; the first serial port is connected with the second serial port through the chip clamp; the transmitting line of the first serial port is connected with the receiving line of the second serial port through the chip clamp, and the receiving line of the first serial port is connected with the transmitting line of the second serial port through the chip clamp.
Specifically, serial port (SERIAL INTERFACE), also known as a serial interface or serial communication interface. The chip to be detected comprises 4 serial ports, the singlechip is provided with 2 serial ports, so that the spontaneous self-receiving flow is required to be carried out for more serial ports on the chip to be detected, namely, the transmitting line of the first serial port is connected with the receiving line of the second serial port, and the receiving line of the first serial port is connected with the transmitting line of the second serial port, so that whether the serial ports have faults or not is detected.
In some alternative embodiments, as shown in fig. 12: the chip detection device comprises: clamp 1201, communication interface 1202, coprocessor (i.e., single-chip microcomputer) 1203, power management module 1204, liquid crystal display 1205, portal 1206, RS232 interface 1207;
The communication interface 1202 is used for connecting with an external PC upper computer, selecting a fault detection program by the upper computer, brushing the fault detection program into a chip to be detected, and monitoring the firmware download state of the upper computer in real time through USB detection to realize power supply, firmware download and later function detection;
The power management module 1204 is used for supplying power to the chip detection device; considering the efficiency problem of workshops, the power supply detection can not be performed only by frequently plugging and unplugging the USB, so that the outside of the chip detection device is also provided with a part of 5v power supply management module for power supply of the production line, and the management module is provided with a switch to prevent the artificial damage caused by static electricity generated by disassembling the core board in the clamp in the power supply process.
The network port 1206 is connected with an external router through a network cable, and the RS232 interface 1207 is connected with a debugging serial port through TTL or RS 232; 1208 in fig. 12 represents programming, 1209 represents debugging.
Specifically, the core board is placed in the fixture, when firmware is downloaded (upgrade package is downloaded and used for upgrading a mobile phone or a computer), the VCC pin and the BOOT pin on the device are required to be short-circuited, and in the device, the high level and the low level of the BOOT pin are realized by keys. When the key is pressed, the upper computer writes the detection program into the chip to be detected through the communication interface.
Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.
Claims (8)
1. A chip inspection method, characterized in that the method is implemented based on a fault detection program written to a chip to be inspected, the method comprising:
performing fault detection on the communication serial port of the chip to be detected;
When the communication serial port has no fault, performing fault detection on a GPIO pin of the chip to be detected;
performing fault detection on the ADC pins of the chip to be detected;
Performing fault detection on other serial ports of the chip to be detected; the chip to be tested comprises four serial ports, serial ports for carrying out serial port fault detection through the singlechip and the chip to be tested are communication serial ports, and serial ports for carrying out fault detection through the chip to be tested are other serial ports;
Performing fault detection on the ADC pins of the chip to be detected, including:
Pulling down the level value of the ADC control pin of the chip to be detected;
When the ADC control pin is at a low level, judging whether a first voltage value corresponding to a first ADC pin, a second voltage value corresponding to a second ADC pin and a third voltage value corresponding to a third ADC pin are the same; the first node between the first resistor and the second resistor is connected with a first ADC pin, the second node between the second resistor and the third resistor is connected with a second ADC pin, the third node between the third resistor and the fourth resistor is connected with a third ADC pin, the ADC control pin of the chip to be detected is connected with a fourth node through a fifth resistor, and the fourth node is positioned between the fourth resistor and a grounding end; the first resistor, the second resistor, the third resistor, the fourth resistor and the grounding end are sequentially connected with a power supply;
if the ADC pins are different, determining that faults exist in the ADC pins of the chip to be detected;
if the two values are the same, the level value of the ADC control pin of the chip to be detected is pulled up;
when the ADC control pin is at a high level, judging whether the first voltage value is in a first voltage range, whether the second voltage value is in a second voltage range and whether the third voltage value is in a third voltage range;
and if the first voltage value is in a first voltage range, the second voltage value is in a second voltage range and the third voltage value is in a third voltage range, determining that the ADC pin of the chip to be detected has no fault.
2. The chip inspection method according to claim 1, wherein performing fault inspection on the communication serial port of the chip to be inspected comprises:
Transmitting a request data frame to the singlechip through the communication serial port; the singlechip is used for judging whether the request data frame is received in a first preset time, and if the request data frame is not received in the first preset time, the singlechip sends the communication serial port fault data frame; if the singlechip receives the request data frame within the first preset time, sending a pin state data frame corresponding to the request data frame to the chip to be detected;
Judging whether the pin state data frame is received in a second preset time; if the pin state data frame is not received within the second preset time, the communication serial port fault data frame is sent; and if the pin state data frame is received within the second preset time, sending the communication serial port safety data frame.
3. The chip detection method according to claim 1 or 2, wherein performing fault detection on the GPIO pin of the chip to be detected comprises:
Pulling up the level value of a target GPIO pin in the chip to be detected, and sending a request data frame of a pin state to the singlechip through the communication serial port; the target GPIO pin is at least one of all GPIO pins; the singlechip is used for determining the pin states of all the GPIO pins according to the received request data frame, and sending a pin state data frame containing the pin states of all the GPIO pins to the chip to be detected through the communication serial port;
after the pin state data frame is received, comparing the pin states of all the GPIO pins with preset pin states, if the states are consistent, determining that the target GPIO pin has no fault, and if the states are inconsistent, determining that the target GPIO pin has fault.
4. The chip testing method according to claim 1 or 2, wherein the other serial ports include a first serial port and a second serial port, and performing fault detection on the other serial ports of the chip to be tested includes:
Transmitting a first preset data frame containing first fixed information to the second serial port through the first serial port;
Analyzing the first preset data frame received by the second serial port to obtain second fixed information; if the second fixed information is the same as the first fixed information, a second preset data frame containing the second fixed information is sent to the first serial port through the second serial port;
analyzing the second preset data frame received by the first serial port to obtain third fixed information; and if the third fixed information is the same as the first fixed information, determining that the first serial port and the second serial port have no faults.
5. The chip detection device is characterized by comprising a chip clamp, a communication interface connected with the chip clamp, a singlechip connected with the chip clamp and an ADC detection circuit;
the chip clamp is used for loading a chip to be detected and is respectively connected with each pin to be detected of the chip to be detected;
the communication interface is used for connecting an upper computer; the upper computer is used for brushing a fault detection program into the chip to be detected;
The singlechip is used for detecting faults of GPIO pins of the chip to be detected; the singlechip is connected with the GPIO pin of the chip to be detected through the chip clamp;
The ADC detection circuit comprises a power supply, a first resistor, a second resistor, a third resistor, a fourth resistor and a grounding end which are sequentially connected with the power supply;
The first node of the ADC detection circuit is connected with a first ADC pin of the chip to be detected, the second node is connected with a second ADC pin of the chip to be detected, the third node is connected with a third ADC pin of the chip to be detected, and the fourth node is connected with an ADC control pin of the chip to be detected through a fifth resistor;
the first node is located between the first resistor and the second resistor, the second node is located between the second resistor and the third resistor, the third node is located between the third resistor and the fourth resistor, and the fourth node is located between the fourth resistor and the ground terminal.
6. The chip inspection apparatus according to claim 5, further comprising an ADC inspection circuit connected to an ADC pin of the chip to be inspected through the chip holder;
the ADC detection circuit is used for detecting faults of the ADC pins of the chip to be detected.
7. The chip detection device according to claim 5 or 6, wherein the single chip microcomputer is connected with the communication serial port of the chip to be detected through the chip clamp; the singlechip is also used for detecting faults of the communication serial port of the chip to be detected.
8. The chip testing device according to claim 5 or 6, wherein the chip to be tested further comprises other serial ports, the other serial ports comprising a first serial port and a second serial port; the first serial port is connected with the second serial port through the chip clamp; the serial ports for fault detection of the chip to be detected are other serial ports.
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| CN105676145A (en) * | 2016-04-01 | 2016-06-15 | 福建联迪商用设备有限公司 | Method and device for detecting temperature and ID of battery |
| WO2019051838A1 (en) * | 2017-09-18 | 2019-03-21 | 深圳市汇顶科技股份有限公司 | Device, method, and system for open/short circuit test of chip |
| CN112034330B (en) * | 2020-09-29 | 2025-04-08 | 珠海一微半导体股份有限公司 | A SOC chip automated QC method and device |
| CN113900006B (en) * | 2021-08-26 | 2024-10-11 | 湖南艾科诺维科技有限公司 | Chip fault testing device, system and method |
| CN215953825U (en) * | 2021-09-17 | 2022-03-04 | 深圳市博联通信技术有限公司 | HDMI interface detection device |
| CN217879540U (en) * | 2022-07-19 | 2022-11-22 | 北京经纬恒润科技股份有限公司 | Key state detection hardware circuit |
| CN115616377A (en) * | 2022-10-11 | 2023-01-17 | 北京嘉楠捷思信息技术有限公司 | Fault chip detection method and device, computing equipment and storage medium |
| CN116338422A (en) * | 2022-12-30 | 2023-06-27 | 赛迪工业和信息化研究院集团(苏州)有限公司 | UART chip testing method and system |
| CN116805879A (en) * | 2023-08-25 | 2023-09-26 | 南京派格测控科技有限公司 | ADC chip testing method and device |
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| CN106443412A (en) * | 2016-09-09 | 2017-02-22 | 杭州万高科技股份有限公司 | IC (integrated circuit) testing device and method |
| CN212364515U (en) * | 2020-09-29 | 2021-01-15 | 珠海市一微半导体有限公司 | A SOC chip automatic QC device |
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