CN118244841A - Server clock architecture and configuration method, device, product and medium thereof - Google Patents

Abstract

The invention discloses a server clock architecture and a configuration method, equipment, a product and a medium thereof, which relate to the field of servers and aim to solve the problem that a clock transmission link of the server clock architecture cannot meet the clock constraint of a common clock architecture. The invention can ensure that the clock transmission link of the server clock architecture meets the clock constraint and has the peripheral compatibility of adapting to the peripheral slot position.

Description

Server clock architecture and configuration method, device, product and medium thereof

Technical Field

The present invention relates to the field of servers, and in particular, to a server clock architecture, and a configuration method, device, product, and medium thereof.

Background

PCIe (PERIPHERAL COMPONENT INTERCONNECT EXPRES, high speed serial computer expansion bus standard) is the most common peripheral expansion bus standard in computer systems, where both the logic unit operation and data transfer are required to be performed under clock drive. The physical layer of PCIe and the external reference clock include three clock architectures, namely, a server clock architecture, a source synchronous clock architecture, and an independent clock architecture, where the server clock architecture is the most commonly used clock architecture in PCIe, and is also a clock architecture that is clock supported in technology iterations of PCIe bus specifications and remains backward compatible.

With the functional complexity of PCIe peripheral devices, a computer system employing a server Clock architecture needs at least two levels of Clock buffers to fan out Clock signals to each peripheral device, where Clock buffers introduce delay and jitter in a Clock transmission link, resulting in degradation of the quality of Clock signals under the server Clock architecture, so that the PCIe Clock transmission link of the computer system cannot meet Clock constraints of the server Clock architecture.

Therefore, how to provide a solution to the above technical problem is a problem that a person skilled in the art needs to solve at present.

Disclosure of Invention

The invention aims to provide a server clock architecture, a configuration method, equipment, a product and a medium thereof, which can enable a clock transmission link of the server clock architecture to meet clock constraint and simultaneously have peripheral compatibility for adapting to peripheral slots.

In order to solve the technical problems, the invention provides a server clock architecture, which comprises a main control component, a chipset, a crystal oscillator circuit and a first-stage clock buffer which are arranged on a server main board, and also comprises a second-stage clock buffer which is arranged on an external card, wherein the server main board also comprises a peripheral groove for connecting the external card, and the server clock architecture comprises:

The chip set is connected with the first-stage clock buffer through a first transmission line, the first-stage clock buffer is connected with the peripheral slot through a second transmission line, the second-stage clock buffer is connected with the peripheral slot through a third transmission line, the second-stage clock buffer is connected with each end device of the external card, and the crystal oscillator circuit is connected with the first-stage clock buffer or the chip set;

The master control component is configured to adjust a working mode of the first stage clock buffer and/or a working mode of the second stage clock buffer when a current transmission delay time of a clock transmission link of the server clock architecture does not meet a clock constraint corresponding to the server clock architecture, so that the current transmission delay time of the clock transmission link meets the clock constraint.

The server clock architecture also comprises a slave control component arranged on the external card;

The master control component is specifically configured to generate a configuration instruction corresponding to a target working mode of the second stage clock buffer when a current transmission delay time of a clock transmission link of the server clock architecture does not meet a clock constraint corresponding to the server clock architecture, so that the current transmission delay time of the clock transmission link meets the clock constraint;

The slave control component is used for adjusting the current working mode of the second-stage clock buffer to the target working mode according to the configuration instruction after receiving the configuration instruction;

The current transmission delay time of the clock transmission link is determined based on a first delay parameter from the input end to the output end of the second-stage clock buffer, and the first delay parameter of the second-stage clock buffer has different corresponding durations in different working modes.

The chip set is connected with the crystal oscillator circuit;

the chip set is used for outputting a first clock signal according to the signal output by the crystal oscillator circuit;

the first stage clock buffer is used for fanning out a plurality of second clock signals according to the first clock signals;

the second stage clock buffer is configured to fan out a plurality of third clock signals to a plurality of end devices on the external card according to the second clock signal, so that the plurality of end devices all work under the third clock signals.

The first-stage clock buffer is connected with the crystal oscillator circuit;

The first-stage clock buffer is used for fanning out a plurality of fourth clock signals according to signals output by the crystal oscillator circuit;

The chipset is used for working under the fourth clock signal;

The second stage clock buffer is configured to fan out a plurality of fifth clock signals to the end devices on the external card according to the fourth clock signal, so that a plurality of the end devices all work under the fifth clock signals.

In order to solve the above technical problem, the present invention further provides a method for configuring a server clock architecture, where the server clock architecture is the server clock architecture as described in any one of the above, and the method includes:

Determining a clock output mode of the server clock architecture; the clock output mode is a first output mode corresponding to a chip group output clock signal in the server clock architecture or a second output mode corresponding to a first stage clock buffer in the server clock architecture outputting the clock signal;

Calculating the current transmission delay time of the clock transmission link in the clock output mode; the current transmission delay time is determined based on a first delay parameter from an input end to an output end of a second-stage clock buffer in the server clock architecture;

judging whether the current transmission delay time meets the clock constraint of the server clock architecture or not;

If not, adjusting the working mode of the first-stage clock buffer and/or the working mode of the second-stage clock buffer so that the current transmission delay time of the clock transmission link in the clock output mode meets the clock constraint; the first delay parameters of the second-stage clock buffer have different corresponding durations in different working modes.

Wherein the process of calculating the current transmission delay time of the clock transmission link in the clock output mode comprises:

Determining a current delay parameter set corresponding to a clock transmission link in the clock output mode; when the clock output mode is the first output mode, the current delay parameter set is a first delay parameter set, and the first delay parameter set comprises a second delay parameter from the input end to the output end of the first stage clock buffer and a first delay parameter from the input end to the output end of the second stage clock buffer; when the clock output mode is the second output mode, the current delay parameter set is a second delay parameter set, and the second delay parameter set comprises an output clock skew parameter and a first delay parameter from the input end to the output end of the second-stage clock buffer;

the current delay time is calculated using all parameters in the current delay parameter set.

The server clock architecture comprises a server main board, wherein peripheral slot positions are arranged on the server main board, and the process of determining the current delay parameter set corresponding to the clock transmission link in the clock output mode comprises the following steps:

when the clock output mode is the first output mode, acquiring a second delay parameter from an input end to an output end of the first-stage clock buffer, a first delay parameter from the input end to the output end of the second-stage clock buffer, a third delay parameter from a phase-locked loop in the chipset to an output pin of the chipset, a fourth delay parameter corresponding to a first transmission line between the chipset and the first-stage clock buffer, a fifth delay parameter corresponding to a second transmission line between the first-stage clock buffer and the peripheral slot, a sixth delay parameter corresponding to a third transmission line between the second-stage clock buffer and an end device on an external card, and a seventh delay parameter corresponding to a bus data link;

constructing the first delay parameter set based on the first delay parameter, the second delay parameter, the third delay parameter, the fourth delay parameter, the fifth delay parameter, the sixth delay parameter, and the seventh delay parameter;

And taking the first delay parameter set as a current delay parameter set corresponding to the clock transmission link of the first output mode.

Wherein the process of calculating the current delay time using all parameters in the current delay parameter set includes:

Establishing a first calculation relation based on all parameters in the current delay parameter set;

Calculating a current delay time by using the first calculation relation;

the first calculation relation is:

T₁=t_delay1+t_clkpcb1+t_clkbuffer1+t_clkpcb2+t_clkbuffer2+t_clkpcb3+t_data；

Wherein T ₁ is the current delay time, T _clkbuffer1 is the first delay parameter, T _clkbuffer2 is the second delay parameter, T _delay1 is the third delay parameter, T _clkpcb1 is the fourth delay parameter, T _clkpcb2 is the fifth delay parameter, T _clkpcb3 is the sixth delay parameter, and T _data is the seventh delay parameter.

The server clock architecture comprises a server main board, wherein peripheral slot positions are arranged on the server main board, and the process of determining the current delay parameter set corresponding to the clock transmission link in the clock output mode comprises the following steps:

When the clock output mode is the second output mode, acquiring the output clock skew parameter, a second delay parameter between an input end and an output end of the second-stage clock buffer, a first line delay parameter corresponding to a second transmission line between the first-stage clock buffer and the peripheral slot, a second line delay parameter corresponding to a third transmission line between the first-stage clock buffer and the chipset, a third line delay parameter corresponding to a third transmission line between the second-stage clock buffer and an external card, a seventh delay parameter corresponding to a bus data link, and an eighth delay parameter corresponding to clock delay in the chipset;

Constructing a second delay parameter set based on the output clock skew parameter, the second delay parameter, the seventh delay parameter, the eighth delay parameter, the first line delay parameter, the second line delay parameter, and the third line delay parameter;

And taking the second delay parameter set as a current delay parameter set corresponding to the clock transmission link of the second output mode.

Wherein the process of calculating the current delay time using all parameters in the current delay parameter set includes:

Establishing a second calculation relation corresponding to the chipset serving as a transmitting end and a third calculation relation corresponding to the external card serving as the transmitting end based on all parameters in the current delay parameter set;

Calculating a first delay time using the second calculation relation;

calculating a second delay time using the third calculation relation;

and taking the maximum value of the first delay time and the second delay time as the current delay time.

Wherein the second calculation relation is:

T_a=|（t_delay2+t_clkpcb4+t_data）-（t_clkpcb5+t_clkbuffer2+t_clkpcb6）|+t_clkskew；

Wherein T _a is the first delay time, T _delay2 is the eighth delay parameter, T _data is the seventh delay parameter, T _clkskew is the output clock skew parameter, T _clkbuffer2 is the second delay parameter, T _clkpcb4 is the first line delay parameter, T _clkpcb5 is the second line delay parameter, and T _clkpcb6 is the third line delay parameter.

Wherein the third calculation relation is:

T_b=|（t_delay2+t_clkpcb4）-（t_clkpcb5+t_clkbuffer2+t_clkpcb6+t_data）|+t_clkskew；

Wherein T _b is the second delay time, T _delay2 is the eighth delay parameter, T _data is the seventh delay parameter, T _clkskew is the output clock skew parameter, T _clkbuffer2 is the second delay parameter, T _clkpcb4 is the first line delay parameter, T _clkpcb5 is the second line delay parameter, and T _clkpcb6 is the third line delay parameter.

The server clock architecture comprises a server main board, and after judging whether the current transmission delay time meets the clock constraint of the server clock architecture, the configuration method further comprises the following steps:

Calculating a time difference between the current transmission delay time and a constraint time corresponding to a clock constraint of the server clock architecture;

Judging whether the time difference value is smaller than or equal to a preset difference value;

if yes, adjusting the position of the first-stage clock buffer on the server main board so that the time difference value is larger than the preset difference value.

Wherein the process of calculating the current transmission delay time of the clock transmission link in the clock output mode comprises:

And calculating the current transmission delay time of the clock transmission link when the clock output mode is adopted and the working mode of the first-stage clock buffer and the working mode of the second-stage clock buffer are both bypass modes.

The process of adjusting the working mode of the first stage clock buffer and/or the working mode of the second stage clock buffer so that the current transmission delay time of the clock transmission link in the clock output mode meets the clock constraint comprises the following steps:

Determining any one of the first stage clock buffer and the second stage clock buffer as a first adjustment buffer, and the other one as a second adjustment buffer;

Switching the working mode of the first adjustment buffer from the bypass mode to a phase-locked loop mode;

calculating the current transmission delay time of the clock transmission link when the clock output mode is adopted, the working mode of the first adjusting buffer is the phase-locked loop mode, and the working mode of the second adjusting buffer is the bypass mode;

judging whether the current transmission delay time meets the clock constraint of the server clock architecture or not;

if yes, judging that the configuration of the server clock architecture is completed;

if not, switching the working mode of the second adjusting buffer from the bypass mode to the phase-locked loop mode;

calculating the current transmission delay time of the clock transmission link when the clock output mode is set, and the working mode of the first adjusting buffer and the working mode of the second adjusting buffer are both the phase-locked loop mode;

judging whether the current transmission delay time meets the clock constraint of the server clock architecture or not;

if yes, judging that the configuration of the server clock architecture is completed;

If not, prompting configuration error information.

Wherein the process of determining either one of the first stage clock buffer and the second stage clock buffer as a first adjustment buffer and the other as a second adjustment buffer comprises:

the second stage clock buffer is determined to be a first adjustment buffer, and the first stage clock buffer is determined to be a second adjustment buffer.

To solve the above technical problem, the present invention also provides a computer program product, which includes a computer program/instruction, and the computer program/instruction implements the steps of the method for configuring a server clock architecture described in any one of the above when executed by a processor.

In order to solve the technical problem, the present invention further provides an electronic device, including:

A memory for storing a computer program;

a processor for implementing the steps of the method for configuring a server clock architecture as described in any one of the preceding claims when executing said computer program.

To solve the above technical problem, the present invention further provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor implements the steps of the method for configuring a server clock architecture as described in any one of the above.

The invention provides a server clock architecture, which comprises a main control component, a chipset, a crystal oscillator circuit and a first-stage clock buffer which are arranged on a server main board, and also comprises a second-stage clock buffer which is arranged on an external card, wherein each end device on the external card can work under the same clock signal through the two-stage clock buffer, and if the current transmission delay time of a clock transmission link does not meet the clock constraint of the server clock architecture, the internal clock delay time of the first-stage clock buffer and the second-stage clock buffer is considered to be different under different working modes, and the invention shortens the internal clock delay time of the first-stage clock buffer and/or the second-stage clock buffer by adjusting the working modes of the clock buffer, so that the clock transmission link of the server clock architecture can meet the clock constraint and simultaneously has the peripheral compatibility of adapting to peripheral slots. The invention also provides a configuration method of the server clock architecture, electronic equipment, a computer storage medium and a computer program product, and the configuration method has the same beneficial effects as the configuration method of the server clock architecture.

Drawings

For a clearer description of embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.

FIG. 1 is a schematic diagram of a first server clock architecture according to the present invention;

FIG. 2 is a schematic diagram of a second server clock architecture according to the present invention;

FIG. 3 is a schematic diagram of a third server clock architecture according to the present invention;

FIG. 4 is a flowchart illustrating a method for configuring a server clock architecture according to the present invention;

FIG. 5 is a schematic diagram of a clock transmission link under a clock output mode according to the present invention;

FIG. 6 is a schematic diagram of a clock transmission link under another clock output mode according to the present invention;

FIG. 7 is a schematic diagram of a configuration system of a server clock architecture according to the present invention;

Fig. 8 is a schematic structural diagram of an electronic device according to the present invention;

Fig. 9 is a schematic structural diagram of a computer readable storage medium according to the present invention.

Detailed Description

The core of the invention is to provide a server clock architecture, a configuration method, equipment, a product and a medium thereof, which can enable a clock transmission link of the server clock architecture to meet clock constraint and simultaneously have peripheral compatibility for adapting to peripheral slots.

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a first server clock architecture according to the present invention, where the server clock architecture includes:

Locate master control subassembly 01, chipset 02, crystal oscillator circuit 03 and first order clock buffer 04 on the server mainboard, still including locating the second level clock buffer 05 on the external card, still including the peripheral hardware trench that is used for connecting the external card on the server mainboard, wherein:

The chip set 02 is connected with the first-stage clock buffer 04 through a first transmission line, the first-stage clock buffer is connected with the peripheral slot position through a second transmission line, the second-stage clock buffer 05 is connected with the peripheral slot position through a third transmission line, the second-stage clock buffer 05 is connected with each end device of the external card, and the crystal oscillator circuit 03 is connected with the first-stage clock buffer 04 or the chip set 02;

And the master control component 01 is used for adjusting the working mode of the first-stage clock buffer 04 and/or the working mode of the second-stage clock buffer 05 when the current transmission delay time of the clock transmission link does not meet the clock constraint corresponding to the server clock architecture so as to enable the current transmission delay time of the clock transmission link to meet the clock constraint.

In this embodiment, the server clock architecture includes a master control component 01, a chipset 02, a first-stage clock buffer 04 and a crystal oscillator circuit 03 connected to the first-stage clock buffer 04 or the master control component 01, where the master control component 01 mainly includes a BMC (Baseboard Management Controller ), and the chipset 02 specifically includes a phase-locked loop, a south bridge or PCH (Platform Controller Hub, integrated south bridge chip), and the south bridge is mainly responsible for tasks such as I/O control, memory control and network control. PCH is the complex of south bridge and north bridge, its main task is to connect CPU (Central Processing Unit ), memory, south bridge and external equipment, it includes USB (Universal Serial Bus ), SATA (SERIAL ADVANCED Technology Attachment, serial advanced technology attachment, a kind of hard disk interface specification), interface such as PCIe, can realize data transmission and control between CPU, memory, south bridge and the external equipment, PCH has still integrated functions such as sound card, network card, wireless network card, can help the computer to realize functions such as multi-media, network.

The server clock architecture further comprises a second-stage clock buffer 05 arranged on the external card, correspondingly, a peripheral slot (not shown in fig. 1) for connecting the external card is further arranged on the server main board, the external card can be fixed in the peripheral slot and also can be connected to an expansion interface slot (PCIe slot) connected with the peripheral slot, the external card further comprises a plurality of end devices, the chipset 02 is connected with the plurality of end devices on the external card in a one-to-one correspondence manner through a plurality of data buses, and the external card can be specifically a PCIe expansion card, such as a memory expansion card, a network card and the like.

The crystal oscillator circuit 03 is an electronic circuit for generating stable frequency, and mainly aims to provide an accurate and stable clock signal, the crystal oscillator circuit 03 can be connected with the chip set 02 or the first-stage clock buffer 04 as shown by a dotted line in fig. 1, when the crystal oscillator circuit 03 is connected with the chip set 02, the chip set 02 outputs the clock signal for an end device on an external card, and when the crystal oscillator circuit 03 is connected with the first-stage clock buffer 04, the first-stage clock buffer 04 outputs the clock signal for an end device on the external card.

Referring to fig. 2, when the phase-locked loop in the chipset 02 is connected to the crystal oscillator circuit 03, the chipset 02 is configured to output a first clock signal, the first stage clock buffer 04 is configured to fan out multiple second clock signals according to the first clock signal, and the second stage clock buffer 05 is configured to fan out multiple third clock signals according to the second clock signal to multiple end devices on the external card, so that the multiple end devices all operate under the third clock signal.

Referring to fig. 3, when the first stage clock buffer 04 is connected to the crystal oscillator circuit 03, the first stage clock buffer 04 is configured to fan out multiple fourth clock signals according to signals output by the crystal oscillator circuit 03, the chipset 02 operates under the fourth clock signals, and the second stage clock buffer 05 is configured to fan out multiple fifth clock signals according to the fourth clock signals to the end devices on the external card, so that the plurality of end devices all operate under the fifth clock signals.

In this embodiment, considering that the internal clock transmission delay time of the first-stage clock buffer 04 and the second-stage clock buffer 05 are different in different working modes, when the current transmission delay time of the clock transmission link of the master control component 01 does not meet the clock constraint corresponding to the server clock architecture, the working modes of the first-stage clock buffer 04 and/or the second-stage clock buffer 05 are adjusted to shorten the internal clock delay time of the first-stage clock buffer 04 and/or the second-stage clock buffer 05, thereby shortening the current transmission delay time, enabling the clock transmission link of the server clock architecture to meet the clock constraint, and simultaneously having peripheral compatibility for adapting to peripheral slots.

Based on the above embodiments:

In an exemplary embodiment, the server clock architecture further includes a slave control component disposed on the external card;

The master control component 01 is specifically configured to generate a configuration instruction corresponding to a target working mode of the second-stage clock buffer 05 when the current transmission delay time of the clock transmission link does not meet the clock constraint corresponding to the server clock architecture, so that the current transmission delay time of the clock transmission link meets the clock constraint;

The slave control component is used for adjusting the current working mode of the second-stage clock buffer 05 to a target working mode according to the configuration instruction after receiving the configuration instruction;

The current transmission delay time is determined based on a first delay parameter from an input end to an output end of the second-stage clock buffer 05, and the first delay parameter of the second-stage clock buffer 05 has different corresponding durations in different working modes.

It can be understood that the master control component 01 can choose to directly adjust the working mode of the second-stage clock buffer 05 on the external card, or can choose to indirectly adjust the working mode of the second-stage clock buffer 05 on the external card, that is, the master control component 01 sends a corresponding configuration instruction to the slave control component on the external card, and the slave control component on the external card configures the working mode of the second-stage clock buffer 05 according to the configuration instruction, thereby improving the adjustment efficiency. The slave control component comprises, but is not limited to, a singlechip on an external card, an MCU (Microcontroller Unit, micro control unit), a BMC and the like.

The clock buffer modes of the PCIe bus include bypass (bypass) mode and Phase-Locked Loop (PLL) mode. The bypass mode produces an output with a greater delay (delay) relative to the input clock than the phase-locked loop mode, typically two to three orders of magnitude. With PCIe bus rate upgrades, PCIe clock device performance metrics are also increasing, with current clock buffers being delayed in bypass mode by about a few nanoseconds (ns). The delay of the phase-locked loop mode is about several hundred femtoseconds (fs), or a negative delay (i.e., output phase lead). The clock jitter (jitter) introduced by the bypass mode is smaller than that of the pll mode, and generally differs by one to two orders of magnitude, the clock jitter jitter (cycle to cycle) generated by the bypass mode is about several hundred femtoseconds (fs) to several tens picoseconds (ps), the clock jitter generated by the pll mode is about several tens to several hundred picoseconds (ps), on the basis, the configuration instruction in the embodiment includes a first configuration instruction configured as the bypass mode and a second configuration instruction configured as the pll mode, after receiving the first configuration instruction, the slave control component determines whether the current working mode of the second stage clock buffer 05 is the bypass mode, if yes, no adjustment is made, the bypass mode is maintained, and if not, the current working mode of the second stage clock buffer 05 is adjusted to be the bypass mode. Correspondingly, after receiving the second configuration instruction, the slave control component determines whether the current working mode of the second stage clock buffer 05 is a phase-locked loop mode, if so, the slave control component does not adjust the current working mode of the second stage clock buffer 05 and maintains the phase-locked loop mode, and if not, the slave control component adjusts the current working mode of the second stage clock buffer 05 to be the phase-locked loop mode.

In a second aspect, the present invention further provides a method for configuring a server clock architecture, where the server clock architecture is a server clock architecture as described in any one of the foregoing embodiments, please refer to fig. 4, and fig. 4 is a flowchart illustrating steps of a method for configuring a server clock architecture according to the present invention, where the method includes:

S101: determining a clock output mode of a server clock architecture; the clock output mode is a first output mode corresponding to a chipset output clock signal in the server clock architecture or a second output mode corresponding to a first stage clock buffer output clock signal in the server clock architecture;

It will be appreciated that the server clock architecture includes at least two clock output modes, the clock output mode of the chipset outputting the clock signal is the first output mode, the clock output mode of the first stage clock buffer outputting the clock signal is the second output mode, the crystal oscillator circuit is connected with the phase-locked loop in the chipset when the chipset outputting the clock signal, as shown in fig. 5, and the crystal oscillator circuit is connected with the first stage clock buffer when the first stage clock buffer outputting the clock signal, as shown in fig. 6.

Referring to fig. 5, in the first output mode, a clock signal is output from the chipset and transmitted to the first stage clock buffer, then the first stage clock buffer is fanned out to each second stage clock buffer, finally the second stage clock buffer is fanned out to each end device, and the transmission path of the clock signal is from the chipset to the first stage clock buffer to the second stage clock buffer to the end device.

Referring to fig. 6, in the second output mode, the first stage clock buffer outputs a clock signal to the second stage clock buffer and the chipset, and the second stage clock buffer fans out to each end device, and the transmission path of the clock signal is from the first stage clock buffer to the second stage clock buffer to the end device.

In different clock output modes, the transmission paths of the clock signals are different, and the delay parameters and the calculation modes for calculating the delay time are also different, so that the delay time of the clock transmission link is different.

S102: calculating the current transmission delay time of the clock transmission link in the clock output mode; the current transmission delay time is determined based on a first delay parameter from an input end to an output end of a second-stage clock buffer in the server clock architecture;

In this embodiment, first, all parameters that may cause delay in clock signal transmission on a clock transmission link in a clock output mode are determined, including but not limited to delay parameters corresponding to a transmission line, delay parameters from an input end to an output end of a clock buffer, etc., where the delay parameters from the input end to the output end of the clock buffer are determined based on the working mode of the clock buffer, and in different working modes, durations corresponding to the delay parameters from the input end to the output end of the clock buffer are different.

S103: judging whether the current transmission delay time meets the clock constraint of the server clock architecture, if not, executing S104, if so, executing S105;

S104: adjusting the working mode of the first-stage clock buffer and/or the working mode of the second-stage clock buffer; the corresponding time length of the first delay parameter of the second-stage clock buffer in different working modes is different, and then S102 is repeated;

S105: it is determined that the server clock architecture configuration is complete.

In this embodiment, first, it is determined whether the current delay time is less than a preset constraint time, the preset constraint time is determined based on a bus type, the bus type is assumed to be a PCIe bus, the preset constraint time is 12ns, if the current delay time is less than 12ns, it is determined that the current transmission delay time meets the clock constraint of the server clock architecture, at this time, the configuration of the server clock architecture is completed, each stage of clock buffer works in the current working mode, if the current delay time is not less than the preset constraint time, it is determined that the current transmission delay time does not meet the clock constraint of the server clock architecture, at this time, the server clock architecture needs to be adjusted. In this embodiment, the time length corresponding to the delay parameter from the input end to the output end of the clock buffer is considered to be different in different working modes, and the current transmission delay time includes the delay time from the input end to the output end of the clock buffer.

It can be understood that in the first transmission mode, since the clock signal is output by the chipset, the delay time from the input to the output of the first stage clock buffer needs to be considered when calculating the current delay time, and in the second transmission mode, since the clock signal is output by the first stage clock buffer, the delay time from the input to the output of the first stage clock buffer does not need to be considered when calculating the current delay time, that is, the working mode of the second stage clock buffer can be preferentially adjusted in the second transmission mode.

In this embodiment, the current clock output mode adopted by the server clock architecture is determined, and the clock signal is output by the chipset or output by the first-stage clock buffer, so that in different output modes, due to different transmission paths of the clock signal, the current transmission delay time of the clock transmission link is different, the current transmission delay time of the clock transmission link in the clock output mode is calculated, whether the current transmission delay time meets the clock constraint of the server clock architecture is judged, and if the current transmission delay time does not meet the clock constraint, the clock delay difference between the first-stage clock buffer and the second-stage clock buffer in different working modes is considered.

Based on the above embodiments:

In an exemplary embodiment, the process of calculating the current transmission delay time of the clock transmission link in the clock output mode includes:

Determining a current delay parameter set corresponding to a clock transmission link in a clock output mode; when the clock output mode is a first output mode, the current delay parameter set is a first delay parameter set, and the first delay parameter set comprises a second delay parameter from the input end to the output end of the first stage clock buffer and a first delay parameter from the input end to the output end of the second stage clock buffer; when the clock output mode is the second output mode, the current delay parameter set is a second delay parameter set, and the second delay parameter set comprises an output clock skew parameter and a first delay parameter from the input end to the output end of the second-stage clock buffer;

the current delay time is calculated using all parameters in the current delay parameter set.

In this embodiment, in each clock output mode, a delay parameter set is established based on all possible delay parameters on the clock transmission link, the clock output mode corresponds to the delay parameter set one by one, each delay parameter in the delay parameter set corresponding to the clock output mode is used to calculate the current delay time, and accuracy of a calculation result of the current delay time is improved.

It can be appreciated that in the first output mode, since the transmission path of the clock signal includes the chipset to the first stage clock buffer to the second stage clock buffer, in order to improve the accuracy of the calculation result of the current delay time in the first transmission mode, the corresponding first delay parameter set needs to include the second delay parameter from the input end to the output end of the first stage clock buffer and the first delay parameter from the input end to the output end of the second stage clock buffer. In the second output mode, the transmission path of the clock signal does not include the path from the chipset to the first stage clock buffer, so that the second delay parameter from the input end to the output end of the first stage clock buffer is not required to be used as one delay parameter in the second delay parameter set.

In an exemplary embodiment, the process of determining a current set of delay parameters for a clock transmission link in a clock output mode includes:

when the clock output mode is a first output mode, acquiring a second delay parameter from the input end to the output end of the first-stage clock buffer, a first delay parameter from the input end to the output end of the second-stage clock buffer, a third delay parameter from a phase-locked loop in the chipset to an output pin of the chipset, a fourth delay parameter corresponding to a first transmission line between the chipset and the first-stage clock buffer, a fifth delay parameter corresponding to a second transmission line between the first-stage clock buffer and a peripheral slot position, a sixth delay parameter corresponding to a third transmission line between the second-stage clock buffer and end equipment on an external card, and a seventh delay parameter corresponding to a bus data link;

Constructing a first delay parameter set based on the first delay parameter, the second delay parameter, the third delay parameter, the fourth delay parameter, the fifth delay parameter, the sixth delay parameter and the seventh delay parameter;

And taking the first delay parameter set as a current delay parameter set corresponding to the clock transmission link of the first output mode.

Referring to fig. 5, the clock signal is multiplied by a phase-locked loop inside the chipset and output to the PCIe physical layer (PHY), while the output clock is used by the external device of PCIe, where delay parameters related to the clock transmission link include, but are not limited to:

the clock delay time t _delay1 from the phase-locked loop in the chipset to the output pin, i.e. the third delay parameter, is denoted by t _d1 in fig. 5;

The chipset outputs a clock signal to the first stage clock buffer for a delay time t _clkpcb1, which is a fourth delay parameter, and is denoted by t _p1 in fig. 5;

The delay time t _clkbuffer1 from the input end to the output end of the first stage clock buffer, namely a second delay parameter, which is denoted by t _b1 in fig. 5, has an order of magnitude difference between the bypass mode and the phase-locked loop mode;

The delay time t _clkpcb2 from the first-stage clock buffer to the PCB line of the peripheral slot of PCIe, namely a fifth delay parameter, which is denoted by t _p2 in FIG. 5;

The delay time t _clkbuffer2 from the input end to the output end of the second-stage clock buffer on the peripheral card, namely a first delay parameter, denoted by t _b2 in fig. 5, has an order of magnitude difference between the bypass mode and the phase-locked loop mode, and if the peripheral card is a single PCIe end device, the peripheral card does not have the second-stage clock buffer;

The delay time t _clkpcb3 from the second-stage clock buffer on the peripheral card to the PCB circuit of the end device on the peripheral card, namely, the sixth delay parameter, denoted by t _p3 in fig. 5, can be understood that the circuit on the peripheral card is shorter, and the parameter is smaller than the delay generated by the circuit of the computer motherboard and the clock buffer itself;

The delay time t _data of the bus data link, the seventh delay parameter, is denoted t _d in fig. 5.

And combining all the delay parameters into a first delay parameter set.

It can be understood that the PCIe data transceiving relation between the chipset and the external device is mutual, that is, when the chipset is used as a transmitting end, the PCIe card peripheral is used as a receiving end, and vice versa, the external card is used as the transmitting end in the case that the clock transmission link delay in the clock output mode is seriously degraded, and the chipset is used as the receiving end, where the process of calculating the current delay time by using all parameters in the current delay parameter set includes:

Establishing a first calculation relation based on all parameters in the current delay parameter set;

calculating the current delay time by using a first calculation relation;

The first calculation relation is T ₁=t_delay1+t_clkpcb1+t_clkbuffer1+t_clkpcb2+t_clkbuffer2+t_clkpcb3+t_data;

Wherein T ₁ is the current delay time, T _clkbuffer1 is the first delay parameter, T _clkbuffer2 is the second delay parameter, T _delay1 is the third delay parameter, T _clkpcb1 is the fourth delay parameter, T _clkpcb2 is the fifth delay parameter, T _clkpcb3 is the sixth delay parameter, and T _data is the seventh delay parameter. Wherein T ₁ needs to be less than 12ns.

T₁=t_delay1+t_clkpcb1+t_clkbuffer1+t_clkpcb2+t_clkbuffer2+t_clkpcb3+t_data；

Accordingly, the clock delay from the intra-chipset pll to the chipset PCIe physical layer PHY:

T₂=t'_delay1。

Further description is made of PCIe clock quality constraints:

The PCIe bus standard clock parameter has a strict standard, and the standard gives a clock jitter calculation model under a common clock topology, and a jitter relation of clock signals on two transmission links is:

X_cc1(s)=X(s)×[H₁(s)×e^-sT-H₂(s)]×H₃(s)；

X_cc2(s)=X(s)×[H₂(s)×e^-sT-H₁(s)]×H₃(s)；

X _cc1(s) is the jitter of the clock signal on the first transmission link, X _cc2(s) is the jitter of the clock signal on the second transmission link, wherein X(s) is the jitter of the reference clock signal, H ₁(s) is the phase-locked loop transfer function of the transmitting end, H ₂(s) is the phase-locked loop transfer function of the receiving end, H ₃(s) is the transfer function of the CDR (Clock Data Recovery, clock recovery module) of the receiving end, and T is the absolute value (the positive number) of the delay time difference of the two links, i.e.:

T=|T₁-T₂|；

From the above, the jitter of the reference clock at the receiving end is X _cc1(s) and X _cc2( s) relative to the maximum MAX [ X _cc1(s),X_cc2( s ].

Based on the jitter relation of clock signals on two transmission links, physical layer phase-locked loop parameters H ₁(s)、H₂(s) of different PCIe devices are considered to be constrained in a small range according to physical layer parameters designed by PCIe bus specifications, and the parameters are close, so that when the parameter T (T= |T ₁-T₂ |) is close to 0, the delay element e ^-sT is close to 1, and the clock jitter X _cc1(s) and X _cc2(s) are minimum.

Generally, the chip interior t _delay1 and t' _delay1 are close to each other, resulting in:

T=t_clkpcb1+t_clkbuffer1+t_clkpcb2+t_clkbuffer2+t_clkpcb3+t_data。

In an exemplary embodiment, the process of determining a current set of delay parameters for a clock transmission link in a clock output mode includes:

When the clock output mode is a second output mode, acquiring output clock skew parameters, second delay parameters between an input end and an output end of a second-stage clock buffer, first line delay parameters corresponding to a second transmission line between a first-stage clock buffer and peripheral slots, second line delay parameters corresponding to a third transmission line between the first-stage clock buffer and a chipset, third line delay parameters corresponding to a third transmission line between the second-stage clock buffer and an external card, seventh delay parameters corresponding to a bus data link, and eighth delay parameters corresponding to clock delay in the chipset;

Constructing a second delay parameter set based on the output clock skew parameter, the second delay parameter, the seventh delay parameter, the eighth delay parameter, the first line delay parameter, the second line delay parameter, and the third line delay parameter;

And taking the second delay parameter set as the current delay parameter set corresponding to the clock transmission link of the second output mode.

In this embodiment, referring to fig. 6, the first stage clock buffer fans out clock signals to the chipset and the peripheral slot respectively, and the delay time of the input and output of the first stage clock buffer is not paid attention to any more, but a parameter t _clkskew is required to be paid attention to, and is denoted by t _s in fig. 6, and the parameter is a phase difference between output clocks, namely, output clock skew;

in addition to the output clock skew, delay parameters involved in its clock transmission link include, but are not limited to:

the clock delay time t _delay2, the eighth delay parameter, denoted by t _d2 in fig. 6, is mainly focused on the IBIS (Input/Output Buffer Information Specification, input/output buffer) parameter of the chipset, and the clock routing to the chipset needs to fan out to multiple PCIe physical layers, thus including the delay of the intra-chipset buffer;

the first stage clock buffer to chipset PCB line delay time t _clkpcb4, the second line delay parameter, denoted as t _p4 in FIG. 6;

The first stage clock buffer to peripheral slot PCB line delay time t _clkpcb5, the first line delay parameter, is denoted as t _p5 in fig. 6.

The input-to-output delay time t _clkbuffer2 of the second-stage clock buffer on the external card is the second delay parameter, the parameter has the order of magnitude difference in the bypass mode and the phase-locked loop mode, and if the peripheral card is a single PCIe terminal device, the clock buffer is not present;

The delay time t _clkpcb6 from the second stage clock buffer on the external card to the PCB line of the end device on the external card, namely the third line delay parameter, indicated by t _p6 in FIG. 6, is shorter in the general line on the external card and is smaller than the delay generated by the line and the clock buffer of the computer main board;

The bus data link delay time t _data, the seventh delay parameter, is denoted t _d in fig. 6.

And forming a second delay parameter set based on the parameters.

In summary, in the clock output mode, one path of the clock transmission link of the first-stage clock buffer is directly connected to the chipset, the delay of the clock transmission link can be evaluated through an IBIS model and a PCB wiring of the chip, and the other path of the clock transmission link is connected to a PCIe peripheral slot or is degraded and delayed through the second-stage clock buffer, so that the delay of a single link needs to be less than 12ns.

When the chipset is the transmitting end:

T_a=|（t_delay2+t_clkpcb4+t_data）-（t_clkpcb5+t_clkbuffer2+t_clkpcb6）|+t_clkskew；

when the external card is a transmitting end:

T_b=|（t_delay2+t_clkpcb4）-（t_clkpcb5+t_clkbuffer2+t_clkpcb6+t_data）|+t_clkskew；

the clock skew t _clkskew is a positive value, and is a parameter for degrading delay and clock jitter, and the most degradation condition of the delay of the whole clock transmission link is obtained:

T_max=MAX[T_a,T_b]。

The current delay times in this embodiment are all calculated under the most degraded delay condition. In an exemplary embodiment, after determining whether the current transmission delay time satisfies the clock constraint of the server clock architecture, the configuration method further includes:

Calculating a time difference between the current transmission delay time and constraint time corresponding to clock constraint of the server clock architecture;

Judging whether the time difference value is smaller than or equal to a preset difference value;

if yes, the position of the first-stage clock buffer on the server main board is adjusted so that the time difference value is larger than a preset difference value.

In this embodiment, in order to further reduce the delay of the always-transmitting link, the position of the first-stage clock buffer is further adjusted, specifically, under the condition that it is determined that the current transmission time delay meets the always constraint, the time difference between the current transmission delay time and the constraint time corresponding to the clock constraint of the server clock architecture is determined, if the time difference is smaller, the position of the first-stage clock buffer may be adjusted at this time to further reduce the current transmission delay time, for example, if the preset difference is 1ns, and if the current transmission delay time is 11ns and the preset constraint time is 12ns, the time difference between the current transmission delay time and the constraint time is less than or equal to 1ns, and at this time, the position of the first-stage clock buffer is adjusted.

In the first output mode, the first-stage clock buffer is located between the chipset and the peripheral slot, so that the delay can be reduced by reducing t _clkpcb1+t_clkpcb2, the clock jitter is improved, and for the design of the motherboard, the first-stage clock buffer is relatively close to the chipset and is far away from the PCIe card slot, and vice versa, and the delay is shortest by considering both.

In the second output mode, under the conditions that the positions of the chip set and the peripheral slots on the server main board are determined and the length of the PCIe data link is determined, the position of the first-stage clock buffer can be adjusted to optimize PCIe clock jitter, namely, two variable parameters of T _clkpcb4 and T _clkpcb are adjusted to minimize the value of T _max.

In another exemplary embodiment, the clock buffer output multiple clock skew t _clkskew,t_clkskew is a parameter of degradation delay and clock jitter, which is the smaller and the better when the device is selected.

In an exemplary embodiment, the process of calculating the current transmission delay time of the clock transmission link in the clock output mode includes:

And calculating the current transmission delay time of the clock transmission link when the clock output mode is adopted and the working mode of the first-stage clock buffer and the working mode of the second-stage clock buffer are both bypass modes.

It is understood that the clock buffer of the PCIe bus includes two configurations: bypass (bypass) mode and Phase-Locked Loop (PLL) mode. The bypass mode produces an output with a greater delay (delay) relative to the input clock than the phase-locked loop mode, typically two to three orders of magnitude. With PCIe bus rate upgrades, PCIe clock device performance metrics are also increasing, with current clock buffers being delayed in bypass mode by about a few nanoseconds (ns). The delay of the phase-locked loop mode is about several hundred femtoseconds (fs), or a negative delay (i.e., output phase lead). The clock jitter (jitter) introduced by the bypass mode is small relative to the phase-locked loop mode, typically differing by one to two orders of magnitude, with the clock jitter jitter (cycle to cycle) generated by the bypass mode being on the order of several hundred femtoseconds (fs) to several tens of picoseconds (ps), and the clock jitter generated by the phase-locked loop mode being on the order of several tens to several hundred picoseconds (ps). Because the clock jitter introduced by the bypass mode is smaller than that of the phase-locked loop mode, the working modes of the two-stage clock buffer are configured into the bypass mode, the current transmission delay time is calculated in the bypass mode, and if the current transmission delay time meets the clock constraint, the clock jitter of the transmission link is relatively smaller, so that the reliability of clock transmission is improved.

In an exemplary embodiment, the process of adjusting the operation mode of the first stage clock buffer and/or the operation mode of the second stage clock buffer such that the current transmission delay time of the clock transmission link in the clock output mode satisfies the clock constraint includes:

determining any one of the first stage clock buffer and the second stage clock buffer as a first adjustment buffer, and the other one as a second adjustment buffer;

Switching the working mode of the first adjusting buffer from a bypass mode to a phase-locked loop mode;

calculating the current transmission delay time of the clock transmission link when the clock output mode is adopted, the working mode of the first adjusting buffer is a phase-locked loop mode, and the working mode of the second adjusting buffer is a bypass mode;

judging whether the current transmission delay time meets the clock constraint of the server clock architecture or not;

if yes, judging that the configuration of the clock architecture of the server is completed;

If not, switching the working mode of the second adjusting buffer from a bypass mode to a phase-locked loop mode;

calculating the current transmission delay time of the clock transmission link when the clock output mode is adopted and the working modes of the first adjusting buffer and the second adjusting buffer are both phase-locked loop modes;

judging whether the current transmission delay time meets the clock constraint of the server clock architecture or not;

if yes, judging that the configuration of the clock architecture of the server is completed;

If not, prompting configuration error information.

In this embodiment, when the two clock buffers are both in the bypass mode, first, one of the two clock buffers is determined to be a first adjustment buffer, and the other is determined to be a second adjustment buffer. The working mode of the first adjusting buffer is adjusted to be a phase-locked loop mode, after the working mode is adjusted to be the phase-locked loop mode, the delay time from the input to the output of the first adjusting buffer is reduced, at the moment, the current transmission delay time of the clock transmission link is recalculated, if the current transmission delay time meets the clock constraint, the completion of the configuration of the clock architecture of the server is judged, because the second adjusting buffer is still in a bypass mode, only one stage of clock buffer is adjusted to be the phase-locked loop mode, compared with two stages of clock buffers, the second adjusting buffer has lower clock jitter, if the one stage of phase-locked loop mode does not enable the current transmission delay to meet the clock constraint, at the moment, the working mode of the second adjusting buffer is also adjusted to be the phase-locked loop mode, the delay time from the input to the output of the second adjusting buffer is reduced, and if the two stages of phase-locked loop mode still enable the current transmission delay time to meet the clock constraint, configuration error information is prompted, and the engineer can conduct targeted processing.

In an exemplary embodiment, the determining of either one of the first stage clock buffer and the second stage clock buffer as the first adjustment buffer, and the other as the second adjustment buffer includes:

the second stage clock buffer is determined as a first trim buffer and the first stage clock buffer is determined as a second trim buffer.

Considering that the adjustment flexibility of the second-stage clock buffer on the external card is relatively high, the second-stage clock buffer is determined to be the first adjustment buffer in the embodiment, and the second-stage clock buffer is preferentially adjusted in working mode, so that the adjustment efficiency is improved.

In a third aspect, referring to fig. 7, fig. 7 is a schematic structural diagram of a configuration system of a server clock architecture according to the present invention, where the server clock architecture is a server clock architecture as described in any one of the above embodiments, and the configuration system includes:

A determining module 11, configured to determine a clock output mode of a server clock architecture; the clock output mode is a first output mode corresponding to a chipset output clock signal in the server clock architecture or a second output mode corresponding to a first stage clock buffer output clock signal in the server clock architecture;

a first calculation module 12 for calculating a current transmission delay time of the clock transmission link in the clock output mode; the current transmission delay time is determined based on a first delay parameter from an input end to an output end of a second-stage clock buffer in the server clock architecture;

the first judging module 13 judges whether the current transmission delay time meets the clock constraint of the server clock architecture, if not, a first trigger instruction is generated;

The first adjusting module 14 is configured to adjust an operation mode of the first stage clock buffer and/or an operation mode of the second stage clock buffer after receiving the first trigger instruction, so that a current transmission delay time of the clock transmission link in the clock output mode meets a clock constraint; the first delay parameters of the second stage clock buffer have different durations corresponding to different working modes.

In an exemplary embodiment, the process of calculating the current transmission delay time of the clock transmission link in the clock output mode includes:

Determining a current delay parameter set corresponding to a clock transmission link in a clock output mode; when the clock output mode is a first output mode, the current delay parameter set is a first delay parameter set, and the first delay parameter set comprises a second delay parameter from the input end to the output end of the first stage clock buffer and a first delay parameter from the input end to the output end of the second stage clock buffer; when the clock output mode is the second output mode, the current delay parameter set is a second delay parameter set, and the second delay parameter set comprises an output clock skew parameter and a first delay parameter from the input end to the output end of the second-stage clock buffer;

the current delay time is calculated using all parameters in the current delay parameter set.

In an exemplary embodiment, the process of determining a current set of delay parameters for a clock transmission link in a clock output mode includes:

when the clock output mode is a first output mode, acquiring a second delay parameter from the input end to the output end of the first-stage clock buffer, a first delay parameter from the input end to the output end of the second-stage clock buffer, a third delay parameter from a phase-locked loop in the chipset to an output pin of the chipset, a fourth delay parameter corresponding to a first transmission line between the chipset and the first-stage clock buffer, a fifth delay parameter corresponding to a second transmission line between the first-stage clock buffer and a peripheral slot position, a sixth delay parameter corresponding to a third transmission line between the second-stage clock buffer and end equipment on an external card, and a seventh delay parameter corresponding to a bus data link;

Constructing a first delay parameter set based on the first delay parameter, the second delay parameter, the third delay parameter, the fourth delay parameter, the fifth delay parameter, the sixth delay parameter and the seventh delay parameter;

And taking the first delay parameter set as a current delay parameter set corresponding to the clock transmission link of the first output mode.

In an exemplary embodiment, the process of calculating the current delay time using all parameters of the current delay parameter set includes:

Establishing a first calculation relation based on all parameters in the current delay parameter set;

calculating the current delay time by using a first calculation relation;

the first calculation relation is:

T₁=t_delay1+t_clkpcb1+t_clkbuffer1+t_clkpcb2+t_clkbuffer2+t_clkpcb3+t_data；

Wherein T ₁ is the current delay time, T _clkbuffer1 is the first delay parameter, T _clkbuffer2 is the second delay parameter, T _delay1 is the third delay parameter, T _clkpcb1 is the fourth delay parameter, T _clkpcb2 is the fifth delay parameter, T _clkpcb3 is the sixth delay parameter, and T _data is the seventh delay parameter.

In an exemplary embodiment, the process of determining a current set of delay parameters for a clock transmission link in a clock output mode includes:

When the clock output mode is a second output mode, acquiring output clock skew parameters, second delay parameters between an input end and an output end of a second-stage clock buffer, first line delay parameters corresponding to a second transmission line between a first-stage clock buffer and peripheral slots, second line delay parameters corresponding to a third transmission line between the first-stage clock buffer and a chipset, third line delay parameters corresponding to a third transmission line between the second-stage clock buffer and an external card, seventh delay parameters corresponding to a bus data link, and eighth delay parameters corresponding to clock delay in the chipset;

Constructing a second delay parameter set based on the output clock skew parameter, the second delay parameter, the seventh delay parameter, the eighth delay parameter, the first line delay parameter, the second line delay parameter, and the third line delay parameter;

And taking the second delay parameter set as the current delay parameter set corresponding to the clock transmission link of the second output mode.

In an exemplary embodiment, the process of calculating the current delay time using all parameters of the current delay parameter set includes:

establishing a second calculation relation corresponding to the chipset serving as a transmitting end and a third calculation relation corresponding to the external card serving as the transmitting end based on all parameters in the current delay parameter set;

Calculating a first delay time by using a second calculation relation;

Calculating a second delay time by using a third calculation relation;

And taking the maximum value of the first delay time and the second delay time as the current delay time.

In an exemplary embodiment, the second computational relationship is:

T_a=|（t_delay2+t_clkpcb4+t_data）-（t_clkpcb5+t_clkbuffer2+t_clkpcb6）|+t_clkskew；

Wherein T _a is a first delay time, T _delay2 is an eighth delay parameter, T _data is a seventh delay parameter, T _clkskew is an output clock skew parameter, T _clkbuffer2 is a second delay parameter, T _clkpcb4 is a first line delay parameter, T _clkpcb5 is a second line delay parameter, and T _clkpcb6 is a third line delay parameter.

In an exemplary embodiment, the third computational relationship is:

T_b=|（t_delay2+t_clkpcb4）-（t_clkpcb5+t_clkbuffer2+t_clkpcb6+t_data）|+t_clkskew；

Wherein T _b is the second delay time, T _delay2 is the eighth delay parameter, T _data is the seventh delay parameter, T _clkskew is the output clock skew parameter, T _clkbuffer2 is the second delay parameter, T _clkpcb4 is the first line delay parameter, T _clkpcb5 is the second line delay parameter, and T _clkpcb6 is the third line delay parameter.

In an exemplary embodiment, the configuration system further comprises:

The second calculation module is used for calculating the time difference between the current transmission delay time and the constraint time corresponding to the clock constraint of the server clock architecture;

The second judging module is used for judging whether the time difference value is smaller than or equal to a preset difference value, and if so, generating a second trigger instruction;

and the second adjusting module is used for adjusting the position of the first-stage clock buffer on the server main board after receiving the second trigger instruction so that the time difference value is larger than a preset difference value.

In an exemplary embodiment, the process of calculating the current transmission delay time of the clock transmission link in the clock output mode includes:

And calculating the current transmission delay time of the clock transmission link when the clock output mode is adopted and the working mode of the first-stage clock buffer and the working mode of the second-stage clock buffer are both bypass modes.

In an exemplary embodiment, the process of adjusting the operation mode of the first stage clock buffer and/or the operation mode of the second stage clock buffer such that the current transmission delay time of the clock transmission link in the clock output mode satisfies the clock constraint includes:

determining any one of the first stage clock buffer and the second stage clock buffer as a first adjustment buffer, and the other one as a second adjustment buffer;

Switching the working mode of the first adjusting buffer from a bypass mode to a phase-locked loop mode;

calculating the current transmission delay time of the clock transmission link when the clock output mode is adopted, the working mode of the first adjusting buffer is a phase-locked loop mode, and the working mode of the second adjusting buffer is a bypass mode;

judging whether the current transmission delay time meets the clock constraint of the server clock architecture or not;

if yes, judging that the configuration of the clock architecture of the server is completed;

If not, switching the working mode of the second adjusting buffer from a bypass mode to a phase-locked loop mode;

calculating the current transmission delay time of the clock transmission link when the clock output mode is adopted and the working modes of the first adjusting buffer and the second adjusting buffer are both phase-locked loop modes;

judging whether the current transmission delay time meets the clock constraint of the server clock architecture or not;

if yes, judging that the configuration of the clock architecture of the server is completed;

If not, prompting configuration error information.

In an exemplary embodiment, the determining of either one of the first stage clock buffer and the second stage clock buffer as the first adjustment buffer, and the other as the second adjustment buffer includes:

the second stage clock buffer is determined as a first trim buffer and the first stage clock buffer is determined as a second trim buffer.

In a fourth aspect, the present invention also provides a computer program product comprising computer programs/instructions which, when executed by a processor, implement the steps of the method of configuring a server clock architecture as described in any one of the embodiments above.

For an introduction to a computer program product provided by the present invention, reference should be made to the above embodiments, and the disclosure is not repeated here.

The computer program product provided by the invention has the same beneficial effects as the configuration method of the server clock architecture.

In a fifth aspect, referring to fig. 8, the present invention further provides an electronic device, including:

a memory 21 for storing a computer program;

A processor 22 for implementing the steps of the method of configuring a server clock architecture as described in any one of the embodiments above when executing a computer program.

The electronic device further includes:

The input interface 23 is connected to the processor 22 via the communication bus 26 for obtaining externally imported computer programs, parameters and instructions, which are stored in the memory 21 under control of the processor 22. The input interface may be coupled to an input device for receiving parameters or instructions manually entered by a user. The input device can be a touch layer covered on a display screen, or can be a key, a track ball or a touch pad arranged on a terminal shell.

A display unit 24 is coupled to the processor 22 via a communication bus 26 for displaying data transmitted by the processor 22. The display unit may be a liquid crystal display or an electronic ink display, etc.

The network port 25 is connected to the processor 22 via the communication bus 26 for communication connection with external terminal devices. The communication technology adopted by the communication connection can be a wired communication technology or a wireless communication technology, such as a mobile high-definition link technology, a universal serial bus, a high-definition multimedia interface, a wireless fidelity technology, a Bluetooth communication technology, a low-power consumption Bluetooth communication technology, an IEEE802.11 s-based communication technology and the like.

For an introduction of an electronic device provided by the present invention, refer to the above embodiment, and the disclosure is not repeated here.

The electronic equipment provided by the invention has the same beneficial effects as the configuration method of the server clock architecture.

In a sixth aspect, referring to fig. 9, the present invention further provides a computer readable storage medium 30, where a computer program 31 is stored on the computer readable storage medium 30, and the computer program 31 implements the steps of the method for configuring a server clock architecture as described in any one of the embodiments above when executed by a processor.

Wherein the computer-readable storage medium 30 may comprise: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

For an introduction to a computer readable storage medium provided by the present invention, refer to the above embodiments, and the disclosure is not repeated here.

The computer readable storage medium provided by the invention has the same beneficial effects as the configuration method of the server clock architecture.

It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (19)

1. The utility model provides a server clock framework which characterized in that, including locating main control module, chipset, crystal oscillator circuit and the first level clock buffer on the server mainboard, still including locating the second level clock buffer on the external card, still including being used for connecting on the server mainboard the peripheral hardware trench of external card, wherein:

The chip set is connected with the first-stage clock buffer through a first transmission line, the first-stage clock buffer is connected with the peripheral slot through a second transmission line, the second-stage clock buffer is connected with the peripheral slot through a third transmission line, the second-stage clock buffer is connected with each end device of the external card, and the crystal oscillator circuit is connected with the first-stage clock buffer or the chip set;

The master control component is configured to adjust a working mode of the first stage clock buffer and/or a working mode of the second stage clock buffer when a current transmission delay time of a clock transmission link of the server clock architecture does not meet a clock constraint corresponding to the server clock architecture, so that the current transmission delay time of the clock transmission link meets the clock constraint.

2. The server clock architecture of claim 1, further comprising a slave control component disposed on the add-on card;

The master control component is specifically configured to generate a configuration instruction corresponding to a target working mode of the second stage clock buffer when a current transmission delay time of a clock transmission link of the server clock architecture does not meet a clock constraint corresponding to the server clock architecture, so that the current transmission delay time of the clock transmission link meets the clock constraint;

The slave control component is used for adjusting the current working mode of the second-stage clock buffer to the target working mode according to the configuration instruction after receiving the configuration instruction;

The current transmission delay time of the clock transmission link is determined based on a first delay parameter from the input end to the output end of the second-stage clock buffer, and the first delay parameter of the second-stage clock buffer has different corresponding durations in different working modes.

3. The server clock architecture of claim 1 or 2, wherein the chipset is connected to the crystal oscillator circuit;

the chip set is used for outputting a first clock signal according to the signal output by the crystal oscillator circuit;

the first stage clock buffer is used for fanning out a plurality of second clock signals according to the first clock signals;

the second stage clock buffer is configured to fan out a plurality of third clock signals to a plurality of end devices on the external card according to the second clock signal, so that the plurality of end devices all work under the third clock signals.

4. The server clock architecture of claim 1 or 2, wherein the first stage clock buffer is connected to the crystal oscillator circuit;

The first-stage clock buffer is used for fanning out a plurality of fourth clock signals according to signals output by the crystal oscillator circuit;

The chipset is used for working under the fourth clock signal;

The second stage clock buffer is configured to fan out a plurality of fifth clock signals to the end devices on the external card according to the fourth clock signal, so that a plurality of the end devices all work under the fifth clock signals.

5. A method for configuring a server clock architecture, wherein the server clock architecture is the server clock architecture according to any one of claims 1 to 4, the method comprising:

Determining a clock output mode of the server clock architecture; the clock output mode is a first output mode corresponding to a chip group output clock signal in the server clock architecture or a second output mode corresponding to a first stage clock buffer in the server clock architecture outputting the clock signal;

Calculating the current transmission delay time of the clock transmission link in the clock output mode; the current transmission delay time is determined based on a first delay parameter from an input end to an output end of a second-stage clock buffer in the server clock architecture;

judging whether the current transmission delay time meets the clock constraint of the server clock architecture or not;

If not, adjusting the working mode of the first-stage clock buffer and/or the working mode of the second-stage clock buffer so that the current transmission delay time of the clock transmission link in the clock output mode meets the clock constraint; the first delay parameters of the second-stage clock buffer have different corresponding durations in different working modes.

6. The method of claim 5, wherein calculating a current transmission delay time of the clock transmission link in the clock output mode comprises:

Determining a current delay parameter set corresponding to a clock transmission link in the clock output mode; when the clock output mode is the first output mode, the current delay parameter set is a first delay parameter set, and the first delay parameter set comprises a second delay parameter from the input end to the output end of the first stage clock buffer and a first delay parameter from the input end to the output end of the second stage clock buffer; when the clock output mode is the second output mode, the current delay parameter set is a second delay parameter set, and the second delay parameter set comprises an output clock skew parameter and a first delay parameter from the input end to the output end of the second-stage clock buffer;

the current delay time is calculated using all parameters in the current delay parameter set.

7. The method for configuring a server clock architecture according to claim 6, wherein the server clock architecture includes a server motherboard, and the server motherboard is provided with a peripheral slot, and the process of determining the current delay parameter set corresponding to the clock transmission link in the clock output mode includes:

when the clock output mode is the first output mode, acquiring a second delay parameter from an input end to an output end of the first-stage clock buffer, a first delay parameter from the input end to the output end of the second-stage clock buffer, a third delay parameter from a phase-locked loop in the chipset to an output pin of the chipset, a fourth delay parameter corresponding to a first transmission line between the chipset and the first-stage clock buffer, a fifth delay parameter corresponding to a second transmission line between the first-stage clock buffer and the peripheral slot, a sixth delay parameter corresponding to a third transmission line between the second-stage clock buffer and an end device on an external card, and a seventh delay parameter corresponding to a bus data link;

constructing the first delay parameter set based on the first delay parameter, the second delay parameter, the third delay parameter, the fourth delay parameter, the fifth delay parameter, the sixth delay parameter, and the seventh delay parameter;

And taking the first delay parameter set as a current delay parameter set corresponding to the clock transmission link of the first output mode.

8. The method of claim 7, wherein calculating the current delay time using all parameters in the current delay parameter set comprises:

Establishing a first calculation relation based on all parameters in the current delay parameter set;

Calculating a current delay time by using the first calculation relation;

the first calculation relation is:

T₁=t_delay1+t_clkpcb1+t_clkbuffer1+t_clkpcb2+t_clkbuffer2+t_clkpcb3+t_data；

Wherein T ₁ is the current delay time, T _clkbuffer1 is the first delay parameter, T _clkbuffer2 is the second delay parameter, T _delay1 is the third delay parameter, T _clkpcb1 is the fourth delay parameter, T _clkpcb2 is the fifth delay parameter, T _clkpcb3 is the sixth delay parameter, and T _data is the seventh delay parameter.

9. The method for configuring a server clock architecture according to claim 6, wherein the server clock architecture includes a server motherboard, and the server motherboard is provided with a peripheral slot, and the process of determining the current delay parameter set corresponding to the clock transmission link in the clock output mode includes:

When the clock output mode is the second output mode, acquiring the output clock skew parameter, a second delay parameter between an input end and an output end of the second-stage clock buffer, a first line delay parameter corresponding to a second transmission line between the first-stage clock buffer and the peripheral slot, a second line delay parameter corresponding to a third transmission line between the first-stage clock buffer and the chipset, a third line delay parameter corresponding to a third transmission line between the second-stage clock buffer and an external card, a seventh delay parameter corresponding to a bus data link, and an eighth delay parameter corresponding to clock delay in the chipset;

Constructing a second delay parameter set based on the output clock skew parameter, the second delay parameter, the seventh delay parameter, the eighth delay parameter, the first line delay parameter, the second line delay parameter, and the third line delay parameter;

And taking the second delay parameter set as a current delay parameter set corresponding to the clock transmission link of the second output mode.

10. The method of claim 9, wherein calculating the current delay time using all parameters in the current delay parameter set comprises:

Establishing a second calculation relation corresponding to the chipset serving as a transmitting end and a third calculation relation corresponding to the external card serving as the transmitting end based on all parameters in the current delay parameter set;

Calculating a first delay time using the second calculation relation;

calculating a second delay time using the third calculation relation;

and taking the maximum value of the first delay time and the second delay time as the current delay time.

11. The method of claim 10, wherein the second computing relationship is:

T_a=|（t_delay2+t_clkpcb4+t_data）-（t_clkpcb5+t_clkbuffer2+t_clkpcb6）|+t_clkskew；

Wherein T _a is the first delay time, T _delay2 is the eighth delay parameter, T _data is the seventh delay parameter, T _clkskew is the output clock skew parameter, T _clkbuffer2 is the second delay parameter, T _clkpcb4 is the first line delay parameter, T _clkpcb5 is the second line delay parameter, and T _clkpcb6 is the third line delay parameter.

12. The method of claim 10, wherein the third calculation relation is:

T_b=|（t_delay2+t_clkpcb4）-（t_clkpcb5+t_clkbuffer2+t_clkpcb6+t_data）|+t_clkskew；

Wherein T _b is the second delay time, T _delay2 is the eighth delay parameter, T _data is the seventh delay parameter, T _clkskew is the output clock skew parameter, T _clkbuffer2 is the second delay parameter, T _clkpcb4 is the first line delay parameter, T _clkpcb5 is the second line delay parameter, and T _clkpcb6 is the third line delay parameter.

13. The method for configuring a server clock architecture according to claim 5, wherein the server clock architecture includes a server motherboard, and after determining whether a current transmission delay time satisfies a clock constraint of the server clock architecture, the method further comprises:

Calculating a time difference between the current transmission delay time and a constraint time corresponding to a clock constraint of the server clock architecture;

Judging whether the time difference value is smaller than or equal to a preset difference value;

if yes, adjusting the position of the first-stage clock buffer on the server main board so that the time difference value is larger than the preset difference value.

14. The method according to any one of claims 5-13, wherein the process of calculating the current transmission delay time of the clock transmission link in the clock output mode comprises:

And calculating the current transmission delay time of the clock transmission link when the clock output mode is adopted and the working mode of the first-stage clock buffer and the working mode of the second-stage clock buffer are both bypass modes.

15. The method according to claim 14, wherein adjusting the operation mode of the first stage clock buffer and/or the operation mode of the second stage clock buffer so that the current transmission delay time of the clock transmission link in the clock output mode satisfies the clock constraint comprises:

Determining any one of the first stage clock buffer and the second stage clock buffer as a first adjustment buffer, and the other one as a second adjustment buffer;

Switching the working mode of the first adjustment buffer from the bypass mode to a phase-locked loop mode;

calculating the current transmission delay time of the clock transmission link when the clock output mode is adopted, the working mode of the first adjusting buffer is the phase-locked loop mode, and the working mode of the second adjusting buffer is the bypass mode;

judging whether the current transmission delay time meets the clock constraint of the server clock architecture or not;

if yes, judging that the configuration of the server clock architecture is completed;

if not, switching the working mode of the second adjusting buffer from the bypass mode to the phase-locked loop mode;

calculating the current transmission delay time of the clock transmission link when the clock output mode is set, and the working mode of the first adjusting buffer and the working mode of the second adjusting buffer are both the phase-locked loop mode;

judging whether the current transmission delay time meets the clock constraint of the server clock architecture or not;

if yes, judging that the configuration of the server clock architecture is completed;

If not, prompting configuration error information.

16. The method of claim 15, wherein determining either one of the first stage clock buffer and the second stage clock buffer as a first adjustment buffer and the other as a second adjustment buffer comprises:

the second stage clock buffer is determined to be a first adjustment buffer, and the first stage clock buffer is determined to be a second adjustment buffer.

17. A computer program product comprising computer programs/instructions which, when executed by a processor, implement the steps of the method of configuring a server clock architecture as claimed in any one of claims 5 to 16.

18. An electronic device, comprising:

A memory for storing a computer program;

A processor for implementing the steps of the method for configuring a server clock architecture according to any one of claims 5-16 when executing said computer program.

19. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when executed by a processor, implements the steps of the method of configuring a server clock architecture according to any of claims 5-16.