CN118234361B

CN118234361B - A novel multi-chip on-chip ultrasonic interconnect packaging method

Info

Publication number: CN118234361B
Application number: CN202410642700.4A
Authority: CN
Inventors: 王鹏杰; 檀明亮; 陈超
Original assignee: Hangzhou Hesheng Technology Co ltd
Current assignee: Hangzhou Hesheng Technology Co ltd
Priority date: 2024-05-23
Filing date: 2024-05-23
Publication date: 2024-09-20
Anticipated expiration: 2044-05-23
Also published as: WO2025241231A1; CN118234361A

Abstract

The invention discloses a novel multi-chip on-chip ultrasonic interconnection packaging method, which relates to the technical field of chip packaging and solves the technical problems of lower multi-chip packaging yield and high cost, the technical scheme is characterized in that the chip is thinned, and the wire bonding and flip chip packaging technology is compatible with the traditional technology, the DRIE technology is avoided, the effective utilization rate of the wafer is improved, the manufacturing of the chips and the interconnection of the multiple chips are decoupled while the multi-chip interconnection packaging is realized, the necessity of wafer-level packaging is relieved, the flexibility of chip manufacturing and testing is increased, and the packaging cost is greatly reduced.

Description

Novel multi-chip on-chip ultrasonic interconnection packaging method

Technical Field

The application relates to the technical field of chip packaging, in particular to a novel multi-chip on-chip ultrasonic interconnection packaging method.

Background

The multi-chip on-chip ultrasonic interconnection technology can flexibly connect a plurality of ultrasonic chips, increase the angle range covered by ultrasonic beams, and is widely applicable to various applications such as wearable ultrasound, interventional ultrasound and the like.

For example, in interventional ultrasound applications, the stiff portion length of the distal end of the ultrasound catheter can affect the passability of the catheter. For example, philips, eagle eye products, a side-looking IVUS phased array imaging catheter, in which the transducer and chip are spaced back and forth along the catheter axis and connected by wires, prevents further reduction in the length of the rigid portion at the distal end of the catheter, and reduces the throughput of the catheter, thereby reducing clinical utility. This problem can be solved by using a Transducer-on-CMOS structure, i.e., the ultrasound Transducer is directly integrated on the upper surface of an ASIC (Application SPECIFIC INTEGRATED Circuit) to form a vertical stack structure of the Transducer and the ASIC, thereby reducing the length of the rigid portion at the distal end of the catheter and increasing the trafficability of the interventional ultrasound probe in the blood vessel.

For the multi-chip package of the transducer described above, the Flex-to-Rigid (F2R, high precision micro-assembly) process published by Philips corporation employs wafer level packaging, polyimide (PI) is spin coated onto the entire wafer, and electrical interconnect layers (RDL, redistribution Layer) are made between PI layers. The process arranges all the chips which are required to be interconnected on the same wafer according to a certain interval, and simultaneously realizes the thinning of the chips and the separation between the multiple chips through a Deep Reactive Ion Etching (DRIE) process on the back surface of the chips. However, making a plurality of chips to be interconnected on the same wafer according to the pitch required for bending is equivalent to regarding the multi-chip system as a large chip, which affects the final yield; meanwhile, the DRIE technology is used for thinning and separating the chips, so that a large proportion of the effective area of the wafer is wasted, and the cost of the probe is increased.

Disclosure of Invention

The application provides a novel multi-chip on-chip ultrasonic interconnection packaging method, which aims to improve the multi-chip packaging yield and reduce the cost.

The technical aim of the application is realized by the following technical scheme:

a novel multi-chip on-chip ultrasonic interconnection packaging method comprises the following steps:

cutting and thinning a plurality of chips to be interconnected independently; wherein the chip comprises a vertical stack structure formed by the direct integration of an ultrasonic transducer to the surface of the ASIC;

Welding the thinned chip onto a flexible substrate to obtain a multi-chip interconnection system; wherein, the flexible substrate is provided with an insulating layer and an electrical interconnection layer;

and bending the multi-chip interconnection system with the flexible substrate to obtain the on-chip ultrasonic integrated module, and completing packaging.

Further, the bonding the thinned chip to the flexible substrate includes:

Welding the thinned chip onto a flexible substrate through a wire bonding process; or (b)

And welding the thinned chip onto the flexible substrate through a flip chip process.

Further, when the thinned chip is soldered to the flexible substrate by flip chip process, it includes:

removing the insulating layer of the mechanical interconnection below each chip and between the chips to form a first window, so as to obtain a multi-chip interconnection system; or (b)

And removing the insulating layer under each chip to form a plurality of second windows, thereby obtaining the multi-chip interconnection system.

Further, when the insulating layer is removed, the insulating layer is removed by exposure and development.

Further, pad may be disposed at any position of the chip and the flexible substrate.

Further, bending a multi-chip interconnect system having a flexible substrate, comprising: and bending the multi-chip interconnection system with the flexible substrate along the radial inner direction of the chip to obtain the on-chip ultrasonic integrated module of the annular phased array.

The application relates to an interventional device, which comprises an on-chip ultrasonic integrated module which is obtained by packaging by the novel multi-chip on-chip ultrasonic interconnection packaging method.

The application relates to wearable equipment, which comprises an on-chip ultrasonic integrated module packaged by the novel multi-chip on-chip ultrasonic interconnection packaging method.

The application has the beneficial effects that: according to the novel multi-chip on-chip ultrasonic interconnection packaging method, the manufacturing of chips and the interconnection of the multiple chips are decoupled, the necessity of wafer-level packaging is relieved, and the flexibility of chip manufacturing and testing is improved; and because the thinning, wire bonding and flip chip packaging processes of the chip are compatible with the traditional processes, the DRIE process is avoided, the effective utilization rate of the wafer is improved, and the packaging cost is greatly reduced while the multi-chip interconnection packaging is realized.

Drawings

FIG. 1 is a cross-sectional view of a structure of a circular phased array imaging system in accordance with an embodiment of the application;

FIG. 2 is a schematic diagram of transducer interconnections using a wire bonding process in accordance with an embodiment of the present application;

FIG. 3 is a schematic diagram of a transducer interconnect without insulation between chips using flip chip technology in an embodiment of the present application;

FIG. 4 is a schematic diagram of a transducer interconnect with insulation layer connection between chips using flip chip process in accordance with an embodiment of the present application;

fig. 5 is a schematic diagram of an annular phased array imaging system after bending of multiple chips in an embodiment of the application.

In the figure: 1-a transducer; a 2-ASIC chip; 3-a flexible substrate; 31-an insulating layer; 32-an electrical interconnect layer; 33-a first window; 34-a second window; 4-transducer-ASIC vertical stack; 5-pad position.

Detailed Description

The technical scheme of the application will be described in detail with reference to the accompanying drawings.

The on-chip ultrasonic integrated module in the embodiment of the application is shown as an on-chip ultrasonic integrated module of the annular phased array in fig. 1 and 5, and the on-chip ultrasonic integrated module is a vertical stack structure formed by integrating a flexible substrate, a plurality of transducers welded on the flexible substrate and an ASIC (application specific integrated circuit) from inside to outside. Each vertical stacking structure is a chip which is cut and thinned independently, and the chips are connected through an RDL (electrical interconnection) layer on the flexible substrate.

The application relates to a novel multi-chip on-chip ultrasonic interconnection packaging method, which specifically comprises the following steps:

(1) And cutting and thinning a plurality of chips which need to be interconnected individually. The thickness of the chip is related to the diameter of the integrated whole module, and the diameter depends on the actual use situation (such as the size of a blood vessel) of the catheter, so that various choices can be made. In addition, the number of chips that can be interconnected is not limited to 3 as shown in fig. 2, 3, and 4, and the number of interconnected chips may be arbitrarily changed as required by the actual design.

(2) Welding the thinned chip onto a flexible substrate to obtain a multi-chip interconnection system; wherein, insulating layer and electrical interconnection layer are equipped with on the flexible substrate.

In the embodiment of the application, the insulating layer on the flexible substrate may be, for example, a polyimide layer.

In the embodiment of the application, the thinned chip is welded to the flexible substrate through a wire bonding packaging process or a flip chip packaging process, and the structural schematic diagram after welding is shown in fig. 2.

Specifically, after the chip is welded to the flexible substrate through a wire bonding packaging process, the flexible substrate is bent along the dotted line direction in fig. 2, so as to obtain the on-chip ultrasonic integrated module of the annular phased array shown in fig. 5.

After soldering by flip chip packaging technology, the insulating layer below the chip at the corresponding position of the flexible substrate needs to be removed, and the removing mode is divided into two modes, wherein one mode is to remove the insulating layer below the chip and between the chips at the corresponding position of the flexible substrate to obtain a large first window, as shown in fig. 3; the other is to remove only the insulating layer below the chips at the corresponding positions of the flexible substrate, and to keep the insulating layer between the chips at the corresponding positions of the flexible substrate, so that a second window is formed between every two adjacent chips, as shown in fig. 4.

The first window and the second window are formed at the aperture position of the transducer, so that the ultrasonic transducer can effectively transmit and receive ultrasonic waves along the radial direction of the catheter.

In the embodiment of the application, for the wire bonding or flip chip interconnection scheme, the pad position on the chip and the pad position on the flexible substrate are not limited to the two ends of the chip shown in fig. 2, and the pad position can be designed at any position according to actual needs.

(3) And bending the multi-chip interconnection system with the flexible substrate to obtain the on-chip ultrasonic integrated module, and completing packaging.

In the embodiment of the application, the multi-chip interconnection system with the flexible substrate is bent along the direction of the radial inner side of the chip (the bending direction of the dotted line in fig. 2, 3 and 4), and an on-chip ultrasonic integrated module of an annular phased array can be obtained, as shown in fig. 5.

The on-chip ultrasonic integrated module can be used for interventional equipment, wearable equipment and the like.

The foregoing is an exemplary embodiment of the application, the scope of which is defined by the claims and their equivalents.

Claims

1. A novel multi-chip on-chip ultrasonic interconnect packaging method, characterized by comprising:

Cut and thin multiple chips that need to be interconnected separately; wherein the chip includes a vertical stacking structure formed by directly integrating an ultrasonic transducer onto the surface of an ASIC;

The thinned chip is welded to a flexible substrate to obtain a multi-chip interconnection system; wherein the flexible substrate is provided with an insulating layer and an electrical interconnection layer;

The multi-chip interconnection system with a flexible substrate is bent to obtain an on-chip ultrasound integrated module and complete the packaging;

The thinned chip is welded to the flexible substrate through a flip chip process, and then includes:

The insulating layer under each chip and the mechanical interconnection between chips is removed to form a first window to obtain a multi-chip interconnection system; or

Only the insulating layer under each chip is removed to form a plurality of second windows, thereby obtaining a multi-chip interconnection system.

2. The packaging method according to claim 1, characterized in that when removing the insulating layer, it is removed by exposure and development.

3. The packaging method according to claim 1, characterized in that a pad can be set at any position of the chip and the flexible substrate.

4. An invasive device, characterized in that the invasive device comprises an on-chip ultrasound integrated module packaged by the novel multi-chip on-chip ultrasound interconnect packaging method described in any one of claims 1 to 3.

5. A wearable device, characterized in that the wearable device comprises an on-chip ultrasound integrated module packaged by the novel multi-chip on-chip ultrasound interconnect packaging method described in any one of claims 1 to 3.