CN118232905A

CN118232905A - Level conversion circuit

Info

Publication number: CN118232905A
Application number: CN202410323345.4A
Authority: CN
Inventors: 高峡; 谢云宁
Original assignee: SG Micro Beijing Co Ltd
Current assignee: SG Micro Beijing Co Ltd
Priority date: 2024-03-20
Filing date: 2024-03-20
Publication date: 2024-06-21

Abstract

The invention discloses a level conversion circuit, comprising: the pull-up circuit is arranged in the second voltage domain and is provided with a first pull-down point and a second pull-down point; the first pull-down circuit is used for pulling down the level potential of one of the first pull-down point and the second pull-down point according to the input signal when the voltage difference of the second voltage domain is larger than a set threshold value; a shaping output circuit for providing an output signal of high and low logic levels according to the high and low levels of the second pull-down point; the second pull-down circuit is used for generating a narrow pulse signal according to the input signal when the voltage difference of the second voltage domain is smaller than a set threshold value, and pulling down the level potential of one of the first pull-down point and the second pull-down point according to the narrow pulse signal so as to enable the output signal to be quickly turned over; and the potential maintaining circuit is used for maintaining the logic state of the second pull-down point after the end of the narrow pulse signal, solves the problem that the second pull-down point cannot be pulled down normally caused by too low pressure difference in a high-voltage domain, and has the advantages of wide level conversion range and high conversion speed.

Description

Level conversion circuit

Technical Field

The present invention relates to the field of integrated circuits, and more particularly, to a level shifter circuit.

Background

Multi-voltage domain electronic devices typically use level shifting (LEVEL SHIFT) circuits to effect the conversion of low-voltage domain signals to high-voltage domain signals. In particular, in a large-scale analog-to-digital mixed multi-voltage domain electronic device, a digital circuit and an analog circuit generally correspond to different power supply voltages, and the power supply voltages may be different, for example, the core voltage of the digital circuit is generally lower than 1V, but more analog circuits are generally higher power supply voltages such as 1.8V, 2.5V or 3.3V, and data interaction often exists between the digital circuit and the analog circuit, so that a level conversion circuit becomes a bridge connecting a low-voltage domain of a chip core and a high-voltage domain of an external analog circuit, and is widely applied to various interface circuits and input-output units to realize logic conversion of a level.

Fig. 1 shows a schematic circuit diagram of a conventional level shift circuit, and the level shift circuit 100 in fig. 1 is mainly used for converting a logic signal Vin in a low voltage domain (VDDL to VSSL) into a logic signal Vout in a high voltage domain (VDDH to VSSH). According to the circuit structure in fig. 1, it can be obtained that if the circuit is expected to operate normally, the voltage difference between the high voltage domains (VDDH to VSSH) needs to be greater than 2 Vth, where Vth is the on threshold of the transistor. The turn-on threshold Vth of the low-voltage MOS transistor is generally about 0.7V, and the turn-on threshold Vth of the high-voltage MOS transistor is generally about 1.2V with great temperature and process deviation. Therefore, the operating range of the conventional level shifter circuit 100 is limited by the on threshold of the transistor, and when the voltage difference in the high voltage domain is small, the circuit cannot operate normally, which limits the application range of the level shifter circuit.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide a level shifter circuit, which solves the problem that the conventional level shifter circuit cannot operate normally when the voltage difference in the high voltage domain is small.

According to an aspect of the present invention, there is provided a level conversion circuit for converting an input signal of a first voltage domain into an output signal of a second voltage domain, comprising: the pull-up circuit is arranged in the second voltage domain and is provided with a first pull-down point and a second pull-down point, and the potential of the first pull-down point is logically complementary with the potential of the second pull-down point; the first pull-down circuit is connected with an input signal positioned in the first voltage domain and is used for pulling down the level potential of one of the first pull-down point and the second pull-down point according to the input signal when the voltage difference of the second voltage domain is larger than a set threshold value; the shaping output circuit is connected with the second pull-down point and is used for providing an output signal with high and low logic levels according to the high and low levels of the second pull-down point; the second pull-down circuit is used for generating a narrow pulse signal according to the input signal when the voltage difference of the second voltage domain is smaller than the set threshold value, and pulling down the level potential of one of the first pull-down point and the second pull-down point according to the narrow pulse signal so as to enable the output signal to be quickly turned over; and a potential maintaining circuit for maintaining a logic state of the second pull-down point after the end of the narrow pulse signal.

Optionally, the pull-up circuit and the first pull-down circuit are of differential structure.

Optionally, the pull-up circuit includes: a first PMOS transistor having a first terminal connected to a second power supply voltage of the second voltage domain, a second terminal connected to the first pull-down point, and a control terminal connected to the second pull-down point; and a second PMOS transistor having a first terminal connected to the second power supply voltage, a second terminal connected to the second pull-down point, and a control terminal connected to the first pull-down point.

Optionally, the first pull-down circuit includes: a first NMOS transistor having a control terminal connected to an inverted signal of the input signal and a second terminal connected to a first reference ground of the first voltage domain; a second NMOS transistor having a control terminal connected to the input signal and a second terminal connected to the first reference ground; a third PMOS transistor having a first terminal connected to the first pull-down point, a second terminal connected to the first terminal of the first NMOS transistor, and a control terminal connected to a second reference ground of the second voltage domain; and a fourth PMOS transistor having a first terminal connected to the second pull-down point, a second terminal connected to the first terminal of the second NMOS transistor, and a control terminal connected to the second reference ground.

Optionally, the second pull-down circuit includes: a first resistor having a first end connected to the first pull-down point; a third NMOS transistor having a first terminal connected to the second terminal of the first resistor and a second terminal connected to the first reference ground of the first voltage domain; a first pulse generator having an input terminal connected to an inverted signal of the input signal and an output terminal connected to a control terminal of the third NMOS transistor; a second resistor having a first end connected to the second pull-down point; a fourth NMOS transistor having a first terminal connected to the second terminal of the second resistor and a second terminal connected to the first reference ground; and a second pulse generator having an input terminal connected to the input signal and an output terminal connected to the control terminal of the fourth NMOS transistor.

Optionally, the potential maintaining circuit includes: the first branch is connected with the first pull-down point and is used for controlling the potential level of the first pull-down point according to the input signal; and a second branch connected with the second pull-down point, wherein the second branch is used for controlling the potential level of the second pull-down point according to the input signal.

Optionally, the first branch includes: a third resistor, a fourth resistor, and a fifth NMOS transistor connected in series between a second supply voltage of the second voltage domain and a first reference ground of the first voltage domain, the fifth NMOS transistor having a control terminal connected to the input signal; a fifth PMOS transistor and a fifth resistor connected in series between the second supply voltage and a second reference ground of the second voltage domain, the fifth PMOS transistor having a control terminal connected to an intermediate node of the third resistor and the fourth resistor, the intermediate node of the fifth PMOS transistor and the fifth resistor being connected to the first pull-down point; and a zener diode connected between the first terminal and the control terminal of the fifth PMOS transistor.

Optionally, the second branch includes: a sixth resistor, a seventh resistor and a sixth NMOS transistor connected in series between the second supply voltage of the second voltage domain and the first reference ground of the first voltage domain, the sixth NMOS transistor having a control terminal connected to the input signal, an intermediate node of the sixth resistor and the seventh resistor being connected to the second pull-down point.

Optionally, the first pull-down circuit further includes: a first diode having an anode connected to the control terminal of the third PMOS transistor and a cathode connected to the first terminal of the third PMOS transistor; and a second diode having an anode connected to the control terminal of the fourth PMOS transistor and a cathode connected to the first terminal of the fourth PMOS transistor.

Optionally, the shaping output circuit includes: a schmitt trigger having an input connected to the second pull-down point; and an inverter having an input connected to the output of the schmitt trigger and an output for providing the output signal.

In summary, the level conversion circuit in the embodiment of the present invention, by setting the second pull-down circuit and the potential maintaining circuit in the circuit, not only can the level conversion circuit normally operate when the voltage difference in the high voltage domain is greater than or equal to 2 vth, but also can normally operate when the voltage difference in the high voltage domain is less than 2 vth, compared with the conventional LEVEL SHIFT circuit, the operating range of the level conversion circuit is not limited by the on threshold value of the transistor in the circuit, and the application range of the circuit is enlarged.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

Fig. 1 shows a schematic circuit diagram of a conventional level shift circuit.

Fig. 2 shows an operation waveform diagram of a conventional level shift circuit.

Fig. 3 shows a schematic circuit diagram of a level shift circuit according to an embodiment of the invention.

Fig. 4 shows an operation waveform diagram of a level shift circuit according to an embodiment of the present invention.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

In the description, it should be noted that like reference numerals have been used to denote like parts in other figures as far as possible for these elements. In the following description, when functions and configurations known to those skilled in the art are irrelevant to the basic configuration of the present disclosure, their detailed description will be omitted. The terms described in the specification should be understood as follows.

Advantages and features of the present disclosure and methods of accomplishing the same will be described below by way of embodiments described with reference to the accompanying drawings. This disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Furthermore, the disclosure is limited only by the scope of the claims.

The shapes, dimensions, ratios, angles, and numbers disclosed in the drawings for describing embodiments of the present disclosure are merely examples, and thus the present disclosure is not limited to the details illustrated. Like numbers refer to like elements throughout. In the following description, a detailed description will be omitted when it is determined that the detailed description of related known functions or constructions will inevitably obscure the gist of the present disclosure.

In the case where the terms "including", "having" and "comprising" described in this specification are used, another part may be added unless "only" is used. Unless otherwise indicated to the contrary, singular terms may include the plural.

It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first component could be termed a second component, and, similarly, a second component could be termed a first component, without departing from the scope of the present disclosure.

The term "at least one" should be understood to include any and all combinations of one or more of the corresponding listed items. For example, the meaning of "at least one of the first, second, and third items" means a combination of all items proposed from two or more of the first, second, and third items, as well as the first, second, or third items.

As those skilled in the art will fully appreciate, the features of the various embodiments of the disclosure may be combined or combined, in part or in whole, with one another and may be interoperable and technically driven in various ways with one another. Embodiments of the present disclosure may be performed independently of each other or may be performed together in mutual dependency.

In all embodiments of the present invention, since the source and drain of a Metal Oxide Semiconductor (MOS) transistor are symmetrical and the on-current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, in embodiments of the present invention, the controlled middle pole of the MOS transistor is referred to as the control terminal and the remaining two ends of the MOS transistor are referred to as the first and second terminals, respectively. For ease of description, in this context, the source, drain and gate of a PMOS transistor are referred to as a first terminal, a second terminal and a control terminal, respectively, and the drain, source and gate of an NMOS transistor are referred to as a first terminal, a second terminal and a control terminal, respectively. In addition, terms such as "first" and "second" are used merely to separate one component (or portion of a component) from another component (or another portion of a component).

Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

Fig. 1 shows a schematic circuit diagram of a conventional level shift circuit. As shown in fig. 1, the voltage level conversion circuit 100 includes a pull-up circuit 110, a pull-down circuit 120, resistors R1 and R2, a schmitt trigger SMIT, and inverters INV1 and INV2. The pull-up circuit 110 is composed of a pair of PMOS transistors (P-Metal-Oxide-Semiconductor field effect transistors) MP1 and MP2, and the pull-down circuit 120 is composed of a pair of NMOS transistors (N-Metal-Oxide-Semiconductor field effect transistors) MN1 and MN2 and a pair of PMOS transistors MP3 and MP 4. The PMOS transistor MP1, the PMOS transistor MP3, and the NMOS transistor MN1 are connected in series between the high power supply voltage VDDH and the voltage VSSL, the PMOS transistor MP2, the PMOS transistor MP4, and the NMOS transistor MN2 are connected in series between the power supply voltage VDDH and the voltage VSSL, the control terminal of the PMOS transistor MP1 is connected to the node B between the PMOS transistors MP2 and MP4, the control terminal of the PMOS transistor MP2 is connected to the node a between the PMOS transistors MP1 and MP3, and the control terminals of the PMOS transistors MP3 and MP4 are connected to the voltage VSSH. Resistor R1 is connected between node a and voltage VSSH, and resistor R2 is connected between supply voltage VDDH and node B. The inverter INV1 is connected between the low power voltage VCCL and the voltage VSSL, the input signal Vin is connected to the control terminal of the NMOS transistor MN2 and the input terminal of the inverter INV1, and the output terminal of the inverter INV1 provides the inverted signal Vinb of the input signal Vin and is connected to the control terminal of the NMOS transistor MN 1. The input of the schmitt trigger SMIT1 is connected to node B, the output thereof is connected to the input of the inverter INV2, and the output of the inverter INV2 is used to provide the output signal Vout.

Fig. 2 shows an operation waveform diagram of a conventional level shift circuit. As shown in fig. 2, when the input signal Vin changes from low level to high level, the NMOS transistor MN2 is turned on, the NMOS transistor MN1 is turned off, the node B is pulled down to vssh+vth (the potential at the point B cannot be lower, or the PMOS transistor MP4 cannot be turned on) by the PMOS transistor MP4, where Vth is the absolute value of the on threshold of the MOS transistor, and after the logic level at the point B passes through the schmitt trigger SMIT1 and the inverter INV1, the output signal Vout is turned to high level. At the same time, the PMOS transistor MP1 is turned on, and the node a is pulled up to the voltage VDDH, so that the PMOS transistor MP2 is turned off. At this time, the gate-source voltage |vgs|=vddh-VSSH-Vth of the PMOS transistor MP1, because the on condition of the PMOS transistor MP1 is |vgs| > Vth, the voltage difference in the high voltage domains (VDDH to VSSH) needs to be greater than 2×vth.

When the input signal Vin changes from high level to low level, the NMOS transistor MN1 is turned on, and the NMOS transistor MN2 is turned off, pulling down the potential of the node a to vssh+vth through the PMOS transistor MP 3. At this time, the gate-source voltage |vgs|=vddh-VSSH-Vth of the PMOS transistor MP2, and similarly, since the on condition of the PMOS transistor MP2 is |vgs| > Vth, the voltage difference in the high voltage domains (VDDH to VSSH) needs to be greater than 2×vth. When VDDH-VSSH > 2 xVth, the point B is pulled up to the voltage VDDH by the PMOS transistor MP2, and the output signal Vout is turned to be low after passing through the Schmitt trigger SMIT1 and the inverter INV 1.

As can be seen from the above analysis, the voltage difference between the high voltage domains (VDDH to VSSH) of the conventional level shifter circuit 100 is required to be greater than 2×vth, where Vth is the on threshold of the transistor. The turn-on threshold Vth of the low-voltage MOS transistor is generally about 0.7V, and the turn-on threshold Vth of the high-voltage MOS transistor is generally about 1.2V with great temperature and process deviation. Therefore, the operating range of the conventional level shifter circuit 100 is limited by the on threshold of the transistor, and when the voltage difference in the high voltage domain is small, the circuit cannot operate normally, which limits the application range of the level shifter circuit.

Fig. 3 shows a schematic circuit diagram of a level shift circuit according to an embodiment of the invention. As shown in fig. 3, the level shifter 200 of the present embodiment includes a pull-up circuit 210, a first pull-down circuit 220, a second pull-down circuit 230, a potential maintaining circuit, and a shaping output circuit 250. The pull-up circuit 210 is disposed in a high voltage domain (VDDH-VSSH), wherein the voltage VDDH is a power supply voltage of the high voltage domain, and the voltage VSSH is a reference ground of the high voltage domain. The pull-up circuit 210 further includes pull-down points a and B whose potentials are logically complementary. The first pull-down circuit 220 is connected to an input signal Vin in a low voltage domain (VDDL-VSSL), wherein the voltage VDDL is a power supply voltage of the low voltage domain, the voltage VSSL is a reference ground of the low voltage domain, and the first pull-down circuit 220 is configured to pull down a potential of one of the pull-down points a and B according to the input signal Vin when a voltage difference in the high voltage domains (VDDH-VSSH) is greater than a set threshold. For example, the set threshold is equal to 2×vth, where Vth is the on threshold of the MOS transistor, the on threshold Vth of the low-voltage MOS transistor is generally about 0.7V, and the on threshold Vth of the high-voltage MOS transistor is generally about 1.2V with great temperature and process deviation. The shaping output circuit 250 is connected to the pull-down point B for providing the output signal Vout with a high-low logic level according to the high-low level of the pull-down point B, wherein the potential of the output signal Vout is in the high-voltage domain (VDDH-VSSH). The second pull-down circuit 230 is configured to generate a narrow pulse signal according to an input signal Vin when a voltage difference between high voltage domains (VDDH to VSSH) is smaller than the set threshold, and pull down one of the pull-down points a and B according to the narrow pulse signal, so that the output signal Vout can be flipped rapidly. The potential maintaining circuit includes a first branch 241 connected to the pull-down point a and a second branch connected to the pull-down point B, and is configured to maintain the logic state of the pull-down point B according to the input signal Vin after the end of the narrow pulse signal in the second pull-down circuit 230, so as to ensure the stability of the output signal Vout.

Specifically, the pull-up circuit 210 may include PMOS transistors MP1 and MP2. The first ends of the PMOS transistors MP1 and MP2 are connected to the power supply voltage VDDH, the second end of the PMOS transistor MP1 and the control end of the PMOS transistor MP2 are connected to the pull-down point a, and the second end of the PMOS transistor MP2 and the control end of the PMOS transistor MP1 are connected to the pull-down point B.

The first pull-down circuit 220 includes NMOS transistors MN1 and MN2, PMOS transistors MP3 and MP4, and diodes D1 and D2. The first end of the PMOS transistor MP3 is connected to the pull-down point a, the control end of the PMOS transistor MP3 is connected to the reference ground VSSH, the second end of the PMOS transistor MP3 is connected to the first end of the NMOS transistor MN1, the control end of the NMOS transistor MN1 is connected to the inverted signal Vinb of the input signal Vin, and the second end of the NMOS transistor MN1 is connected to the reference ground VSSL. The level shifter 200 of the present embodiment further includes an inverter INV2, where the inverter INV2 is configured to obtain an inverted signal Vinb of the input signal Vin, and a power supply terminal of the inverter INV2 is connected to the power supply voltage VDDL of the low voltage domain and the reference ground VSSL. The first end of the PMOS transistor MP4 is connected to the pull-down point B, the control end of the PMOS transistor MP4 is connected to the reference ground VSSH, the second end of the PMOS transistor MP4 is connected to the first end of the NMOS transistor MN2, the control end of the NMOS transistor MN2 is connected to the input signal Vin, and the second end of the NMOS transistor MN2 is connected to the reference ground VSSL. The anode of the diode D1 is connected to the control terminal of the PMOS transistor MP3, and the cathode of the diode D1 is connected to the first terminal of the PMOS transistor MP 3. The anode of the diode D2 is connected to the control terminal of the PMOS transistor MP4, and the cathode of the diode D2 is connected to the first terminal of the PMOS transistor MP 4.

The second pull-down circuit 230 includes NMOS transistors MN3 and MN4, resistors R1 and R2, and pulse generators 231 and 232. The first end of the resistor R1 is connected to the pull-down point a, the second end of the resistor R1 is connected to the first end of the NMOS transistor MN3, the second end of the NMOS transistor MN3 is connected to the reference ground VSSL, the input of the pulse generator 231 is connected to the inverted signal Vinb of the input signal Vin, and the output of the pulse generator 231 is connected to the control end of the NMOS transistor MN 3. Illustratively, the level shifter 200 of the present embodiment further includes an inverter INV1, an input of the inverter INV1 is used for receiving the input signal Vin, an output of the inverter INV1 is used for providing the output signal Vinb, and a power supply terminal of the inverter INV1 is connected to the power supply voltage VDDL of the low voltage domain and the reference ground VSSL. The first end of the resistor R2 is connected to the pull-down point B, the second end of the resistor R2 is connected to the first end of the NMOS transistor MN4, the second end of the NMOS transistor MN4 is connected to the reference ground VSSL, the input of the pulse generator 232 is connected to the input signal Vin, and the output of the pulse generator 232 is connected to the control end of the NMOS transistor MN 4.

The first branch 241 of the potential maintaining circuit includes resistors R3 to R5, an NMOS transistor MN5, a PMOS transistor MP5, and a zener diode D0. The resistor R3, the resistor R4 and the NMOS transistor MN5 are connected in series between the power supply voltage VDDH and the reference ground VSSL, the control end of the NMOS transistor MN5 is connected to the input signal Vin, the intermediate node of the resistor R3 and the resistor R4 is connected to the control end of the PMOS transistor MP5, the first end of the PMOS transistor MP5 is connected to the power supply voltage VDDH, the second end of the PMOS transistor MP5 is connected to the first end of the resistor R5 and the pull-down point a, and the second end of the resistor R5 is connected to the reference ground VSSH of the high voltage domain. An anode of the zener diode D0 is connected to the control terminal of the PMOS transistor MP5, and a cathode of the zener diode D0 is connected to the first terminal of the PMOS transistor MP5, for clamping the gate-source voltage Vgs of the PMOS transistor MP 5.

The second branch 242 of the potential maintaining circuit includes resistors R6 and R7 and an NMOS transistor MN6. The resistor R6, the resistor R7, and the NMOS transistor MN6 are connected in series between the power supply voltage VDDH and the reference ground VSSL, the control terminal of the NMOS transistor MN6 is connected to the input signal Vin, and the intermediate node of the resistors R6 and R7 is connected to the pull-down point B.

The shaping output circuit 250 is typically implemented by a digital inverter, a digital buffer and/or a schmitt trigger, and is used for shaping and filtering the high and low levels of the pull-down point B, so as to obtain the output signal Vout with high voltage. Illustratively, the shaping output circuit 250 of the present embodiment includes a schmitt trigger SMIT1 and an inverter INV3. The input of the schmitt trigger SMIT1 is connected to the pull-down point B, the output of the schmitt trigger SMIT1 is connected to the input of the inverter INV3, and the output of the inverter INV3 is used for providing the output signal Vout.

In the present embodiment, the PMOS transistors MP1, MP2, and MP5 are implemented by, for example, low-voltage PMOS transistors, the PMOS transistors MP3 and MP4 are implemented by, for example, high-voltage PMOS transistors, and the NMOS transistors MN1 to MN6 are implemented by, for example, high-voltage NMOS transistors. It should be noted that the low-voltage MOS transistor and the high-voltage MOS transistor herein are generally relatively, and for example, the transistors may be classified into a high-voltage transistor or a low-voltage transistor according to an on threshold of the MOS transistor, and the on threshold of the low-voltage MOS transistor is typically around 0.7V, and the on threshold of the high-voltage MOS transistor is typically around 1.2V.

Fig. 4 shows an operation waveform diagram of a level shift circuit according to an embodiment of the present invention. Pulsea and Pulseb in fig. 4 are narrow pulse signals output from the pulse generators 231 and 232, respectively, the waveform change of the pull-down point a is shown by a solid line, and the waveform change of the pull-down point B is shown by a broken line. The operation principle of the level shift circuit 200 according to the embodiment of the present invention will be described with reference to fig. 4.

When the voltage difference between the high voltage domains (VDDH to VSSH) is greater than 2×vth, the operation of the level shifter circuit 200 is the same as that of the conventional level shifter circuit 100 shown in fig. 1, and will not be described herein again, and the operation principle of the level shifter circuit 200 when the voltage difference between the high voltage domains (VDDH to VSSH) is small will be described in detail.

When the voltage difference in the high voltage domain (VDDH to VSSH) is low, the PMOS transistors MP3 and MP4 in the first pull-down circuit 220 will not act as pull-down. When the input signal Vin transitions from low to high, the output Pulseb of the pulse generator 232 generates a 20ns high pulse to turn on the NMOS transistor MN4, which in turn pulls the pull-down point B down to the potential VSSH-Vth through the resistor R2, instead of the conventional potential vssh+vth, so that the output signal Vout can be quickly flipped to high. Wherein diode D2 is used primarily to protect low voltage devices in the circuit, clamping the potential of pull-down point B to VSSH-Vd, where Vd is the forward conduction voltage drop of the diode. Since the input signal Vin is at a high level, the NMOS transistors MN5 and MN6 are also in an on state, the gate of the PMOS transistor MP5 is pulled down by the NMOS transistor MN5, so the PMOS transistor MP5 is also in an on state at this time, and then the pull-down point a is pulled up to the voltage VDDH by the PMOS transistor MP5, so that the PMOS transistor MP2 in the pull-up circuit 210 is turned off. Therefore, after the high level pulse of the pulse signal Pulseb is ended, the state of the pull-down point B is determined by the voltage division of the resistors R6 and R7, and the current logic state of the point B can be maintained by reasonably setting the resistance values of the resistors R6 and R7.

When the input signal Vin transitions from high level to low level, the narrow pulse signal Pulsea output by the pulse generator 231 generates a 20ns high level pulse, then turns on the NMOS transistor MN3, pulls down the potential at the point a to the potential VSSH-Vth through the resistor R1, instead of the conventional vssh+vth, then turns on the PMOS transistor MP2, and pulls up the point B to the voltage VDDH through the PMOS transistor MP2, so that the output signal Vout can be quickly flipped to low level. Likewise, diode D1 clamps the lowest voltage at point A to VSSH-Vd in order to protect the low voltage device. Since the input signal Vin is at a low level at this time, the NMOS transistors MN5 and MN6 are in an off state, and then the gate of the PMOS transistor MP5 is pulled up by the resistor R3, so that the PMOS transistor MP5 is also in an off state. Therefore, after the high pulse of the signal Pulsea is ended, the potential at the point a is pulled down to the voltage VSSH by the resistor R5, so that the PMOS transistor MP2 can be kept on, and the pull-down point B can be maintained at the current logic state.

In the above description, well-known structural elements and steps have not been described in detail. Those of ordinary skill in the art will understand that the corresponding structural elements and steps may be implemented by various technical means. In addition, in order to form the same structural elements, those skilled in the art can also devise methods which are not exactly the same as the methods described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.

Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The scope of the invention should be determined by the following claims.

Claims

1. A level shifting circuit for converting an input signal of a first voltage domain to an output signal of a second voltage domain, comprising:

The pull-up circuit is arranged in the second voltage domain and is provided with a first pull-down point and a second pull-down point, and the potential of the first pull-down point is logically complementary with the potential of the second pull-down point;

The first pull-down circuit is connected with an input signal positioned in the first voltage domain and is used for pulling down the level potential of one of the first pull-down point and the second pull-down point according to the input signal when the voltage difference of the second voltage domain is larger than a set threshold value;

The shaping output circuit is connected with the second pull-down point and is used for providing an output signal with high and low logic levels according to the high and low levels of the second pull-down point;

the second pull-down circuit is used for generating a narrow pulse signal according to the input signal when the voltage difference of the second voltage domain is smaller than the set threshold value, and pulling down the level potential of one of the first pull-down point and the second pull-down point according to the narrow pulse signal so as to enable the output signal to be quickly turned over; and

And the potential maintaining circuit is used for maintaining the logic state of the second pull-down point after the end of the narrow pulse signal.

2. The level shifter circuit of claim 1, wherein the pull-up circuit and the first pull-down circuit are of differential construction.

3. The level shift circuit of claim 2, wherein the pull-up circuit comprises:

a first PMOS transistor having a first terminal connected to a second power supply voltage of the second voltage domain, a second terminal connected to the first pull-down point, and a control terminal connected to the second pull-down point;

And a second PMOS transistor having a first terminal connected to the second power supply voltage, a second terminal connected to the second pull-down point, and a control terminal connected to the first pull-down point.

4. The level shifter circuit of claim 3, wherein the first pull-down circuit comprises:

a first NMOS transistor having a control terminal connected to an inverted signal of the input signal and a second terminal connected to a first reference ground of the first voltage domain;

A second NMOS transistor having a control terminal connected to the input signal and a second terminal connected to the first reference ground;

a third PMOS transistor having a first terminal connected to the first pull-down point, a second terminal connected to the first terminal of the first NMOS transistor, and a control terminal connected to a second reference ground of the second voltage domain; and

A fourth PMOS transistor having a first terminal connected to the second pull-down point, a second terminal connected to the first terminal of the second NMOS transistor, and a control terminal connected to the second reference ground.

5. The level shifter circuit of claim 1, wherein the second pull-down circuit comprises:

A first resistor having a first end connected to the first pull-down point;

A third NMOS transistor having a first terminal connected to the second terminal of the first resistor and a second terminal connected to the first reference ground of the first voltage domain;

a first pulse generator having an input terminal connected to an inverted signal of the input signal and an output terminal connected to a control terminal of the third NMOS transistor;

a second resistor having a first end connected to the second pull-down point;

a fourth NMOS transistor having a first terminal connected to the second terminal of the second resistor and a second terminal connected to the first reference ground; and

And a second pulse generator having an input terminal connected to the input signal and an output terminal connected to the control terminal of the fourth NMOS transistor.

6. The level shift circuit according to claim 1, wherein the potential maintaining circuit includes:

The first branch is connected with the first pull-down point and is used for controlling the potential level of the first pull-down point according to the input signal; and

And the second branch is connected with the second pull-down point and is used for controlling the potential level of the second pull-down point according to the input signal.

7. The level shifter circuit of claim 6, wherein the first branch comprises:

A third resistor, a fourth resistor, and a fifth NMOS transistor connected in series between a second supply voltage of the second voltage domain and a first reference ground of the first voltage domain, the fifth NMOS transistor having a control terminal connected to the input signal;

A fifth PMOS transistor and a fifth resistor connected in series between the second supply voltage and a second reference ground of the second voltage domain, the fifth PMOS transistor having a control terminal connected to an intermediate node of the third resistor and the fourth resistor, the intermediate node of the fifth PMOS transistor and the fifth resistor being connected to the first pull-down point; and

And a zener diode connected between the first terminal and the control terminal of the fifth PMOS transistor.

8. The level shifter circuit of claim 6, wherein the second leg comprises:

A sixth resistor, a seventh resistor and a sixth NMOS transistor connected in series between the second supply voltage of the second voltage domain and the first reference ground of the first voltage domain, the sixth NMOS transistor having a control terminal connected to the input signal, an intermediate node of the sixth resistor and the seventh resistor being connected to the second pull-down point.

9. The level shifter circuit of claim 4, wherein the first pull-down circuit further comprises:

A first diode having an anode connected to the control terminal of the third PMOS transistor and a cathode connected to the first terminal of the third PMOS transistor; and

A second diode having an anode connected to the control terminal of the fourth PMOS transistor and a cathode connected to the first terminal of the fourth PMOS transistor.

10. The level shift circuit of claim 1, wherein the shaping output circuit comprises:

a schmitt trigger having an input connected to the second pull-down point; and

An inverter having an input connected to the output of the schmitt trigger and an output for providing the output signal.