CN118231465A - Semiconductor power devices - Google Patents

Abstract

The embodiment of the invention provides a semiconductor power device, which comprises: an n-type semiconductor layer; a plurality of p-type pillars within the n-type semiconductor layer; the p-type body region is positioned in the n-type semiconductor layer and positioned at the top of the p-type column, and an n-type source region is arranged in the p-type body region; a gate structure recessed in the n-type semiconductor layer for controlling the opening and closing of a current channel, wherein the gate structure comprises a gate dielectric layer and a gate; the clamping gate is recessed in the p-type body region and is isolated from the p-type body region through a first gate dielectric layer; and the source metal layer is electrically connected with the n-type source region and the clamping gate, and a p-n junction diode structure is formed between the source metal layer and the p-type body region.

Description

Semiconductor power devices

Technical Field

The present invention belongs to the technical field of semiconductor power devices, and in particular relates to a semiconductor power device.

Background technique

When the semiconductor power device of the prior art is turned off, when the drain-source voltage Vds is less than 0V, the parasitic body diode in the semiconductor power device is in a forward bias state, and the reverse current flows from the source to the drain through the body diode. At this time, the current of the body diode has the phenomenon of injecting minority carriers, and these minority carriers perform reverse recovery when the semiconductor power device is turned on again, resulting in a large reverse recovery current and a long reverse recovery time. At present, the method of improving the reverse recovery speed of semiconductor power devices is: connecting the semiconductor power device in parallel with a SiC Schottky diode. At this time, in order to suppress the reverse recovery current from flowing from the semiconductor power device, it is necessary to increase the forward conduction voltage drop Vfsd of the diode, which increases the Miller platform voltage of the semiconductor power device during the turn-on process, and requires a high gate drive voltage when applied.

Summary of the invention

In view of this, an object of the present invention is to provide a semiconductor power device that improves the reverse recovery speed while not increasing the Miller platform voltage during the switching process, thereby eliminating the need to increase the gate drive voltage.

An embodiment of the present invention provides a semiconductor power device, comprising:

n-type semiconductor layer;

a plurality of p-type pillars located within the n-type semiconductor layer;

a p-type body region located in the n-type semiconductor layer and at the top of the p-type column, wherein an n-type source region is disposed in the p-type body region;

A gate structure recessed in the n-type semiconductor layer and controlling the opening and closing of the current channel, the gate structure comprising a gate dielectric layer and a gate;

a clamp gate recessed in the p-type body region, the clamp gate being isolated from the p-type body region by a first gate dielectric layer;

A source metal layer electrically connected to the n-type source region and the clamp gate, wherein a p-n junction diode structure is formed between the source metal layer and the p-type body region.

Optionally, the source metal layer contacts the p-type body region to form a Schottky barrier diode structure; or, an n-type doped region is provided in the p-type body region, the p-type body region and the n-type doped region form a p-n junction diode structure, and the source metal layer is electrically connected to the n-type doped region.

Optionally, in the length direction of the current channel, the contact region between the source metal layer and the p-type body region is located between the n-type source region and the clamping gate, and the n-type doped region is located between the n-type source region and the clamping gate.

Optionally, in the width direction of the current channel, the contact region between the source metal layer and the p-type body region is located on one side or both sides of the clamping gate, and the n-type doping region is located on one side or both sides of the clamping gate.

Optionally, the bottom of the clamp gate is located in the p-type body region or extends downward into the p-type column.

The semiconductor power device of the present invention forms a clamping gate structure in the p-type body region. The clamping gate is externally connected to the source voltage through the source metal layer, which can couple the charge of the semiconductor power device during the turn-on process, so that the p-type body region is clamped at zero potential, thereby not affecting the charging of the Miller capacitor during the turn-on process, so that the Miller platform voltage is reduced, and there is no need to increase the gate drive voltage additionally during application.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solution of the exemplary embodiment of the present invention, the following briefly introduces the drawings required for describing the embodiment.

1 is a schematic cross-sectional view of a semiconductor power device according to a first embodiment of the present invention along a current channel length direction;

2 and 3 are schematic cross-sectional views of a second embodiment of a semiconductor power device according to the present invention;

FIG. 4 is a schematic cross-sectional view of a third embodiment of a semiconductor power device according to the present invention.

Detailed ways

In order to make the purpose, technical solution and advantages of the present invention more clear, the technical solution of the present invention will be fully described in a specific manner below in conjunction with the drawings in the embodiments of the present invention.

FIG1 is a schematic diagram of a cross-sectional structure of a first embodiment of a semiconductor power device provided by the present invention along the length direction of a current channel. As a common sense structure, the current channel is not described in detail in the embodiments of the present invention. As shown in FIG1 , the semiconductor power device of the present invention includes an n-type semiconductor layer 21, the material of the n-type semiconductor layer 21 is generally silicon and is formed on an n-type silicon substrate 20, and the n-type silicon substrate 20 can be used as an n-type drain region of the semiconductor power device.

A plurality of p-type pillars 22 are located in the n-type semiconductor layer 21. In the embodiment shown in FIG. 1, only two p-type pillars 22 are shown by way of example. The number of p-type pillars 22 is set according to the specific specifications of the semiconductor power device. A p-type body region 23 is located in the n-type semiconductor layer 21 and on top of the p-type pillars 22, and an n-type source region 24 is located in the p-type body region 23.

A gate structure recessed in the n-type semiconductor layer 21 for controlling the opening and closing of the current channel, the gate structure comprising a gate dielectric layer 27 and a gate 28;

The clamp gate 26 is recessed in the p-type body region 23. The bottom of the clamp gate 26 may be located in the p-type body region 23, or may extend downward into the p-type column 22. FIG. 1 shows an example in which the bottom of the clamp gate 26 extends downward into the p-type column 22. The clamp gate 26 is isolated from the p-type body region 23 by the first gate dielectric layer 25.

The source metal layer 30 is electrically connected to the n-type source region 24 and the clamping gate 26, and the interlayer insulating layer 29 is used to isolate the source metal layer 30 from the gate metal layer (based on the positional relationship of the cross section, not shown in FIG. 1). A p-n junction diode structure is formed between the source metal layer 30 and the p-type body region 23. Preferably, the source metal layer 30 directly contacts the p-type body region 23 to form a Schottky barrier diode structure to simplify the structure and manufacturing process of the semiconductor power device. In FIG. 1, in the length direction of the current channel, the contact area between the source metal layer 30 and the p-type body region 23 is located between the n-type source region 24 and the clamping gate 26.

FIG. 2 and FIG. 3 are schematic cross-sectional structural diagrams of a second embodiment of a semiconductor power device provided by the present invention. FIG. 2 is a schematic cross-sectional structural diagram along the length direction of the current channel, and FIG. 3 is a schematic cross-sectional structural diagram along the width direction of the current channel. The difference between the semiconductor power devices shown in FIG. 2 and FIG. 3 and the semiconductor super power device shown in FIG. 1 is that, in the length direction of the current channel, no contact region between the source metal layer 30 and the p-type body region 23 is provided between the clamping gate 26 and the n-type source region 24, and the contact region between the source metal layer 30 and the p-type body region 23 is provided in the width direction of the current channel and the contact region between the source metal layer 30 and the p-type body region 23 is located on one side or both sides of the clamping gate 26. For example, FIG. 3 shows a structure in which the contact region between the source metal layer 30 and the p-type body region 23 is located on one side of the clamping gate 26. In the width direction of the current channel, the contact region between the source metal layer 30 and the p-type body region 23 is provided on one side or both sides of the clamping gate 26, which can effectively reduce the chip area of the semiconductor power device.

FIG4 is a schematic diagram of the cross-sectional structure of the third embodiment of the semiconductor power device provided by the present invention, and FIG4 is a schematic diagram of the cross-sectional structure along the width direction of the current channel. As shown in FIG4, an n-type doping region 40 is provided in the p-type body region 23, and the p-type body region 23 and the n-type doping region 40 form a p-n junction diode structure, and the source metal layer 30 is directly contacted and connected with the n-type doping region 40. In the width direction of the current channel, the n-type doping region 40 is located on one side or both sides of the clamping gate 26. Exemplarily, FIG4 shows a structure in which the n-type doping region 40 is located on one side of the clamping gate 26. Optionally, in the length direction of the current channel, the n-type doping region can be located between the n-type source region and the clamping gate, and this structure is no longer specifically shown in the embodiments of the present invention.

The semiconductor power device of the present invention forms a clamping gate structure in the p-type body region. The clamping gate is externally connected to the source voltage through the source metal layer, which can couple the charge of the semiconductor power device during the turn-on process, so that the p-type body region is clamped at zero potential, thereby not affecting the charging of the Miller capacitor during the turn-on process, so that the Miller platform voltage is reduced, and there is no need to increase the gate drive voltage additionally during application.

Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and the implementation modes, and they can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and the illustrations shown and described herein.

Claims (5)

1. A semiconductor power device, characterized in that it comprises: n-type semiconductor layer; a plurality of p-type pillars located within the n-type semiconductor layer; a p-type body region located in the n-type semiconductor layer and at the top of the p-type column, wherein an n-type source region is disposed in the p-type body region; A gate structure recessed in the n-type semiconductor layer and controlling the opening and closing of the current channel, the gate structure comprising a gate dielectric layer and a gate; a clamp gate recessed in the p-type body region, the clamp gate being isolated from the p-type body region by a first gate dielectric layer; A source metal layer electrically connected to the n-type source region and the clamp gate, wherein a p-n junction diode structure is formed between the source metal layer and the p-type body region. 2. The semiconductor power device as described in claim 1 is characterized in that the source metal layer contacts the p-type body region to form a Schottky barrier diode structure; or, an n-type doped region is provided in the p-type body region, the p-type body region and the n-type doped region form a p-n junction diode structure, and the source metal layer is electrically connected to the n-type doped region. 3. The semiconductor power device as described in claim 2 is characterized in that, in the length direction of the current channel, the contact area between the source metal layer and the p-type body region is located between the n-type source region and the clamping gate, and the n-type doped region is located between the n-type source region and the clamping gate. 4. The semiconductor power device as described in claim 2 is characterized in that, in the width direction of the current channel, the contact area between the source metal layer and the p-type body region is located on one side or both sides of the clamping gate, and the n-type doped region is located on one side or both sides of the clamping gate. 5 . The semiconductor power device according to claim 1 , wherein a bottom of the clamp gate is located in the p-type body region or extends downward into the p-type column.