CN118213372B - 16-bit transparent latch - Google Patents

Abstract

The present application provides a 16-bit transparent latch, which includes: an input cache level circuit and an output driver level circuit to realize a complete 16-bit operation function; in its layout design, SOI process, triple-well process and guard ring process are adopted; the SOI process adopts a substrate suspended CMOS SOI process so that the PMOS transistor and the NMOS transistor are isolated by an insulator to avoid a latch effect; the triple-well process eliminates the latch effect by isolating the third well of the P well and the P substrate; the guard ring process includes: a P+ guard ring, an N+ guard ring or a double-well N+ guard ring to complete radiation resistance reinforcement, and the radiation resistance capability can reach 300K rad (Si).

Description

16-bit transparent latch

Technical Field

The present application relates to the field of semiconductor technology, and in particular to a 16-bit transparent latch.

Background Art

The existing triggers have only partial design reinforcement for radiation resistance, so the general radiation resistance is 10-100Krad (Si). In the case of strong radiation environment, electronic devices are easily damaged, resulting in internal signal mutations, which can cause functional failures and damage to electronic components. Moreover, long-term radiation can also change the device properties.

Summary of the invention

The purpose of the present application is to provide a 16-bit transparent latch, in which SOI process, triple-well process and guard ring process are adopted in its layout design; the SOI process adopts substrate suspended CMOS SOI process so that PMOS and NMOS transistors are isolated by insulators to avoid latch-up effect; the triple-well process eliminates latch-up effect by isolating the third well of P well and P substrate; the guard ring process includes: P+ guard ring, N+ guard ring or double-well N+ guard ring to complete radiation resistance reinforcement, and the radiation resistance capability can reach 300K rad (Si).

In the first aspect, the present application provides a 16-bit transparent latch, and the circuit structure of the 16-bit transparent latch includes: two groups of input enable terminals, each group of input enable terminals controls 8 output terminals and 8 separate latches; each latch is controlled by a separate byte, and the control terminals are connected together to complete a complete 16-bit operation function; the 16-bit transparent latch can be used as two 8-bit latches or four 4-bit latches; the enable terminal determines the state of the eight outputs; in the layout design of the 16-bit transparent latch, SOI process, triple-well process and guard ring process are used; the SOI process uses a substrate suspended CMOS SOI process so that the PMOS transistor and the NMOS transistor are isolated by an insulator to avoid a latch effect; the triple-well process eliminates the latch effect by isolating the P well and the third well of the P substrate; the guard ring process includes: a P+ guard ring, an N+ guard ring or a double-well N+ guard ring to complete radiation resistance reinforcement.

Furthermore, the NMOS transistor uses a P+ guard ring, and the PMOS transistor uses an N+ guard ring, so as to eliminate the field oxygen leakage current path induced by the total dose.

Furthermore, the above-mentioned 16-bit transparent latch includes: an input cache level circuit and an output drive level circuit; the input cache level circuit includes: a first inverter, a second inverter and a latch composed of a transmission gate, a third inverter and a NAND gate; the signal is amplified step by step by the first inverter and the second inverter according to a ratio, and then output through the latch; in the latch, the first transmission gate, the NAND gate, the third inverter and the second transmission gate are connected in sequence; the second transmission gate is also connected to the connection line between the first transmission gate and the NAND gate; when the CK signal is at a low level, the first transmission gate is turned on, and the input signal reaches the output through the inverter; when the CK signal is at a high level, the first transmission gate is turned off, the second transmission gate is turned on, and the output signal is output between the first inverter, the NAND gate and the second The transmission gate is stored and performs a latching function; the transmission gate is composed of a NMOS transistor and a PMOS transistor whose source and drain are connected in common, wherein the gate signal of the PMOS transistor is opposite to the gate signal of the NMOS transistor, and the NMOS transistor and the PMOS transistor are connected in parallel to form a CMOS transmission gate, and the output signal can ensure that the input and output voltages are consistent regardless of whether it is a high level or a low level, and the output voltage will not shift; the output drive stage circuit includes: a current source circuit and a current redundancy circuit; the current source circuit adopts a Darlington structure; the current redundancy circuit adopts an NPN tube plus a Schottky diode anti-saturation structure; the output end adopts a push-pull amplifier circuit made of two NPNs to enhance the load capacity of the entire circuit.

Furthermore, in the layout design of the 16-bit transparent latch, an ESD structure with a specific common emitter structure is adopted, and the ESD structure is an ESD two-stage double ESD common emitter structure composed of two-stage NPN transistors and three resistors; the collector of the NPN transistor Q0 is connected to the input signal, the base is connected to the resistor R1 and is grounded, the emitter is grounded, the PAD is connected to one end of the resistor R8 through the collector of Q0, the other end of R8 is connected to one end of R9, the other end of R9 is connected to the collector of the NPN transistor Q1, the base of Q1 is suspended, and the emitter is grounded; the ESD structure uses a diode structure formed by short-circuiting the base and emitter of the transistor Q0, and the base of the transistor Q1 is suspended, forming a two-stage ESD protection of a diode structure composed of the collector and the emitter, wherein the resistor plays a role of current limiting and voltage dividing.

Furthermore, the above-mentioned product tape-out process anti-radiation reinforcement step includes: it is characterized in that the product tape-out process anti-radiation reinforcement step includes: a low interface state gate oxidation preparation process step and a composite passivation layer process step.

Furthermore, the low interface state gate oxide preparation process comprises: pre-treating the silicon surface, including growing pre-gate oxide and optimizing the cleaning process; controlling the atmosphere and growth temperature during the gate oxide growth process, using slow annealing, and thermally growing the gate oxide layer using _H2 , _O2 synthesis process.

Furthermore, the gate oxide layer thickness is controlled to be 25±10 nm by treating the substrate under an inert atmosphere at 740° C.-760° C. for 20 min-40 min and treating the substrate under an inert atmosphere at 940° C.-950° C. with oxygen flowing for 60 min-80 min.

Furthermore, the above-mentioned composite passivation layer process steps include: preparing _SiO2 film _by PECVD, using silane and laughing gas to react; adjusting _Si3N4 process technology, preparing _Si3N4 film by PECVD, using _silane and ammonia to react; wherein the process technology is: _SiH4 : _NH3 = 1:7; obtaining a composite passivation layer of _{SiO2 + Si3N4} .

Furthermore, the thickness ratio of the above SiO ₂ and Si ₃ N ₄ = 550nm:300nm.

Furthermore, ceramic packaging is used to reinforce the product against radiation: packaging mainly includes three process steps: wafer bonding, bonding and capping. Wafer bonding adopts a fully automatic wafer bonding process, capping adopts a parallel seam welding process, a black ceramic capping process and a colored ceramic melting sealing process, and bonding adopts aluminum wire ultrasonic bonding technology.

The 16-bit transparent latch provided in the present application adopts SOI process, triple-well process and guard ring process in its layout design; the SOI process adopts substrate suspension CMOS SOI process so that the PMOS transistor and the NMOS transistor are isolated by an insulator to avoid the latch effect; the triple-well process eliminates the latch effect by isolating the P well and the third well of the P substrate; the guard ring process includes: P+ guard ring, N+ guard ring or double-well N+ guard ring to complete anti-radiation reinforcement, and the anti-radiation capability can reach 300K rad (Si).

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

FIG1 is a logic diagram of a 16-bit transparent latch provided in an embodiment of the present application;

FIG2 is a circuit diagram of an input cache level circuit in a 16-bit transparent latch provided in an embodiment of the present application;

FIG3 is a circuit diagram of an output driver stage circuit provided in an embodiment of the present application;

FIG4 is a schematic diagram of a specific ESD structure provided in an embodiment of the present application;

FIG5 is a cross-sectional view of a substrate suspension CMOS SOI process provided in an embodiment of the present application;

FIG6 is a cross-sectional view of a triple-well process provided in an embodiment of the present application;

FIG. 7 is a flow chart of a packaging process provided in an embodiment of the present application.

DETAILED DESCRIPTION

The technical solution of the present application will be described clearly and completely in conjunction with the embodiments below. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present application.

With the rapid development of aerospace technology, space technology, nuclear energy industry, high-energy physics research and other technologies, especially the application of these technologies and products in national defense, military, weapons and equipment systems, semiconductor devices are forced to work in radiation-resistant environments. Improving the radiation resistance of products has become the focus of research in the fields of aviation, aerospace, and nuclear applications. The market demand for chips with radiation-resistant designs is very small, and the manufacturing process requirements are high and the cycle is long. Therefore, the design and manufacture of highly radiation-resistant chips is expensive and difficult to find in the market.

A latch is also a circuit that can store data. Its characteristic is that when the latch signal does not come, the state of the output terminal changes with the change of the input terminal state; when the latch signal comes, the data of the input terminal is latched to the output terminal, that is, when the signal of the input terminal changes again, the output terminal will not change.

The product is controlled by byte. Each byte functions identically but independently. Additionally, the control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the latch enable (LEn) input is high, the data on Dn enters the latch. In this case, the latch is closed transparent, that is, the latch output changes state every time its D input changes. When high to low, the latch stores the information present on the D input during the setup time before the high to low transition of LEn. The three-state standard output is controlled by the output enable (OEn) input. When OEn is low, the standard output is in two-state mode. When OEn is high, the standard output is in high impedance mode, but this does not interfere with the input of new data into the latch.

Currently, the commercial three-state output 16-bit transparent latch on the market has not been reinforced with a dedicated radiation-resistant design process. The radiation environment can cause damage to electronic devices, resulting in internal signal mutations, which can cause functional failures and damage to electronic components. Long-term radiation can also change device properties. The existing radiation-resistant design is only a local design reinforcement, so the general radiation resistance is 10-100K rad (Si).

Based on this, an embodiment of the present application provides a 16-bit transparent latch, in whose layout design, SOI process, triple-well process and guard ring process are adopted; the SOI process adopts substrate suspended CMOS SOI process, so that the PMOS transistor and the NMOS transistor are isolated by an insulator to avoid the latch effect; the triple-well process eliminates the latch effect by isolating the P well and the third well of the P substrate; the guard ring process includes: P+ guard ring, N+ guard ring or double-well N+ guard ring to complete anti-radiation reinforcement, and the anti-radiation capability can reach 300K rad (Si).

A 16-bit transparent latch is provided in an embodiment of the present application. The circuit structure of the 16-bit transparent latch includes: two groups of input enable terminals, each group of input enable terminals controls 8 output terminals and 8 separate latches; each latch is controlled by a separate byte, each byte has the same function but is independent of other bytes, and the control terminals are connected together to complete a complete 16-bit operation function; the 16-bit transparent latch can be used as two 8-bit latches or four 4-bit latches; the enable terminal determines the state of the eight outputs (high level, low level or high impedance state); in the layout design of the 16-bit transparent latch, SOI process, triple-well process and guard ring process are used; the SOI process uses a substrate suspended CMOS SOI process so that the PMOS transistor and the NMOS transistor are isolated by an insulator to avoid a latch effect; the triple-well process eliminates the latch effect by isolating the P well and the third well of the P substrate; the guard ring process includes: a P+ guard ring, an N+ guard ring or a double-well N+ guard ring to complete radiation resistance reinforcement.

The logic symbol and logic diagram of the 16-bit transparent latch are shown in Figure 1. The latch is controlled by a byte. When the latch enable (LE) is high, it is transparent to the data. When LE is low, the data that meets the setup time is latched. When the output is enabled, the data appears on the bus (OE) with a low value. When OE is high, the output is in the high Z state. Its truth table is shown in Table 1:

Table 1

Furthermore, the NMOS transistor uses a P+ guard ring, and the PMOS transistor uses an N+ guard ring, so as to eliminate the field oxygen leakage current path induced by the total dose.

Further, the above-mentioned 16-bit transparent latch includes: an input cache level circuit and an output drive level circuit; as shown in FIG2 , the input cache level circuit includes: a first inverter, a second inverter and a latch composed of a transmission gate, a third inverter and a NAND gate; the signal is amplified step by step by the first inverter and the second inverter according to a ratio, and then output through the latch; in the latch, the first transmission gate, the NAND gate, the third inverter, and the second transmission gate are connected in sequence; the second transmission gate is also connected to the connection line between the first transmission gate and the NAND gate; when the CK signal is at a low level, the first transmission gate is turned on, and the input signal reaches the output through the inverter; when the CK signal is at a high level, the first transmission gate is turned off, the second transmission gate is turned on, and the output signal is stored between the first inverter, the NAND gate and the second transmission gate to perform a latching function; because the latch participates in the NAND gate, the latch signal can be controlled by an external signal to be set to 1 or 0, forming a latch with a set reset terminal. The transmission gate is composed of an NMOS transistor and a PMOS transistor whose source and drain are connected together, where the gate signal of the PMOS transistor is opposite to the gate signal of the NMOS transistor. The NMOS transistor and the PMOS transistor are connected in parallel to form a CMOS transmission gate. Whether the output signal is high or low, it can ensure that the input and output voltages are consistent without output voltage offset.

Each group of input signals OE/LE/CLK needs to drive 8 output modules. Due to the large chip area, the signal routing is long, and the parasitic resistance and capacitance are large, so a circuit with higher driving capability and faster response speed is required. The design uses a circuit composed of an inverter and an NPN tube to achieve this. When the output of the inverter is greater than the NPN tube conduction voltage, the NPN tube begins to charge the signal line. Compared with using a CMOS inverter to directly drive the signal line, not only is the flip voltage small, but the response speed is also fast. Under the condition of the same area, the driving output current of this structure is larger. Then use an inverter with an asymmetric ratio of upper and lower tubes to drive the signal line, so that the signal line finally reaches the power supply voltage to ensure that there is no leakage in the output stage.

As shown in FIG3 , the output driver stage circuit includes: a current source circuit and a current redundancy circuit; the current source circuit adopts a Darlington structure; the current redundancy circuit adopts an NPN tube plus a Schottky diode anti-saturation structure; the output end of the output driver stage circuit adopts a push-pull amplifier circuit composed of two NPNs to enhance the load capacity of the entire circuit.

The current source circuit adopts the structure of Darlington tube, which has high current driving capability. At the same time, in order to improve the response speed, a Schottky diode is used to fix the VCE of the NPN tube to achieve the purpose of anti-saturation. In order to eliminate the path between the output pin and VCC when the chip is out of power, a diode is connected in series in the current source path. At the same time, considering that multiple groups of current source outputs are turned on at the same time, a current limiting resistor is added to reduce the SSN effect. The above diodes and current limiting resistors require special layout design. The current sink circuit adopts the structure of NPN tube plus Schottky diode anti-saturation to overcome the charge storage effect; at the same time, considering the SSN (switching noise) effect caused by the simultaneous opening of multiple groups of current sinks, a special circuit is designed to limit the current flowing into the base. The switching timing is specially designed to ensure that the opening time of the current source and the current sink does not overlap, and the dynamic power consumption is small.

Furthermore, in the layout design of the 16-bit transparent latch, an ESD structure with a specific common emitter structure is adopted, as shown in Figure 4, the ESD structure is an ESD two-stage double ESD common emitter structure composed of two-stage NPN transistors and three resistors; the collector of the NPN transistor Q0 is connected to the input signal, the base is connected to the resistor R1 and is grounded, the emitter is grounded, the PAD is connected to one end of the resistor R8 through the collector of Q0, the other end of R8 is connected to one end of R9, the other end of R9 is connected to the collector of the NPN transistor Q1, the base of Q1 is suspended, and the emitter is grounded; the ESD structure uses a diode structure formed by short-circuiting the base and emitter of the transistor Q0, and the base of the transistor Q1 is suspended, forming a two-stage ESD protection of a diode structure composed of the collector and the emitter, in which the resistor plays a role of current limiting and voltage dividing.

The NPN with special layout design is used as the ESD protection tube, which has high current discharge capacity per unit size. Its size is much smaller than that of the NMOS ESD tube under the same ESD capacity. The base is connected to the ground through a large resistor, which can avoid the noise introduced when the base is suspended, and can achieve a trigger voltage of about 10V and a holding voltage of about 8V, which has good latch-up robustness. In order to further improve the anti-static ability, a protection ring is designed around the welding electrode.

Furthermore, the above-mentioned product tape-out process radiation resistance reinforcement step includes: a low interface state gate oxidation preparation process step and a composite passivation layer process step.

Furthermore, the low interface state gate oxide preparation process comprises: pre-treating the silicon surface, including growing pre-gate oxide and optimizing the cleaning process; controlling the atmosphere and growth temperature during the gate oxide growth process, using slow annealing, and thermally growing the gate oxide layer using _H2 , _O2 synthesis process.

Further, the gate oxide layer is 25±10nm. The oxide layer is treated in an inert atmosphere at 740°C-760°C for 20min-40min, and in an inert atmosphere at 940°C-950°C with oxygen for 60min-80min, and the thickness of the oxide layer is controlled to be 25±10nm.

Furthermore, the above-mentioned composite passivation layer process steps include: preparing _SiO2 film _by PECVD, using silane and laughing gas to react; adjusting _Si3N4 process technology, preparing _Si3N4 film by PECVD, using _silane and ammonia to react; wherein the process technology is: _SiH4 : _NH3 = 1:7; obtaining a composite passivation layer of _{SiO2 + Si3N4} .

Furthermore, the thickness ratio of the above SiO ₂ and Si ₃ N ₄ is 550nm:300nm.

Furthermore, ceramic packaging is used to reinforce the product against radiation: packaging mainly includes three process steps: wafer bonding, bonding and capping. Wafer bonding adopts a fully automatic wafer bonding process, capping adopts a parallel seam welding process, a black ceramic capping process and a colored ceramic melting sealing process, and bonding adopts aluminum wire ultrasonic bonding technology.

The above-mentioned guard ring process includes: setting a P+ isolation guard ring outside the NMOS transistor and setting an N+ isolation guard ring outside the PMOS transistor. The product layout is designed with a guard ring structure: the NMOS transistor is surrounded by the P+ active area, and the P-channel device is surrounded by the N+ active area, forming a cutoff effect on the field oxygen inversion leakage channel, thereby improving the circuit's radiation resistance.

In the embodiment of the present application, in order to improve the radiation resistance, a BiCMOS process is used in the layout design, including, in addition to the guard ring process described above, an SOI process and a triple-well process.

① SOI process: SOI process can effectively make latch-up immune. The design adopts substrate suspension CMOS SOI process so that PMOS and NMOS transistors are isolated by insulators. There is no PnPn path, so latch-up will not occur. Figure 5 shows a cross-sectional view of substrate suspension CMOS SOI process.

② Triple-well process: The triple-well process isolates the P-well and the P-substrate through the third well (deep N-well). In this structure, not only the NMOS transistor is isolated from the substrate, but also the PMOS transistor is isolated from the deep N-well. Although this structure has bipolar transistors, it cannot form PnPn, thus completely eliminating latch-up. Figure 6 shows a cross-sectional view of the triple-well process.

The steps of radiation hardening for the product tape-out process are described in detail below, specifically including: low interface state gate oxide preparation process steps and composite passivation layer process steps.

Furthermore, the above-mentioned low interface state gate oxide preparation process steps include: pre-treating the silicon surface, including growing pre-gate oxide and optimizing the cleaning process; controlling the atmosphere and growth temperature during the gate oxide growth process, using slow annealing, and using _H2 , _O2 synthesis process to thermally grow the gate oxide layer. Further, the gate oxide layer is 25±10nm. The process is carried out under an inert atmosphere at 740℃-760℃ for 20min-40min, and under an inert atmosphere at 940℃-950℃ with oxygen for 60min-80min, and the oxide layer thickness is controlled to be 25±10nm.

Specifically, the role of gate oxide is to ensure the smooth flow of circuit current and to be a medium capable of field control. From the basic principle of ionizing radiation effect, it is known that ionizing radiation environment will not only accumulate hole charges in the _SiO2 dielectric layer, but also generate new interface trap charges or interface states at the Si/ _SiO2 interface, which will cause the threshold voltage of MOS transistors to drift, causing the channel current, transconductance and surface mobility to degrade, and have an adverse effect on the performance parameters of the device such as switching speed and driving capability.

The process of forming a thin gate structure using low interface state gate dielectric technology is as follows:

First, in order to improve the quality of the gate oxide layer, the silicon surface must be processed before the gate oxide layer grows, including growing pre-gate oxide, optimizing the cleaning process, etc., to avoid the influence of ion contamination and defects and ensure the quality of the silicon and silicon dioxide interface.

Secondly, during the growth of gate oxide, attention should be paid to the control of atmosphere and growth temperature, and slow annealing should be used to reduce interface state charge and improve gate oxide quality. After preparing the gate dielectric, the thermal process should be minimized to avoid affecting the gate dielectric.

Thirdly, according to the radiation resistance mechanism, reducing the oxide layer thickness can enhance the ability of power BiCMOS to resist ionizing radiation. However, when using BiCMOS, its gate-source breakdown voltage is much higher than that of MOS tubes in conventional integrated circuits. In addition, it is necessary to improve the single-particle gate penetration capability. Therefore, the thickness of the gate dielectric layer of BiCMOS cannot be too thin. This is also one of the many contradictions that need to be comprehensively considered in the manufacture of radiation-resistant BiCMOS devices. High-quality low-interface state gate dielectric preparation and high-quality gate structure control are the core processes of strengthening semiconductor device technology. The quality of the gate oxide layer largely determines the device's ability to resist ionizing radiation. Through a large number of studies and comparative verification experiments, the _H2 and _O2 synthesis processes were finally used to thermally grow a gate oxide layer of about 25nm, which can meet the product parameter requirements.

The above-mentioned composite passivation layer process steps include:

SiO ₂ thin film is prepared by PECVD, and silane and laughing gas are used for reaction; Si ₃ N ₄ process is adjusted, Si ₃ N ₄ thin film is prepared by PECVD, and silane and ammonia are used for reaction; wherein the process is: SiH ₄ :NH ₃ =1:7; and a composite passivation layer of SiO ₂ + Si ₃ N ₄ is obtained. Furthermore, the thickness ratio of the above SiO ₂ and Si ₃ N ₄ =550nm:300nm.

The main function of surface passivation is to cover the surface of semiconductor devices with a dielectric protective film to prevent the surface of semiconductor chips from being contaminated by impurities such as water vapor, dust, and harmful ions. At the same time, it can effectively protect the internal interconnection of the device and prevent the internal circuit from being mechanically and chemically damaged. At present, more composite _passivation layers are used. The company adopts the composite layer passivation method of _SiO2 + _Si3N4 , which can not only achieve a good passivation effect, but also take advantage of the strong contamination blocking ability, strong corrosion resistance, and good radiation resistance _{of Si3N4} itself to form more effective protection for the device. In order to form a good step coverage ability and ensure the density and uniformity of the dielectric layer, the deposition method of the passivation layer uses plasma enhanced chemical vapor deposition (PECVD).

In the SiO ₂ + Si ₃ N ₄ composite layer structure, the stress problem of the Si ₃ N ₄ film layer is the main concern of the passivation layer process.

(1) Select the appropriate SiO ₂ thickness to minimize the stress of Si ₃ N ₄ : In the process research of this product, PECVD is used to prepare SiO ₂ thin film using silane and nitrous oxide to react, and the SiH ₄ -N ₂ O method is used to prepare SiO ₂ film.

(2) Adjust the Si ₃ N ₄ process to reduce its stress and avoid cracking of silicon wafers: PECVD preparation of Si ₃ N ₄ thin films usually uses silane and ammonia to react. Through many experiments with different gas ratios, the stress test after completion proved that when SiH ₄ :NH ₃ =1:7, the film stress formed is moderate and the performance is good.

(3) In addition to considering stress, the impact on radiation hardening performance was also considered in the ratio of SiO ₂ / Si ₃ N ₄ of different thicknesses. Finally, it was confirmed that the ratio of SiO ₂ : Si ₃ N ₄ = 550nm: 300nm was used to effectively protect the device, thereby avoiding stress problems while improving the device's radiation resistance.

Furthermore, the above-mentioned product packaging adopts ceramic packaging: packaging mainly includes three processes: wafer bonding, bonding and capping. In order to meet the requirements of reliability and mass production, the wafer bonding adopts a fully automatic wafer bonding process, the capping adopts a parallel seam welding process, a black ceramic capping process and a colored ceramic melting sealing process, and the bonding adopts an aluminum wire ultrasonic bonding technology to improve product consistency and make the process stable and controlled. The packaging process flow is shown in Figure 7.

The 16-bit transparent latch provided in the embodiment of the present application is designed to be radiation-resistant from multiple aspects such as circuit design, layout design, process flow, and packaging process. An N+ or P+ isolation protection ring is added to the outside of the MOS tube, and a silicon nitride process with high radiation resistance is used. The flattening process is designed, and the packaging design adopts a highly sealed tube shell packaging process with radiation-resistant ceramics to reinforce the solution, and the radiation resistance can reach 300K rad (Si).

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (1)

1. A 16-bit transparent latch, wherein a line structure of the 16-bit transparent latch comprises: two sets of input enabling terminals, each set of input enabling terminals controlling 8 outputs and 8 individual latches; each latch is controlled by a separate byte, and the control ends are connected together to complete the complete 16-bit operation function; the 16-bit transparent latch may be used as two 8-bit latches or four 4-bit latches; the enabling end determines eight paths of output states;

In the layout design of the 16-bit transparent latch, an SOI process, a triple well process and a protection ring process are adopted; the SOI technology adopts a substrate suspension CMOS SOI technology, so that the PMOS transistor and the NMOS transistor are isolated by an insulator, and the latch-up effect is avoided; the triple-well process eliminates latch-up by isolating the P-well from the third well of the P-substrate; the protection ring process comprises the following steps: the P+ protection ring, the N+ protection ring or the double-well N+ protection ring to finish anti-irradiation reinforcement; the NMOS transistor adopts a P+ protection ring, and the PMOS transistor adopts an N+ protection ring, so that a field-oxygen leakage current path induced by total dose is eliminated;

The 16-bit transparent latch includes: an input buffer stage circuit and an output drive stage circuit; the input buffer stage circuit includes: the first inverter, the second inverter and the latch formed by the transmission gate, the third inverter and the NAND gate; the signal is amplified step by the first inverter and the second inverter according to the proportion and then is output through the latch; in the latch, a first transmission gate, a NAND gate, a third inverter and a second transmission gate are sequentially connected; the second transmission gate is also connected to the connecting line between the first transmission gate and the NAND gate; when the CK signal is at a low level, the first transmission gate is started, and the input signal reaches the output through the inverter; when CK is the high level of the signal, the first transmission gate is turned off, the second transmission gate is turned on, the output signal is stored among the first inverter, the NAND gate and the second transmission gate, and the latch function is executed; the transmission gate consists of an NMOS transistor and a PMOS transistor, wherein the grid signal of the PMOS transistor is opposite to the grid signal of the NMOS transistor, the parallel connection method of the NMOS transistor and the PMOS transistor forms the CMOS transmission gate, and the output signal can ensure that the input voltage is consistent with the output voltage and the output voltage deviation cannot occur no matter the output signal is in a high level or a low level; the output driver stage circuit includes: a current source circuit and a current redundancy circuit; the current source circuit adopts a Darlington structure; the current redundancy circuit adopts an NPN tube and Schottky diode anti-saturation structure; the output end adopts a push-pull amplifying circuit made of two NPNs to enhance the load carrying capacity of the whole circuit;

In the layout design of the 16-bit transparent latch, an ESD structure with a specific common emitter structure is adopted, wherein the ESD structure is an ESD two-stage double-ESD common emitter structure consisting of a two-stage NPN triode and three resistors; the collector of NPN triode Q0 is connected with input signal, base electrode is connected with resistor R1 to be grounded, emitter electrode is grounded, PAD is connected with one end of resistor R8 through collector electrode of Q0, the other end of the R8 is connected with one end of the R9, the other end of the R9 is connected with the collector electrode of the NPN triode Q1, the base electrode of the Q1 is suspended, and the emitter electrode is grounded; the ESD structure utilizes a diode structure formed by shorting the base electrode and the emitter electrode of the triode Q0, the base electrode of the triode Q1 is suspended, and two-stage ESD protection of the diode structure formed by the collector electrode and the emitter electrode is formed, wherein the resistor plays a role in current limiting and voltage dividing;

the irradiation-resistant reinforcement step of the product flow sheet process comprises the following steps: a low interface state gate oxidation preparation process step and a composite passivation layer process step;

The preparation process of the low interface state gate oxidation comprises the following steps: pretreating the silicon surface, including growing pre-grid oxide and optimizing cleaning process; controlling atmosphere and growth temperature in the process of growing gate oxide, adopting a slow annealing mode, and adopting an H ₂、O₂ synthesis process to thermally grow a gate oxide layer; treating for 20min-40min under the condition of 740-760 ℃ in inert atmosphere, and treating for 60min-80min under the condition of 940-950 ℃ in inert atmosphere by introducing oxygen, wherein the thickness of the gate oxide layer is controlled to be 25+/-10 nm;

The composite passivation layer process comprises the following steps: preparing a SiO ₂ film by PECVD, and reacting with silane and laughing gas; adjusting a Si ₃N₄ process, preparing a Si ₃N₄ film by adopting PECVD, and reacting with silane and ammonia gas; the process comprises the following steps: siH ₄:NH₃ =1:7; obtaining a composite layer passivation layer of SiO ₂+ Si₃N₄; ratio of thicknesses of SiO ₂ and Si ₃N₄ = 550nm:300nm;

the product is subjected to radiation-resistant reinforcement by adopting ceramic package: the packaging mainly comprises three technological processes of bonding sheets, bonding and sealing covers, wherein the bonding sheets adopt a full-automatic bonding sheet process, the sealing covers adopt a parallel seam welding process, a black ceramic sealing cover process and a color ceramic melting sealing process, and the bonding adopts an aluminum wire ultrasonic bonding technology.