CN118174528B - Discharge protection circuits, electronic equipment and vehicles - Google Patents
Discharge protection circuits, electronic equipment and vehicles Download PDFInfo
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- CN118174528B CN118174528B CN202410578710.6A CN202410578710A CN118174528B CN 118174528 B CN118174528 B CN 118174528B CN 202410578710 A CN202410578710 A CN 202410578710A CN 118174528 B CN118174528 B CN 118174528B
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- 238000001514 detection method Methods 0.000 claims description 37
- 239000003990 capacitor Substances 0.000 claims description 30
- 238000007599 discharging Methods 0.000 claims description 20
- 238000010586 diagram Methods 0.000 description 16
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 8
- 230000002159 abnormal effect Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000000446 fuel Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000010891 electric arc Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B60—VEHICLES IN GENERAL
- B60L—PROPULSION OF ELECTRICALLY-PROPELLED VEHICLES; SUPPLYING ELECTRIC POWER FOR AUXILIARY EQUIPMENT OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRODYNAMIC BRAKE SYSTEMS FOR VEHICLES IN GENERAL; MAGNETIC SUSPENSION OR LEVITATION FOR VEHICLES; MONITORING OPERATING VARIABLES OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRIC SAFETY DEVICES FOR ELECTRICALLY-PROPELLED VEHICLES
- B60L3/00—Electric devices on electrically-propelled vehicles for safety purposes; Monitoring operating variables, e.g. speed, deceleration or energy consumption
- B60L3/0023—Detecting, eliminating, remedying or compensating for drive train abnormalities, e.g. failures within the drive train
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
- G01R19/16566—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
- G01R19/16576—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533 comparing DC or AC voltage with one threshold
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H1/00—Details of emergency protective circuit arrangements
- H02H1/0007—Details of emergency protective circuit arrangements concerning the detecting means
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
- H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
- H02H7/122—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers for inverters, i.e. DC/AC converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
- H02M1/322—Means for rapidly discharging a capacitor of the converter for protecting electrical components or for preventing electrical shock
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
- H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Life Sciences & Earth Sciences (AREA)
- Sustainable Development (AREA)
- Sustainable Energy (AREA)
- Transportation (AREA)
- Mechanical Engineering (AREA)
- Protection Of Static Devices (AREA)
Abstract
本公开涉及一种放电保护电路，包括：控制电路，控制电路具有输出端、第一输入端、第二输入端和第三输入端，控制电路的输出端连接放电电路并输出控制信号以控制放电电路的放电；超时关闭电路，超时关闭电路配置为：在放电执行预定时间时，检测放电电路的母线电压是否低于第一参考电压，并输出第一电信号；过流锁存电路，过流锁存电路配置为检测放电电路是否发生过流并输出第二电信号；控制电路的第一输入端、第二输入端分别接收第一电信号和第二电信号，控制电路的第三输入端接收放电使能信号。本公开还涉及一种包括这样的放电保护电路的电子设备以及包括这样的电子设备的车辆。
The present disclosure relates to a discharge protection circuit, comprising: a control circuit, the control circuit having an output terminal, a first input terminal, a second input terminal and a third input terminal, the output terminal of the control circuit is connected to the discharge circuit and outputs a control signal to control the discharge of the discharge circuit; a timeout shutdown circuit, the timeout shutdown circuit is configured to: when the discharge is executed for a predetermined time, detect whether the bus voltage of the discharge circuit is lower than the first reference voltage, and output a first electrical signal; an overcurrent latch circuit, the overcurrent latch circuit is configured to detect whether an overcurrent occurs in the discharge circuit and output a second electrical signal; the first input terminal and the second input terminal of the control circuit receive the first electrical signal and the second electrical signal respectively, and the third input terminal of the control circuit receives a discharge enable signal. The present disclosure also relates to an electronic device including such a discharge protection circuit and a vehicle including such an electronic device.
Description
Technical Field
The present disclosure relates to a discharge protection circuit. The disclosure also relates to an electronic device comprising such a discharge protection circuit and a vehicle comprising such an electronic device.
Background
With the increasing energy crisis and the requirements of environmental regulations, various manufacturers of large automobiles continuously push out electric automobiles with batteries as sources. The inverter is one of the cores of the electric automobile, receives the whole automobile signal and controls the motor to realize various functions such as running, acceleration, deceleration and the like of the automobile. The battery voltage of the electric automobile is mainly classified into a plurality of grades, the battery voltage is safe and first at any time, and the higher the voltage grade is, the higher the requirement on the voltage safety is.
In some scenarios, the whole vehicle loop is charged with the risk of personal shock, thus requiring active discharge of the inverter. When the inverter receives an active discharge instruction of the whole vehicle or the low voltage KL30 is abnormal, the active discharge is executed. Standard GB/T188488 specifies that the bus voltage of the discharge circuit is to be reduced to below 60V within 3 s. The active discharge can be realized in various forms, and when the motor and the inverter are normal, the discharge can be realized by controlling the motor, but in the active discharge process, there may be some abnormal situations, and the active discharge function needs to be turned off, for example:
(1) The relay of the battery is adhered, the high voltage cannot be disconnected, the discharging function is required to be closed within a certain time, and the discharging circuit is ensured not to be damaged. Because then if the inverter is discharged for a long time, some devices in the discharge circuit may overheat and be damaged.
(2) When the active discharging circuit works, the circuit needs to be immediately closed once abnormal, so that arc discharge, spark, explosion and the like of the inverter under high voltage and high current are prevented.
Therefore, a discharge protection circuit is required to turn off the active discharge function when an abnormality occurs in the active discharge.
Disclosure of Invention
Accordingly, the present disclosure is directed to solving the above-described problems, and an object thereof is to provide a novel discharge protection circuit, an electronic device, and a vehicle. According to the discharge protection circuit, the discharge circuit can safely and reliably perform an active discharge function, and key devices of the discharge circuit are protected from being continuously heated to cause damage.
The object is achieved by a discharge protection circuit provided according to an embodiment of the present disclosure, including: the control circuit is provided with an output end, a first input end, a second input end and a third input end, and the output end of the control circuit is connected with the discharge circuit and outputs a control signal to control the discharge of the discharge circuit; a timeout shutdown circuit configured to: detecting whether a bus voltage of the discharge circuit is lower than a first reference voltage when the discharge is performed for the predetermined time, and outputting a first electrical signal; an overcurrent latch circuit configured to detect whether the discharge circuit is overcurrent and output a second electric signal; the first input end and the second input end of the control circuit respectively receive the first electric signal and the second electric signal, and the third input end of the control circuit receives a discharge enabling signal.
According to one embodiment of the present disclosure, the discharge protection circuit further includes a bus voltage detection circuit configured to detect a bus voltage of the discharge circuit and output a bus voltage detection signal.
According to one embodiment of the present disclosure, the control circuit is an or gate, and the discharge circuit performs discharge when the first electrical signal, the second electrical signal, and the discharge enable signal are all at a logic low level, otherwise, the discharge circuit stops the discharge.
According to one embodiment of the present disclosure, the timeout closing circuit includes a timer circuit for outputting the bus voltage detection signal when discharge is performed for a predetermined time, and a first comparison circuit including a first comparator for comparing the first reference voltage and the bus voltage detection signal and outputting the first electric signal.
According to one embodiment of the present disclosure, the timer circuit includes a gate voltage control circuit and a first transistor, the gate voltage control circuit being configured to control on and off of the first transistor.
According to one embodiment of the present disclosure, the bus voltage detection signal is sent to the drain of the first transistor with the first transistor turned off.
According to one embodiment of the present disclosure, the gate voltage control circuit includes a first capacitor and a charge-discharge circuit for charging and discharging the first capacitor, a voltage of the first capacitor being supplied to a gate of the first transistor to control on and off of the first transistor.
According to one embodiment of the present disclosure, the charge and discharge circuit includes: a charging path including a second transistor, an emitter of the second transistor receiving a first input voltage, a collector of the second transistor being connected to a first end of the first capacitor, a second end of the first capacitor being grounded; a discharge path including a first resistor having a first end connected to the first end of the first capacitor and the gate of the first transistor, and a second end grounded; the first input voltage charges the first capacitor in a state where the second transistor is turned on, and the first capacitor discharges through the first resistor in a state where the second transistor is turned off.
According to one embodiment of the present disclosure, the charging path further includes a voltage dividing circuit and a third transistor, wherein the voltage dividing circuit includes a second resistor and a third resistor connected in series, one end of the voltage dividing circuit receives the first input voltage and is connected to an emitter of the second transistor, the other end of the voltage dividing circuit is connected to a collector of the third transistor, a midpoint of the voltage dividing circuit is connected to the base of the second transistor, an emitter of the third transistor is grounded, and a base of the third transistor receives the discharge enable signal for controlling on and off of the third transistor.
According to one embodiment of the present disclosure, the over-current latch circuit includes a second comparison circuit including a second comparator for comparing a discharge loop current signal of the discharge circuit with a second reference voltage and outputting a fourth electrical signal, and a flip-flop circuit for receiving the fourth electrical signal and outputting the second electrical signal.
According to one embodiment of the disclosure, the flip-flop circuit includes a first input terminal, a second input terminal, a third input terminal, and an output terminal, the first input terminal of the flip-flop circuit receives the fourth electrical signal, the second input terminal of the flip-flop circuit is connected to a clock signal generation circuit, the third input terminal of the flip-flop circuit receives the first input voltage, the output terminal of the flip-flop circuit generates an output signal and is connected to a second electrical signal generation circuit, the clock signal generation circuit is used for generating a clock signal of the flip-flop circuit, and the second electrical signal generation circuit is used for generating the second electrical signal based on the output signal of the flip-flop circuit.
According to one embodiment of the present disclosure, the flip-flop circuit includes a D flip-flop.
According to one embodiment of the present disclosure, the clock signal generating circuit includes a fourth transistor, a base of the fourth transistor receives the discharge enable signal, a collector of the fourth transistor receives the first input voltage and is connected to the second input terminal of the flip-flop circuit, an emitter of the fourth transistor is grounded, the second electric signal generating circuit includes a fifth transistor, a base of the fifth transistor receives the output signal of the flip-flop circuit, a collector of the fifth transistor receives the first input voltage and outputs the second electric signal, an emitter of the fifth transistor is grounded, the discharge enable signal controls on and off of the fourth transistor, and an output signal of the flip-flop circuit controls on and off of the fifth transistor.
According to one embodiment of the present disclosure, the bus voltage detection circuit includes a voltage dividing circuit for dividing the bus voltage signal and outputting a divided signal, a low pass filter circuit for filtering the divided signal and outputting a filtered signal, and a voltage follower circuit for receiving the filtered signal and outputting the bus voltage detection signal.
The present disclosure also relates to an electronic device comprising a discharge protection circuit as described above.
The present disclosure also relates to a vehicle comprising an electronic device as described above.
Drawings
The above and other features and advantages of the present disclosure will become more apparent from the following detailed description of exemplary embodiments in conjunction with the accompanying drawings, which are provided for illustrative purposes only and are not intended to limit the scope of the present disclosure in any way. The following drawings are not intended to be drawn to scale on actual dimensions, emphasis instead being placed upon illustrating the principles of the disclosure.
FIG. 1 is a schematic diagram of a discharge protection circuit provided by an embodiment of the present disclosure;
FIG. 2 is a simplified schematic diagram of a discharge circuit;
FIG. 3 is a simplified schematic diagram of a timeout shutdown circuit provided by an embodiment of the present disclosure;
FIG. 4 is a detailed schematic diagram of a timeout shutdown circuit provided by an embodiment of the present disclosure;
FIG. 5 is a simplified schematic diagram of an over-current latch circuit provided by an embodiment of the present disclosure;
FIG. 6 is a detailed schematic diagram of an over-current latch circuit provided by an embodiment of the present disclosure;
FIG. 7 is a simplified schematic diagram of a bus voltage detection circuit provided by an embodiment of the present disclosure;
Fig. 8 is a detailed schematic diagram of a bus voltage detection circuit provided by an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure.
For ease of description, the drawings of the present disclosure accordingly simplify or omit components commonly used in the art, such as external connection wires and other components not relevant to the description of the present disclosure. These omitted or simplified components do not affect the understanding of the present disclosure by those skilled in the art.
Aiming at the problems existing in the prior art, the following solutions mainly exist at present:
(1) The temperature of key devices of the discharge circuit is detected, and over-temperature protection is set. However, the temperature of the device cannot be suddenly changed, the detection has time delay, the threshold value of over-temperature protection needs to be tested and calibrated, the scheme is easily influenced by the ambient temperature, and the design and verification are complex.
(2) And detecting whether the voltage signal after the active discharge is reduced according to a certain slope through software, if not, judging that the discharge fails, and closing the discharge function. But this scheme is subject to software and if the software fails during discharge, this protection scheme will also fail.
At least one embodiment of the present disclosure provides a discharge protection circuit. The discharge protection circuit can enable the discharge circuit to safely and reliably execute an active discharge function, and key devices of the discharge circuit are protected from being damaged due to continuous heating.
Fig. 1 shows a schematic diagram of a discharge protection circuit provided by an embodiment of the present disclosure.
As shown in fig. 1, the discharge protection circuit includes a control circuit 10, a timeout closing circuit 11, and an overcurrent latch circuit 12. The control circuit 10 has an output terminal OUT, a first input terminal IN1, a second input terminal IN2, and a third input terminal IN3. The output terminal OUT of the control circuit 10 is connected to the discharge circuit 14 and outputs a control signal to control the discharge of the discharge circuit 14.
The timeout closing circuit 11 is configured to: when the discharging is performed for a predetermined time, it is detected whether a bus voltage of the discharging circuit is lower than a first reference voltage, and a first electric signal is output.
The overcurrent latch circuit 12 is configured to detect whether or not the discharge circuit is overcurrent and output a second electric signal.
The first input terminal IN1 and the second input terminal IN2 of the control circuit 10 are respectively connected to the timeout closing circuit 11 and the overcurrent latch circuit 12 to respectively receive the first electric signal and the second electric signal, and the third input terminal IN3 of the control circuit 10 receives the discharge enable signal n_adis_en. The discharge enable signal is controlled by a micro control unit (Microcontrollel unit, MCU), for example, a logic low active.
For example, in one embodiment of the present disclosure, the control circuit 10 is an or gate. The discharge circuit 14 performs the discharge when the first electrical signal, the second electrical signal, and the discharge enable signal are all at the logic low level, otherwise, the discharge circuit 14 stops the discharge. It should be noted that the control circuit 10 may take other forms as long as the same control logic can be implemented.
Fig. 2 shows a simplified schematic diagram of the discharge circuit 14 of fig. 1.
As shown in fig. 2, the discharging circuit 14 includes a commutation switch M2, a constant power control unit, a voltage sensor (not shown in fig. 2), and a current sensor (not shown in fig. 2), wherein the current sensor includes a current measuring resistor r_short. The voltage sensor obtains the voltage HVDC by measuring the voltage across the discharge capacitance (not shown in fig. 2) of the discharge circuit 14 and the current sensor measures the current i_discharge flowing through the converter switch M2 by measuring the voltage drop across the current measuring resistor r_shot. The constant power control unit receives three inputs, namely a voltage HVDC, a current I_discharge and a control signal output by the discharge protection circuit, and controls the on and off of the converter switch M2 based on the three inputs, so as to control whether to execute a discharge function.
Fig. 3 shows a simplified schematic diagram of a timeout shutdown circuit provided by an embodiment of the present disclosure.
As shown in fig. 3, the timeout closing circuit 11 includes a timer circuit 101 and a first comparing circuit 102.
The timer circuit 101 is configured to output a bus voltage detection signal when discharge is performed for a predetermined time, and the first comparison circuit 102 includes a first comparator configured to compare a first reference voltage Uref1 with the bus voltage detection signal and output a first electrical signal bat_con.
In some embodiments of the present disclosure, the discharge protection circuit further includes a bus voltage detection circuit 13, the bus voltage detection circuit 13 being configured to generate a bus voltage detection signal, the bus voltage detection circuit 13 being configured to detect a bus voltage of the discharge circuit and output the bus voltage detection signal. The specific structure of the bus voltage detection circuit 13 will be described in detail below, and will not be described here again.
For example, the predetermined time is 5 seconds, the bus voltage is 60V, and the bus voltage passes through the bus voltage detection circuit to obtain a bus voltage detection signal. After the discharge is performed for 5 seconds, the timer circuit 101 outputs a bus voltage detection signal to one input terminal of a first comparator, the other input terminal of the first comparator receives a first reference voltage, and the first comparator compares the bus voltage detection signal with the first reference voltage. If the bus voltage is not lower than 60V after the active discharge is carried out for 5 seconds, judging the discharge timeout, reporting the discharge timeout fault of the micro-control unit, and immediately closing the discharge function.
The overtime closing circuit can automatically close the discharging function in a certain time to protect the discharging circuit. For example, when the relay of the high-voltage battery is not opened, it is necessary to stop the active discharge and turn off the discharge function after the discharge circuit continues to discharge for a predetermined time (e.g., 5 seconds) to protect key components of the discharge circuit from continuous heating and damage.
Fig. 4 shows a detailed schematic diagram of a timeout shutdown circuit provided by an embodiment of the present disclosure.
As shown in fig. 4, the timer circuit 101 includes a gate voltage control circuit 111 and a first transistor M1, and the gate voltage control circuit 111 is configured to control on and off of the first transistor M1. The gate voltage control circuit 111 includes a first capacitor C1 and a charge-discharge circuit for charging and discharging the first capacitor C1, the voltage of the first capacitor C1 being supplied to the gate of the first transistor M1 to control on and off of the first transistor M1.
The charge-discharge circuit includes a charge path and a discharge path. The charging path includes a second transistor Q1, a voltage dividing circuit, and a third transistor Q2, and resistors R5 and R6 shown in the figure are internal structures of the third transistor Q2, which are not described herein. An emitter of the second transistor Q1 receives the first input voltage p5_hv, a collector of the second transistor Q1 is connected to a first end of the first capacitor C1, and a second end of the first capacitor C1 is grounded. The voltage dividing circuit comprises a second resistor R3 and a third resistor R4 which are connected in series, one end of the voltage dividing circuit receives a first input voltage P5_HV, the other end of the voltage dividing circuit is connected with a collector of a third transistor Q2, a midpoint of the voltage dividing circuit is connected with a base of a second transistor Q1, an emitter of the third transistor Q2 is grounded, the base of the third transistor Q2 receives a discharge enable signal N_ADIS_EN, and the discharge enable signal N_ADIS_EN is used for controlling the on and off of the third transistor Q2.
The discharge path includes a first resistor R8, a first end of the first resistor R8 is connected to a first end of the first capacitor C1 and a gate of the first transistor M1, and a second end of the first resistor R8 is grounded. The first input voltage p5_hv charges the first capacitor C1 in a state where the second transistor Q1 is turned on, and the first capacitor C1 is discharged through the first resistor R8 in a state where the second transistor Q1 is turned off.
As shown in fig. 4, the first comparison circuit 102 includes a first comparator U6, and the first comparator U6 compares the first reference voltage Uref1 with the bus voltage detection signal and outputs a first electric signal bat_con.
The functional implementation of the timeout closing circuit is described below with reference to fig. 4.
When the discharging command of the MCU is not received, the discharging enable signal n_adis_en is at a high level, the third transistor Q2 is in a conductive state, the second resistor R3 and the third resistor R4 divide the first input voltage p5_hv such that the second transistor Q1 operates in the conductive state, the first input voltage p5_hv charges the first capacitor C1, and the voltage on the first capacitor C1 is equal to the first input voltage p5_hv. For example, the first input voltage p5_hv is 5V, and it should be noted that the voltage value of the first input voltage is not limited in this disclosure. At this time, the first transistor M1 is turned on, the signal delay_timer at the drain of the first transistor M1 is grounded and sent to one end of the first comparator U6, and the first reference voltage Uref1 is input to the other end of the first comparator U6, for example, the first reference voltage Uref1 is obtained by dividing the first input voltage p5_hv by the resistors R53 and R54. The first comparator U6 compares delay_timer with Uref1, and at this time, the first comparator U6 outputs a logic low level. When the discharging instruction of the MCU is received, the active discharging is immediately performed, the discharging enable signal is at a logic low level, the second transistor Q1 is turned off, the third transistor Q2 is turned off, and the first capacitor C1 starts to discharge through the first resistor R8. After 5s, the voltage of the first capacitor C1 is lower than the on voltage of the first transistor M1, the first transistor M1 is turned off, and the bus voltage detection signal hv_meas generates a signal delay_timer at the drain of the first transistor M1 through the resistor R18, which is supplied to one input terminal of the first comparator U6. The first comparator U6 compares delay_timer with the first reference voltage Uref 1. If the delay_timer is higher than the first reference voltage Uref1, outputting a high level, closing the discharging function and reporting the MCU active discharging failure, otherwise outputting a low level.
The timeout shutdown circuit may periodically shut down the discharge function to protect the discharge circuit. For example, when the relay of the high-voltage battery is not disconnected, active discharge is required to be executed, the discharge function is closed after the discharge is continuously carried out for 5 seconds within the capacity range of the discharge circuit, and key devices of the discharge circuit are protected from being continuously heated to cause damage.
Fig. 5 shows a simplified schematic diagram of an over-current latch circuit provided by an embodiment of the present disclosure.
As shown in fig. 5, the overcurrent latch circuit 12 includes a second comparison circuit 201 and a flip-flop circuit 202. The second comparing circuit 201 is configured to compare the discharge loop current signal adis_cur_meas of the discharge circuit 14 with the second reference voltage Vref2 (e.g., the second reference voltage Vref2 is scaled by the first input voltage p5_hv) and output a fourth electrical signal. The flip-flop circuit 202 includes a D flip-flop. The flip-flop circuit 202 includes a first input, a second input, a third input, and an output. A first input terminal of the flip-flop circuit 202 receives the fourth electrical signal, a second input terminal of the flip-flop circuit 202 is connected to the clock signal generation circuit 203, a third input terminal of the flip-flop circuit 202 receives the first input voltage p5_hv, and an output terminal of the flip-flop circuit 202 generates an output signal and is connected to the second electrical signal generation circuit 204.
The clock signal generation circuit 203 is configured to generate a clock signal of the flip-flop circuit 202, and the second electrical signal generation circuit 204 is configured to generate a second electrical signal adis_cur_oc_latch based on an output signal of the flip-flop circuit.
Fig. 6 shows a detailed schematic diagram of an over-current latch circuit provided by an embodiment of the present disclosure.
As shown in fig. 6, the second comparison circuit 201 includes a second comparator U5, for example, the model number of the second comparator U5 is LT1716. It should be noted that the present disclosure does not limit the model of the second comparator. The resistor R52 and the capacitor C2 are both internal components of the second comparator, and are not described here again. One input end of the second comparator U5 receives the discharge loop current signal adis_cur_meas of the discharge circuit 14, and the other input end receives the second reference voltage Uref2, wherein the second reference voltage Uref2 is obtained by dividing the first input voltage p5_hv by a voltage dividing circuit formed by resistors R55 and R56. The second comparator U5 may compare the second reference voltage Uref2 and the discharge loop current signal adis_cur_meas. The output end of the second comparator U5 outputs a fourth electrical signal adis_cur_oc, and is connected to a pull-up circuit, the pull-up resistor is R49, and the pull-up voltage is p5_hv.
For example, in this embodiment, the flip-flop circuit 202 includes a D flip-flop. The first input terminal of the flip-flop circuit 202 is the set terminal PRE of the D flip-flop, the terminal receives the fourth electrical signal adis_cur_oc, the second input terminal of the flip-flop circuit 202 is the clock signal terminal CLK of the D flip-flop, the terminal is connected to the clock signal generating circuit 203, the third input terminal of the flip-flop circuit 202 is the data terminal D of the D flip-flop, the terminal receives the first input voltage p5_hv, the output terminal of the flip-flop circuit 202 is the output terminal Q of the D flip-flop, and the terminal is connected to the second electrical signal generating circuit 204.
As shown in fig. 6, the clock signal generating circuit 203 includes a fourth transistor Q5, a base of the fourth transistor Q5 receives the discharge enable signal n_adis_en, a collector of the fourth transistor Q5 receives the first input voltage p5_hv and is connected to the data terminal D of the D flip-flop, and an emitter of the fourth transistor Q5 is grounded. The second electric signal generating circuit 204 includes a fifth transistor Q6, a base of the fifth transistor Q6 is connected to the output terminal Q of the D flip-flop, a collector of the fifth transistor Q6 is connected to a pull-up circuit (a pull-up resistor of the pull-up circuit is R63, a pull-up voltage is a first input voltage p5_hv) and outputs a second electric signal adis_cur_oc_latch, and an emitter of the fifth transistor Q6 is grounded. The discharge enable signal n_adis_en controls on and off of the fourth transistor Q5, and the output signal of the flip-flop circuit controls on and off of the fifth transistor Q6.
The functional implementation of the overcurrent latch circuit is described below with reference to fig. 6.
When detecting that the discharge circuit has an overcurrent fault, the second comparator U5 outputs a low level, that is, the fourth electrical signal adis_cur_oc is low, and at this time, no matter what the inputs of the data terminal D and the clock signal terminal CLK are, the output terminal Q of the D flip-flop outputs a low level, the electrical signal input to the base of the fifth transistor Q6 is low (the resistors R62 and R57 are the internal resistors of the fifth transistor Q6, which are not described herein), the fifth transistor Q6 is turned off, the first input voltage p5_hv is output to the collector of the fifth transistor Q6 through the resistor R63, and the second electrical signal adis_cur_oc_latch is high, which indicates that the discharge function is disabled. When the discharge circuit has no overcurrent fault, the second comparator U5 outputs a high level, i.e., the fourth electrical signal adis_cur_oc is a high level. In the case where the discharge enable signal n_adis_en is at a low level, the electric signal divided by the resistors R59 and R58 is at a low level (the resistors R59 and R58 are internal resistances of the fourth transistor Q5, which will not be described here in detail), the fourth transistor Q5 is turned off, and the first input voltage p5_hv is input to the clock signal input terminal CLK through the resistor R60, i.e., the clock signal of the D flip-flop is at a rising edge. The first input voltage p5_hv is input to the data terminal D of the D flip-flop through the resistor R1, the output terminal Q of the D flip-flop outputs a high level, the fifth transistor Q6 is turned on, the second electrical signal adis_cur_oc_latch is a logic low level, and the active discharging function can be normally performed. When the overcurrent fault disappears and the discharge enable signal is received again, the clock signal terminal CLK of the D flip-flop is on the rising edge, and the second electrical signal adis_cur_oc_latch is low level, thereby allowing the active discharge to be performed again.
The overcurrent latch circuit can latch a fault signal immediately after detecting the overcurrent fault of the discharge loop, and close the discharge function. After protection due to failure of discharge caused by external reasons, the discharge can be re-executed after the active discharge request command is received again.
Fig. 7 shows a simplified schematic diagram of a bus voltage detection circuit provided by an embodiment of the present disclosure.
As shown in fig. 7, the bus voltage detection circuit 13 includes a voltage division circuit 301, a low-pass filter circuit 302, and a voltage follower circuit 303. The voltage dividing circuit 301 is configured to divide the bus voltage dcp_adis_sgn and output a divided signal, the low-pass filter circuit 302 is configured to filter the divided signal and output a filtered signal, and the voltage follower circuit 303 is configured to receive the filtered signal and output a bus voltage detection signal hv_meas.
Fig. 8 shows a detailed schematic diagram of a bus voltage detection circuit provided by an embodiment of the present disclosure.
As shown in fig. 8, the bus voltage dcp_adis_sgn is divided by a voltage dividing circuit (the voltage dividing circuit includes resistors R2, R7, R9, R10, R11, R12, R13, R14, R15, R16), passes through a low-pass filter circuit (the low-pass filter circuit is a first-order low-pass filter circuit composed of a resistor R17 and a capacitor C3, for example), and then passes through a voltage follower circuit U1, and outputs a bus voltage detection signal hv_meas. For example, the voltage follower circuit U1 receives a second input voltage p18_hv_red, for example, the second input voltage is 18V.
According to another aspect of the present disclosure, an electronic device is presented that includes a discharge protection circuit as described above. It should be appreciated that the electronic device of the present disclosure also has the advantages described above with respect to the discharge protection circuit.
According to another aspect of the present disclosure, a vehicle is presented comprising an electronic device as described above. The vehicle may be an electrified vehicle (ELECTRIFIED VEHICLE), such as a Battery electric vehicle (BEV, battery ELECTRIC VEHICLE), a Hybrid electric vehicle (HEV, hybrid ELECTRIC VEHICLE), a Plug-in Hybrid ELECTRIC VEHICLE, an extended range electric vehicle (Range extended EV), a Fuel cell vehicle (FCEV, fuel CELL ELECTRIC VEHICLE). The vehicle may also be a hydrogen-powered vehicle. It should be appreciated that the vehicle of the present disclosure also has the advantages described above with respect to the discharge protection circuit.
Certain features, structures, or characteristics of one or more embodiments of the present disclosure may be combined as suitable.
The foregoing is illustrative of the present disclosure and is not to be construed as limiting thereof. Although a few exemplary embodiments of this disclosure have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this disclosure. Accordingly, all such modifications are intended to be included within the scope of this disclosure as defined in the claims. It is to be understood that the foregoing is illustrative of the present disclosure and that the present disclosure is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the disclosure.
Claims (11)
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104626995A (en) * | 2013-11-06 | 2015-05-20 | 联合汽车电子有限公司 | High-voltage discharge system of electric vehicle |
| CN218569880U (en) * | 2022-10-27 | 2023-03-03 | 湖北亿纬动力有限公司 | Rapid overcurrent protection circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2012078601A1 (en) * | 2010-12-06 | 2012-06-14 | Coda Automotive, Inc. | Measuring isolated high voltage and detecting isolation breakdown with measures for self-detection of circuit faults |
| CN103647323A (en) * | 2013-12-13 | 2014-03-19 | 海能达通信股份有限公司 | Cell discharge overcurrent protection circuit and cell discharge overcurrent protection method |
| CN108123428B (en) * | 2016-11-29 | 2020-03-03 | 长城汽车股份有限公司 | Voltage discharge method and system of motor controller and vehicle |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104626995A (en) * | 2013-11-06 | 2015-05-20 | 联合汽车电子有限公司 | High-voltage discharge system of electric vehicle |
| CN218569880U (en) * | 2022-10-27 | 2023-03-03 | 湖北亿纬动力有限公司 | Rapid overcurrent protection circuit |
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