CN118171624B

CN118171624B - Circuit layout method, system, semiconductor chip and electronic equipment

Info

Publication number: CN118171624B
Application number: CN202410585056.1A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Shenzhen Dianke Xingtuo Technology Co ltd
Current assignee: Shenzhen Dianke Xingtuo Technology Co ltd
Priority date: 2024-05-13
Filing date: 2024-05-13
Publication date: 2024-08-13
Anticipated expiration: 2044-05-13
Also published as: CN118171624A

Abstract

The invention provides a circuit layout method, a circuit layout system, a semiconductor chip and electronic equipment, and relates to the technical field of integrated circuits. The turn-off area is divided based on the power consumption reference data, and the size of the turn-off area and the number of power switching units are determined. And determining a second interval between adjacent normally-open power supply lines according to the number of the power supply switch units, the size of the turn-off area and the self parameters of the functional module. Determining a screening range according to the initial coordinates and the second interval of the special units; and selecting a normally open power line closest to the special unit from the screening range, and adjusting the initial coordinates of the special unit according to the coordinates of the normally open power line to obtain the target position. The invention makes the path from the special unit to the normally open power line in the power grid shortest by adjusting the position of the special unit, thereby reducing the length of the power winding and the voltage drop.

Description

Circuit layout method, system, semiconductor chip and electronic equipment

Technical Field

The present invention relates to the field of integrated circuits, and in particular, to a circuit layout method, a system, a semiconductor chip, and an electronic device.

Background

With the rapid development of semiconductor processes, the feature sizes of the processes are also continuously reduced. Meanwhile, as the scale of the semiconductor chip and the complexity of the system are continuously improved, the power consumption of the semiconductor chip is also increased. In order to meet the energy saving specification and cope with the market demand for energy saving, it has been a great trend to reduce the power consumption of semiconductor chips. Accordingly, more and more semiconductor chip designs employ power-off technology to reduce power consumption. The power-off technology generally refers to that when some modules in a semiconductor chip do not work, a connection link between the modules and a power supply is turned off through a power switch unit. When the module works, the connecting link between the module and the power supply is conducted through the power switch unit.

In low power design of semiconductor chips, the power-off technique can reduce leakage current in the power-off region (hereinafter referred to as the off region for convenience of description), and the leakage current value can be close to zero, greatly reducing the static power consumption of the chip. Therefore, the power-off technology is important in realizing low-power design. In the process of physical implementation of the digital back end, the power supply shutdown technology is also important in the placement of special units and the connection mode of the special units and a power supply in the low-power design. The special unit is a module for correctly realizing the shutdown of multiple voltages or a certain voltage domain in the low-power-consumption design. Specific units include, but are not limited to: isolation unit, voltage/level converter, power switch unit and normally open unit.

In the prior art, the placement and connection of each functional module in the low-power design can be realized through an automatic wiring tool, but the effect is often poor. The reason is that the automatic routing tool typically only considers the conditions of timing constraints, design rule constraints, etc., and does not consider voltage Drop (IR Drop), resulting in random placement of the specific cells under the automatic routing tool. The random placement results in too long power lines for most of the functional modules, especially for special units. Because the secondary power pins of a particular unit are not typically on the power rail, the automatic routing tool will directly connect the secondary power pins to the power grid via the signal path without regard to voltage drop effects. This design process often results in excessive signal routing for a particular cell.

Further, the excessive signal winding of the special unit may cause an excessive voltage drop of the special unit. The above voltage drop is a voltage value describing a phenomenon of voltage rise or fall in a circuit, for example, in a semiconductor chip in a flip-chip package form, the voltage drop is equal in value to a voltage consumed at a power input pin of a metal bump to each functional module in the semiconductor chip. That is, the actual voltage of the power input pin is the power supply voltage at the metal bump minus the voltage drop. The voltage drop is too large, and the power input pins of the functional modules can cause logic errors or stop working due to insufficient voltage.

Based on this, a circuit layout method applied to low power design is needed to adjust the layout of special cells and reduce the voltage drop.

Disclosure of Invention

The invention aims to provide a circuit layout method, a system, a semiconductor chip and electronic equipment, wherein the position of a special unit is adjusted to enable the path from the special unit to a normally-open power line in a power grid to be shortest, so that the length of a winding wire, particularly the length of the winding wire from a secondary power pin in the special unit to the normally-open power line, is reduced, and the voltage drop is reduced.

The invention can be realized as follows:

in a first aspect, the present invention provides a circuit layout method for laying out a power grid and a special cell in a semiconductor chip, the circuit layout method comprising the steps of:

Dividing a turn-off area based on the power consumption reference data, and determining the size of the turn-off area and the number of power switch units in the turn-off area;

Determining the initial position of a target power switch unit and a first interval between two adjacent power switch units according to the number of the power switch units, the size of the turn-off area and the self parameters of the power switch units;

determining a second interval between adjacent normally open power supply lines and an initial position of a power grid according to the self parameters of the power line sub-module, the initial position of the target power supply switch unit and the first interval; the power line submodule comprises a normally open power line, a power line of a cut-off area and a ground line; the normally open power line, the power line of the turn-off area and the ground line form the power grid;

randomly placing each special unit according to the time sequence reference data and the design rule data, and determining the initial coordinates of each special unit;

Taking any special unit as a target special unit, and determining a screening range according to the second interval; wherein the screening range comprises at least one normally open power line; selecting a normally open power line closest to the target special unit from the at least one normally open power line as a target normally open power line; determining the coordinates of the normally open power line of the target, updating the initial coordinates of the special unit of the target according to the coordinates, and determining the target position of the special unit of the target;

and determining the arrangement structure among the special units according to the corresponding target positions of the special units.

Optionally, the step of dividing the turn-off area based on the power consumption reference data and determining the size of the turn-off area and the number of the power switch units in the turn-off area further includes:

Acquiring configuration parameters and self parameters of the functional module; the configuration parameters comprise time sequence reference data, power consumption reference data and design rule data; the functional module at least comprises a power switch sub-module, a power line sub-module and a special sub-module; the power switch submodule comprises a plurality of power switch units, and the power switch units comprise target power switch units; the special sub-module comprises a plurality of special units; the parameters of the functional module are used for representing the position and the size of the functional module.

Optionally, the step of determining the screening range according to the second interval includes:

Selecting any special unit as a target special unit, and determining a screening range by taking an initial coordinate of the target special unit as a circle center and a preset distance as a radius; the value of the preset distance is determined according to the second interval.

Optionally, the step of determining the value of the preset distance according to the second interval includes:

and determining the radius of the screening range by taking one half of the second interval as a preset distance.

Optionally, the semiconductor chip includes a plurality of wiring layers; wherein the power grid and the special unit are located at different wiring layers in the semiconductor chip; the circuit layout method further comprises the following steps:

And a connecting hole is arranged at the secondary power supply pin of the target special unit, and a metal wire is filled in the connecting hole so as to conduct a link between the target special unit and the target normally-open power supply line through the metal wire.

Optionally, when the power consumption reference data includes a static power consumption, a standard voltage, an on resistance of the power switching unit, and a voltage drop duty ratio of the power switching unit; the number of the power switch units in the turn-off area satisfies the formula:

Ron/Xnum * W/V = V*Pswitch

Wherein Ron is the on resistance of the power switch unit; xnum is the number of power switch units; w is static power consumption; v is a standard voltage; pswitch is the voltage drop duty cycle of the power switching unit.

Optionally, the step of determining the initial position of the target power switch unit and the first interval between two adjacent power switch units according to the number of the power switch units, the size of the turn-off area and the self parameters of the power switch units includes:

Determining a first interval between two adjacent power switch units according to the number of the power switch units, the size of the turn-off area and the self parameters of the power switch units;

The power switch units are connected in series step by step according to the first interval and the sequence from top to bottom to form a plurality of sub-chains which are arranged in rows;

all the sub-chains are sequentially connected in series according to the sequence from left to right, and a loop chain is formed;

taking the column coordinate corresponding to the initial sub-chain in the loop chain as the initial position of the target power switch unit;

the power switch unit comprises a gating signal output end and a gating signal input end; the gating signal output end of any power switch unit is connected with the gating signal input end of the next stage power switch unit.

Optionally, when the size of the turn-off region includes a turn-off region length and a turn-off region width; the self parameters of the power switch unit comprise the width of the power switch unit; when the first pitch includes a column pitch of the power switch units in the turn-off region; the step of determining the initial position of the target power switch unit and the first interval between two adjacent power switch units according to the number of the power switch units, the size of the turn-off area and the self parameters of the power switch units further comprises:

determining the number of rows of the power switch units in the turn-off area according to the width of the turn-off area and the width of the power switch units;

Determining the column number of the power switch units in the turn-off area according to the number of the rows of the power switch units and the number of the power switch units;

Determining the column spacing of the power switch units in the turn-off area according to the length of the turn-off area and the column number of the power switch units;

Taking the power switch units corresponding to the first column and the first row as target power switch units; and determining an initial position of the target power switching unit.

Optionally, when the self parameters of the power line sub-module include a line width, an initial distance between the normally open power line and the power line in the off region, and a third distance between the normally open power line and the ground line; the step of determining the second interval between the adjacent normally open power lines and the initial position of the power grid according to the self parameters of the power line sub-module, the initial position of the target power switch unit and the first interval comprises the following steps:

Adjusting the third interval, the line width and the first interval until the initial interval meets a preset relation, and taking the initial interval meeting the preset relation as a second interval; wherein the preset relation satisfies:

gap=N*pitch =2N *（space+width）

Wherein pitch is the second spacing between the adjacent normally open power supply lines; the space is a third interval between the normally open power line and the ground line; width is the line width; gap is the first pitch; n is a positive integer.

Optionally, the step of determining the second interval between adjacent normally open power supply lines and the initial position of the power grid according to the self parameters of the power line sub-module, the initial position of the target power supply switch unit and the first interval further includes:

Taking the initial position of the target power supply switch unit as the initial coordinate of the power supply grid to determine the initial position of the power supply grid;

And respectively arranging the normally open power line, the power line of the turn-off area and the ground line in the turn-off area according to the second interval and the third interval by taking the initial coordinates as references.

Optionally, the functional module further comprises a macro unit and a standard unit; before the step of dividing the turn-off area based on the power consumption reference data and determining the size of the turn-off area and the number of power switch units in the turn-off area, the method further comprises:

And randomly placing the macro cells and the standard cells according to the design rule data, the time sequence reference data and the design rule data by using an automatic wiring tool.

In a second aspect, the present invention further provides a semiconductor chip, including a power grid and a special unit, where a circuit layout between the power grid and the special unit is determined by the circuit layout method according to any one of the first aspect.

In a third aspect, the present invention further provides a circuit layout system for performing the circuit layout method according to any one of the first aspect, comprising:

the area dividing module is used for dividing a turn-off area based on the power consumption reference data and determining the size of the turn-off area and the number of power switch units in the turn-off area;

the power switch layout module is used for determining the initial position of a target power switch unit and the first interval between two adjacent power switch units according to the number of the power switch units, the size of the turn-off area and the self parameters of the power switch units;

The power grid layout module is used for determining a second interval between adjacent normally open power supply lines and an initial position of a power grid according to the self parameters of the power line sub-module, the initial position of the target power supply switch unit and the first interval; the power line submodule comprises a normally open power line, a power line of a cut-off area and a ground line; the normally open power line, the power line of the turn-off area and the ground line form the power grid;

The special unit layout module is used for randomly placing the special units according to the time sequence reference data and the design rule data and determining the initial coordinates of the special units;

The special unit layout optimization module is used for taking any special unit as a target special unit and determining a screening range according to the second interval; wherein the screening range comprises at least one normally open power line; selecting a normally open power line closest to the target special unit from the at least one normally open power line as a target normally open power line; determining the coordinates of the normally open power line of the target, updating the initial coordinates of the special unit of the target according to the coordinates, and determining the target position of the special unit of the target; and determining the arrangement structure among the special units according to the corresponding target positions of the special units.

In a fourth aspect, the present invention also provides an electronic device comprising a processor and a memory, the memory storing a computer program executable by the processor, the processor being executable to implement the circuit layout method as described in any of the first aspects above.

The beneficial effects of the invention include, for example:

The invention provides a circuit layout method, a system, a semiconductor chip and electronic equipment, wherein a turn-off area is divided based on power consumption reference data according to configuration parameters and self parameters of a functional module, the turn-off area is divided, and the size of the turn-off area and the number of power switch units are determined. And determining the initial position of the target power switch unit and the first interval between two adjacent power switch units according to the number of the power switch units, the size of the turn-off area and the self parameters of the power switch units. And then determining a second interval between adjacent normally open power supply wires in the power grid and the initial position of the power grid according to the self parameters of the power line sub-module, the initial position of the target power switch unit and the first interval. After the initial coordinates of the special units are obtained, a screening range is determined according to the initial coordinates and the second interval, a normally open power line closest to any special unit is selected from the screening range, and the initial coordinates of the special units are adjusted according to the coordinates of the normally open power line, so that the target positions of the special units are obtained. According to the invention, the position of the special unit is adjusted, so that the path from the special unit to the normally open power line is shortest, the length of a signal winding is further reduced, and particularly, the length of the secondary power pin in the special unit to the normally open power line is reduced, and the voltage drop is reduced.

Drawings

In order to more clearly illustrate the technical solutions of the present invention, the drawings that are needed in the present invention will be briefly described below, it being understood that the following drawings only illustrate some of the technical solutions of the present invention and should not be considered as limiting the scope, and that other related drawings can be obtained according to these drawings without the inventive effort of a person skilled in the art.

Fig. 1 is a schematic structural diagram of an electronic device according to the present invention;

FIG. 2 is a flowchart showing steps of a circuit layout method according to the present invention;

FIG. 3 is a schematic diagram showing the steps of step 207 according to the present invention;

FIG. 4 is a second flowchart illustrating a circuit layout method according to the present invention;

FIG. 5 is a schematic diagram showing the distribution of the turn-off regions in the present invention;

FIG. 6 is a schematic diagram showing a sub-step of step 204 of the present invention;

FIG. 7 is a schematic diagram showing an arrangement of a power switch unit according to the present invention;

FIG. 8 is a second schematic diagram of the power switch unit of the present invention;

FIG. 9 is a second step diagram of step 204 of the present invention;

FIG. 10 is a schematic diagram showing the steps of step 205 of the present invention;

FIG. 11 is a schematic diagram of the arrangement of the power grid and the power switch unit according to the present invention;

FIG. 12 is a schematic diagram showing the effect of random placement of special cells on a power grid in the present invention;

FIG. 13 is a schematic view showing the effect of the screening range in step 207 according to the present invention;

FIG. 14 is a schematic diagram showing the effect of the special unit after adjustment in step 207 of the present invention;

FIG. 15 is a third flowchart illustrating a circuit layout method according to the present invention;

FIG. 16 is a fourth flowchart illustrating steps of a circuit layout method according to the present invention;

FIG. 17 is a schematic layout of functional modules in the present invention;

Fig. 18 is a schematic structural diagram of a circuit layout system according to the present invention.

Icon: 100-an electronic device; a 101-processor; 102-memory; 300-a circuit layout system; 301-a region dividing module; 302-a power switch layout module; 303-a power grid layout module; 304-a special cell layout module; 305-a special cell layout optimization module; 400-a first initial unit; 500-a second initial unit; 600-a third initial unit; 700-off region; 800-a first special unit; 801-a second special unit; 802-a third special unit; 900-nuclear region; 901-an input-output unit; 902-standard cell; 903—a memory cell; 904-IP core.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention, and it is apparent that the described technical solutions are some of the technical solutions of the present invention, but not all the technical solutions. The components of the inventive arrangements generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Accordingly, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the technical scheme in the invention, all other technical schemes obtained by a person of ordinary skill in the art without making creative work fall within the protection scope of the invention.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.

In the description of the present invention, it should be noted that, if the terms "upper", "lower", "inner", "outer", and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or the azimuth or the positional relationship in which the inventive product is conventionally put in use, it is merely for convenience of describing the present invention and simplifying the description, and it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus it should not be construed as limiting the present invention.

Furthermore, the terms "first," "second," and the like, if any, are used merely for distinguishing between descriptions and not for indicating or implying a relative importance.

It should be noted that the features of the present invention may be combined with each other without conflict.

As described in the background art, in the process of physically implementing the digital back end, the placement of a special unit and power connection are of great importance in the power shutdown technology. In general, when placing and wiring, the automatic wiring tool only considers the conditions such as time sequence constraint, design rule constraint and the like, and can lead to random positions of all functional modules, especially special units. The secondary power supply pins of the special unit are not usually located on the basis of the power supply rail, so that the secondary power supply pins of the special unit can only be connected to the power grid in a signal path mode, namely through signal winding, however, the wiring mode is not attractive, and the signal winding is overlong. Too long signal windings can cause excessive voltage drop, which in turn can cause logic errors in the secondary power pins of the particular unit due to insufficient voltage.

Based on the above, the invention provides a circuit layout method, a system, a semiconductor chip and electronic equipment, and the positions of special units are reasonably arranged, so that the paths from the special units to a normally-open power line are shortest, the length of signal winding wires is reduced, and the voltage drop is reduced.

Typically, voltage drops are classified into static voltage drops and dynamic voltage drops. The calculation of the static voltage drop does not consider the change of the current along with time, the calculation of the resistance value R is relatively simple, and the static voltage drop can be evaluated according to the resistance value R so as to rapidly evaluate the power grid of the semiconductor chip. The calculation of the resistance value R in the dynamic voltage drop is relatively complex, and the change of the current along with the time is considered. For dynamic voltage drops, researchers determine that the input current of a functional module is periodically varying over time through long-term simulation of the semiconductor chip, and accordingly, dynamic voltage drops can also be understood as a function of time.

The technical scheme provided by the invention is mainly used for optimizing the layout design of the special unit, for example, reducing the signal winding length of the special unit, so that the invention is mainly aimed at static voltage drop. Hereinafter, this scheme will be described in detail.

Fig. 1 shows a schematic structural diagram of an electronic device 100 according to an embodiment of the invention. The electronic device 100 may perform automatic layout planning for integrated circuits (e.g., chip designs). Referring to fig. 1, an electronic device 100 includes a processor 101 and a memory 102, the memory 102 storing a computer program executable by the processor 101, the processor 101 being executable to implement various implementations of circuit arrangements provided by the following examples of the present invention.

The processor 101 may be, among other things, a central processor, an image processor, a neural network processor, a microcontroller, a programmable logic device, a digital signal processor, an application specific integrated circuit, or one or more integrated circuits. The processor 101 may be configured to perform functions related to the techniques described in the present technical solutions. In some aspects, processor 101 may also include multiple processors integrated as a single logic component. The memory 102 may be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). In some embodiments, the method of layout planning the circuit may be a computer program stored in the memory 102. The data stored by the memory 102 may include program instructions and data to be processed. The processor 101 may also access program instructions and data stored by the memory 102 and execute the program instructions to operate on the data to be processed. The memory 102 may include volatile storage or nonvolatile storage. In some embodiments, the memory 102 may include random access memory, read only memory, optical disk, magnetic disk, hard disk, solid state disk, flash memory, memory stick, and the like.

It should be noted that, although the above-mentioned host architecture only shows the processor 101 and the memory 102, in a specific implementation, the architecture of the electronic device 100 may further include other components necessary for implementing normal operation. Furthermore, it will be understood by those skilled in the art that the architecture of the electronic device 100 may include only the components necessary for implementing the technical solution of the present invention, and not all the components shown in the drawings.

In another possible implementation method, taking a normally open unit in a special unit as an example, the normally open unit is placed in the shutdown area, so as to ensure activation of the power management unit in the shutdown area. The power supply of the secondary power supply pin of the normally open unit is from a normally open power supply line in the turn-off area. Referring to fig. 2, a circuit layout method is provided for laying out power grids and special units in a semiconductor chip, and the circuit layout method can be applied to the electronic device 100 provided in the above technical solution, and the following steps 203-208 are performed.

And 203, dividing the turn-off area based on the power consumption reference data, and determining the size of the turn-off area and the number of power switch units in the turn-off area.

Step 204, determining an initial position of a target power switch unit and a first interval between two adjacent power switch units according to the number of the power switch units, the size of the turn-off area and the self parameters of the power switch units.

Step 205, determining a second interval between adjacent normally open power lines and an initial position of a power grid according to the self parameters of the power line sub-module, the initial position of the target power switch unit and the first interval.

The power line submodule comprises a normally open power line, a power line of a cut-off area and a ground line; the normally open power line, the power line of the turn-off area and the ground line form the power grid.

And 206, randomly placing each special unit according to the time sequence reference data and the design rule data, and determining the initial coordinates of each special unit.

Step 207, determining a screening range according to the second interval for each special unit, wherein the screening range comprises at least one normally open power line; selecting a normally open power line closest to the special unit from at least one normally open power line as a target normally open power line; determining coordinates of a target normally-open power line; and updating the initial coordinates of the special unit according to the coordinates, and determining the target position of the special unit.

Step 208, determining the arrangement structure among the special units according to the corresponding target positions of the special units.

In this embodiment, when the target position between the special units is obtained in step 207, the special units may be executed in parallel or may be executed in a loop. The order of execution is not limited in this embodiment.

For example, when the specific unit acquisition target position is executed in a loop, referring to fig. 3, step 207 includes:

Step 2071, using any special unit with an undetermined target position as a target special unit, and determining a screening range according to a second interval, wherein the screening range comprises at least one normally open power line; selecting a normally open power line closest to the target special unit from at least one normally open power line as a target normally open power line; determining coordinates of a target normally-open power line; and updating the initial coordinates of the target special unit according to the coordinates, and determining the target position of the target special unit.

Step 2072, judging whether all special units have determined the target position. If yes, go to step 208; if not, go back to execute step 2071.

In this embodiment, after the target positions of all the special units are obtained, the special units may be moved to the corresponding target positions to determine the arrangement structure between the special units. Based on the method, the position of the special unit is adjusted, so that the path from the special unit to the normally open power line is shortest, the length of the signal winding is reduced, and particularly the length of the secondary power pin in the special unit to the normally open power line is reduced, so that the voltage drop is reduced.

Optionally, in one possible implementation, referring to fig. 4, before the step 203 of dividing the turn-off area based on the power consumption reference data and determining the size of the turn-off area and the number of power switch units in the turn-off area, the method further includes:

step 201, acquiring configuration parameters and self parameters of the functional module.

In this embodiment, the configuration parameters and the self parameters of the function module may be obtained from a gate level netlist, a time sequence constraint file, a power domain constraint file, a function module physical information base file, a process base file, a time sequence base file and the like, where the function module includes a standard unit, a macro unit and the like, and the function module physical information base file may include a standard unit physical information base file, a macro unit physical information base file and the like.

The configuration parameters may be timing criteria, power consumption criteria, and design rules provided in the layout design of the integrated circuit, such as timing reference data, power consumption reference data, and design rule data, among others. Wherein the timing reference data may be used to determine the timing of the semiconductor chip, including, for example, cell delay, line delay, etc.; the power consumption reference data may be used to determine the power consumption of the semiconductor chip, including, for example, the position and size parameters of the turn-off region, the static power consumption, the standard voltage, the on resistance of the power switching unit, the voltage drop duty ratio of the power switching unit, and the like; design rule data may be used to ensure that the semiconductor chip meets specifications for the manufacturing process at the time of physical design. The self parameters of the functional module may include: line width, initial spacing of the normally open power line and the power line of the off region, third spacing between the normally open power line and the ground line, and the like.

Alternatively, the functional module may include: a power switch sub-module, a power line sub-module and a special sub-module.

Wherein, this switch submodule can include: a plurality of power switch units. Specifically, the plurality of power switching units includes a target power switching unit. In this embodiment, the arrangement of the power switch units satisfies the first layout rule, and the target power switch unit is the power switch unit corresponding to the initial position under the first layout rule.

The power line sub-module may include a normally open power line, a shutdown region power line, and a ground line. And the normally open power line, the power line of the turn-off area and the ground line can form a power grid. The special sub-module may comprise a plurality of special units. The special unit is a module for correctly realizing the shutdown of multiple voltages or a certain voltage domain in the low-power consumption design, such as a normally-open unit, an isolation unit and the like. In this embodiment, the power supply of the special unit is from a normally open power line in the off region. Accordingly, the power supply of the other functional modules except the special unit in the off-region comes from the off-region power supply line.

The parameters of the functional module are used for representing the position and the size of the functional module, such as the width, the initial position and the like of the power switch unit.

After the configuration parameters are acquired, the shutdown regions may be partitioned based on the power consumption reference data therein. The turn-off area is an area needing to turn off power supply in low power consumption design and is used for reducing the power consumption of the whole integrated circuit, and the turn-off area is used for controlling the on or off of the power supply through the power supply switch unit, so that the placement of the power supply switch unit in the turn-off area is also important. And further determining the size of the turn-off region and the number of power switch units within the turn-off region.

In the embodiment of the invention, the power domain division scheme defined by the front end design can be obtained from the power domain constraint file, and then the position and the size of the turn-off region are determined according to the power domain division scheme. Specifically, referring to fig. 5, fig. 5 is a schematic distribution diagram of the turn-off region in the semiconductor chip. Fig. 5 illustrates four Input/Output Pads (IO) 901 and two turn-off regions 700 as examples, wherein the Input/Output Pads 901 are respectively arranged around the semiconductor chip and surround the turn-off regions 700.

In one possible implementation, the specific implementation of step 203 shown in fig. 2 is:

first, the power consumption reference data may include a static power consumption, a standard voltage, an on-resistance of the power switching unit, and a voltage drop duty ratio of the power switching unit.

Furthermore, the number of power switching units in the off region satisfies the formula:

Ron/Xnum * W/V = V*Pswitch

Wherein Ron is the on resistance of the power switch unit; xnum is the number of power switch units; w is static power consumption; v is a standard voltage; pswitch is the voltage drop duty cycle of the power switching unit. The static power consumption and the standard voltage are the static power consumption, standard voltage of the defined turn-off region of the integrated circuit. The ratio of the static power consumption to the standard voltage is the average current in the off region. The product of the standard voltage and the voltage drop duty ratio of the power switch unit is the voltage drop of the power switch unit, wherein the voltage drop standard of the power switch unit is different under different technologies.

In the embodiment of the present invention, after determining the number of the power switch units and the size of the turn-off area, the first layout rule of the power switch sub-module may be determined by combining the data and the parameters of the power switch units. The first layout rule may include an initial position of the target power switching unit and a first interval between two adjacent power switching units.

Referring to fig. 6, in order to determine the initial position of the target power switch unit and the first spacing between two adjacent power switch units, a possible implementation manner is provided below for step 204 shown in fig. 2, specifically, step 204 includes steps 401-403.

Step 401, determining an initial position of a target power switch unit and a first interval between two adjacent power switch units according to the number of the power switch units, the size of the turn-off area and the self parameters of the power switch units.

Alternatively, the number of power switching units that can be arranged per column or per row of power switching units within the turn-off region may be determined according to the size of the turn-off region, e.g., the length, width, in combination with the width of the power switching units. The number of rows or columns of the power switch units can be determined according to the number of the power switch units, so that the first interval between two adjacent power switch units can be determined. The first pitch may be a column pitch or a row pitch. And selecting a target power switching unit from the power switching units, and determining an initial position of the target power switching unit. The initial position of the target power switch unit may be a column coordinate of the target power switch unit.

Step 402, connecting the power switch units in series step by step according to the first interval from top to bottom to form a plurality of sub-chains arranged in columns.

Step 403, sequentially concatenating all the sub-chains in the left-to-right order, and forming a loop chain.

The power switch unit may include a gate signal output end and a gate signal input end; the gating signal output end of any power switch unit is connected with the gating signal input end of the next stage power switch unit.

In the embodiment of the invention, a known number of power switch units can be arranged into the turn-off area according to the size of the turn-off area, and the arrangement mode can be a loop-chain mode. In one possible implementation, the series connection is specifically: and connecting the power switch units in series step by step according to the first interval from top to bottom to form a plurality of sub-chains which are arranged in rows. Thus, the connection relationship of each column of sub-chains may be: the gate signal is from left to right and then from bottom to top.

For convenience of description, a plurality of sub-chains arranged in columns may be numbered, where the numbers satisfy 1,2,3, …, N (N is a positive integer), and thus the sub-chains arranged in columns may be divided into sub-chains in odd columns and sub-chains in even columns. Wherein, the power switch unit corresponding to the last row in the sub-chain (from top to bottom) of the odd columns with n=1 is taken as the first initial unit 400; the power switch unit corresponding to the last row in the sub-chain (from top to bottom) of the even numbered columns with n=2 is taken as the second initial unit 500; the power switch unit corresponding to the first row in the sub-chain (from top to bottom) of even columns with n=2 is the third initial unit 600.

In one possible implementation, the gating signals between the power switching units in the sub-chains of the odd columns are transmitted in a top-to-bottom order; gating signals among power switch units in even-numbered subchains are transmitted in a sequence from bottom to top. Referring to fig. 7, fig. 7 shows an example of a connection structure of a power switch sub-module, that is, an arrangement diagram among power units, and shows 4 sub-chains arranged in columns, that is, a sub-chain with number n=1, a sub-chain with number n=2, a sub-chain with number 2N-1, and a sub-chain with number 2N.

Wherein the sub-chain with the number of N=1 and the sub-chain with the number of 2N-1 are sub-chains corresponding to odd columns; the child chain with the number n=2 and the child chain with the number 2N are child chains corresponding to even columns.

Referring specifically to fig. 7, the power switch unit corresponding to the last row in the odd column sub-chain (from top to bottom) with n=1 is taken as the first initial unit 400; the power switch unit corresponding to the last row in the even column sub-chain (from top to bottom) with n=2 is taken as the second initial unit 500; the power switch unit corresponding to the first row in the even column sub-chain (from top to bottom) with n=2 is the third initial unit 600. In one possible implementation, the gating signal output of the first initiation unit 400 may be connected to the gating signal input of the second initiation unit 500 using an automatic routing tool.

Note that, the arrangement schematic diagram shown in fig. 7 also illustrates omission of the sub-chains arranged in columns, for example, a connection relationship between the even column sub-chain with the number n=2 and the odd column sub-chain with the number 2N-1 is a broken line, which indicates that the column sub-chain may exist between the even column sub-chain with the number n=2 and the odd column sub-chain with the number 2N-1. For example, the gate signal output terminal of the third initial unit 600 in the even column sub-chain with the number n=2 is connected to the gate signal input terminal of the power switch unit corresponding to the first row (from top to bottom) in the odd column sub-chain with the number n=3 (not shown in the drawing).

In another possible implementation, the gating signals between the power switching units in the sub-chains of the odd columns are transmitted in a top-to-bottom order; gating signals among power switch units in the subchains of even columns are transmitted in a sequence from top to bottom. Referring to fig. 8, fig. 8 shows another example of a connection structure of a power switch sub-module, and shows 4 sub-chains arranged in columns, namely, a sub-chain with number n=1, a sub-chain with number n=2, a sub-chain with number 2N-1, and a sub-chain with number 2N.

Referring specifically to fig. 8, the power switch unit corresponding to the last row in the odd column sub-chain (from top to bottom) with the number n=1 is taken as the first initial unit 400; the power switch unit corresponding to the last row in the even column sub-chain (from top to bottom) with the number n=2 is taken as the second initial unit 500; the power switch unit corresponding to the first row in the even column sub-chain (from top to bottom) with the number n=2 is the third initial unit 600. In one possible implementation, the gating signal output of the first initial cell 400 may be connected to the gating signal input of the third initial cell 600 using an automatic routing tool.

Note that, the arrangement schematic diagram shown in fig. 8 also illustrates omission of the sub-chains arranged in columns, for example, a connection relationship between the even column sub-chain with the number n=2 and the odd column sub-chain with the number 2N-1 is a broken line, which indicates that the column sub-chain may exist between the even column sub-chain with the number n=2 and the odd column sub-chain with the number 2N-1. For example, the gating signal output terminal of the second initial unit 500 in the even column sub-chain with the number n=2 is connected to the gating signal input terminal of the power switching unit corresponding to the first row (from top to bottom) in the odd column sub-chain with the number n=3 (not shown in the drawing).

In the embodiment of the present invention, the column coordinate of the sub-chain with the sequence number n=1 in the sub-chain of the odd-numbered columns may be used as the initial position of the target power switch unit.

Referring to fig. 9, in one possible implementation, when the size of the off-region includes the length of the off-region and the width of the off-region, the parameters of the power switch unit include the width of the power switch unit, and the first pitch is the column pitch of the power switch units in the off-region, in order to determine the initial position of the further target power switch and the first pitch between the two adjacent power switch units, step 401 in the above example may include the following steps: step 4011-step 4014.

Step 4011, determining the number of rows of the power switch units in the turn-off area according to the width of the turn-off area and the width of the power switch units.

Step 4012, determining the number of columns of the power switch units in the turn-off area according to the number of rows of the power switch units and the number of the power switch units.

Step 4013, determining a column spacing of the power switch units in the turn-off area according to the length of the turn-off area and the column number of the power switch units.

In the embodiment of the invention, when the width of the turn-off area is fixed to the width of the power switch unit, the power switch units which can be placed in each row can be determined. The number of rows of power switch cells in the off-region can be determined. The number of the power switch units is determined, so that the number of columns and the column spacing of the power switch units in the turn-off area can be determined according to the number of the columns.

Step 4014, taking the power switch units corresponding to the first row and the first column as target power switch units; and determines an initial position of the target power switching unit.

In the embodiment of the invention, the initial position of the target power switch unit is formed by row and column coordinates of the target power switch unit, and is used for positioning the arrangement structure of the process among the power switch units. The initial position is the coordinates of the target switching unit, and in a preferred manner, the coordinates of the target switching unit are corresponding column coordinates.

In the prior art, the turn-off area includes a plurality of power switch units, and the power switch units have relatively large resistances, which may cause the output voltage of the power supply to be lost after passing through the power switch units. Through the experimental detection of the inventor, after the initial output voltage of the power supply passes through each power switch unit, loss exists in comparison with the initial output voltage, wherein the loss value is different under different processes. And then from the power switching unit to other functional modules, the output voltage drops still further. The invention can greatly reduce the resistance of the power switch sub-module and further reduce the voltage drop by adjusting the first layout rule of the power switch sub-module, in particular the number of the power switch units, the initial positions of the target power switch units and the first spacing between two adjacent power switch units.

In the embodiment of the invention, after the initial position and the first interval of the target power switch unit are determined, the second interval between the adjacent normally open power lines and the initial position of the power grid can be determined by combining the self parameters of the power line sub-modules.

The power grid is formed by arranging normally open power lines, power lines in a cut-off area and ground lines in a power line sub-module according to preset interval distances. Therefore, in the embodiment of the invention, the second interval between the adjacent normally open power supply lines and the initial position of the power grid are mainly determined. In one possible implementation, the initial position of the power grid corresponds to the coordinates of the normally open power line or the power line of the off-region, and the coordinates are numerically the same as the initial position of the target power switch unit.

Alternatively, the above-mentioned coordinates may be column coordinates of the normally open power supply line.

It should be noted that the manner of adjusting the power grid in the present invention is not limited to the second pitch and the initial position of the power grid, and also considers the parameters of the normally open power line, the power line in the off region, and the ground line, such as the line width. The second interval is adjusted by utilizing the line width and the third interval between the normally open power line and the ground line.

In the embodiment of the present invention, when the self parameters of the power line sub-module include the line width, the initial distance between the normally open power line and the power line of the off region, and the third distance between the normally open power line and the ground line, the second distance is obtained by adjusting the line width, the third distance, and the third distance to the initial distance, so step 205 in fig. 2 may be:

adjusting the third interval, the line width and the first interval until the initial interval meets a preset relation, and taking the initial interval meeting the preset relation as the second interval; wherein, the preset relation satisfies:

gap=N*pitch=2N*（space+width）

Wherein pitch is the second spacing between adjacent normally open power supply lines; the space is a third interval between the normally open power line and the ground line; width is the line width; gap is the first pitch; n is a positive integer.

In the embodiment of the present invention, the second pitch satisfies: pitch=2 (space+width), and the first pitch gap also needs to be an integer multiple of the second pitch, i.e.: gap=n×pitch. In one possible implementation, the second pitch may be determined by adjusting the third pitch and/or the line width, and the second pitch may be made to satisfy an integer multiple relationship with the first pitch gap. The line width and the third pitch can satisfy a proportional relation, and the larger the line width is, the larger the third pitch can be.

The invention can adjust the density and the line width of the power grid by adjusting the third interval and/or the line width between the normally open power line and the ground line and/or the first interval between two adjacent power switch units, thereby reducing the voltage drop. For example, the voltage drop may be reduced by increasing the density of the power grid, reducing the second pitch and/or the third pitch; the voltage drop can be reduced by increasing the linewidth.

After determining the third interval according to the second interval, please refer to fig. 10, the step 205 of determining the second interval between adjacent normally open power supply lines and the initial position of the power grid according to the self parameters of the power line sub-module, the initial position of the target power switch unit and the first interval further includes steps 501-502.

Step 501, taking the initial position of the target power switch unit as the initial coordinate of the power grid to determine the initial position of the power grid.

In one possible implementation, the initial position of the power grid may be the column coordinates of the normally open power lines or the off-region power lines. That is, after the initial position of the target power switching unit is determined, the column coordinates of the normally open power line or the column coordinates of the power line of the off-region may be correspondingly determined.

And 502, respectively arranging a normally open power line, a power line of a turn-off area and a ground line in the turn-off area according to a second interval and a third interval by taking the initial coordinates as references.

In one embodiment, when the column coordinate of the normally open power line is taken as the initial position of the power grid, the column coordinate of the normally open power line can be determined according to the initial position of the target power switch unit, and the arrangement structure of the power grid is determined according to the second interval and the third interval in the turn-off area by taking the column coordinate of the normally open power line (the initial coordinate of the power grid) as a reference.

Referring to fig. 11, fig. 11 illustrates an example of an arrangement structure between the power grid and the power switching unit when the column coordinates of the normally open power line are the initial positions of the power grid, and illustrates an arrangement structure of the power supply line (Voltage DRAIN DRAIN, VDD) in the power line sub-module, for example, the normally open power line VDD ₁, the off-region power line VDD ₂, the ground line GND, and the power switching unit.

The normally open power lines VDD ₁, the off-area power lines VDD ₂ and the ground line GND are arranged in parallel according to a preset interval, for example, the adjacent normally open power lines VDD ₁ are arranged at a second interval pitch, the normally open power lines VDD ₁ and the ground line GND are arranged at a third interval space, the normally open power lines VDD ₁ and the off-area power lines VDD ₂ are also arranged at a preset interval, and in this embodiment, the intervals among the third interval space, the adjacent normally open power lines VDD ₁ and the off-area power lines VDD ₂ can be determined through design rule data. The sub-chains which correspond to the power switch units and are arranged in rows are arranged at a first interval. In one possible implementation, the power switch unit is disposed on or directly above or directly below the power line sub-module and intersects the normally open power line VDD ₁ and the off-region power line VDD ₂.

With continued reference to fig. 11, fig. 11 also shows the power line sub-module linewidth width. In the embodiment of the invention, the line width values corresponding to the normally open power line VDD ₁, the ground line GND and the power line VDD ₂ in the power line sub-module are equal.

In one possible implementation method, when the layer of the power grid in the semiconductor chip is different from the layer of the power switch unit, the view structure between the power grid and each power switch unit from top to bottom (from bottom to top) may continue to refer to fig. 11, where the power switch unit in this embodiment is disposed directly above or directly below the power line sub-module and intersects the positions of the normally open power line VDD ₁ and the power line VDD ₂ in the off region. Specifically, the starting coordinate of the power grid is consistent with the column coordinate of the target power switch unit, M is the number of columns of the minimum power line unit formed by the normally open power line VDD ₁, the off-area power line VDD ₂ and the ground line GND in the power grid, and M is a positive integer. In this embodiment, each column corresponds to a minimum power line unit, the minimum power line unit includes a power on power line VDD ₁, a power off area power line VDD ₂ and a ground line GND, and the power on line VDD ₁, the power off area power line VDD ₂ and the ground line GND in the minimum power line unit are arranged according to a predetermined interval.

Similarly, in another embodiment, when the column coordinate of the power line in the off region is taken as the initial position of the power grid, the column coordinate of the power line in the off region may be determined according to the initial position of the target power switch unit, and the power grid is formed by arranging the power line in the off region, the normally open power line and the ground line in the off region according to the second pitch and the third pitch with the column coordinate of the power line in the off region (the initial coordinate of the power grid) as a reference.

The difference between the two embodiments is that the initial positions of the power grids are different, and the difference of the initial positions of the power grids does not affect the acquisition mode of the second spacing between the adjacent normally open power lines and the value corresponding to the second spacing. It should be noted that, after determining the initial position of the power grid, the present technical solution may determine the arrangement of the power grid according to the second pitch and the third pitch. The method for determining the initial position of the power grid is not limited, namely the initial position of the power grid can be the column coordinates of the power line in the turn-off area or the column coordinates of the normally-open power line.

After confirming the first layout rule of the power switch sub-module and the second layout rule of the power grid, each special unit can be randomly placed according to the time sequence reference data and the design rule data, and initial coordinates of each special unit are determined.

In the embodiment of the present invention, step 206 may be to roughly place the special units according to the time sequence reference data and the design rule data by an automatic wiring tool, and take the coordinates of each special unit under the current layout as the initial coordinates. In one possible implementation manner, after the special units are randomly and roughly placed on the arrangement structure example between the power grid and the power switch units shown in fig. 11 by using an automatic wiring tool, the special units are placed on the layers of the special units, the layers of the power switch sub-modules and the layers of the power grid in the semiconductor chip, and fig. 12 is a view from top to bottom (or from bottom to top), and fig. 12 is a schematic diagram showing the effect of random placement of the special units on the power grid, and fig. 12 only shows the normally-open power line VDD ₁, the off-area power line VDD ₂, the power switch units and the special units for convenience of description. The special units are randomly arranged through an automatic wiring tool and can not be directly contacted with the normally-open power line VDD ₁ or the power line VDD ₂ in the off region. The arrangement of the normally open power line VDD ₁, the off-region power line VDD ₂, and the power switching unit is described with reference to the previous example fig. 11, and will not be repeated here.

With continued reference to fig. 12, taking the first special unit 800, the second special unit 801, and the third special unit 802 in the special sub-module as an example, it can be seen from fig. 12 that the first special unit 800 is distributed near the turn-off area power line VDD ₂ in the minimum power line unit with the column number of m=1; the second special unit 801 is distributed on the turn-off area power line VDD ₂ in the minimum power line unit of column number m=2; the third special cell 802 is distributed in the vicinity of the off-region power line VDD ₂ in the smallest power line cell of column number m=4.

After the initial position of each special unit is determined, any special unit can be used as a target special unit, and a screening range is determined according to the second interval; wherein, the screening range comprises at least one normally open power line. Selecting a normally open power line closest to the target special unit from at least one normally open power line as a target normally open power line; and determining the coordinates of the normally open power line of the target, updating the initial coordinates of the special unit of the target according to the coordinates, and determining the target position of the special unit of the target.

In the embodiment of the present invention, the step of determining the screening range according to the second interval in step 207 includes:

selecting any special unit as a target special unit, taking the initial coordinate of the target special unit as a circle center, and determining a screening range by taking a preset distance as a radius; wherein the value of the preset distance is determined according to the second interval.

Further, the step of determining the value of the preset distance according to the second interval includes:

and taking one half of the second interval as a preset distance to determine the radius of the screening range.

In an embodiment of the present invention, the placement constraints of the special unit in step 207 satisfy: the moving distance is shortest, no winding overlapping is generated, and the connection line between the secondary power supply pin of the special unit and the normally open power supply wire is shortest. On the schematic view of the effect of random placement of the special units shown in fig. 12, initial coordinates of the first special unit 800, the second special unit 801 and the third special unit 802 are respectively used as circle centers, a preset distance is used as a radius, and screening ranges corresponding to the first special unit 800, the second special unit 801 and the third special unit 802 are determined. Referring to fig. 13, fig. 13 is a schematic view showing the effect of each screening range, and fig. 13 only shows the normally open power line VDD ₁, the off-area power line VDD ₂, the power switching unit, and the special unit for convenience of description, wherein each screening range is represented by a dotted frame, and the preset distance shown in the dotted frame is determined according to the second pitch. In this embodiment, the predetermined distance is one half of the second pitch. With continued reference to fig. 13, the arrangement of the normally open power line VDD ₁, the off-region power line VDD ₂, the power switching unit, and the like in the drawings is referred to the description of the previous example fig. 11, and will not be repeated here.

On this basis, the normally open power supply line VDD ₁ closest to the first special unit 800, the second special unit 801, and the third special unit 802, respectively, in the screening range can be determined. With continued reference to fig. 12, the normally open power line VDD ₁ in the minimum power line unit corresponding to the first special unit 800 having the column number m=2 as the nearest normally open power line; the normally open power line VDD ₁ in the minimum power line unit with the nearest normally open power line corresponding to the second special unit 801 having the column number m=2; the third special unit 802 corresponds to the normally open power line VDD ₁ in the smallest power line unit with the nearest normally open power line in the column number m=4.

On the basis of the effect schematic diagram of each screening range shown in fig. 13, after determining a normally open power line with the closest target special unit distance, using the corresponding normally open power line as a target normally open power line corresponding to the target special unit, updating initial coordinates of the corresponding target special unit with coordinates of the target normally open power line, and in one possible implementation manner, moving the first special unit 800 to the position of the normally open power line VDD ₁ in the minimum power line unit with the column number of m=2; moving the second special unit 801 to the corresponding position of the normally open power line VDD ₁ in the minimum power line unit of column number m=2; the third special cell 802 moves to the corresponding position of the normally open power line VDD ₁ in the smallest power line cell of column number m=4. Referring to fig. 14, fig. 14 shows an effect diagram of the target special unit after the target normally-open power line is adjusted in step 207, and fig. 14 only shows the normally-open power line VDD ₁, the off-area power line VDD ₂, the power switch unit, and the special unit for convenience of description. The special unit is adjusted according to the method shown in step 207, and the adjusted special unit is located on or directly above or directly below the corresponding normally-open power line VDD ₁. The arrangement of the normally open power line VDD ₁, the off-region power line VDD ₂, and the power switch unit is described with reference to the previous example fig. 11, and will not be repeated here.

The method has the advantages that in the moving process, the nearest normally-open power line in the circle with the preset radius corresponding to the target special unit is selected as the target normally-open power line, so that the distance from the initial position of the target special unit to the corresponding target normally-open power line is nearest, the moving distance is shortest, the influence of the increase of the movement of the special unit on time sequence and power consumption is avoided, and the requirements of the semiconductor device on the power consumption and the time sequence in the low-power-consumption design are met to a great extent.

In one possible implementation, any one of the special sub-modules may be selected randomly as the target special unit, and the screening range may be determined by taking the initial coordinates of the target special unit as the center of a circle and one half of the second pitch as the radius. Because at least one normally open power line exists in the screening range, a normally open power line closest to the target special unit is required to be screened in the screening range, the screened normally open power line is used as the target normally open power line, and the initial coordinates of the target special unit are updated according to the coordinates of the target normally open power line.

The method for determining the coordinates of the target normally-open power line on the X axis is as follows: and reading a coordinate value llx of the left lower corner of the target normally-open power line on the X axis. After the coordinate value llx is determined, since the normally open power line has a certain line width size X, the coordinate value of the target normally open power line on the X axis represents a, and the following conditions are satisfied: a= llx-1/2 x size x. And similarly, the determination mode of the coordinates of the target normally-open power line on the Y axis is identical with the determination mode.

After the coordinates of any target normally-open power line are determined, the target special unit can be moved to the coordinates of the target normally-open power line. The moving distance is also shortest, so that the influence of time sequence and power consumption is ensured to be minimum to a large extent.

In this embodiment, since the special sub-module includes a plurality of special units, in confirming the target positions of the special units, a cyclic traversal execution mode or a parallel execution mode may be adopted, and in a possible implementation embodiment, reference may be continued to fig. 3, and the initial coordinates of the special units may be adjusted by traversing all the special units in the special sub-module, so as to obtain corresponding target positions, so as to determine the arrangement of the special sub-modules in the shutdown area.

After determining the arrangement of the special units, referring to fig. 15, the present invention further provides a wiring mode of the special units, where the semiconductor chip includes a plurality of wiring layers; wherein the power grid and the special unit are positioned on different wiring layers in the semiconductor chip; the circuit layout method further includes step 209.

Step 209, setting a connection hole at the secondary power pin of the target special unit, and filling a metal wire in the connection hole to conduct a link between the target special unit and a target normally-open power line in the power grid through the metal wire.

In the embodiment of the present invention, after the initial position of the target special unit is adjusted according to the method of step 207 in the above technical solution, the position of the target special unit is moved to a position directly above or directly below the target normally-open power line, so that the secondary power pin of the target special unit can be directly connected to the target normally-open power line in the power grid through the connection hole by means of setting the connection hole, and further, the connection of the link between the special unit and the target normally-open power line can be realized through the metal wire filled in the connection hole.

For a single functional module, the resistance value R of the input pin from the power grid to the functional module is related to the length L and the line width S of the link, namely, the resistance value R meets the following conditions: r=ρl/S, where ρ is the resistivity of the conductive material. When the line width S is fixed, the longer the length L of the link is, the larger the resistance value R is; the smaller the line width S, the larger the resistance value R at a given length L of the link. The larger the resistance value R, the larger the corresponding voltage drop. In the embodiment of the invention, the position of the target special unit is positioned right above or right below the target normally-open power line, and the connection of the link can be directly displayed in a mode of connecting holes, so that the line width S is increased to a certain extent, the length L of the link is reduced, and the resistance value R is smaller under corresponding adjustment, and the corresponding voltage drop is smaller.

In one possible implementation, the semiconductor chip may employ a nine metal layer process, i.e., including metal layers M1 to M9 disposed in sequence. The normally open power line, the power line of the off region and the ground line can be laid from the metal layer M9 to the metal layer M5 to form a power grid. After setting a special unit on the metal layer M2 and selecting any special unit as a target special unit, moving the target special unit to a position right below a corresponding target normally-open power line according to the scheme of the step 207, setting a connecting hole directly from the metal layer where the target normally-open power line is located, and connecting a secondary power pin of the target special unit to the target normally-open power line. For example, when the normally open power line is disposed on the metal layer M5, a connection hole is disposed at a position corresponding to the secondary power pin of the target special unit on the metal layer M2, and the connection hole is connected to the corresponding coordinate of the target normally open power line on the metal layer M5, so as to conduct a link between the target normally open power line and the secondary power of the target special unit.

In another possible implementation manner, an automatic wiring tool can be utilized to determine the logic relationship among the functional modules and the constraint conditions corresponding to the time sequence and the process according to the time sequence reference data, the power consumption reference data and the design rule data, and the physical connection and the detailed wiring of the functional modules except the special units are realized by using metal connection lines. The clock tree may also be determined from the root node of the clock according to design rule data using an automatic routing tool.

In the present invention, please refer to fig. 16, when the functional module further includes a macro unit and a standard unit; step 202 is further included before step 203 of dividing the turn-off area based on the power consumption reference data and determining the size of the turn-off area and the number of power switching units within the turn-off area.

Step 202, randomly placing macro cells and standard cells according to the design rule data, the time sequence reference data and the design rule data by utilizing an automatic wiring tool.

In this embodiment, step 202 may be disposed after step 201 in the above embodiment.

Referring to fig. 17, fig. 17 is a schematic layout diagram of functional modules after being randomly placed by using an automatic wiring tool. When the macro unit includes an input/output unit 901, a storage unit 903, and an IP core (Intellectual Property Core) 904, where the input/output unit 901 is disposed at the periphery of the core area 900, the standard unit 902 may be disposed at the center of the core area 900; the storage unit 903 and the IP core 904 are disposed around the core area 900, where the space between the IP core 904 and the core area 900 meets the requirements corresponding to the design rule data, and physical constraints may be added around the IP core 904.

In the present invention, the automatic wiring tool may employ an Electronic Design Automation (EDA) software tool. When the automatic wiring tool arranges macro units such as the input/output unit 901, the storage unit 903, the IP core 904, and the standard unit 902, the following conditions need to be satisfied:

1) And placing macro units according to the sequence of the data streams.

In the embodiment of the present invention, with continued reference to fig. 17, when the time-series reference data includes a data stream, the placement order of the storage unit 903 is consistent with the direction of the data stream, and the direction indicated by the arrow in fig. 17 is the direction of the data stream.

2) The macro-cell placement should meet the packaging requirements.

For example, the input/output unit 901 may be placed directly according to the signal sequence on the package substrate to avoid signal crossing, and a predetermined distance is reserved between the input/output unit and the core area 900 of the semiconductor chip to avoid latch-up.

3) When the functional module is turned over or mirrored, the requirements corresponding to the design rule data need to be met.

4) The standard cell 902 is disposed in a blank area of the core area 900 of the semiconductor chip except for the macro cell corresponding position, for example, in a center position of the core area 900 of the semiconductor chip.

As can be seen from the foregoing description, a particular unit may include a variety of different device modules. In this scheme, different device modules have different setting modes.

Therefore, in the following description, when a particular cell is an isolation cell, the isolation cell is a cell that can keep the input or output of the semiconductor chip constant when a certain power domain is turned off. An isolation unit is typically provided between the off-region and the normally open region for isolating two different power domains. For example, when a signal is transmitted from the off-region to the normally-open region, if the power supply of the off-region is turned off, an unpredictable value may occur in the output signal, and directly transmitting this value to the normally-open region may cause problems in some functions of the semiconductor chip, so that the off-region and the normally-open region need to be isolated by an isolation unit. When the isolation unit is arranged in the turn-off area, the link between the secondary power pin and the normally-open power pin in the isolation unit can be determined through the circuit layout method.

When the particular cell is a voltage/level shifter, the voltage/level shifter is used to switch the signal from one voltage domain to another. When a signal is transferred from a low voltage domain to a high voltage domain, a lower voltage in a field effect transistor, for example, at the gate of the field effect transistor, may cause the gate to be incompletely turned off, resulting in an abnormal leakage current. Therefore, a voltage/level converter is required to be applied when the signal is transmitted across the voltage domain. And the voltage/level converter comprises a secondary power supply pin of a high voltage power supply terminal and a low voltage power supply terminal. When the voltage/level converter is arranged in the turn-off area, the link between the secondary power pin of the voltage/level converter and the normally-open power line can be determined by the circuit layout method.

In summary, the embodiments of the present invention provide a circuit layout method for laying out power grids and special cells in a semiconductor chip. The power consumption reference data is used for dividing the turn-off area according to the configuration parameters and the self parameters of the functional module, and determining the size of the turn-off area and the number of the power switch units. And determining the second interval of the power lines of the power switch areas and the initial position of the power grid according to the number of the power switch units, the size of the power switch areas and the self parameters of the functional modules. After the initial coordinates of the target special units are obtained, a screening range is determined according to the initial coordinates and the second interval, a normally open power line closest to the target special units is selected from the screening range, and the initial coordinates of the special units are adjusted according to the coordinates of the normally open power line, so that the target positions are obtained. The special unit is used for correctly realizing multi-voltage or certain voltage domain shutdown in low-power consumption design, and is usually arranged in a shutdown area. The invention reduces the length of the power supply winding of the secondary power supply pin in the special unit in the turn-off area and reduces the voltage drop by adjusting the position of the special unit.

Based on the above-mentioned concept of the circuit layout method, in another technical solution, please refer to fig. 18, a circuit layout system 300 is provided for laying out power grids and special units in a semiconductor chip, which includes: a region division module 301, a power switch layout module 302, a power grid layout module 303, a special cell layout module 304, and a special cell layout optimization module 305.

The area dividing module 301 is configured to divide the turn-off area based on the power consumption reference data, and determine the size of the turn-off area and the number of power switch units in the turn-off area.

The power switch layout module 302 is configured to determine an initial position of a target power switch unit and a first interval between two adjacent power switch units according to the number of power switch units, the size of the turn-off area, and the parameters of the power switch units.

The power grid layout module 303 is configured to determine a second interval between the normally open power line and the power line in the off area and an initial position of the power grid according to the self parameters of the power line sub-module, the initial position of the target power switch unit and the first interval.

The power line submodule comprises a normally open power line, a power line of a cut-off area and a ground line; the normally open power line, the power line of the turn-off area and the ground line form a power grid.

The special cell layout module 304 is configured to randomly place special cells according to the timing reference data and the design rule data, and determine initial coordinates of the special cells.

A special unit layout optimizing module 305, configured to determine a screening range according to the second pitch by using any special unit as a target special unit; wherein, the screening range comprises at least one normally open power line; selecting a normally open power line closest to the target special unit from at least one normally open power line as a target normally open power line; determining the coordinates of a normally open power line of the target, updating the initial coordinates of the special unit of the target according to the coordinates, and determining the target position of the special unit of the target; and determining the arrangement structure among the special units according to the target positions corresponding to the special units.

Based on the above-mentioned concept of the circuit layout method, in another technical scheme, a semiconductor chip is provided, which includes a power grid and a special unit, and a circuit layout between the power grid and the special unit is determined by the above-mentioned circuit layout method.

In the several technical solutions provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other manners. The apparatus technical solutions described above are merely illustrative, for example, the flowcharts and block diagrams in the figures show the architecture, functionality, and operation of possible implementations of apparatuses, methods and computer program products according to various technical solutions of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, each functional module in each technical scheme of the invention can be integrated together to form an independent part, each module can exist alone, and two or more modules can be integrated to form an independent part.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the respective technical solution of the present invention.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1.A circuit layout method for laying out a power grid and a special cell in a semiconductor chip, the circuit layout method comprising the steps of:

Dividing a turn-off area based on power consumption reference data, and determining the size of the turn-off area and the number of power switch units in the turn-off area;

determining a second interval between adjacent normally open power supply lines and an initial position of a power grid according to the self parameters of the power line sub-module, the initial position of the target power supply switch unit and the first interval;

The power line submodule comprises a normally open power line, a power line of a cut-off area and a ground line; the normally open power line, the power line of the turn-off area and the ground line form the power grid;

Determining an arrangement structure among the special units according to the corresponding target positions of the special units;

when the self parameters of the power line sub-module comprise line width, initial distance between the normally open power line and the power line of the turn-off area and third distance between the normally open power line and the ground line; the step of determining the second interval between the adjacent normally open power supply lines according to the self parameters of the power supply line sub-module, the initial position of the target power supply switch unit and the first interval comprises the following steps:

gap =N*pitch =2N*（space+width）

2. The circuit layout method according to claim 1, wherein the step of dividing the turn-off area based on the power consumption reference data and determining the size of the turn-off area and the number of the power switching units in the turn-off area further comprises, before:

3. The circuit layout method according to claim 1 or 2, wherein the step of determining the screening range according to the second pitch includes:

4. The circuit layout method according to claim 3, wherein the step of determining the value of the preset distance according to the second pitch comprises:

5. The circuit layout method according to claim 1 or2, wherein the semiconductor chip includes a plurality of wiring layers; wherein the power grid and the special unit are located at different wiring layers in the semiconductor chip; the circuit layout method further comprises the following steps:

6. The circuit layout method according to claim 1 or 2, wherein when the power consumption reference data includes a static power consumption, a standard voltage, an on resistance of the power switching unit, and a voltage drop duty ratio of the power switching unit; the number of the power switch units in the turn-off area satisfies the formula:

Ron/Xnum * W/V = V*Pswitch

7. The circuit layout method according to claim 1 or 2, wherein the step of determining the initial position of the target power switch unit and the first spacing between two adjacent power switch units according to the number of the power switch units, the size of the turn-off area, and the self-parameters of the power switch units comprises:

8. The circuit layout method according to claim 7, wherein when the size of the turn-off region includes a turn-off region length and a turn-off region width; the self parameters of the power switch unit comprise the width of the power switch unit; when the first pitch includes a column pitch of the power switch units in the turn-off region; the step of determining the initial position of the target power switch unit and the first interval between two adjacent power switch units according to the number of the power switch units, the size of the turn-off area and the self parameters of the power switch units further comprises:

9. The circuit layout method according to claim 1, wherein the step of determining the second pitch between adjacent normally open power supply lines and the initial position of the power grid according to the self parameters of the power line sub-module, the initial position of the target power supply switch unit, and the first pitch further comprises:

10. The circuit layout method according to claim 2, wherein the functional module further comprises a macro cell and a standard cell; the method further includes, before the steps of dividing the turn-off region based on the power consumption reference data and determining the size of the turn-off region and the number of power switching units in the turn-off region:

11. A semiconductor chip comprising a power grid and a special cell, the circuit layout between the power grid and the special cell being determined by the circuit layout method of any of the preceding claims 1 to 10.

12. A circuit layout system for performing the circuit layout method of any of claims 1 to 10, comprising:

The special unit layout optimization module is used for taking any special unit as a target special unit and determining a screening range according to the second interval; wherein the screening range comprises at least one normally open power line; selecting a normally open power line closest to the target special unit from the at least one normally open power line as a target normally open power line; determining the coordinates of the normally open power line of the target, updating the initial coordinates of the special unit of the target according to the coordinates, and determining the target position of the special unit of the target; determining an arrangement structure among the special units according to the corresponding target positions of the special units;

The power grid layout module is further used for when the parameters of the power line sub-module include line width, initial distance between the normally open power line and the power line of the turn-off area and third distance between the normally open power line and the ground line; the step of determining the second interval between the adjacent normally open power supply lines according to the self parameters of the power supply line sub-module, the initial position of the target power supply switch unit and the first interval comprises the following steps:

gap =N*pitch =2N*（space+width）

13. An electronic device comprising a processor and a memory, the memory storing a computer program executable by the processor, the processor executable to implement the circuit layout method of any of claims 1 to 10.