CN118170217A - Data time sequence synchronization method and device, electronic equipment and storage medium - Google Patents
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Abstract
The invention provides a data timing synchronization method, a data timing synchronization device, electronic equipment and a storage medium. The method comprises the following steps: adding clock information into each piece of data to be transmitted to obtain a plurality of pieces of data to be transmitted containing the clock information; and sending each piece of data to be sent containing the clock information to a data receiving end, so that the data receiving end performs time sequence synchronization on each piece of data to be sent based on the clock information. According to the data time sequence synchronization method, the device, the electronic equipment and the storage medium, a plurality of data to be transmitted are obtained through the data transmitting end, clock information is added to each data to be transmitted, and then the data are transmitted to the data receiving end. The data receiving terminal automatically performs clock synchronization by extracting clock information after receiving data, does not need to manually adjust clock parameters, can automatically realize the synchronization time sequence process, can reduce delay errors, improves the accuracy of time sequence synchronization, and is beneficial to the stability of data transmission in a high-speed digital circuit.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a data timing synchronization method, apparatus, electronic device, and storage medium.
Background
In the field of digital circuit design, a sequential logic circuit is a digital circuit based on clock signals, and is characterized in that the excitation condition and clock pulse of a trigger are directly obtained from a state transition diagram of the sequential circuit. The sequential logic circuit includes a synchronous sequential circuit in which all state variable variations are synchronized with a common clock signal.
In the prior art, synchronous sequential circuits are generally adopted for data transmission among modules in a chip and between chips. Because of factors such as line delay, board level delay, clock distribution delay and the like, all modules of the circuit cannot be completely synchronized, delay errors exist, data transmission is affected, and the accuracy of data synchronization is low.
Disclosure of Invention
The invention provides a data time sequence synchronization method, a data time sequence synchronization device, electronic equipment and a storage medium, which are used for improving the accuracy of data time sequence synchronization.
In a first aspect, the present invention provides a data timing synchronization method, applied to a data transmitting end, where the method includes:
acquiring a plurality of data to be transmitted, and adding clock information into each data to be transmitted to obtain the plurality of data to be transmitted containing the clock information;
and sending each piece of data to be sent containing clock information to a data receiving end, so that the data receiving end performs time sequence synchronization on each piece of data to be sent containing the clock information based on the clock information in each piece of data to be sent containing the clock information after receiving the data to be sent containing the clock information.
According to the data timing synchronization method provided by the invention, clock information is added in each data to be transmitted to obtain a plurality of data to be transmitted containing the clock information, and the method comprises the following steps:
Under the condition that the data transmitting end transmits the plurality of data to be transmitted one by one, adding clock bits in each data to be transmitted, and adding clock information in the clock bits of each data to be transmitted to obtain a plurality of data to be transmitted containing the clock information;
Determining data length information of the plurality of data to be transmitted under the condition that the data transmitting end performs combined transmission on the plurality of data to be transmitted;
Determining merging data of a plurality of data to be transmitted, and adding data length bits into the merging data;
and adding the data length information serving as clock information of the combined data into the data length bit to obtain the combined data containing the clock information.
According to the data timing synchronization method provided by the invention, after obtaining the combined data containing the clock information, the method further comprises the following steps:
Determining a plurality of key values in a symmetric encryption algorithm, the key values comprising a plurality of weak key values in the symmetric encryption algorithm and a plurality of semi-weak key values in the symmetric encryption algorithm;
Adding a key bit in the merged data, randomly determining a key value from the plurality of key values, and adding the key value to the key bit of the merged data.
According to the data timing synchronization method provided by the invention, before clock information is added to each piece of data to be transmitted to obtain a plurality of pieces of data to be transmitted containing the clock information, the method further comprises the steps of:
encrypting each data to be transmitted based on an initial vector of an output feedback OFB encryption mode and a key of the OFB encryption mode;
In the process of encrypting the data to be sent, based on a preset error interval, injecting errors in the process of encryption to obtain key error injection information of the data to be sent;
and taking the key error injection information as clock information of the data to be transmitted.
In a second aspect, the present invention further provides a data timing synchronization method, applied to a data receiving end, where the method includes:
receiving a plurality of pieces of data to be transmitted, which are transmitted by a data transmitting end and contain clock information, wherein the pieces of data to be transmitted, which contain the clock information, are obtained based on the fact that the data transmitting end adds the clock information into the acquired pieces of data to be transmitted;
And carrying out time sequence synchronization on each data to be transmitted based on the clock information in each data to be transmitted containing the clock information.
According to the data timing synchronization method provided by the invention, based on the clock information in the data to be sent containing the clock information, the data to be sent are timing synchronized, and the method comprises the following steps:
And under the condition that the clock information is key error injection information of each piece of data to be transmitted, carrying out time sequence synchronization on each piece of data to be transmitted based on an error interval in the key error injection information, wherein the key error injection information is determined by injecting errors in the encryption process based on a preset error interval in the process that the data transmitting end encrypts each piece of data to be transmitted based on an output feedback OFB encryption mode.
In a third aspect, the present invention further provides a data timing synchronization device, and an application data sending end, where the device includes:
The clock information adding module is used for obtaining a plurality of data to be sent, adding clock information into each data to be sent, and obtaining a plurality of data to be sent containing the clock information;
And the sending module is used for sending each piece of data to be sent containing the clock information to the data receiving end so that the data receiving end can perform time sequence synchronization on each piece of data to be sent containing the clock information based on the clock information in each piece of data to be sent containing the clock information after receiving the data to be sent containing the clock information.
In a fourth aspect, the present invention further provides a data timing synchronization device, applied to a data receiving end, where the device includes:
The receiving module is used for receiving a plurality of pieces of data to be transmitted, which are transmitted by the data transmitting end and contain clock information, wherein the plurality of pieces of data to be transmitted, which contain the clock information, are obtained by adding the clock information into the plurality of pieces of data to be transmitted, which are acquired by the data transmitting end;
And the synchronization module is used for carrying out time sequence synchronization on each data to be transmitted based on the clock information in the data to be transmitted containing the clock information.
In a fifth aspect, the present invention further provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing any one of the data timing synchronization methods when executing the computer program.
In a sixth aspect, the present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a data timing synchronization method as any one of the above.
According to the data time sequence synchronization method, the device, the electronic equipment and the storage medium, a plurality of data to be transmitted are obtained through the data transmitting end, clock information is added to each data to be transmitted, and then the data are transmitted to the data receiving end. The data receiving terminal automatically performs clock synchronization by extracting clock information after receiving data, does not need to manually adjust clock parameters, can automatically realize a synchronous time sequence process, can reduce delay errors, improves the accuracy of data time sequence synchronization, is favorable for the stability of data transmission in a high-speed digital circuit, and has low added hardware cost and easy deployment and implementation.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the invention, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a first synchronous sequential circuit scheme in a related method;
FIG. 2 is a schematic diagram of a second synchronous sequential circuit scheme in a related method;
FIG. 3 is a schematic diagram of a delay structure in a related method;
FIG. 4 is a flow chart of a data timing synchronization method according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a data timing synchronization structure according to the present invention;
FIG. 6 is a schematic diagram illustrating the injection of clock information sent one by one according to the present invention;
FIG. 7 is a schematic diagram illustrating clock information injection for merging transmissions provided by the present invention;
FIG. 8 is a schematic diagram of a synchronization structure using a key provided by the present invention as clock information;
FIG. 9 is a schematic diagram illustrating the injection of a key as clock information provided by the present invention;
fig. 10 is a schematic diagram of an OFB encryption mode structure provided by the present invention;
FIG. 11 is a schematic diagram of a synchronization structure using key errors as clock information according to the present invention;
FIG. 12 is a schematic diagram of key error injection provided by the present invention;
FIG. 13 is a second flowchart of a data timing synchronization method according to an embodiment of the present invention;
FIG. 14 is a schematic diagram of a data timing synchronization device according to an embodiment of the present invention;
FIG. 15 is a second schematic diagram of a data timing synchronization device according to an embodiment of the present invention;
fig. 16 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the field of digital circuit design, the sequential logic circuit is a digital circuit based on clock signals, and is characterized in that the excitation condition and clock pulse of a trigger are directly obtained from a state transition diagram of the sequential circuit, the design principle is simple and convenient, and complex calculation of a state equation and a driving equation is avoided. Sequential logic circuits are further divided into synchronous sequential circuits and asynchronous sequential circuits. In the synchronous sequential circuit, all state variable changes are synchronous with the universal clock signal; in an asynchronous sequential circuit, all state variable changes are asynchronous and can change at any time.
When data is transmitted between modules in a chip and between chips, a synchronous time sequence circuit is generally adopted, and the method has the advantages of being favorable for keeping the synchronization between data transmission and data reception and good in instantaneity. However, due to factors such as line delay, board-level delay, clock distribution delay and the like, all modules of the circuit cannot be completely synchronized, and delay errors can exist. Although the delay error has a small influence on data transmission in the low-speed circuit, the data transmission is influenced in the high-speed digital circuit, and the problems of data receiving errors, data loss and the like are caused by asynchronous clocks, so that the clock offset, line delay parameters and the like need to be manually adjusted to enable the timing sequence to converge.
The scheme for realizing the synchronous time sequence circuit in the related method mainly comprises the following steps:
scheme 1 (with unified clock source): as shown in the schematic diagram of the first synchronous sequential circuit scheme in the related method of fig. 1, when the modules 1 and 2 perform data transmission, the clock terminals of the modules 1 and 2 are connected to the same clock source as clock synchronous signals.
Scheme 2 (with separate clock signals): as shown in the second synchronous sequential circuit scheme of the related method of fig. 2, when the module 1 and the module 2 perform data transmission, the module 1 generates a separate clock signal, and the module 2 uses the clock signal to perform data reception.
Disadvantages in the related methods are:
For scheme 1: as shown in the schematic diagram of the delay structure in the related method of fig. 3, there is board-level delay and clock distribution delay, so that the data received by the receiving module cannot be completely matched with the clock signal, and there is a risk of data transmission errors, loss and the like in the high-speed digital system, and parameters such as wiring, clock and the like of the circuit need to be manually adjusted so as to offset the influence of the delay.
For scheme 2: the lengths of the data line and the clock line are not completely equal in practice due to the fact that the lengths of the data line and the clock line are not matched, and errors of receiving data can be caused by the fact that the lengths of the data line and the clock line are not matched.
In order to address the drawbacks of the related methods, the present application proposes a data timing synchronization method, fig. 4 is one of the flow charts of the data timing synchronization method provided by the embodiment of the present application, and referring to fig. 4, the data timing synchronization method provided by the embodiment of the present application is applied to a data transmitting end, and the method includes the following steps:
Step 410, obtaining a plurality of data to be transmitted, and adding clock information to each data to be transmitted to obtain a plurality of data to be transmitted including the clock information;
Step 420, sending each data to be sent including clock information to a data receiving end, so that after the data receiving end receives each data to be sent including clock information, timing synchronization is performed on each data to be sent based on the clock information in each data to be sent including clock information.
The embodiment of the application comprises a data sending end and a data receiving end. The data transmitting end generally refers to a source of data, and is responsible for converting the data from an original form into a format capable of being transmitted, and transmitting the data onto a network or other transmission media. The data sender also needs to select an appropriate transmission protocol and communication mode to ensure that the data can be reliably transmitted to the target location.
The data receiving end refers to a target position of the data and is responsible for receiving and analyzing the data transmitted from the transmitting end. The data receiving end needs to perform corresponding processing according to the transmission protocol and the communication mode used by the sending end so as to ensure that the data can be correctly restored to the original form.
Specifically, the data transmitting end and the receiving end may be in the same chip or in different chips. The data transmission and exchange are completed by physical connection or network connection.
The technical scheme of the invention is described in detail below by taking the data transmitting end to execute the data time sequence synchronization method provided by the invention as an example.
In step 410, a plurality of data to be transmitted are obtained, and clock information is added to each data to be transmitted, so as to obtain a plurality of data to be transmitted including the clock information.
The plurality of data to be transmitted are any data to be transmitted to the data receiving end in the data transmitting end and are subjected to synchronous time sequence.
Adding clock information into the data to be transmitted to obtain the data to be transmitted containing the clock information, so that the receiving end can perform clock synchronization of the data when receiving the data.
Wherein the clock information may be constituted by a clock signal. A clock signal is a periodic electrical signal, typically in the form of a square wave or pulse. The clock signal may include positive pulses and negative pulses. Positive pulses refer to the rising edge of the clock corresponding to the generation of a pulse, while the falling edge corresponds to the end of the pulse. For clock information added to data to be transmitted, a data bit "1" may be used to represent a positive pulse and a data bit "0" may be used to represent a negative pulse.
It will be appreciated that the data to be transmitted is typically transmitted in parallel over the data bus in bytes (8 bits), words (16 bits), double words (32 bits), quad words (64 bits), etc.
For converting Data on parallel Data buses into serial Data, for example, for one byte Data [7..0], 8bit parallel Data on 8 Data buses need to be serial transmitted through 1 Data line after parallel-serial conversion, and then clock information is added.
In step 420, each data to be transmitted including clock information is sent to a data receiving end, so that after the data receiving end receives each data to be transmitted including clock information, each data to be transmitted is time-sequence synchronized based on the clock information in each data to be transmitted including clock information.
After the data sending end obtains the data to be sent containing the clock information, each data to be sent containing the clock information is sent to the data receiving end.
After receiving the data to be transmitted containing the clock information, the data receiving end analyzes the clock information field.
Based on the received clock information, the data receiving end can adopt different time sequence synchronization algorithms to perform time sequence synchronization on the data to be transmitted.
It can be understood that when data transmission is performed between the data transmitting end and the data receiving end, the data transmitting end adds clock information when data is output, and the data receiving end automatically performs clock synchronization by extracting the clock information when data is received, so that manual adjustment of clock parameters is not required.
Optionally, the data transmitting end may be formed by a data transmitting module, a parallel-serial converting module and a clock signal injecting module, and the data receiving end may be formed by a clock signal detecting module, a serial-parallel converting module and a data receiving module. The data transmission schematic diagram of each specific module is shown in fig. 5, which is a schematic diagram of a data timing synchronization structure provided by the present invention.
The data transmitting module of the data transmitting end is used for transmitting data to be transmitted, and the data to be transmitted is generally transmitted in parallel through a data bus in a byte (8 bit), word (16 bit), double word (32 bit), quad word (64 bit) and other modes.
The parallel-serial conversion module of the Data transmitting end is used for converting the Data on the parallel Data bus into serial Data, for example, 8bit parallel Data on 8 Data buses are subjected to parallel-serial conversion and then are subjected to serial transmission through 1 Data line.
And the clock information injection module of the data transmitting end adds clock information into the serial data so that the receiving end performs clock synchronization of the data when receiving the data.
The clock signal detection module of the data receiving end is used for detecting the start bit of the data to be transmitted sent by the data sending end, indicating the start of data receiving, and then detecting the clock signal.
And the serial-parallel conversion module of the data receiving end is used for converting 1 serial data to be sent of 8 bits into parallel data every time the serial data to be sent are received, and carrying out parallel transmission through 8 data buses.
And the Data receiving module of the Data receiving end is used for receiving the Data [ n.0 ] transmitted on the parallel Data bus.
According to the data timing synchronization method provided by the embodiment of the invention, a plurality of data to be transmitted are acquired through the data transmitting end, and clock information is added in each data to be transmitted and then transmitted to the data receiving end. The data receiving terminal automatically performs clock synchronization by extracting clock information after receiving data, does not need to manually adjust clock parameters, can automatically realize a synchronous time sequence process, can reduce delay errors, improves the accuracy of data time sequence synchronization, is favorable for the stability of data transmission in a high-speed digital circuit, and has low added hardware cost and easy deployment and implementation.
In one embodiment, adding clock information to each data to be sent to obtain a plurality of data to be sent containing the clock information includes: under the condition that the data transmitting end transmits the plurality of data to be transmitted one by one, adding clock bits in each data to be transmitted, and adding clock information in the clock bits of each data to be transmitted to obtain a plurality of data to be transmitted containing the clock information; determining data length information of the plurality of data to be transmitted under the condition that the data transmitting end performs combined transmission on the plurality of data to be transmitted; determining merging data of a plurality of data to be transmitted, and adding data length bits into the merging data; and adding the data length information serving as clock information of the combined data into the data length bit to obtain the combined data containing the clock information.
For a plurality of data to be sent in the data sending end, the plurality of data to be sent are sent to the data receiving end one by one, or the plurality of data to be sent are combined and sent to the data receiving end together.
In the case of performing a one-by-one transmission for a plurality of data to be transmitted, a schematic diagram of adding clock information specifically is shown in fig. 6, which is a schematic diagram of one-by-one transmission clock information injection provided by the present invention.
For each data to be transmitted, it may be constituted by data bits of a data length of 8 bits. Adding a clock bit to each data to be transmitted, and adding clock information to the clock bit to obtain a plurality of data to be transmitted containing the clock information.
In the case of performing the merged transmission on the plurality of data to be transmitted, a schematic diagram of adding clock information specifically is shown in fig. 7, which is a schematic diagram of clock information injection of the merged transmission provided by the present invention.
And the Data to be transmitted for the Data1-DataN are transmitted to a Data receiving end as one combined Data.
For example, if the data to be transmitted is composed of a group of 8-bit data, the data length is also 8 bits, and if the data length is 20, the value represents 20 consecutive 8-bit data to be transmitted. The start bit in fig. 7 is 1bit, and is used to identify the start of a certain data transmission between the transmitting end and the receiving end. After the data receiving end receives the data length bits, it can determine how many data to be sent are specifically included in the received combined data.
Based on the specific number of data to be transmitted determined based on the start bit and the data length bit, a data timing synchronization process for a plurality of data to be transmitted can be realized.
In one embodiment, after obtaining the combined data containing the clock information, the method further comprises: determining a plurality of key values in a symmetric encryption algorithm, the key values comprising a plurality of weak key values in the symmetric encryption algorithm and a plurality of semi-weak key values in the symmetric encryption algorithm; adding a key bit in the merged data, randomly determining a key value from the plurality of key values, and adding the key value to the key bit of the merged data.
Because the data transmission mode is generally serial transmission, in order to further improve the data transmission speed, the parallel transmission mode can be adopted, the parallel-serial conversion process of the data in the serial transmission process is omitted, and the key value of the symmetric encryption algorithm can be adopted as the synchronous signal of the clock. Specific symmetric encryption algorithms include DES (Data Encryption Standard): data encryption standard, using a 56-bit key; 3DES (TRIPLE DATA Encryption Algorithm): triple data encryption algorithm is an enhanced version of DES, using multiple DES operations; AES (Advanced Encryption Standard): advanced encryption standards, currently in common use, support 128, 192, and 256 bit keys.
The key value of the symmetric encryption algorithm DES is used as a synchronizing signal of a clock, as shown in a schematic diagram of a synchronizing structure with the key provided by the invention as clock information in fig. 8, and the specific description is as follows:
The DES cryptographic algorithm is used for encrypting/decrypting data, but there is a certain disadvantage in encrypting by the DES algorithm, namely, weak key and semi-weak key exist. The normal key is operated by encrypting the plaintext to obtain the ciphertext and decrypting the ciphertext to obtain the plaintext, i.e., p=d k(Ek (P)). The weak key is operated to encrypt the plaintext to form the ciphertext, and then the ciphertext is not decrypted, but the ciphertext is encrypted again by using the weak key to obtain the plaintext, namely: p=e k(Ek (P)). There are also 6 half weak keys k1, k2 (k1+.k2), and the same ciphertext is obtained by encrypting the same plaintext using the half weak key, that is, E k1(P)＝Ek2 (P). Whereas a normal key is that for any 2 different keys k1+.k2, encrypting the same plaintext results in a different ciphertext, E k1(P)≠Ek2 (P).
Specific weak key and semi-weak key values for DES are as follows:
(1) 4 weak key values: 0101010101010101,1F1F1F1F0E0E0E0E,E0E0E0E0F1F1F1F1,FEFEFEFEFEFEFEFE
(2) 6 Half weak key values:
01FE01FE01FE01FE，FE01FE01FE01FE01；
1FE01FE00EF10EF1，E01FE01FF10EF10E；
01E001E001F101F1，E001E001F101F101；
1FFE1FFE0EFE0EFE，FE1FFE1FFE0EFE0E；
011F011F010E010E，1F011F010E010E01；
E0FEE0FEF1FEF1FE，FEE0FEE0FEF1FEF1。
Therefore, in this embodiment, the data is not encrypted by the key value of DES, but the key value is used for clock synchronization of data transmission, and even if the key value leaks in the transmission process, the system security will not be affected. The DES weak key generator in fig. 8 is used for randomly generating one key value (64 bits) of the 16 weak keys/semi-weak keys, and the clock signal injection module attaches the start bit, the key value and the data length value to the data to be transmitted before the data, and then the data is sent to the data receiving end in a parallel manner. Taking 64bit parallel data transmission as an example, the clock signal injection mode is shown in an injection schematic diagram of the key provided by the invention as clock information in fig. 9, the roles of the start bit and the data length are consistent with those in the above basic embodiment, the key value is a DES weak key/semi-weak key generated randomly, and the data part represents N64 bit data to be transmitted.
The clock signal detection module of the data receiving end detects the key value and then is used as a clock synchronous signal of the data, and then N64-bit data to be transmitted shown by the data length value are automatically received.
In one embodiment, before adding clock information to each data to be sent to obtain a plurality of data to be sent containing the clock information, the method further includes: encrypting each data to be transmitted based on an initial vector of an output feedback OFB encryption mode and a key of the OFB encryption mode; in the process of encrypting the data to be sent, based on a preset error interval, injecting errors in the process of encryption to obtain key error injection information of the data to be sent; and taking the key error injection information as clock information of the data to be transmitted.
The Output Feedback (OFB) is an encryption mode of the symmetric cryptographic algorithm, and the structure of the Output Feedback (OFB) is shown in fig. 10, which is a schematic diagram of the structure of the OFB encryption mode provided by the present invention, and the encryption process is as follows:
IVi＝E(IVi-1,K)；
Ci＝Pi⊕IVi,i＝1,2,…,n；
Wherein P represents unencrypted data (plaintext), C represents encrypted data (ciphertext), IV represents an initial vector, E represents an encryption algorithm (e.g., DES, AES, SM, etc. symmetric cryptographic algorithm), K represents a key, and a block represents an exclusive-or operation XOR.
The problem with the OFB mode is that during the encryption of the initial vector IV, if an error occurs, the error diffusion of the ciphertext is caused, for example, if an error occurs in the 2 nd iteration encryption of the initial vector IV in fig. 10, the error from the ciphertext block C2 to the ciphertext block Cn is caused. By utilizing the characteristics, a mode of injecting errors into the key in the OFB mode can be adopted as clock information, and the implementation process can be shown as a synchronous structure diagram of the key injection errors provided by the invention in FIG. 11 as the clock information.
The data transmitting module transmits plaintext data, the encryption algorithm adopts an OFB mode, the plaintext data is encrypted by combining an initial vector IV and a secret key K, and the encrypted data is transmitted to the receiving end in a ciphertext mode. The clock signal injection module is used for injecting errors into the IV encryption process based on a preset error interval, namely, forming an error key K in a certain encryption process based on the preset error interval; the clock detection module at the receiving end detects the secret key, and if the OFB decryption module is used for finding out the error of the decrypted data in the data decryption process, the data receiving module refuses to receive the error data. For example, as shown in fig. 10, the 3 rd encryption process of IV is injected with an error, resulting in an error from ciphertext block C3 to ciphertext block Cn, when the receiving end decrypts with the OFB decryption module, it finds the error of C3, and then refuses to decrypt C3 to Cn, and only decrypts C1 and C2 and then receives correct plaintext P1 and P2. And so on, if the sending end correctly encrypts the 3 rd and 4 th encryption processes of the IV, the receiving end can correctly receive the plaintext P3 and P4.
The error order for the IV encryption process may be set according to a preset error interval. The preset error interval may be determined based on timing synchronization requirements. As shown in the key error injection schematic diagram provided in fig. 12, for example, the 3 rd, 5 th and … th encryption process errors, the key error injection information is used as clock information to realize the synchronization of the transmission process of the data packets P1, P2, … and Pn to be sent.
Fig. 13 is a second flowchart of a data timing synchronization method according to an embodiment of the present application, and referring to fig. 13, the data timing synchronization method according to an embodiment of the present application is applied to a data receiving end, and the method includes the following steps:
Step 1310, receiving a plurality of data to be transmitted including clock information, which are transmitted by a data transmitting terminal, wherein the plurality of data to be transmitted including clock information is obtained based on adding clock information in the plurality of acquired data to be transmitted by the data transmitting terminal;
step 1320, performing timing synchronization on each data to be sent based on the clock information in the data to be sent containing the clock information.
The embodiment of the application comprises a data sending end and a data receiving end. The data transmitting end generally refers to a source of data, and is responsible for converting the data from an original form into a format capable of being transmitted, and transmitting the data onto a network or other transmission media. The data sender also needs to select an appropriate transmission protocol and communication mode to ensure that the data can be reliably transmitted to the target location.
The data receiving end refers to a target position of the data and is responsible for receiving and analyzing the data transmitted from the transmitting end. The data receiving end needs to perform corresponding processing according to the transmission protocol and the communication mode used by the sending end so as to ensure that the data can be correctly restored to the original form.
Specifically, the data transmitting end and the receiving end may be in the same chip or in different chips. The data transmission and exchange are completed by physical connection or network connection.
The technical scheme of the invention is described in detail below by taking the data receiving end to execute the data time sequence synchronization method provided by the invention as an example.
In step 1310, a plurality of data to be transmitted including clock information sent by the data transmitting end is received, where the plurality of data to be transmitted including clock information is obtained based on adding clock information to the plurality of acquired data to be transmitted by the data transmitting end.
The plurality of data to be transmitted are any data to be transmitted to the data receiving end in the data transmitting end and are subjected to synchronous time sequence.
Adding clock information into the data to be transmitted to obtain the data to be transmitted containing the clock information, so that the receiving end can perform clock synchronization of the data when receiving the data.
Wherein the clock information may be constituted by a clock signal. A clock signal is a periodic electrical signal, typically in the form of a square wave or pulse. The clock signal may include positive pulses and negative pulses. Positive pulses refer to the rising edge of the clock corresponding to the generation of a pulse, while the falling edge corresponds to the end of the pulse. For clock information added to data to be transmitted, a data bit "1" may be used to represent a positive pulse and a data bit "0" may be used to represent a negative pulse.
It will be appreciated that the data to be transmitted is typically transmitted in parallel over the data bus in bytes (8 bits), words (16 bits), double words (32 bits), quad words (64 bits), etc.
For converting Data on parallel Data buses into serial Data, for example, for one byte Data [7..0], 8bit parallel Data on 8 Data buses need to be serial transmitted through 1 Data line after parallel-serial conversion, and then clock information is added.
In step 1320, timing synchronization is performed on each data to be transmitted based on the clock information in the data to be transmitted including the clock information.
After receiving the data to be transmitted containing the clock information, the data receiving end analyzes the clock information field.
Based on the received clock information, the data receiving end can adopt different time sequence synchronization algorithms to perform time sequence synchronization on the data to be transmitted.
It can be understood that when data transmission is performed between the data transmitting end and the data receiving end, the data transmitting end adds clock information when data is output, and the data receiving end automatically performs clock synchronization by extracting the clock information when data is received, so that manual adjustment of clock parameters is not required.
According to the data timing synchronization method provided by the embodiment of the invention, a plurality of data to be transmitted are acquired through the data transmitting end, and clock information is added in each data to be transmitted and then transmitted to the data receiving end. The data receiving terminal automatically performs clock synchronization by extracting clock information after receiving data, does not need to manually adjust clock parameters, can automatically realize a synchronous time sequence process, can reduce delay errors, improves the accuracy of data time sequence synchronization, is favorable for the stability of data transmission in a high-speed digital circuit, and has low added hardware cost and easy deployment and implementation.
In one embodiment, based on the clock information in the data to be sent, performing timing synchronization on the data to be sent, where the data to be sent includes: and under the condition that the clock information is key error injection information of each piece of data to be transmitted, carrying out time sequence synchronization on each piece of data to be transmitted based on an error interval in the key error injection information, wherein the key error injection information is determined by injecting errors in the encryption process based on a preset error interval in the process that the data transmitting end encrypts each piece of data to be transmitted based on an output feedback OFB encryption mode.
The data transmitting end encrypts each data to be transmitted based on the OFB encryption mode by combining an initial vector of the OFB encryption mode and a key of the OFB encryption mode.
And in the process of encrypting each piece of data to be transmitted by the data transmitting end, injecting errors in the process of encryption based on a preset error interval, so as to obtain key error injection information of each piece of data to be transmitted.
And under the condition that clock information received by the data receiving end is key error injection information of each data to be sent, carrying out time sequence synchronization on each data to be sent based on error intervals in the key error injection information.
Fig. 14 is a schematic structural diagram of a data timing synchronization device according to an embodiment of the invention. Referring to fig. 14, a data timing synchronization apparatus provided in an embodiment of the present invention includes:
the clock information adding module 1410 is configured to obtain a plurality of data to be sent, and add clock information to each data to be sent, so as to obtain a plurality of data to be sent including the clock information;
The sending module 1420 is configured to send each data to be sent including clock information to a data receiving end, so that after the data receiving end receives each data to be sent including clock information, each data to be sent includes clock information in each data to be sent including clock information, and perform timing synchronization on each data to be sent.
The data timing synchronization device provided by the embodiment of the invention acquires a plurality of data to be transmitted through the data transmitting end, adds clock information into each data to be transmitted, and transmits the data to the data receiving end. The data receiving terminal automatically performs clock synchronization by extracting clock information after receiving data, does not need to manually adjust clock parameters, can automatically realize a synchronous time sequence process, can reduce delay errors, improves the accuracy of data time sequence synchronization, is favorable for the stability of data transmission in a high-speed digital circuit, and has low added hardware cost and easy deployment and implementation.
In one embodiment, the clock information adding module 1410 is specifically configured to:
adding clock information to each data to be transmitted to obtain a plurality of data to be transmitted containing the clock information, wherein the method comprises the following steps:
Under the condition that the data transmitting end transmits the plurality of data to be transmitted one by one, adding clock bits in each data to be transmitted, and adding clock information in the clock bits of each data to be transmitted to obtain a plurality of data to be transmitted containing the clock information;
Determining data length information of the plurality of data to be transmitted under the condition that the data transmitting end performs combined transmission on the plurality of data to be transmitted;
Determining merging data of a plurality of data to be transmitted, and adding data length bits into the merging data;
and adding the data length information serving as clock information of the combined data into the data length bit to obtain the combined data containing the clock information.
In one embodiment, the clock information adding module 1410 is further specifically configured to:
after obtaining the combined data containing the clock information, the method further comprises the following steps:
Determining a plurality of key values in a symmetric encryption algorithm, the key values comprising a plurality of weak key values in the symmetric encryption algorithm and a plurality of semi-weak key values in the symmetric encryption algorithm;
Adding a key bit in the merged data, randomly determining a key value from the plurality of key values, and adding the key value to the key bit of the merged data.
In one embodiment, the clock information adding module 1410 is further specifically configured to:
Adding clock information to each data to be transmitted, and before obtaining a plurality of data to be transmitted containing the clock information, further comprising:
encrypting each data to be transmitted based on an initial vector of an output feedback OFB encryption mode and a key of the OFB encryption mode;
In the process of encrypting the data to be sent, based on a preset error interval, injecting errors in the process of encryption to obtain key error injection information of the data to be sent;
and taking the key error injection information as clock information of the data to be transmitted.
Fig. 15 is a second schematic structural diagram of a data timing synchronization device according to an embodiment of the invention. Referring to fig. 15, a data timing synchronization apparatus provided in an embodiment of the present invention includes:
the receiving module 1510 is configured to receive a plurality of data to be sent including clock information sent by the data sending end, where the plurality of data to be sent including clock information is obtained based on adding clock information to the plurality of acquired data to be sent by the data sending end;
A synchronization module 1520, configured to perform timing synchronization on each data to be sent based on the clock information in the data to be sent that includes the clock information.
According to the data timing synchronization method provided by the embodiment of the invention, a plurality of data to be transmitted are acquired through the data transmitting end, and clock information is added in each data to be transmitted and then transmitted to the data receiving end. The data receiving terminal automatically performs clock synchronization by extracting clock information after receiving data, does not need to manually adjust clock parameters, can automatically realize a synchronous time sequence process, can reduce delay errors, improves the accuracy of data time sequence synchronization, is favorable for the stability of data transmission in a high-speed digital circuit, and has low added hardware cost and easy deployment and implementation.
In one embodiment, the synchronization module 1520 is specifically configured to:
Based on the clock information in the data to be sent containing the clock information, performing time sequence synchronization on the data to be sent, including:
And under the condition that the clock information is key error injection information of each piece of data to be transmitted, carrying out time sequence synchronization on each piece of data to be transmitted based on an error interval in the key error injection information, wherein the key error injection information is determined by injecting errors in the encryption process based on a preset error interval in the process that the data transmitting end encrypts each piece of data to be transmitted based on an output feedback OFB encryption mode.
The present invention also provides an electronic device, as shown in fig. 16, which may include: processor 1610, communication interface (Communication Interface) 1620, memory 1630, and communication bus (bus) 1640, wherein processor 1610, communication interface 1620, memory 1630 complete communication with each other via communication bus 1640. Processor 1610 may invoke logic instructions in memory 1630 to perform data timing synchronization methods, including, for example:
acquiring a plurality of data to be transmitted, and adding clock information into each data to be transmitted to obtain the plurality of data to be transmitted containing the clock information;
and sending each piece of data to be sent containing clock information to a data receiving end, so that the data receiving end performs time sequence synchronization on each piece of data to be sent containing the clock information based on the clock information in each piece of data to be sent containing the clock information after receiving the data to be sent containing the clock information.
Further, the logic instructions in memory 1630 described above may be implemented in the form of software functional units and stored in a computer-readable storage medium when sold or used as a stand-alone product. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
In another aspect, the present invention also provides a computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, are capable of performing the data timing synchronization method provided by the above method embodiments, for example comprising:
acquiring a plurality of data to be transmitted, and adding clock information into each data to be transmitted to obtain the plurality of data to be transmitted containing the clock information;
and sending each piece of data to be sent containing clock information to a data receiving end, so that the data receiving end performs time sequence synchronization on each piece of data to be sent containing the clock information based on the clock information in each piece of data to be sent containing the clock information after receiving the data to be sent containing the clock information.
In yet another aspect, the present invention further provides a non-transitory computer readable storage medium, on which a computer program is stored, which when executed by a processor, implements a data timing synchronization method provided by the above method embodiments, for example, including:
acquiring a plurality of data to be transmitted, and adding clock information into each data to be transmitted to obtain the plurality of data to be transmitted containing the clock information;
and sending each piece of data to be sent containing clock information to a data receiving end, so that the data receiving end performs time sequence synchronization on each piece of data to be sent containing the clock information based on the clock information in each piece of data to be sent containing the clock information after receiving the data to be sent containing the clock information.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A method for synchronizing data timing, which is applied to a data transmitting end, the method comprising:
acquiring a plurality of data to be transmitted, and adding clock information into each data to be transmitted to obtain the plurality of data to be transmitted containing the clock information;
and sending each piece of data to be sent containing clock information to a data receiving end, so that the data receiving end performs time sequence synchronization on each piece of data to be sent containing the clock information based on the clock information in each piece of data to be sent containing the clock information after receiving the data to be sent containing the clock information.
2. The method for synchronizing data timing according to claim 1, wherein adding clock information to each data to be transmitted to obtain a plurality of data to be transmitted including the clock information, comprises:
Under the condition that the data transmitting end transmits the plurality of data to be transmitted one by one, adding clock bits in each data to be transmitted, and adding clock information in the clock bits of each data to be transmitted to obtain a plurality of data to be transmitted containing the clock information;
Determining data length information of the plurality of data to be transmitted under the condition that the data transmitting end performs combined transmission on the plurality of data to be transmitted;
Determining merging data of a plurality of data to be transmitted, and adding data length bits into the merging data;
and adding the data length information serving as clock information of the combined data into the data length bit to obtain the combined data containing the clock information.
3. The method of claim 2, wherein after obtaining the combined data including the clock information, further comprising:
Determining a plurality of key values in a symmetric encryption algorithm, the key values comprising a plurality of weak key values in the symmetric encryption algorithm and a plurality of semi-weak key values in the symmetric encryption algorithm;
Adding a key bit in the merged data, randomly determining a key value from the plurality of key values, and adding the key value to the key bit of the merged data.
4. The method for synchronizing data timing according to claim 1, wherein before adding clock information to each data to be transmitted to obtain a plurality of data to be transmitted including the clock information, further comprising:
encrypting each data to be transmitted based on an initial vector of an output feedback OFB encryption mode and a key of the OFB encryption mode;
In the process of encrypting the data to be sent, based on a preset error interval, injecting errors in the process of encryption to obtain key error injection information of the data to be sent;
and taking the key error injection information as clock information of the data to be transmitted.
5. A method for synchronizing data timing, applied to a data receiving end, the method comprising:
receiving a plurality of pieces of data to be transmitted, which are transmitted by a data transmitting end and contain clock information, wherein the pieces of data to be transmitted, which contain the clock information, are obtained based on the fact that the data transmitting end adds the clock information into the acquired pieces of data to be transmitted;
And carrying out time sequence synchronization on each data to be transmitted based on the clock information in each data to be transmitted containing the clock information.
6. The method of claim 5, wherein the performing timing synchronization on each data to be transmitted based on the clock information in each data to be transmitted including the clock information comprises:
And under the condition that the clock information is key error injection information of each piece of data to be transmitted, carrying out time sequence synchronization on each piece of data to be transmitted based on an error interval in the key error injection information, wherein the key error injection information is determined by injecting errors in the encryption process based on a preset error interval in the process that the data transmitting end encrypts each piece of data to be transmitted based on an output feedback OFB encryption mode.
7. A data timing synchronization device, applied to a data transmitting end, the device comprising:
The clock information adding module is used for obtaining a plurality of data to be sent, adding clock information into each data to be sent, and obtaining a plurality of data to be sent containing the clock information;
And the sending module is used for sending each piece of data to be sent containing the clock information to the data receiving end so that the data receiving end can perform time sequence synchronization on each piece of data to be sent containing the clock information based on the clock information in each piece of data to be sent containing the clock information after receiving the data to be sent containing the clock information.
8. A data timing synchronization apparatus for use in a data receiving terminal, the apparatus comprising:
The receiving module is used for receiving a plurality of pieces of data to be transmitted, which are transmitted by the data transmitting end and contain clock information, wherein the plurality of pieces of data to be transmitted, which contain the clock information, are obtained by adding the clock information into the plurality of pieces of data to be transmitted, which are acquired by the data transmitting end;
And the synchronization module is used for carrying out time sequence synchronization on each data to be transmitted based on the clock information in the data to be transmitted containing the clock information.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the data timing synchronization method according to any one of claims 1 to 4 or the data timing synchronization method according to claim 5 or 6 when executing the computer program.
10. A non-transitory computer readable storage medium having stored thereon a computer program, wherein the computer program when executed by a processor implements the data timing synchronization method according to any one of claims 1 to 4 or the data timing synchronization method according to claim 5 or 6.
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