CN118164429B - Laminated structure for micro-nano device and preparation method thereof - Google Patents
Laminated structure for micro-nano device and preparation method thereof Download PDFInfo
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- CN118164429B CN118164429B CN202410587503.7A CN202410587503A CN118164429B CN 118164429 B CN118164429 B CN 118164429B CN 202410587503 A CN202410587503 A CN 202410587503A CN 118164429 B CN118164429 B CN 118164429B
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- 238000002360 preparation method Methods 0.000 title abstract description 10
- 239000000463 material Substances 0.000 claims abstract description 108
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 74
- 229910052751 metal Inorganic materials 0.000 claims abstract description 50
- 239000002184 metal Substances 0.000 claims abstract description 50
- 238000000151 deposition Methods 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 27
- 238000009713 electroplating Methods 0.000 claims abstract description 21
- 229910021645 metal ion Inorganic materials 0.000 claims abstract description 10
- 239000011248 coating agent Substances 0.000 claims abstract description 7
- 238000000576 coating method Methods 0.000 claims abstract description 7
- 238000001259 photo etching Methods 0.000 claims abstract description 4
- 238000012546 transfer Methods 0.000 claims abstract description 3
- 238000007747 plating Methods 0.000 claims description 21
- 230000008021 deposition Effects 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 239000011810 insulating material Substances 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 238000004026 adhesive bonding Methods 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910052742 iron Inorganic materials 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 13
- 230000004888 barrier function Effects 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 103
- 235000012431 wafers Nutrition 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- GNTDGMZSJNCJKK-UHFFFAOYSA-N divanadium pentaoxide Chemical compound O=[V](=O)O[V](=O)=O GNTDGMZSJNCJKK-UHFFFAOYSA-N 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 238000001883 metal evaporation Methods 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- ZNOKGRXACCSDPY-UHFFFAOYSA-N tungsten trioxide Chemical compound O=[W](=O)=O ZNOKGRXACCSDPY-UHFFFAOYSA-N 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- 229910012463 LiTaO3 Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910020286 SiOxNy Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001017 electron-beam sputter deposition Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00349—Creating layers of material on a substrate
- B81C1/00373—Selective deposition, e.g. printing or microcontact printing
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B1/00—Devices without movable or flexible elements, e.g. microcapillary devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00349—Creating layers of material on a substrate
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
- C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Organic Chemistry (AREA)
- Metallurgy (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrochemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a laminated structure for a micro-nano device and a preparation method thereof, wherein the method comprises the following steps: coating photoresist on the wafer and performing soft baking; exposing the photoresist by using a photoetching machine and a mask plate to transfer the pattern on the mask plate to a wafer; developing out an inverted trapezoid photoresist image by using a developing solution, and forming a positive trapezoid opening between the two photoresist images; depositing a first layer of material in the photoresist image and the right trapezoid-shaped opening; setting a metal seed layer, and electroplating electroplated layer metal on the first layer material by using electroplating solution containing the same metal ions; depositing a second layer of material on the electroplated layer metal to form a laminated structure, wherein the laminated structure is a combination of the first layer of material and the second layer of material deposited in the right trapezoid opening; and removing the photoresist to retain the laminated structure. The invention can eliminate the risk of dropping or directly depositing materials except the first layer of material on the substrate, and improve the barrier reliability of the first layer of material.
Description
Technical Field
The invention belongs to the technical field of photoetching micro-nano processing, and particularly relates to a laminated structure for a micro-nano device and a preparation method thereof.
Background
The common stripping process is to coat photoresist on the substrate, expose and develop, take photoresist film with certain pattern as mask, deposit required material with photoresist, then strip the material deposited on the film completely while removing photoresist, and leave only the material with original pattern on the substrate to form laminated structure with the substrate. As a prior art, CN1397986a discloses a metal lift-off method, CN107331601a discloses a double exposure photoresist deposition and metal lift-off method.
In fabricating a multi-layer stack structure for a micro-nano device on a substrate, a first layer of material that is typically in direct contact with the substrate needs to be resistant to a second layer of material and the materials thereon being in direct contact with the substrate, and the accuracy of deposition of these materials is typically limited by the size of the photoresist mask. However, during the deposition of the multi-layer material, the photoresist mask dimensions used in the prior art methods have hardly changed, so that it is difficult to eliminate the risk of material other than the first layer material falling off or being deposited directly on the substrate.
Disclosure of Invention
The invention aims to provide a laminated structure for a micro-nano device and a preparation method thereof, which can eliminate the risk that materials except for a first layer of material fall off or are directly deposited on a substrate and improve the barrier reliability of the first layer of material.
One aspect of the present invention provides a method for manufacturing a stacked structure for a micro-nano device, including:
Gluing and soft baking step S1: coating photoresist on the wafer and performing soft baking;
exposure step S2: exposing the photoresist by using a photoetching machine and a mask plate to transfer the pattern on the mask plate to a wafer;
Developing step S3: developing out an inverted trapezoid photoresist image by using a developing solution, and forming a positive trapezoid opening between the two photoresist images;
A first layer material deposition step S4: depositing a first layer of material in the photoresist image and the right trapezoid-shaped opening;
Electroplating step S5: setting a metal seed layer, and electroplating electroplated layer metal on the first layer material by using electroplating solution containing the same metal ions;
Second layer material deposition step S6: depositing a second layer of material on the electroplated layer metal to form a laminated structure, wherein the laminated structure is a combination of the first layer of material and the second layer of material deposited in the right trapezoid opening;
Step S7 of photoresist stripping: and removing the photoresist to retain the laminated structure.
Preferably, the first layer material is a metal, and in the plating step S5, the first layer material is plated with a plating metal using a plating solution containing the same metal ions, with the metal being set as a seed layer.
Preferably, the metal is Fe, co, cr, ni, ru, rh, pd, os, ir, pt, ti or Au.
Preferably, the first layer material is an insulating material, and in the electroplating step S5, a layer of metal is continuously deposited on the first layer material, the layer of metal is set as a seed layer, and the electroplating layer metal is electroplated on the first layer material by using an electroplating solution containing the same metal ions.
Preferably, the insulating material is SiOx, siNx, siOxNy, al 2O3, alOxNy or AlN.
Preferably, the size of the positive trapezoid-shaped opening after plating out the plating layer metal in the plating step S5 is reduced by 0.5 to 1000um from the size of the positive trapezoid-shaped opening formed in the developing step S3.
Preferably, the thickness of the electroplated metal in the positive trapezoid opening is 0.13-230 um.
Preferably, a repeated stacking step is further included between the second layer material deposition step S6 and the photoresist removal step S7, in which the electroplating step S5 and the second layer material deposition step S6 are repeated to form a laminated structure including three or more layers of materials.
Preferably, in the photoresist coating and soft baking step S1, the coating thickness of the photoresist is 0.5-150 um, and the soft baking temperature is 85-125 ℃.
In another aspect, the present invention provides a laminated structure for a micro-nano device, which is prepared by the above method.
According to the laminated structure for the micro-nano device and the preparation method thereof, the risk that materials except the first layer of materials fall off or are directly deposited on the substrate can be eliminated, and the barrier reliability of the first layer of materials is improved.
Drawings
For a clearer description of the technical solutions of the present invention, the following description will be given with reference to the attached drawings used in the description of the embodiments of the present invention, it being obvious that the attached drawings in the following description are only some embodiments of the present invention, and that other attached drawings can be obtained by those skilled in the art without the need of inventive effort:
fig. 1 is a flowchart of a method of manufacturing a stacked structure for a micro-nano device according to an embodiment of the present invention.
Fig. 2 is a process schematic of a method of fabricating a stacked structure for a micro-nano device according to an embodiment of the present invention.
Fig. 3 is a process schematic of a comparative example of a method of manufacturing a stacked structure for a micro-nano device according to an embodiment of the present invention.
Reference numerals illustrate: 11-wafer, 12-photoresist, 12 a-first photoresist image, 12 b-second photoresist image, 13-first layer material, 14-second layer material, 15-electroplated layer metal.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The embodiment of the invention provides a preparation method of a laminated structure for a micro-nano device, and fig. 1 is a flow chart of the preparation method of the laminated structure for the micro-nano device according to one embodiment of the invention. Fig. 2 is a process schematic of a method of fabricating a stacked structure for a micro-nano device according to an embodiment of the present invention. As shown in fig. 1, the method for manufacturing a stacked structure for a micro-nano device according to an embodiment of the present invention includes steps S1 to S7.
Step S1 is a photoresist coating and soft baking step in which a layer of photoresist 12 is coated on a wafer 11, as shown in fig. 2 (a), and soft baking is performed. Wafer 11 is a clean wafer that has undergone a cleaning process, including but not limited to wafers common in the semiconductor, flat panel display, microelectromechanical system, optical element, etc., such as Si, gaAs, inP, gaN, siC, liNbO 3、LiTaO3, znO, glass, polyimide, any modified substrate thereof, etc.
In this step, the photoresist is preferably coated to a thickness of 0.5 to 150um (micrometers), a soft bake temperature of 85 to 125 deg.c, and a soft bake time of 30 to 600 sec.
The photoresist 12 may be a variety of types of photoresist, and in particular, may be a negative type photoresist, a positive type photoresist suitable for a pattern inversion process, or an inversion type photoresist. The photoresist 12 may be a single layer of photoresist or a bilayer photoresist having a first layer and a second layer with a difference in development rate.
Step S2 is an exposure step of exposing the photoresist using a photolithography machine and a reticle, and transferring the pattern on the reticle onto the wafer 11 coated with the photoresist 12. As shown in fig. 2 (b), a first photoresist image 12a and a second photoresist image 12b are formed on the wafer 11, the first photoresist image 12a being a photoresist image to be left in the developing step, and the second photoresist image 12b being a photoresist image to be removed in the developing step.
Step S3 is a developing step, in which a desired inverse trapezoidal photoresist image is developed using a developing solution, and as shown in fig. 2 (d), the first photoresist image 12a is inverse trapezoidal, and a positive trapezoidal opening is formed between the two first photoresist images 12 a.
In the case that the photoresist 12 is a positive photoresist or a reverse photoresist of a pattern inversion process, the method further includes post-baking and flood-exposure steps between the exposure step S2 and the development step S3, and the post-baking and flood-exposure are performed on the photoresist, so that the first photoresist image 12a which would otherwise be developed is retained, and the second photoresist image 12b which would otherwise be retained is developed, as shown in (c) of fig. 2, to achieve image inversion. Preferably, ammonia gas may be used for post-bake and flood exposure.
Step S4 is a first layer material deposition step in which a first layer material 13 is deposited in the positive trapezoid-shaped opening between the two first photoresist images 12a using electron beam metal evaporation, chemical vapor deposition, or electron beam sputtering, as shown in fig. 2 (e). The first layer of material 13 forms a diffusion barrier layer for preventing material subsequently deposited thereon from falling onto the semiconductor material (wafer 11). The materials deposited thereon as described herein include a second layer of material, a third layer of material, or more layers of material.
In one embodiment, the first layer of material 13 is a metal, preferably Fe, co, cr, ni, ru, rh, pd, os, ir, pt, ti or Au.
In another embodiment, the first layer material 13 is an insulating material, preferably SiOx, siNx, siOxNy, al 2O3, alOxNy or AlN, or SiOx, siNx or SiOxNy containing a small amount of Al or B. Wherein x and y represent positive integers.
Step S5 is a plating step in which, if the first layer material 13 deposited on the photoresist is a metal, the plating layer metal 15 is plated on the first layer material 13 on the photoresist using a plating solution containing the same metal ions as a seed layer. If the first layer of material 13 deposited on the photoresist is an insulating material, a layer of metal is continuously deposited on the first layer of material 13, the layer of metal is set as a seed layer, and a plating layer metal 15 is plated on the first layer of material 13 on the photoresist using a plating solution containing the same metal ions, as shown in fig. 2 (f). The metal that continues to be deposited may be Cr/Au or TiW/Au, such as depositing 500 a. Thereby, the size of the positive trapezoid-shaped openings between the first photoresist images 12a is reduced by electroplating, thereby reducing the risk of the second layer of material to be subsequently deposited onto the first layer of material 13 falling onto the substrate of the wafer 11.
In this step, the size of the positive trapezoid-shaped opening after plating out the plating layer metal 15 is preferably reduced by 0.5 to 1000um from the positive trapezoid-shaped opening formed in the developing step S3. The thickness of the plating metal 15 in the opening of the positive trapezoid is, for example, 0.13 to 230um.
Step S6 is a second layer material deposition step in which a second layer material 14 is deposited on the plating layer metal 15 using electron beam metal evaporation or chemical vapor deposition, as shown in fig. 2 (g), forming a stacked structure that is a combination of the first layer material 13 and the second layer material 14 deposited in the right trapezoid-shaped opening.
The second layer of material 14 may be an oxide semiconductor including, but not limited to IGZO, znO, znSnO, inZnO. The second layer material 14 may also be an inorganic electrochromic material including, but not limited to, tungsten trioxide, titanium dioxide, or vanadium pentoxide. The second layer of material 14 may be any metal. The second layer of material 14 may also be a low resistance electrode metal including, but not limited to, au, al, ag, and Cu.
Step S7 is a photoresist removing step in which the photoresist is removed to retain the laminated structure, as shown in fig. 2 (h).
In one embodiment, a repeat stacking step is further included between the second layer material deposition step S6 and the photoresist stripping step S7, in order to repeat electroplating and deposition on the second layer material 14 as needed, thereby further repeating deposition of a plurality of layers of materials on the second layer material 14 to form a stacked structure including a third layer material, a fourth layer material, a fifth layer material, and the like after the photoresist stripping step S7.
The embodiment of the invention also provides a laminated structure for the micro-nano device, which is prepared by the preparation method of the embodiment of the invention.
Comparative example
Fig. 3 is a process schematic of a comparative example of a method of manufacturing a stacked structure for a micro-nano device according to an embodiment of the present invention, in which (a) and (b) respectively show a case of directly depositing a second layer material on a first layer material and a stacked structure formed thereby. As shown in fig. 3 (a) and (b), when the second layer material 14 is directly deposited on the first layer material 13, the second layer material 14 may form metal balls or hooks at the edge of the first layer material 13, which may be dropped, and even directly deposited on the semiconductor, resulting in an influence on the electrical performance of the semiconductor.
According to the preparation method of the laminated structure for the micro-nano device, an electroplating step is added between the first layer material deposition step and the second layer material deposition step, the first layer material 13 or the metal which is continuously deposited is used as a seed layer, the electroplating liquid containing the same metal ions is selected to electroplate the electroplated layer metal 15, and the second layer material 14 is deposited on the electroplated layer metal 15, so that the opening of the positive trapezoid is reduced, and a stepped double-layer metal laminated layer is formed, thereby avoiding the risk that the second layer material 14 falls off from the edge of the first layer material 13 or is directly deposited on a semiconductor, and further improving the multi-layer material deposition effect.
In summary, according to the method for manufacturing a stacked structure for a micro-nano device in the above embodiment of the present invention, the deposited first layer material or the metal that is continuously deposited is used as the seed layer, and the evaporation and electroplating processes are integrated to manufacture the stepped double-layer metal stack, so that the risk that other materials to be deposited on the first layer material fall onto the substrate of the wafer 11 can be reduced, the upper layer material is prevented from being deposited on the boundary of the first layer material, and the barrier reliability of the first layer material is improved.
While certain exemplary embodiments of the present invention have been described above by way of illustration only, it will be apparent to those of ordinary skill in the art that modifications may be made to the described embodiments in various different ways without departing from the spirit and scope of the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive of the scope of the invention, which is defined by the appended claims.
Claims (9)
1. A method for manufacturing a stacked structure for a micro-nano device, comprising:
Gluing and soft baking step S1: coating photoresist on the wafer and performing soft baking;
exposure step S2: exposing the photoresist by using a photoetching machine and a mask plate to transfer the pattern on the mask plate to a wafer;
Developing step S3: developing out an inverted trapezoid photoresist image by using a developing solution, and forming a positive trapezoid opening between the two photoresist images;
A first layer material deposition step S4: depositing a first layer of material in the photoresist image and the right trapezoid-shaped opening;
Electroplating step S5: setting a metal seed layer, and electroplating electroplated layer metal on a first layer material with a photoresist image below the metal seed layer by using electroplating solution containing the same metal ions;
Second layer material deposition step S6: depositing a second layer of material on the electroplated layer metal to form a laminated structure, wherein the laminated structure is a combination of the first layer of material and the second layer of material deposited in the right trapezoid opening;
step S7 of photoresist stripping: the photoresist is removed to leave the laminated structure,
Wherein the size of the positive trapezoid opening after plating the plating metal in the plating step S5 is reduced by 0.5 to 1000um from the size of the positive trapezoid opening formed in the developing step S3.
2. The method of claim 1, wherein,
In the plating step S5, the first layer material is a metal, the seed layer is set to the metal, and the plating layer metal is plated on the first layer material using a plating solution containing the same metal ions.
3. The method of claim 2, wherein,
The metal is Fe, co, cr, ni, ru, rh, pd, os, ir, pt, ti or Au.
4. The method of claim 1, wherein,
In the electroplating step S5, a layer of metal is continuously deposited on the first layer of material, the layer of metal is set as a seed layer, and the electroplating layer metal is electroplated on the first layer of material by using an electroplating solution containing the same metal ions.
5. The method of claim 4, wherein,
The insulating material is SiOx, siNx, siOxNy, al 2O3, alOxNy or AlN.
6. The method of any one of claim 1 to 5,
The thickness of the electroplated metal in the positive trapezoid opening is 0.13-230 um.
7. The method of any one of claim 1 to 5,
A repeated stacking step is further included between the second layer material deposition step S6 and the photoresist removal step S7, in which the electroplating step S5 and the second layer material deposition step S6 are repeated to form a laminated structure including three or more layers of materials.
8. The method of any one of claim 1 to 5,
In the step S1 of gluing and soft baking, the coating thickness of the photoresist is 0.5-150 um, and the soft baking temperature is 85-125 ℃.
9. A laminate structure for micro-nano devices, characterized in that it is produced by the method according to any one of claims 1-8.
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Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US5316974A (en) * | 1988-12-19 | 1994-05-31 | Texas Instruments Incorporated | Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer |
| US5112448A (en) * | 1989-11-28 | 1992-05-12 | The Boeing Company | Self-aligned process for fabrication of interconnect structures in semiconductor applications |
| KR100262399B1 (en) * | 1992-08-31 | 2000-08-01 | 구자홍 | Gold plating method using lift off method |
| US5554488A (en) * | 1994-07-28 | 1996-09-10 | Northern Telecom Limited | Semiconductor device structure and method of formation thereof |
| US6807734B2 (en) * | 1998-02-13 | 2004-10-26 | Formfactor, Inc. | Microelectronic contact structures, and methods of making same |
| EP1433740A1 (en) * | 2002-12-24 | 2004-06-30 | Interuniversitair Microelektronica Centrum Vzw | Method for the closure of openings in a film |
| KR100791078B1 (en) * | 2006-09-25 | 2008-01-02 | 삼성전자주식회사 | Method of forming metallization filling the recessed area using electroplating method |
| CN117791297B (en) * | 2023-12-26 | 2024-10-29 | 武汉敏芯半导体股份有限公司 | Method for preparing electrode of semiconductor laser and electrode |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101330010A (en) * | 2007-06-20 | 2008-12-24 | 中国科学院微电子研究所 | A method of making T-type HBT emitter/HEMT grid |
| CN111312688A (en) * | 2020-02-28 | 2020-06-19 | 西安微电子技术研究所 | Chip TSV (through silicon Via) through hole etching structure and preparation method thereof |
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