CN118157809A - Time delay information transmission method, clock recovery method and device - Google Patents

Abstract

A time delay information transmission method, a clock recovery method and a device relate to an OTN network. The method comprises the following steps: the OTN equipment acquires a first OTN frame; performing a processing operation on the first OTN frame, the processing operation including at least one of mapping and demapping; acquiring time delay information of a designated processing operation in the processing operation; and sending the time delay information to another OTN device. The end-to-end delay information on the OSU transmission path can be transmitted to the access device in the OTN network, and the access device can perform clock recovery according to the delay information, so that the clock recovery performance can be improved.

Description

Time delay information transmission method, clock recovery method and device

Technical Field

The present application relates to the field of optical transport networks, and in particular, to a method for transmitting delay information, a method for recovering clock, and an apparatus thereof.

Background

The optical service units (optical service unit, OSU) are the next generation technology developed on the basis of the optical transport network (optical transport network, OTN) technology architecture. OSU technology is oriented to flexible bandwidth, multi-service access, and low latency applications. OSU is a fixed bit rate (constant bit rate, CBR) traffic such as E1 (rate 2.048 Mbps), STM-1 (rate 155.520 Mbps), STM-4 (rate 622.080 Mbps), etc. that divides an optical data unit (optical data unit, ODU) into smaller bandwidth particles to carry small particles (e.g., sub-1G, i.e., rates below 1 GHz).

Because the rate of the CBR service is fixed, when the OSU is used for bearing the CBR service, the CBR service clock needs to be recovered, so that the CBR service receiving end and the CBR service clock of the CBR service transmitting end are synchronous, and the CBR service transmission is ensured.

Disclosure of Invention

The embodiment of the application provides a time delay information transmission method, a clock recovery method and a device, which are used for improving clock recovery performance.

In a first aspect, a delay information transmission method is provided, which is applied to an OTN device. The method comprises the following steps: acquiring a first OTN frame; performing a processing operation on the first OTN frame, the processing operation including at least one of mapping and demapping; acquiring time delay information of a designated processing operation in the processing operation; and sending the time delay information to another OTN device.

Alternatively, the first OTN frame may be a first OSU frame or other OTN frame.

In the above implementation manner, the OTN device acquires, for a specified processing operation, delay information for performing the processing operation, and sends the delay information to other OTN devices. Based on the above implementation manner, each OTN network on the OSU transmission path may transmit the delay information of the specified processing operation to the downstream device, so that the end device (such as the access device) may obtain the total delay of the specified processing operation on the OSU transmission path, where the total delay may be used for clock recovery, thereby providing a guarantee for improving the clock recovery performance.

In a possible implementation manner, the sending the delay information to another OTN device includes: and sending the delay information to the other OTN equipment through an overhead area of the OSU frame.

In a possible implementation manner, the sending the delay information to the other OTN device includes: and transmitting the time delay information to the other OTN equipment through one OSU frame.

In a possible implementation manner, the sending, by one OSU frame, the delay information to the other OTN device includes: and sending the time delay information to the other OTN equipment through the first OSU frame.

In a possible implementation manner, the sending, by one OSU frame, the delay information to another OTN device includes: and sending the delay information to the other OTN device through a second OSU frame, wherein the second OSU frame is positioned after the first OSU frame.

In a possible implementation manner, the sending, by the second OSU frame, the delay information to the other OTN device includes: and sending the delay information to the other OTN device through at least two bytes in the second OSU frame.

In a possible implementation manner, the sending the delay information to the other OTN device includes: and transmitting the delay information to the other OTN device through at least two OSU frames, wherein the at least two OSU frames are located after the first OSU frame or the at least two OSU frames comprise the first OSU frame.

In a possible implementation, each of the at least two OSU frames includes at least one byte of the delay information. It should be noted that the delay information may be represented by at least two bytes, and in the current implementation, each OSU frame carries part of the delay information, for example, carries one byte of information.

In a possible implementation manner, the at least two OSU frames include a third OSU frame and a fourth OSU frame, and the sending, by at least two OSU frames, the delay information to the other OTN device includes: transmitting the low-bit byte of the delay information to the other OTN device through the third OSU frame; and transmitting the high-bit byte of the time delay information to the other OTN device through the fourth OSU frame.

In the implementation manner, the low-bit byte of the delay information is transmitted first, so that if the low-bit byte of the delay information is calculated, a carry is generated, and the carry can be accumulated to the higher-bit byte transmitted later, thereby ensuring the accuracy of the delay information.

In a possible implementation manner, before the delay information is sent to the other OTN device through the overhead area of the OSU frame, the method further includes: and accumulating the time value corresponding to the time delay information to the value of the time stamp field in the overhead area of the OSU frame.

In the implementation manner, the time delay information can be transmitted to the downstream equipment in an accumulated manner based on the timestamp field in the overhead area of the OSU frame, the implementation manner is simple, and the structure of the existing OSU frame can be compatible.

In a possible implementation manner, the specified processing operation includes at least one of mapping and demapping processing operations, where processing operation delays are not fixed.

In one possible implementation, the processing operation includes at least one of interleaving, mapping, and demapping.

In a second aspect, a clock recovery method is provided, which is applied to an access device in an OTN. The method comprises the following steps: acquiring an OTN frame; acquiring delay information in the OTN frame, where the delay information is used to indicate delay information of a processing operation specified on an OSU transmission path from an originating access device to the optical service unit of the access device, and the processing operation includes at least one of mapping and demapping; and recovering the OSU clock according to the time delay information.

Alternatively, the OTN frame may be an OSU frame or other OTN frame.

In the implementation manner, the access device can obtain the total time delay of the designated processing operation on the OSU transmission path and perform OSU clock recovery according to the total time delay, so that the influence of the PDV on the OSU transmission path can be reduced or avoided, and the clock recovery performance can be improved. On the other hand, according to the implementation manner, clock recovery is not required to be carried out on each OTN device, and clock recovery is only carried out on the access device, so that the resource cost of the OTN device can be reduced, and a larger number of service links can be supported.

In a possible implementation manner, the acquiring delay information in the OTN frame includes: and acquiring the time delay information from the overhead area of the OSU frame.

In a possible implementation manner, the acquiring an OTN frame includes: acquiring at least two OSU frames; the obtaining delay information in the OSU frame includes: obtaining at least one byte of the delay information from each of the at least two OSU frames; the delay information is obtained from at least one byte of the delay information obtained from each OSU frame.

In a possible implementation manner, the specified processing operation includes at least one of mapping and demapping processing operations, where processing operation delays are not fixed.

In one possible implementation, the processing operation further includes at least one of interleaving, mapping, and demapping.

In a third aspect, an apparatus is provided. The apparatus may include: a processor and an optical transceiver; the optical transceiver is configured to obtain a first OTN frame; the processor is configured to perform a processing operation on the first OTN frame, where the processing operation includes at least one of mapping and demapping; acquiring time delay information of a designated processing operation in the processing operation; and transmitting the time delay information to another OTN device through the transceiver unit.

In a fourth aspect, an apparatus is provided. The apparatus may include: a processor and an optical transceiver; the optical transceiver is used for acquiring an OTN frame; the processor is configured to obtain delay information in the OTN frame, where the delay information is used to indicate delay information of a processing operation specified on an OSU transfer path from an originating access device to the originating access device, and the processing operation includes at least one of mapping and demapping; and recovering the OSU clock according to the time delay information.

In a fifth aspect, an optical transport network system is provided. The system may include: at least one OTN device; the at least one OTN device is configured to perform the method according to any of the first aspects above.

In a possible implementation manner, the system further comprises an access device for performing the method according to any of the second aspects above.

In a sixth aspect, an apparatus is provided. The device comprises: one or more processors; wherein the instructions of the one or more computer programs, when executed by the one or more processors, cause the apparatus to perform the method of any of the first aspect above, or to perform the method of any of the second aspect above.

In a seventh aspect, a computer readable storage medium is provided. The computer readable storage medium comprises a computer program which, when run on a computing device, causes the computing device to perform the method of any one of the first aspects or to perform the method of any one of the second aspects.

In an eighth aspect, a chip is provided. The chip is coupled to a memory for reading and executing program instructions stored in the memory for implementing the method according to any of the first aspects or for implementing the method according to any of the second aspects.

In a ninth aspect, a computer program product is provided. The computer program product, when invoked by a computer, causes the computer to perform the method of any of the first aspects above, or to perform the method of any of the second aspects above.

Drawings

FIG. 1 is a schematic diagram of a system architecture to which embodiments of the present application are applicable;

FIG. 2 is a schematic diagram of an OTN device;

FIG. 3 is a schematic diagram of an OSU frame;

FIG. 4 is a schematic diagram of the end-to-end adaptive clock recovery of the CBR service provided in the related art;

FIG. 5 is a schematic diagram of the principle of end-to-end watermark adaptive clock recovery of CBR service provided in the related art;

fig. 6 is a schematic diagram of an OTN device on a transmission path from a sender to a receiver according to an embodiment of the present application;

Fig. 7 is a flow chart of a delay information transmission method according to an embodiment of the present application;

FIG. 8 is a schematic diagram of recording a first timestamp and a second timestamp according to an embodiment of the present application;

Fig. 9 is a schematic diagram of acquiring delay information based on a processing module for mapping/demapping according to an embodiment of the present application;

Fig. 10 is a schematic diagram of acquiring delay information based on a processing module for mapping/demapping and interleaving in an embodiment of the present application;

Fig. 11 is a schematic diagram of acquiring delay information based on a processing module for mapping/demapping and interleaving in an embodiment of the present application;

FIG. 12 is a schematic diagram of acquiring a delay and transmitting delay information over multiple OSU base frames according to an embodiment of the present application;

Fig. 13 is a schematic diagram of an end-to-end delay information transmission process from a sender to a receiver according to an embodiment of the present application;

FIG. 14 is a schematic diagram of a clock recovery process according to an embodiment of the present application;

FIG. 15 is a schematic view of a device according to an embodiment of the present application;

FIG. 16 is a schematic view of another device according to an embodiment of the present application;

Fig. 17 is a schematic structural diagram of yet another apparatus according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. The terminology used in the following examples is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification of the application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include, for example, "one or more" such forms of expression, unless the context clearly indicates to the contrary. It should also be understood that in embodiments of the present application, "one or more" means one, two, or more than two; "and/or", describes an association relationship of the association object, indicating that three relationships may exist; for example, a and/or B may represent: a alone, a and B together, and B alone, wherein A, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship.

Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

The plurality of the embodiments of the present application is greater than or equal to two. It should be noted that, in the description of the embodiments of the present application, the terms "first," "second," and the like are used for distinguishing between the descriptions and not necessarily for indicating or implying a relative importance, or alternatively, for indicating or implying a sequential order.

The technology related to the embodiment of the present application is first described below.

Clock recovery: clock information is embedded into a transmitted data stream by data encoding, and is acquired at a receiving end (receiving end) by clock recovery, so that a clock recovery circuit generates a clock signal according to the acquired clock information, the clock signal being synchronous with a clock signal associated with input data. The method of obtaining clock information from the transmitted data is called clock recovery or clock regeneration.

(II) OTN network architecture

Fig. 1 is a schematic diagram of a system architecture to which an embodiment of the present application is applicable. As shown in fig. 1, the system architecture includes an originating (also referred to as a source) device 101, an optical transport network 102, and a receiving device 103, where the originating device 101 and the receiving device 103 communicate through the Optical Transport Network (OTN) 102.

The optical transmission network 102 may include a plurality of transmission devices connected by optical fibers, such as the first transmission device 1021, the second transmission device 1022, the third transmission device 1023, and the fourth transmission device 1024 shown in fig. 1. For ease of illustration, a transmission device that communicates directly with the originating device 101 is referred to as an originating access device, e.g., the first transmission device 1021; a transmission device that directly communicates with the sink device 103 is referred to as a sink device, for example, a fourth transmission device 1024; the transmission devices between the originating access device and the access device are referred to as intermediate devices, e.g., the second transmission device 1022 and the third transmission device 1023.

The communication process between the transmitting device and the receiving device is as follows: the method comprises the steps that an originating terminal device sends a data frame to an originating terminal access device, after the originating terminal access device receives the data frame from the originating terminal device, the data frame is converted into an OTN frame, the OTN frame is transmitted to the originating terminal access device through an intermediate device, and the received OTN frame is converted into the data frame and is transmitted to a receiving terminal device by the originating terminal access device.

The transport devices in an OTN may also be referred to as OTN devices or OTN nodes or network devices. OTN devices in one OTN may be composed of different topology types such as linear, ring, and mesh according to specific needs.

(III) Structure of OTN device

One OTN device may have different functions. Generally, OTN devices are classified into optical layer devices, electrical layer devices, and opto-electronic hybrid devices. An optical layer device refers to a device capable of processing an optical layer signal, such as: an optical amplifier (optical amplifier, OA), an optical add-drop multiplexer (OADM). OA may also be referred to as Optical Line Amplifier (OLA), and is mainly used for amplifying an optical signal to support transmission over a longer distance while ensuring specific performance of the optical signal. OADM is used to spatially transform an optical signal so that it may be output from different output ports (sometimes also referred to as directions). An electrical layer device refers to a device capable of processing an electrical layer signal, such as: a device capable of processing OTN signals. An opto-electronic hybrid device refers to a device that has the capability to process both optical layer signals and electrical layer signals. Depending on the specific integration requirements, one OTN device may aggregate a variety of different functions. The technical scheme provided by the embodiment of the application can be suitable for OTN equipment with different forms and integration levels and containing the function of an electric layer.

Fig. 2 is a schematic diagram of one possible OTN device configuration. The OTN device herein may refer to the transmission device in fig. 1. As shown in fig. 2, the OTN device 200 includes a tributary board 201, a cross board 202, a circuit board 203, an optical layer processing board (not shown in the figure), and a system control and communication class board 204. The types and numbers of boards included in the network device may be different depending on the particular needs. For example, the network device as a core node does not have a tributary board 201. As another example, a network device that is an edge node has multiple tributary boards 201, or no optical cross boards 202. For another example, a network device that supports only electrical layer functions may not have an optical layer processing board.

The tributary board 201, the cross board 202 and the wiring board 203 are used for processing the electrical layer signals. The tributary board 201 is used to implement receiving and transmitting of various customer services, such as Synchronous Digital Hierarchy (SDH) service, packet service, ethernet service and/or forwarding service, etc. Still further, the tributary board 201 may be divided into a client side transceiver module and a signal processor. The client-side transceiver module may also be referred to as an optical transceiver, for receiving and/or transmitting traffic data. The signal processor is used for realizing the mapping and demapping processing of the business data to the data frame. The cross board 202 is used to implement exchange of data frames, and exchange of one or more types of data frames is completed. The line board 203 mainly realizes processing of line-side data frames. Specifically, the wiring board 203 may be divided into a line-side optical module and a signal processor. The line-side optical module may be referred to as an optical transceiver, for receiving and/or transmitting data frames. The signal processor is used for multiplexing and demultiplexing data frames at the line side or mapping and demapping processing. The system control and communication class board 204 is used to implement system control. Specifically, information may be collected from different boards, or control instructions may be sent to corresponding boards.

It is to be understood that the specific components (e.g., signal processor) may be one or more, and that the embodiments of the application are not limited, unless specifically indicated. The embodiment of the application does not limit any limitation on the type of the single board contained in the device and the functional design and the number of the single boards. In a specific implementation, the two boards may also be designed as one board. In addition, the OTN device may further include a backup power supply, a fan for heat dissipation, and the like.

(IV) OTN frame

The OTN frame is a data frame, which is used for carrying various service data and providing rich management and monitoring functions.

The OTN frame may be an OSU frame, an optical data unit frame (Optical Data Unit k, ODUk), ODUCn, ODUflex, or an optical channel transmission unit k (optical transport unit k, OTUk), an OTUCn, or a flexible OTN (FlexO) frame, or the like. The ODU frame is different from the OTU frame in that the OTU frame includes an ODU frame and an OTU overhead. k represents different rate levels, e.g., k=1 represents 2.5Gbps and k=4 represents 100Gbps; cn represents a variable rate, in particular a rate that is a positive integer multiple of 100 Gbps. Unless specifically stated, an ODU frame refers to any one of ODUk, ODUCn, or ODUflex, and an OTU frame refers to any one of OTUk, OTUCn, or FlexO. It should also be noted that with the development of optical transport network technology, new types of OTN frames may be defined, and the method is also applicable to the embodiments of the present application. In addition, the method disclosed by the embodiment of the application can be also applied to FlexE frames and other optical transmission network frames.

OSU frames consist of an integer number of bytes or bits. Fig. 3 illustrates one possible structure of an OSU frame. As shown in fig. 3, the OSU frame contains an overhead region and a payload region. The overhead region may carry overhead (or header), which may include, but is not limited to, at least one of: traffic frame header indication, path trace indication (TRAIL TRACE IDENTIFIER, TTI), X-Bit interleaved parity BIP-X (X Bit-INTERLEAVED PARITY, BIP-X), backward error indication (backward error indication, BEI), backward defect indication (backward defect indication, BDI), status indication (Status, STAT), time stamp, sequence identification and mapping overhead, etc. The payload area is used to carry traffic data. Illustratively, the OSU frame may be 8 bytes (8B), 16B,32B,64B,128B,196B,256B, 512B, or the like, which is not limited by the embodiments of the present application.

Multiple OSU frames may constitute one multiframe. For example, 64 base frames may be included in a multiframe, where the base frames are OSU frames. The embodiment of the application does not limit the quantity of the base frames contained in one multiframe. It is understood that an OSU frame may also be expressed as an OSU and an ODU frame may also be expressed as an ODU. An OSU in this context may also be understood as an OSU frame, and an ODU may also be understood as an ODU frame.

The ITU-T defined adaptive clock recovery (CES ACR) scheme based on circuit emulation service (circuit emulation service, CES) is a method for recovering the end-to-end clock of CBR service, as shown in fig. 4, and the technical principle is that a receiving device uses the size of a buffer waterline of received CBR service data as an input of a clock recovery circuit, or uses a received CBR service data packet timestamp as an input of the clock recovery circuit, and recovers the CBR clock after jitter filtering.

Fig. 5 illustrates the principle of recovering CBR clocks from a cache pipeline in CES ACR scheme. As shown in fig. 5, after a CBR service data packet (a box marked with a letter D in the figure) sent by an originating device passes through an OTN network, a delay change occurs in the data packet, after a receiving device writes data into a buffer, a clock recovery circuit generates a read clock for reading the buffer data according to the change of a buffer waterline, reads the data in the buffer based on the read clock, and recovers CBR service data with a fixed bit rate again. The jitter size of the cache line can affect the performance of read clock recovery.

The principle of recovering the CBR clock according to the time stamp in CES ACR scheme is: the originating device makes a time stamp t1 for the CBR service data packet, and makes a time stamp t2 after reaching the receiving device; the sender device makes a time stamp t1 'for the next CBR service data packet, makes a time stamp t2' after reaching the receiver device, and so on, then the following can be obtained:

Δ＝t2-t1

Δ’＝t2’-t1’

The change of delta and delta 'can reflect the speed of the CBR clocks of the transmitting end and the receiving end, and if delta is larger than delta', the CBR clock of the receiving end is slower and needs to be regulated; if delta < delta', the CBR clock of the receiving end is faster, the CBR clock needs to be slowed down, and the tracking recovery of the CBR clocks of the receiving end and the transmitting end can be completed according to the principle.

The clock recovery method provided by the CES ACR scheme is greatly influenced by the packet delay variation (PACKET DELAY variation, PDV) of the OTN network, and the delay jitter of the CBR service data passing through the OTN network directly influences the buffer watermark jitter or the stamping jitter of the receiving end, thereby influencing the CBR clock recovery performance.

For the clock cascade application scenario of the SDH network at the two ends of the OTN network, the CES ACR scheme is used for SDH clock recovery, and the SDH clock recovery performance cannot meet the requirement of SDH service.

The embodiment of the application provides a time delay information transmission method, a clock recovery method, a device and a system, which can be applied to an optical transmission network. In the embodiment of the application, the time delay of the OSU processing operation on the OSU transmission path can be gradually accumulated and transmitted to the access equipment, and the access equipment can recover the OSU clock according to the time delay of the OSU processing operation on the OSU transmission path, so that the CBR service clock can be recovered based on the OSU clock, the clock recovery performance can be improved, and further, excessive resource expenditure can be avoided.

Here, the "OSU processing operation" may also be expressed as "processing operation performed on OSU frames" or simply as "processing operation". Embodiments of the present application will be described in detail below with reference to the accompanying drawings.

After OSU framing, the delay created within the OTN system may include the following:

Δa: the delay resulting from the mapping/demapping operations associated with OSU frames;

Δb: delay resulting from OSU frame crossing operations;

Δc: delay time generated by the ODU interleaving operation;

Δd: the time delay of the mapping/demapping operation parameters associated with the ODU frame.

Of these, Δa and Δb are large, and if Δa and Δb are not fixed, the clock recovery performance is greatly affected. Because of the hard pipe nature of the ODU itself, Δc and Δd are small, and therefore even though Δc and Δd are not fixed, their impact on clock recovery performance is negligible. Therefore, for the processing operation of the OSU layer in the OSU transmission path, the embodiment of the application needs to determine the time delay and transmit the time delay information to the downstream equipment so that the access equipment can perform OSU clock recovery according to the time delay of the OSU processing operation on the OSU transmission path.

Optionally, the OSU processing operation may include: at least one of mapping and demapping.

By way of example, the mapping may include one or more of the following operations: CBR data frames are mapped to OSU frames and OSU frames are mapped to other OTN frames (such as OSTU frames or ODU frames).

Illustratively, the demapping may include one or more of the following operations: the OSU frames are demapped to CBR data frames and other OTN frames (such as OSTU frames or ODU frames) are demapped to OSU frames.

Optionally, the OSU processing operation may also include interleaving. Alternatively, the interleaving operation may be combined with at least one of mapping and demapping. An example of one combination of interleaving and mapping operations is: firstly, crossing the OSU frames, and then mapping the crossed OSU frames into ODU frames or OSTU frames; one example of a combination of interleaving and demapping operations is: the method comprises the steps of firstly demapping an ODU frame or an OSTU frame into an OSU frame, intersecting the OSU frame, and mapping the intersected OSU frame into an ODU frame OSTU frame.

It will be appreciated that the above is merely exemplary of a few OSU processing operations, and embodiments of the present application are not limited in this respect.

In one possible implementation, given that the latency of one or some OSU processing operations may be relatively fixed, its impact on clock performance may be negligible, and the latency of one or more OSU processing operations may not be fixed, so that its latency may be determined for the OSU processing operations whose latency is not fixed and passed on to downstream devices, and may not be required for OSU processing operations whose latency is relatively fixed.

For example, one or more OSU processing operations with possibly unfixed time delay may be pre-designated, and when the OTN device needs to perform the designated OSU processing operation, the method provided by the embodiment of the present application may be used to determine the time delay of the OSU processing operation, and transfer the time delay to the downstream device.

The delay information transmission method provided by the embodiment of the application can be executed by OTN equipment in an OTN network. The OTN device may be a device for performing OSU processing operations in an OTN network, and may include, for example, the following devices:

1) An OTN device for performing an OSU frame crossing operation, the OTN device may include a cross board as shown in fig. 2, the cross board may perform an OSU frame crossing processing operation;

2) An OTN device for performing OSU frame mapping/demapping operations, the OTN device may include a circuit board as shown in fig. 2, and the circuit board may perform OSU frame mapping/demapping processing operations;

3) An OTN device for performing OSU interleaving and OSU mapping/demapping operations may include an interleaving board and a wiring board as shown in fig. 2.

Alternatively, if an OSU processing operation is specified in advance, for example, the specified OSU processing operation includes mapping, the OTN performing the flow shown in fig. 7 is an OTN device capable of performing the mapping processing operation, for example, the OTN device may be the OTN device described in 2) above or the OTN device described in 3) above.

Taking the example of the specified OSU operation including the mapping operation of OSU frames to ODU frames and OSU interleaving, fig. 6 schematically illustrates OTN devices on a transmission path from a sender to a receiver. As shown in fig. 6, the OSU transmission path from the transmitting end to the receiving end includes 6 OTN devices, such as OTN device 1 to OTN device 6 in fig. 6. The processing operations in the dashed boxes in the OTN device 1, the OTN device 2 and the OTN device 4 are designated processing operations, so that the OTN devices acquire the delay information by adopting the method provided by the embodiment of the present application for the processing operations in the dashed boxes. The processing operations performed by the OTN device 2 and the OTN device 4 include an ODU-to-OSU demapping operation, an OSU interleaving operation, and an OSU-to-ODU mapping operation, where only for the OSU interleaving operation and the OSU-to-ODU mapping operation, the time delays of the two operations need to be determined. The OTN device 3 may pass through the delay information from the OTN device 2 to the OTN device 4, and similarly, the OTN device 5 may pass through the delay information from the OTN device 4 to the OTN device 6.

Referring to fig. 7, a flow chart of a delay information transmission method according to an embodiment of the present application is shown. The flow may be performed by an OTN device, which may be a device for performing OSU processing operations, alternatively, a device for performing specified OSU processing operations, such as the OTN device may be the OTN device 1, 2, 4 as shown in fig. 6.

As shown in fig. 7, the process may include the steps of:

s701: the OTN device acquires a first OTN frame.

The OTN frames may include ODU frames, OSU frames, etc. data frames that may be transmitted in the OTN network.

Taking the first OTN frame as the first OSU frame as an example, in one possible implementation manner, when the OTN device is an originating access device, the step of obtaining, by the OTN device, the first OSU frame may include: the originating access device receives a CBR data frame from the originating device and maps the CBR data frame to a first OSU frame.

Taking the first OTN frame as the first OSU frame as an example, in another possible implementation manner, when the OTN device is an intermediate device, such as the second transmission device or the third transmission device in fig. 1, the step of acquiring the first OSU frame by the intermediate device may include: the intermediate device receives an ODU frame from its upstream OTN device and demaps the ODU frame into a corresponding first OSU frame. An example of this implementation may be referred to OTN device 2 in fig. 6, where OTN device 2 demaps the received ODU frame to obtain a corresponding OSU frame. Of course, other types of OTN frames may be received by the OTN device, and the OTN device may convert the OTN frame into a corresponding OSU frame through demapping or demultiplexing or other operations, or obtain the corresponding OSU frame based on the OTN frame, which is not limited in the embodiment of the present application.

S702: the OTN device performs a processing operation on the first OTN frame, the processing operation including at least one of mapping and demapping.

Possible processing operations performed by the OTN device on the first OTN frame may be referred to in the foregoing description, and one possible example may be referred to the processing operations performed by the OTN devices 1, 2, 4 in fig. 6.

S703: the OTN equipment acquires the time delay information of the processing operation appointed in the processing operation.

Alternatively, the processing operation performed by the OTN device may include a plurality of processing operations, but only a part of the plurality of processing operations is a specified processing operation, in which case the OTN device determines its delay only for the specified processing operation. For example, the processing operation performed by the OTN device includes an OSU cross operation and mapping an OSU frame to an ODU frame, where the OSU cross operation is a designated processing operation, and the OTN device only determines a delay of the OSU cross operation, that is, obtains delay information of the processing operation.

In a possible implementation manner, taking a first OTN frame as an example of a first OSU frame, after the OTN device acquires the first OSU, the OTN device records a first timestamp and a second timestamp, where the first timestamp is used to indicate a start time of performing a specified processing operation, and the second timestamp is used to indicate an end time of performing the specified processing operation. In this way, the time delay information of the specified processing operation can be determined based on the first time stamp and the second time stamp.

Illustratively, recording the first timestamp and the second timestamp may be accomplished by: as shown in fig. 8, when an OSU frame is input to the processing module, the count value Ts1 of the current time of the counter is recorded, and when the processing module processes the OSU frame and outputs a processing result (such as an OSU frame after crossing or an ODU frame after mapping), the count value Ts2 of the counter or a counter synchronized with the counter at the current time is recorded. Similarly, the implementation of recording the first timestamp and the second timestamp may also be: when an ODU frame (or other OTN frame) is input to the processing module, a count value Ts1 of a current time of the counter is recorded, and when the processing module processes the ODU frame and outputs a processing result (for example, an OSU frame obtained by demapping or an OSU frame obtained by performing OSU cross operation after demapping the OSU frame), a count value Ts2 of the counter or a counter synchronized with the counter at the current time is recorded.

Since the counter may count at a fixed time interval, the count value Ts1 may be used as the first timestamp, the count value Ts2 may be used as the second timestamp, and the processing operation delay of the processing module may be obtained according to the difference obtained by subtracting the count value Ts1 from the count value Ts2, where the processing operation delay may be expressed as:

Δdelay＝Ts1-Ts2

Alternatively, the counter may be replaced by a timer. Illustratively, when an OSU frame is input to the processing module, a time value Ts1 of the current time of the timer is recorded, and when an OSU frame is output from the processing module, a time value Ts2 of the timer or a timer synchronized with the timer at the current time is recorded. The time value Ts1 is the first time stamp, and the time value Ts2 is the second time stamp.

The processing module is a generic term for a module or unit or component within the OTN device that is capable of performing OSU processing operations. The processing module may be a software module, a hardware module, or a module based on a software and hardware implementation. Alternatively, the processing module may be a module capable of implementing a specified processing operation. By way of example, the following figures 9, 10 and 11 illustrate the processing functions comprised by several processing modules, respectively. It will be appreciated that fig. 9, 10 and 11 are only a few examples of processing modules, and embodiments of the present application do not limit the processing operations that can be performed by the processing modules.

As shown in fig. 9, the processing module may be configured to perform mapping from OSU frame to ODU frame and demapping from ODU frame to OSU frame. When the OSU frame enters the processing module, the current count value Ts1 of the counter is recorded, and when the processing module outputs the mapped ODU frame, the current count value Ts2 of the counter is recorded. The timing unit may calculate the time delay Δdelay of the above processing operation from the count value Ts1 and the count value Ts2. A possible example may be exemplified by the processing functions identified by the dashed boxes in the OTN device 1 in fig. 6. Similarly, the ODU frame-to-OSU frame demapping process is similar to the flow described above and will not be described in detail herein.

As shown in fig. 10, the processing module may be configured to perform mapping from ODU frame to OSU frame, interleaving of OSU frame, and mapping from OSU frame to ODU frame. When the demultiplexed ODU frame enters a processing module, recording the current count value Ts1 of the counter; the processing module demaps the ODU frame into an OSU frame, executes OSU frame cross processing operation, and maps the cross processed OSU frame into an ODU frame; when the processing module outputs the mapped ODU frame, the current count value Ts2 of the counter is recorded. Further, the mapped ODU frame may be multiplexed. The timing unit may calculate the time delay Δdelay of the above processing operation from the count value Ts1 and the count value Ts2.

As shown in fig. 11, the processing module may be configured to perform OSU interleaving and mapping/demapping between OSU frames and ODU frames. When the OSU frame enters the processing module, recording the current count value Ts1 of the counter; the processing module performs OSU crossing, and maps the OSU after crossing processing into an ODU frame; when the processing module outputs the mapped ODU frame, the current count value Ts2 of the counter is recorded. The timing unit may calculate the time delay Δdelay of the above processing operation from the count value Ts1 and the count value Ts2. One possible example may be as exemplified by the processing functions identified by the dashed boxes in the OTN device 4 in fig. 6. Similarly, when the ODU frame enters the processing module, recording a current count value Ts1 of the counter; the processing module demaps the ODU frame into an OSU frame and then performs OSU crossing; when the processing module outputs the crossed OSU frame, the current count value Ts2 of the counter is recorded. The timing unit may calculate the time delay Δdelay of the above processing operation from the count value Ts1 and the count value Ts2.

S704: the OTN device sends the time delay information to another OTN device.

The other OTN device is a device connected to the OTN device, and is a next-hop device of the OTN device.

In one possible implementation, the delay information may be carried in an overhead region of the OSU frame. The implementation manner of the OTN device sending the time delay information to another OTN device is as follows: and sending the delay information to the other OTN equipment through an overhead area of the OSU frame.

The overhead area of the OSU frame includes a timestamp field, which may be used by embodiments of the present application to transmit the delay information. Alternatively, the time value corresponding to the delay information may be added to the value of the timestamp field in the overhead area of the OSU frame, and the value of the timestamp field may be replaced with the added value. Illustratively, the value in the timestamp field in the overhead area of the OSU frame is TS, and the delay Δdelay corresponding to the delay information may be added to the TS to obtain the TS ', and the added value TS' is used to replace the value TS in the timestamp field in the overhead area of the OSU frame. Of course, other manners may be used to transfer the delay information to another OTN device, which is not limited by the embodiment of the present application.

In one possible implementation, the delay information may be sent to another OTN device through one OSU frame.

In one possible implementation manner of transmitting delay information through one OSU frame, the OTN device may send the delay information to another OTN device through the first OSU frame. Based on the implementation, the OSU frame for acquiring the processing operation delay information and the OSU frame for transmitting the delay information are the same frame.

Optionally, the time value corresponding to the delay information occupies at least two bytes, for example, the bit width of the delay information Δdelay is 2 ¹⁶ =65.536 us, or 2 ²⁴ =16.7 ms; according to the above calculation, at least 2 bytes are required. The timestamp field (or information field) used for carrying the delay information occupies a plurality of bytes in the overhead area of the OSU frame used for transmitting the delay information, and the number of the bytes is not less than the number of the bytes occupied by the delay information. In this way, the delay information may be carried in the timestamp field in the OSU overhead area.

In a possible implementation manner, taking an example that N (N is an integer greater than 1) OSU frames form a multiframe, for each base frame (OSU frame) in the multiframe, the OTN device may acquire delay information of a specified processing operation in the foregoing manner, and transmit the delay information to a downstream device through the same base frame.

In another possible implementation manner, taking still that N (N is an integer greater than 1) OSU frames form a multiframe as an example, for a base frame agreed in the multiframe, or for each base frame in a plurality of base frames agreed in the multiframe, the OTN device may acquire delay information of a specified processing operation in the above manner, and transmit the delay information to the downstream device through the same base frame.

Based on the above scheme that the OSU frame used for acquiring the processing operation delay information and the OSU frame used for transmitting the delay information are the same frame, in one possible implementation manner, after the OTN device records the first timestamp, the value of a timestamp field in an overhead area of the OSU frame is updated based on the first timestamp, for example, the original value of the field is TS, the updated value is TS ', TS' =ts-TS 1, where TS1 is the value of the first timestamp; after the second timestamp is recorded, the value of the timestamp field in the overhead region of the OSU frame is updated again based on the second timestamp, e.g., the updated value is TS ", TS" =ts' +ts2, where TS2 is the value of the second timestamp. In this way, delay information (Δdelay=ts2-Ts 1) can be accumulated into the timestamp field in the overhead region of the OSU frame and passed to downstream devices.

In one possible implementation manner of transmitting delay information through one OSU frame, the OTN device may send the delay information to the other OTN device through a second OSU frame, where the second OSU frame is located after the first OSU frame. Based on this implementation, the OSU frame used to obtain the processing operation delay information and the OSU frame used to communicate the delay information are not the same frame.

Alternatively, taking an example that N (N is an integer greater than 1) OSU frames form a multiframe, it may be agreed that delay information of a specified processing operation is obtained based on the kth base frame, and the delay information is transmitted using the kth+n base frame. Wherein K and N are positive integers, and K+n is less than or equal to N. For example, it may be agreed that delay information for a specified processing operation is obtained based on the kth base frame, and the delay information is transmitted using the kth+1th base frame. For another example, it may be agreed that delay information for a specified processing operation is obtained based on the 1 st base frame, and the delay information is transmitted using the nth base frame (e.g., the 5 th base frame).

Alternatively, the delay information may be sent to the other OTN device by at least two bytes in the second OSU frame. The time value corresponding to the delay information may occupy at least two bytes. The timestamp field (or information field) used for carrying the delay information occupies a plurality of bytes in the overhead area of the OSU frame used for transmitting the delay information, and the number of bytes is not less than the maximum number of bytes occupied by the delay information. In this way, the delay information may be carried in the timestamp field in the OSU overhead area.

In a possible implementation manner, in S704, the OTN device may send the delay information to another OTN device through at least two OSU frames. Optionally, the at least two OSU frames are located after the first OSU frame. Optionally, the at least two OUS frames include at least the first OSU frame, and other OSU frames of the at least two OSU frames are located after the first OUS frame.

Optionally, taking an example that N (N is an integer greater than 1) OSU frames form a multiframe, it may be agreed that delay information of a specified processing operation is obtained based on a kth base frame, and the delay information is transmitted using a plurality of base frames such as a kth+n base frame, a kth+n+1, a kth+n+2 base frame, and the like. Wherein K and n are positive integers. Illustratively, it may be agreed that the delay information for the specified processing operation is obtained based on the 1 st base frame, and is transmitted using the 2 nd, 3 rd, 4 th, and 5 th base frames.

Optionally, in the plurality of OSU frames for transmitting the delay information, each OSU frame includes at least one byte of the delay information. Based on the above implementation, all bytes of the delay information may be transferred to the downstream device through multiple OSU frames, and each OSU frame transmits only a portion of the bytes of the delay information.

The number of base frames used to transmit the delay information may be determined based on the number of bytes occupied by the delay information and the number of bytes occupied by the timestamp field in the overhead area of one base frame. For example, in the case where the timestamp field in the overhead area of each OSU frame occupies 1 byte, if the delay information Δdelay occupies 2 bytes, 2 OSU frames are required to transmit the delay information, and if the delay information Δdelay occupies 4 bytes, 4 OSU frames are required to transmit the delay information.

In one possible implementation, the low-bit bytes of delay information are sent first. Alternatively, the plurality of bytes of the delay information may be sequentially transmitted in order from low to high.

Taking an example that the OSU frame for transmitting the delay information includes a third OSU frame and a fourth OSU frame, the OTN device may send the low-bit byte of the delay information to another OTN device through the overhead area of the third OSU frame, and then send the low-bit byte of the delay information to the another OTN device through the overhead area of the fourth OSU frame.

By way of example, taking an OSU multiframe of N (N is an integer greater than 1) OSU base frames as an example, fig. 12 shows a schematic diagram of delay acquisition and transmission over multiple OSU base frames. As shown in fig. 12, when the fixed frame header of the 1 st base frame is at the entrance of the processing module, the current count value Ts1 of the counter is recorded, and when the fixed frame header of the 1 st base frame is at the exit of the processing module, the count value Ts2 of the counter is recorded, the timer unit calculates Δdelay=ts2-Ts 1, the Δdelay includes 4 bytes, and from the low bit to the high bit, the Δdelay_l, Δdelay_m1, Δdelay_m2, and Δdelay_h are respectively:

adding Δdelay_l to the overhead area of the kth base frame, the timestamp field in the overhead area updated with a value of ts_l', i.e.:

ts_l' =ts_l+Δdelay_l, where ts_l is the value of the timestamp field before update;

Adding Δdelay_m1 to the overhead region of the k+1th base frame, where the timestamp field is updated to a value of ts_m1', i.e.:

ts_m1' =ts_m1+Δdelay_m1, where ts_m1 is the value of the timestamp field before update;

if a carry is generated when calculating ts_l ', the carry may be added to the timestamp field of the overhead region of the k+1th base frame, i.e., ts_m1' =ts_m1+Δdelay_m1+1;

Adding Δdelay_m2 to the overhead area of the k+2th base frame, the timestamp field in the overhead area updated with a value of ts_m2', namely:

ts_m2' =ts_m2+Δdelay_m2, where ts_m2 is the value of the timestamp field before update;

Adding Δdelay_h to the overhead area of the k+3 base frame, the timestamp field in the overhead area updated with a value of ts_h', i.e.:

Ts_h' =ts_h+Δdelay_h, where ts_h is the value of the timestamp field before update.

Thus, 4 bytes of Δdelay are passed to downstream devices through consecutive K-th, k+1-th, k+2-th, and k+3-th base frames.

It will be appreciated that the above description is given by taking the example of using a plurality of bytes of transmission delay information of a plurality of consecutive base frames, and that a plurality of bytes of transmission delay information may also be obtained using a plurality of discontinuous base frames, which is not limited in this embodiment of the present application.

Based on the flow shown in fig. 7, in conjunction with the OTN device on the OSU transmission path shown in fig. 6, taking time delay information acquisition based on a certain OSU frame and using the OSU frame to transmit the time delay information, as shown in fig. 13, the time delay information transmission process from the sender to the end may include:

After the OTN device 1, the cbr data frame is mapped into an OSU frame, the OSU frame records a first time Ts1 _OTN1 when entering a processing module (such as a module identified by a dashed box in the OTN device 1) for performing OSU interleaving, and records a second time stamp Ts2 _OTN1 when output from the processing module, and the timing unit calculates Δdelay ₁:

Δdelay₁＝Ts2_OTN1-Ts1_OTN1；

The delay correction unit updates the timestamp TS1 in the overhead of the OSU frame to TS1' according to Δdelay ₁:

TS1′＝TS1+Δdelay₁。

After the OTN device 2 demaps the ODU frame into an OSU frame, the OSU frame records a first time Ts1 _OTN2 when entering a processing module (such as a module identified by a dashed box in the OTN device 2) for performing the OSU frame-to-ODU frame mapping, and records a second time stamp Ts2 _OTN2 when output from the processing module, and the timing unit calculates Δdelay ₂:

Δdelay₂＝Ts2_OTN2-Ts1_OTN2；

The delay correction unit updates the timestamp TS1 'in the overhead of the OSU frame to TS2' according to the Deltadelay ₂:

TS2′＝TS1′+Δdelay₂＝TS1+Δdelay₁+Δdelay₂。

After the OTN device 4 demaps the ODU frame into an OSU frame, the OSU frame records a first time Ts1 _OTN4 when entering a processing module (such as a module identified by a dashed box in the OTN device 4) for performing OSU interleaving and OSU-to-ODU mapping, and records a second time stamp Ts2 _OTN4 when output from the processing module, and the timing unit calculates Δdelay ₃:

Δdelay₃＝Ts2_OTN4-Ts1_OTN4；

the delay correction unit updates the timestamp TS2 'in the overhead of the OSU frame to TS3' according to Δdelay ₃:

TS3′＝TS2′+Δdelay₃＝TS1+Δdelay₁+Δdelay₂+Δdelay₃。

the time stamps in the overhead area of the OSN frame are transmitted at the OTN devices 3, 5, so that the delay in the relevant device on the OSN transmission path is transmitted to the receiving access device (OTN device 6), and the OTN device 6 can perform OSU clock recovery according to the delay.

In the above description, taking the case that 3 OTN devices perform delay computation and delay transmission on an OSU transmission path as an example, the embodiment of the application can achieve end-to-end delay information acquisition and clock recovery based on the delay information under the scene that more or fewer OTN devices perform delay computation and delay transmission. For example, n OTN devices on the OSU transmission path perform delay calculation and delay transmission, after n delay accumulation, relative to the original timestamp field value TS in the overhead area of the OSU frame, the timestamp field values TS of Δdelay1 and Δdelay2 … … Δdelay n are accumulated in the overhead area of the OSU frame, that is, after n accumulation, the value of the field is ts+Δdelay1+Δdelay2+ … … +Δdelay n.

Based on the embodiment of the application, the end-to-end delay error can meet the requirement of CBR service on the clock recovery performance. An authentication procedure is given below by way of example. Normally, a processing module in an OTN device performs specified processing operation, the working clock frequency offset of a local counter is 4.6ppm, the clock precision of the counter is 1G clock, the error is +/-1ns, the inherent Delay of the processing module is Delay, and then the correction error of recording a first timestamp and a second timestamp based on the counter is:

Delta = 4.6ppm x delay +1ns x 2 (error of recording first timestamp at ingress + error of recording second timestamp at egress);

according to the example that the OSU network end-to-end has 20 OTN devices, the maximum delay error from end to end is:

ΣΔ＝Σ4.6PPM*Delay+2ns*20

because of the low latency characteristics of OSU networks, the end-to-end latency is typically less than 1ms, and the above error translates into:

ΣΔ＝4.6PPM*1ms+2ns*20＝4.6ns+40ns＝46.6ns

Due to the characteristics of the hard pipeline, the jitter of the ODU cross and the high-low order mapping of the ODU is small, and after the tail end (receiving end) is subjected to proper clock loop filtering, the error of the tail end (receiving end) can meet the requirement on clock recovery performance in a CBR over OSU scene.

Based on the above procedure, one transmission device may transfer the delay information of the OSU processing operation performed therein to the next transmission device. If the next transmission device needs to acquire the time delay of the OSU processing operation, the time delay of the OSU processing operation can be acquired according to the flow, and accumulated to an OSU frame to be continuously transmitted to the downstream device; the next transmitting device may transparently transmit the delay information in the OSU frame if it is not required to acquire the delay of the OSU processing operation. In this way, the access device can obtain the time delay information of the end-to-end OSU processing operation on the OSU transmission path, and can perform OSU clock recovery according to the time delay information from end to end.

On the one hand, compared with the related art shown in fig. 4 and fig. 5, in the embodiment of the present application, because the access device for performing OSU clock recovery can obtain the total time delay of OSU processing operation on the OSU transmission path, and perform clock recovery according to the time delay, the influence of PDV on the OSU transmission path can be reduced or avoided, so that the clock recovery performance can be improved, and further the requirements of STM service or other CBR service application scenarios on clock performance can be satisfied, and the requirements of clock cascading application scenarios on clock performance can be supported.

On the other hand, the above flow of the embodiment of the present application does not need to perform clock recovery at each OTN device, and only performs clock recovery at the access device, so that the resource overhead of the OTN device can be reduced, so that the number of CBR service links is not limited, and under the low-speed CBR over OSU application scenario, multiple super-multiple low-speed CBR applications can be supported, thereby meeting the requirements of super-multiple E1 or other low-speed CBR scenario applications.

Fig. 14 is a schematic flow chart of clock recovery provided for an embodiment of the present application, where the flow may be performed by an access device in an OTN network. As shown in fig. 14, the process may include the steps of:

s1401: and acquiring the OTN frame.

Optionally, the OTN frame may be an OSU frame, an ODU frame, or an OTN frame.

The OTN frame includes delay information, where the delay information is used to indicate delay information of a designated processing operation on an OSU transfer path from an originating access device to the terminating access device.

The method for acquiring the delay information and the method for transmitting the delay information can be referred to the foregoing embodiments, and are not repeated here.

Optionally, the processing operation includes at least one of mapping and demapping. Further, the cross-over may also be included, or at least one of mapping, demapping, and cross-over.

Optionally, the specified processing operation includes at least one processing operation of interleaving, mapping, and demapping, where the processing operation is not delayed by a fixed processing operation time.

The specific meaning of the specified processing operations can be found in the previous embodiments and will not be repeated here.

S1402: and acquiring delay information in the OTN frame.

Optionally, the delay information is carried in an overhead area of the OSU frame, and the access device may acquire the delay information from the overhead area of the OSU frame.

Optionally, taking the OTN frame as an OSU frame as an example, different bytes of transmission delay information of multiple OSU frames may be used, where in this case, in S1401, the access device receives at least two OSU frames; at S1402, the access device may obtain at least one byte of the delay information from each OSU frame of the at least two OSU frames, and obtain the delay information based on the at least one byte of the delay information obtained from each OSU frame.

S1403: and recovering the OSU clock according to the acquired time delay information.

Alternatively, the value of the timestamp field in the overhead area of the OSU frame received by the access device may be expressed as: TS+Δdelay1+Δdelay2+ … … +Δdelay n. The TS may be an initial value of the timestamp field, for example, a value of the field when the data frame enters the OTN network, a value of the timestamp field in the data frame received by the originating access device, and Δdelay1+Δdelay2+ … … +Δdelay n represents a sum of delays added to the timestamp field by the OTN device in the OSU transmission path. The originating access device may obtain the initial value TS of this field, and thus may obtain the sum of the delays accumulated by the OTN devices in the OSU delivery path onto this timestamp field based on the value of this timestamp field in the overhead area of the received OSU frame.

Based on the same technical concept, the embodiment of the application also provides a device, which can realize the functions realized by the OTN equipment in the embodiment. As shown in fig. 15, the apparatus 1500 may include a processing unit 1501 and a transceiving unit 1502.

A transceiver unit 1502, configured to obtain a first OTN frame; a processing unit 1501, configured to perform a processing operation on the first OTN frame, where the processing operation includes at least one of mapping and demapping; acquiring time delay information of a designated processing operation in the processing operation; and transmitting the time delay information to another OTN device through the transceiver unit.

Optionally, the processing unit 1501 is specifically configured to: the delay information is sent to the other OTN device through the transceiver unit 1502 through the overhead area of the OSU frame of the optical service unit.

Optionally, the processing unit 1501 is specifically configured to: the delay information is sent to the other OTN device through one OSU frame by the transceiver unit 1502.

Optionally, the first OTN frame is a first OSU frame, and the processing unit 1501 is specifically configured to: and sending the time delay information to the other OTN equipment through the first OSU frame.

Optionally, the first OTN frame is a first OSU frame, and the processing unit 1501 is specifically configured to: and sending the delay information to the other OTN device through a second OSU frame, wherein the second OSU frame is positioned after the first OSU frame.

Optionally, the processing unit 1501 is specifically configured to: the delay information is sent to the other OTN device by the transceiver unit 1502 through at least two bytes in the second OSU frame.

Optionally, the first OTN frame is a first OSU frame, and the processing unit 1501 is specifically configured to: the delay information is sent to the other OTN device through at least two OSU frames by the transceiver unit 1502, where the at least two OSU frames are located after the first OSU frame or the at least two OSU frames include the first OSU frame.

Optionally, each of the at least two OSU frames includes at least one byte of the delay information.

Optionally, the processing unit 1501 is specifically configured to: transmitting the low-bit byte of the delay information to the other OTN device through the third OSU frame; and transmitting the high-bit byte of the time delay information to the other OTN device through the fourth OSU frame.

Optionally, the processing unit 1501 is further configured to: and accumulating the time value corresponding to the time delay information to the value of the time stamp field in the overhead area of the OSU frame.

Optionally, the specified processing operation includes at least one of mapping and demapping processing operations, where processing operation latency is not fixed.

Optionally, the processing operation further comprises interleaving, or at least one of mapping and demapping and interleaving.

It can be understood that the above device provided in the embodiment of the present application can implement all the method steps implemented by the corresponding devices in the method embodiment, and can achieve the same technical effects, and detailed descriptions of the same parts and beneficial effects as those in the method embodiment in this embodiment are omitted.

Based on the same technical concept, the embodiment of the application also provides a device which can realize the functions realized by the access equipment in the embodiment. As shown in fig. 16, the apparatus 1600 may include a processing unit 1601 and a transceiver unit 1602.

A transceiver unit 1602, configured to obtain an OTN frame; a processing unit 1601, configured to obtain delay information in the OTN frame, where the delay information is used to indicate delay information of a processing operation specified on an OSU transfer path from an originating access device to the access device, where the processing operation includes at least one of mapping and demapping; and recovering the OSU clock according to the time delay information.

Optionally, the OTN frame is an OSU frame, and the processing unit 1601 is specifically configured to: and acquiring the time delay information from the overhead area of the OSU frame.

Optionally, the OTN frame is an OSU frame; the processing unit 1601 specifically is configured to: acquiring at least two OSU frames; obtaining at least one byte of the delay information from each of the at least two OSU frames; the delay information is obtained from at least one byte of the delay information obtained from each OSU frame.

Optionally, the specified processing operation includes at least one of mapping and demapping processing operations, where processing operation latency is not fixed.

Optionally, the processing operation further comprises interleaving, or at least one of mapping and demapping and interleaving.

It can be understood that the above device provided in the embodiment of the present application can implement all the method steps implemented by the corresponding devices in the method embodiment, and can achieve the same technical effects, and detailed descriptions of the same parts and beneficial effects as those in the method embodiment in this embodiment are omitted.

Based on the same technical conception, the embodiment of the application also provides a device. The device can realize the functions realized by the OTN equipment in the embodiment. The device may include a processor and an optical transceiver. The optical transceiver is configured to obtain a first OTN frame. The processor is configured to perform a processing operation on the first OTN frame, where the processing operation includes at least one of mapping and demapping; acquiring time delay information of a designated processing operation in the processing operation; and transmitting the time delay information to another OTN device through the transceiver unit.

Based on the same technical conception, the embodiment of the application also provides a device. The device can realize the functions realized by the access equipment in the embodiment. The device may include a processor and an optical transceiver. The optical transceiver is configured to obtain an OTN frame. The processor is configured to obtain delay information in the OTN frame, where the delay information is used to indicate delay information of a processing operation specified on an OSU transmission path from an originating access device to the terminating access device, and the processing operation includes at least one of mapping and demapping; and recovering the OSU clock according to the time delay information.

Based on the same technical concept, the embodiment of the application also provides a device which can realize the functions realized by the related equipment in the embodiment. As shown in fig. 17, the apparatus 1700 may include a transceiver 1701, a memory 1703, and a processor 1702, the transceiver 1701, the memory 1703, and the processor 1702 may be connected by a bus 1704. The transceiver 1701 may be used for communication by a device, such as for transmitting or receiving signals. The memory 1703 is coupled to the processor 1702 and is operable to store programs and data necessary for the apparatus 1700 to perform various functions. The above memory 1703 and the processor 1702 may be integrated or independent.

The transceiver 1701 may be, for example, a communication port, such as a communication port (or interface) between network elements for communication. The transceiver 1701 may also be referred to as a transceiver unit or a communication unit. The processor 1702 may be implemented by a processing chip or processing circuit. The transceiver 1701 may receive or transmit information wirelessly or by wire.

In addition, according to the actual use requirement, the device provided by the embodiment of the application can comprise a processor, and the processor invokes an external transceiver and/or a memory to realize the functions or steps or operations. The apparatus provided by the embodiment of the present application may also include a memory, where the processor invokes and executes a program stored in the memory to implement the above functions or steps or operations. Or the device provided by the embodiment of the application can also comprise a processor and a transceiver (or a communication interface), and the processor invokes and executes a program stored in an external memory to realize the functions or steps or operations. Or the device provided by the embodiment of the application can also comprise a processor, a memory and a transceiver.

Based on the same concept as the above method embodiments, in an embodiment of the present application, a computer readable storage medium is further provided, where a program instruction (or called a computer program, an instruction) is stored, where the program instruction when executed by a processor causes the computer to perform an operation performed by an OTN device in any one of possible implementation manners of the above method embodiments and method embodiments.

Based on the same conception as the above method embodiments, the present application further provides a computer program product comprising program instructions, which when executed by a computer, can cause the computer to implement the operations performed by the OTN device in any one of the possible implementation manners of the above method embodiments.

Based on the same conception as the above method embodiments, the present application also provides a chip or a chip system, the chip being coupled to the transceiver for implementing the operations performed by the OTN device in any one of the possible implementations of the above method embodiments. The chip system may include the chip, as well as components including memory, communication interfaces, and the like.

Based on the same conception as the method embodiment, the embodiment of the application also provides a communication system. The communication system includes an OTN device that can perform the method shown in fig. 7. An access device may also be included in the communication system, which may perform the method shown in fig. 14.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (22)

1. A method for transmitting delay information, which is applied to an OTN device of an optical transport network, the method comprising:

acquiring a first OTN frame;

Performing a processing operation on the first OTN frame, the processing operation including at least one of mapping and demapping;

acquiring time delay information of a designated processing operation in the processing operation;

and sending the time delay information to another OTN device.

2. The method of claim 1, wherein the sending the latency information to another OTN device comprises:

and sending the time delay information to the other OTN equipment through an overhead area of an OSU frame.

3. The method of claim 1 or 2, wherein the first OTN frame is a first OSU frame.

4. The method according to any one of claims 1-3, wherein said sending the latency information to the other OTN device comprises:

And transmitting the time delay information to the other OTN equipment through one OSU frame.

5. The method of claim 4, wherein said transmitting said latency information to said another OTN device over an OSU frame comprises:

and sending the time delay information to the other OTN equipment through the first OSU frame.

6. The method of claim 4, wherein said sending the delay information to another OTN device via an OSU frame comprises:

and sending the delay information to the other OTN device through a second OSU frame, wherein the second OSU frame is positioned after the first OSU frame.

7. The method of claim 5, wherein the transmitting the latency information to the other OTN device over a second OSU frame comprises:

and sending the delay information to the other OTN device through at least two bytes in the second OSU frame.

8. The method according to any one of claims 1-3, wherein said sending the latency information to the other OTN device comprises:

And transmitting the delay information to the other OTN device through at least two OSU frames, wherein the at least two OSU frames are located after the first OSU frame or the at least two OSU frames comprise the first OSU frame.

9. The method of claim 8, wherein each of the at least two OSU frames includes at least one byte of the delay information therein.

10. The method of claim 8 or 9, wherein the at least two OSU frames include a third OSU frame and a fourth OSU frame, and wherein the transmitting the delay information to the other OTN device by the at least two OSU frames includes:

Transmitting the low-bit byte of the delay information to the other OTN device through the third OSU frame;

And transmitting the high-bit byte of the time delay information to the other OTN device through the fourth OSU frame.

11. The method of any of claims 2-9, wherein the method further comprises, prior to the sending the latency information to the other OTN device via an overhead region of an OSU frame:

and accumulating the time value corresponding to the time delay information to the value of the time stamp field in the overhead area of the OSU frame.

12. The method of any of claims 1-11, wherein the specified processing operation comprises a processing operation in which latency is not fixed in at least one of the mapping and demapping.

13. The method of any of claims 1-12, wherein the processing operation comprises at least one of interleaving, mapping, and demapping.

14. A clock recovery method, applied to an access device in an OTN, the method comprising:

Acquiring an OTN frame;

Acquiring delay information in the OTN frame, where the delay information is used to indicate delay information of a processing operation specified on an OSU transmission path from an originating access device to the optical service unit of the access device, and the processing operation includes at least one of mapping and demapping;

and recovering the OSU clock according to the time delay information.

15. The method of claim 14, wherein the OTN frame is an OSU frame.

16. The method of claim 15, wherein the obtaining delay information in the OTN frame comprises:

And acquiring the time delay information from the overhead area of the OSU frame.

17. The method of claim 15, wherein the acquiring the OTN frame comprises:

Acquiring at least two OSU frames;

The obtaining delay information in the OSU frame includes:

obtaining at least one byte of the delay information from each of the at least two OSU frames;

The delay information is obtained from at least one byte of the delay information obtained from each OSU frame.

18. The method of any of claims 14-17, wherein the specified processing operation comprises at least one of the mapping and demapping processing operations with a processing operation latency that is not fixed.

19. The method of any of claims 14-18, wherein the processing operation further comprises interleaving, or comprises at least one of mapping and demapping and interleaving.

20. An apparatus, comprising: a processor and an optical transceiver;

the optical transceiver is configured to obtain a first OTN frame;

The processor is configured to perform a processing operation on the first OTN frame, where the processing operation includes at least one of mapping and demapping; acquiring time delay information of a designated processing operation in the processing operation; and transmitting the time delay information to another OTN device through the transceiver unit.

21. An apparatus, comprising: a processor and an optical transceiver;

the optical transceiver is used for acquiring an OTN frame;

The processor is configured to obtain delay information in the OTN frame, where the delay information is used to indicate delay information of a processing operation specified on an OSU transmission path from an originating access device to the terminating access device, and the processing operation includes at least one of mapping and demapping; and recovering the OSU clock according to the time delay information.

22. An apparatus, comprising: one or more processors; wherein the instructions of the one or more computer programs, when executed by the one or more processors, cause the apparatus to perform the method of any of claims 1-13 or perform the method of any of claims 14-19.