CN118157698A - Receiver circuit, corresponding isolated driver device, electronic system and method for decoding differential signal into digital output signal - Google Patents

Abstract

A receiver circuit receives a differential signal including positive spikes and negative spikes and generates an output signal based on the differential signal. A first comparator generates an intermediate set signal, which includes a pulse at each positive spike of the differential signal, and a second comparator generates an intermediate reset signal, which includes a pulse at each negative spike of the differential signal. A logic circuit detects whether the digital signal switches between a first value and a second value, and whether the intermediate reset signal and the intermediate set signal include pulses with a duration longer than a threshold. The logic generates a set correction signal and a reset correction signal. The logic circuit generates a correction set signal and a correction reset signal. The output circuit generates an output signal based on the correction set signal and the correction reset signal.

Description

Receiver circuit, corresponding isolation driver device, electronic system and method for decoding a differential signal into a digital output signal

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority from Italian Patent Application No. 102022000025200, filed on December 7, 2022, entitled “RECEIVER CIRCUIT, CORRESPONDING ISOLATED DRIVER DEVICE, ELECTRONIC SYSTEM AND METHOD OF DECODING ADIFFERENTIAL SIGNAL INTO A DIGITAL OUTPUT SIGNAL”, which is incorporated herein by reference to the maximum extent permitted by law.

Technical Field

This specification relates to isolated gate driver devices that can be applied to traction inverters, DC/DC converters, on-board chargers (OBCs), and belt starter generators (BSGs) for electric vehicles (EVs) and hybrid electric vehicles (HEVs).

Background technique

Conventional isolated gate driver devices are system-on-chip devices used to switch transistors (such as IGBTs, SiC or Si MOSFETs) in high-voltage motor control applications. Conventional isolated gate driver devices typically include two semiconductor dies arranged in the same package: a low-voltage die that exchanges signals with a microcontroller, and a high-voltage die that includes the driver circuit. The low-voltage die and the high-voltage die are electrically isolated from each other by a galvanic isolation barrier, which typically includes one or more high-voltage capacitors (HVCaps) arranged between the two dies.

FIG1 is a circuit block diagram of an isolated gate driver device. FIG2 is a timing diagram including example waveforms of signals in the device of FIG1, illustrating possible operation of the device.

As shown in FIG1 , the isolated gate driver device 10 includes a low voltage semiconductor die 10a and a high voltage semiconductor die 10b arranged in the same package. A communication channel is provided in the device 10 so that a (single-ended) pulse width modulation (PWM) input signal PWM _IN (also referred to as a low voltage transmission signal, for example, a PWM signal with a frequency between 15kHz and 5MHz received from a microcontroller) received at an input pin 101 of the low voltage die 10a can be propagated as a (single-ended) PWM output signal PWM _OUT (also referred to as a high voltage receiving signal) generated at an output pin 106 of the high voltage die 10b. In some applications, the communication channel can be bidirectional so that a (single-ended) PWM input signal (also referred to as a high voltage transmission signal) received at an input pin of the high voltage die 10b, which is not visible in FIG1 , can be propagated as a (single-ended) PWM output signal (also referred to as a low voltage receiving signal) transmitted by an output pin of the low voltage die 10a, which is also not visible in FIG1 .

In particular, the low voltage die 10a includes a transmitter circuit 102 coupled to an input pin 101 and configured to convert a received single-ended signal PWM _IN into a pair of differential PWM signals OUT _P , OUT _N. For example, the signal OUT _P may be generated at the output of a buffer circuit that receives the signal PWM _IN at an input, and the signal OUT _N may be generated at the output of another buffer circuit (e.g., an inverting buffer) that receives a complementary signal (e.g., an inverted copy) of the signal PWM _IN at an input. The low voltage die 10a also includes a first high voltage capacitor 103P (e.g., an isolation capacitor) having a first terminal coupled to a first output of the transmitter circuit 102 to receive the signal OUT _P , and a second high voltage capacitor 103N (e.g., an isolation capacitor) having a first terminal coupled to a second output of the transmitter circuit 102 to receive the signal OUT _N. The second terminals of the capacitors 103P and 103N provide an output node of the low voltage die 10a, which is electrically connected (e.g., via bonding wires) to an input node of the high voltage die 10b. The signals _OUTP , _OUTN are thus filtered by the isolation capacitors 103P, 103N (acting as high pass filters) so that the pulse differential signal Vd reaches the high voltage die 10b. In addition, the transmitter circuit 102 can implement a "gate retry" mechanism: the PWM input signal PWM _IN is clocked by a clock signal CLK available in the low voltage die 10a and having a frequency higher than the frequency of the signal PWM _IN (e.g., five times higher, ten times higher, or higher), so that a spike is generated in the differential signal Vd at each edge of the clock signal CLK, so as to facilitate recovery from possible pulse loss and allow correct reconstruction of the signal PWM _IN at the receiver side. Therefore, the differential signal Vd includes a series of temporary spikes (positive and negative) corresponding to the edges of the input signal PWM _IN and the edges of the clock signal CLK, wherein the signs of these spikes depend on the value of the input signal PWM _IN , as shown in FIG. 2 . Specifically, when the input signal PWM _IN has a high logic value (logic “1”), the peak of the signal Vd is positive, and when the input signal PWM _IN has a low logic value (logic “0”), the peak of the signal Vd is negative.

The high voltage die 10 b includes a receiver circuit 104 coupled to an input node of the die 10 b to receive the differential signal Vd and configured to generate a reconstructed PWM signal PWM _RX according to the received differential signal Vd. For example, the receiver circuit 104 may be configured to set the signal PWM _RX to a high logic value (logic “1”) as a result of detecting a positive pulse in the differential signal Vd, and to set the signal PWM RX to a low logic value (“0”) as a result of detecting a negative pulse in the differential signal Vd, as shown in FIG2 . Thus, _{the reconstructed signal PWM RX may} substantially correspond to a (slightly) delayed copy of the input signal PWM _IN . The high voltage die 10b may also include a driver stage 105, which includes a pre-driver circuit (e.g., buffers 1051, 1052, 1053) configured to receive the reconstructed signal PWM _RX and drive the output switch circuit according to the reconstructed signal PWM _RX (e.g., inverting at inverter 1051 and/or amplifying the reconstructed signal PWM _RX at buffers 1052, 1053). For example, the output switch circuit may include a half-bridge driver stage, which includes a high-side switch (e.g., a transistor) and a low-side switch (e.g., a transistor) arranged in series between a high voltage power supply pin VH and a high voltage reference (or ground) pin VL of the gate driver device 10. The node between the high-side switch and the low-side switch can be electrically coupled to the output pin 106 of the gate driver device 10. The high-side switch and the low-side switch are driven by the pre-driver circuits 1051 , 1052 , 1053 so that an output switching signal PWM _OUT is generated at the output pin 106 (e.g., when PWM _RX = “1”, the high-side switch is in a conducting state, and when PWM _RX = “0”, the low-side switch is in a conducting state).

In the present disclosure, reference is made to the case where the isolation capacitors 103P, 103N are implemented in the low voltage die 10a. However, it should be understood that the isolation capacitors may alternatively be implemented in the high voltage die 10b, for example, arranged between an input pin of the high voltage die 10b and an input terminal of the receiver circuit 104.

FIG3 is an exemplary circuit block diagram of a possible implementation of the receiver circuit 104, and FIG4 is a timing diagram including exemplary waveforms of signals in the receiver circuit 104 of FIG3, which illustrates possible operation of the receiver circuit. The input terminals of the circuit 104 (which may be referenced to a local (high voltage) ground GND _HV via corresponding resistors) receive the differential signal Vd and are coupled to an amplifier stage 40, which produces an amplified copy of the differential signal Vd. The amplified differential signals are received at a pair of comparators 42, 44 having opposite input polarities (e.g., the positive output of the amplifier 40 may be coupled to the negative input of the comparator 42 and the positive input of the comparator 44, and the negative output of the amplifier 40 may be coupled to the positive input of the comparator 42 and the negative input of the comparator 44). Therefore, the comparator 42 generates a (digital) signal COMP _N including pulses corresponding to the positive peaks of the signal Vd (e.g., the signal COMP _N is normally high and includes a low pulse, as shown in FIG4 ), and the comparator 44 generates a (digital) signal COMP _P including pulses corresponding to the negative peaks of the signal Vd (e.g., the signal COMP _P is normally high and includes a low pulse, as shown in FIG4 ). The signals COMP _N and COMP _P are used as set and reset signals for a set-reset (SR) flip-flop 46 of the receiver 104. In particular, the flip-flop 46 receives a bias voltage V _DD (e.g., 3.3 V) at its data input terminal D, receives the signal COMP _N (possibly supplemented by an inverter stage) at its clock input terminal _CP , and receives the signal COMP _P at its reset input terminal _CD . Therefore, the data output terminal Q of the flip-flop 46 is set to a high logic value (logic "1") in response to a pulse of the signal COMP _N (particularly, in response to a falling edge of the signal COMP _N ), and is set to a low logic level (logic "0") in response to a pulse of the signal COMP _P (particularly, in response to a falling edge of the signal COMP _P ), thereby generating a reconstructed PWM signal PWM _RX corresponding to a (delayed) copy of the input PWM signal _{PWM IN sent} by the low voltage die 10a of the device 10 (as shown in FIG. 4). The time interval between two consecutive peaks of the signal Vd (and therefore between two consecutive pulses of the signal COMP _N or COMP _P ) is equal to half of the clock period T _CLK of the low voltage clock signal CLK (e.g., T _CLK /2).

As expected, the driver device 10 can be used in motor control applications, as shown in the circuit block diagram of FIG5 , which shows the driver portion of the device 10 , whose output pin 106 (e.g., the center node or switch node of a half-bridge driver including a high-side switch HS and a low-side switch LS) is coupled to an external load (such as a motor M). As shown in FIG5 , the low-side driver circuit 1053 can be powered between the power supply voltage of the die 10b available at pin VH and the local ground voltage GND _HV (which is available at pin VL), while the high-side driver circuit 1052 can be powered between the power supply voltage of the die 10b available at pin VH and the switch node 106 (i.e., which can be referenced to the floating ground GND _S ). In such a scenario, during the switching activity of the half-bridge circuit, the switch node 106 providing the high-side floating ground GND _S is continuously switched between the local ground voltage GND _HV (e.g., 0V) and the power supply voltage of the die 10b available at pin VH (which can be on the order of kilovolts). As a result, driver device 1052 may be subject to fast slew rate voltage transitions of die 10a and 10b between GND and GND _S. These events may generate bursts of current that produce common-mode voltages at the input terminals of receiver circuit 104. The input terminals of receiver 104 may be subject to mismatches (e.g., due to parasitic capacitors toward a low voltage ground associated with a bond wire), so the common-mode voltage may be converted to a stray differential voltage that is summed with signal Vd.

The above scenario is illustrated in the circuit block diagram of FIG. 6 , which essentially replicates the circuit block diagram of FIG. 3 , but additionally indicates a common-mode voltage V _CM applied to the input terminals of the amplifier 40. FIG. 7 is a time diagram including exemplary waveforms of signals in the receiver circuit of FIG. 6 when such common-mode voltage V _CM affects the differential signal Vd. It should be understood that the voltage generator shown in FIG. 6 is not an actual implemented component in the circuit, but merely indicates the effect of applying a common-mode voltage to the input terminals of the receiver 104. In particular, the waveform of the common-mode voltage V _CM generated between the low voltage ground GND _LV and the high voltage ground GND _HV during the transient event may include a high slew rate slope following a ringing phase (e.g., a damped sinusoidal curve) due to the influence of (external) parasitic components. As a result, due to the mismatch of the input terminals of the amplifier 40, the receiver 104 senses a differential damped sinusoidal high frequency signal, whose frequency may fall within the amplification band of the receiver chain (e.g., the band of the amplifier 40). Therefore, the damped sinusoidal signal can be amplified and produce a series of spurious set and reset pulses (e.g., spurious pulses SP of signals COMP _N and COMP _P , as shown in FIG. 7 ), which are subsequently sensed by the flip-flop 46 and produce unwanted commutations of the reconstructed signal PWM _RX (e.g., commutations UC of signal PWM _RX , as shown in FIG. 7 ).

In order to mitigate the above-mentioned spurious pulse problem in the reconstructed signal PWM _RX due to the common-mode ringing effect in the differential signal Vd, one possible approach is to implement the isolation capacitors 103P, 103N in the high-voltage die 10b. This implementation eliminates the effect of the mismatch of the bonding wires between the die 10a and the die 10b, which will be dominated by the low equivalent impedance of the transmitter. However, this approach requires the isolation capacitors 103P, 103N to be implemented in the same technology of the high-voltage die 10b, which may be cumbersome, expensive and/or area consuming.

Therefore, there is a need in the art to provide a receiver circuit (e.g., for implementation in an isolated communication channel of a gate driver device) having an improved architecture that solves the above-mentioned problems, or in other words, to provide a receiver circuit with improved common-mode transient immunity (CMTI).

Summary of the invention

Embodiments of the present disclosure facilitate providing improved receiver circuits.

One or more embodiments may be directed to corresponding isolation driver devices.

One or more embodiments may be directed to a corresponding electronic system.

One or more embodiments may be directed to corresponding methods of decoding a differential pulse signal transmitted across a galvanic isolation barrier to produce a pulse width modulated digital signal.

The claims are an integral part of the technical teaching provided herein with respect to the exemplary embodiments.

According to one aspect of the specification, in a receiver circuit, a pair of input nodes is configured to receive a differential signal therebetween. The differential signal includes a spike of a first polarity (e.g., positive) and a spike of a second polarity (e.g., negative). The output node is configured to generate a digital output signal based on the differential signal. The first comparator circuit is configured to receive the differential signal and generate an intermediate set signal, which includes a pulse at each spike of the differential signal having a first polarity. The second comparator circuit is configured to receive the differential signal and generate an intermediate reset signal, which includes a pulse at each spike of the differential signal having a second polarity. The logic circuit is configured to receive the intermediate set signal, the intermediate reset signal, and the digital output signal. The logic circuit is also configured to:

detecting whether the digital output signal switches between a first logic value and a second logic value;

detecting whether the intermediate reset signal includes a pulse having a duration greater than a certain time interval (e.g., a threshold);

generating a set correction signal including a pulse when the digital output signal switches between the first logic value and the second logic value and simultaneously the intermediate reset signal includes a pulse having a duration greater than a specific time interval;

generating a correction set signal including pulses of the intermediate set signal and pulses of the set correction signal;

detecting whether the intermediate set signal includes a pulse having a duration greater than a specific time interval;

generating a reset correction signal including a pulse when the digital output signal switches between the first logic value and the second logic value and simultaneously the intermediate set signal includes a pulse having a duration greater than a specific time interval; and

A correction reset signal including pulses of the intermediate reset signal and pulses of the reset correction signal is generated.

The receiver circuit includes an output control circuit configured to receive a correction set signal and a correction reset signal, and further configured to assert (also referred to as "activate") a digital output signal in response to detecting a pulse in the correction set signal, and to de-assert the digital output signal in response to detecting a pulse in the correction reset signal.

Thus, one or more embodiments may provide a receiver circuit having improved robustness to common mode noise using simple logic circuitry.

Optionally, the logic circuit includes:

a first asymmetric buffer circuit configured to receive the intermediate reset signal and generate a first detection signal by passing an active edge (e.g., a falling edge) of the intermediate reset signal with a delay equal to a specific time interval and passing an inactive edge (e.g., a rising edge) of the intermediate reset signal without a substantial delay;

A first gating logic gate is configured to pass the first detection signal when the digital output signal switches between the first logic value and the second logic value, and to shield the first detection signal otherwise, so as to generate a setting correction signal;

a second asymmetric buffer circuit configured to receive the intermediate set signal and generate a second detection signal by passing an active edge (e.g., a falling edge) of the intermediate set signal with a delay equal to a specific time interval and passing an inactive edge (e.g., a rising edge) of the intermediate set signal without a substantial delay; and

The second gating logic gate is configured to pass the second detection signal when the digital output signal switches between the first logic value and the second logic value, and to shield the second detection signal otherwise, so as to generate a reset correction signal.

According to another aspect of the specification, an isolated driver device includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes an input pin configured to receive a digital input signal. The first semiconductor die includes a transmitter circuit configured to receive the digital input signal and generate a pair of complementary digital signals. The first digital signal in the complementary digital signal is a copy of the digital input signal and is generated at a first output node of the transmitter circuit, and the second digital signal in the complementary digital signal is a complementary signal of the digital input signal and is generated at a second output node of the transmitter circuit. The first semiconductor die includes a galvanic isolation barrier, which includes a first isolation capacitor and a second isolation capacitor, the first isolation capacitor having a first terminal coupled to the first output node of the transmitter circuit, and the second isolation capacitor having a first terminal coupled to the second output node of the transmitter circuit. A differential signal is generated between the second terminal of the first isolation capacitor and the second terminal of the second isolation capacitor. The differential signal includes a spike of a first polarity at each rising edge of the digital input signal and a spike of a second polarity at each falling edge of the digital input signal. The second semiconductor die includes a receiver circuit according to one or more embodiments. A first input node of the receiver circuit is electrically coupled to a second terminal of the first isolation capacitor, and a second input node of the receiver circuit is electrically coupled to a second terminal of the second isolation capacitor to receive the differential signal.

According to another aspect of the present specification, an electronic system includes a processing unit and an isolated driver device according to one or more embodiments. The processing unit is configured to generate a digital input signal received by the isolated driver device.

According to another aspect of the present specification, a method for decoding a differential signal into a digital output signal includes:

receiving a differential signal including a spike of a first polarity (e.g., positive) and a spike of a second polarity (e.g., negative);

generating an intermediate set signal including a pulse at each peak of the differential signal having a first polarity;

generating an intermediate reset signal including a pulse at each peak of the differential signal having a second polarity;

detecting whether the digital output signal switches between a first logic value and a second logic value;

detecting whether the intermediate reset signal includes a pulse having a duration greater than a certain time interval (e.g., a threshold);

generating a set correction signal including a pulse when the digital output signal switches between the first logic value and the second logic value and simultaneously the intermediate reset signal includes a pulse having a duration greater than a specific time interval;

generating a correction set signal including pulses of the intermediate set signal and pulses of the set correction signal;

detecting whether the intermediate set signal includes a pulse having a duration greater than a specific time interval;

generating a reset correction signal including a pulse when the digital output signal switches between the first logic value and the second logic value and simultaneously the intermediate set signal includes a pulse having a duration greater than a specific time interval;

generating a correction reset signal including pulses of the intermediate reset signal and pulses of the reset correction signal; and

The digital output signal is asserted in response to detecting a pulse in the correction set signal, and the digital output signal is de-asserted in response to detecting a pulse in the correction reset signal.

BRIEF DESCRIPTION OF THE DRAWINGS

One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

Figures 1 to 7 have been described above;

FIG8 is a timing diagram including exemplary waveforms of signals in a conventional receiver circuit, e.g., for use in an isolated communication channel of a driver device;

9 is an exemplary circuit block diagram of a receiver circuit according to one or more embodiments of the present specification, for example, for use in an isolated communication channel of a driver device;

FIG. 10 is an exemplary circuit block diagram of a gate-level implementation of a portion of the receiver circuit of FIG. 9 according to one or more embodiments of the present specification; and

FIG. 11 is a timing diagram including exemplary waveforms of signals in the receiver circuit of FIG. 9 , according to one or more embodiments of the present description.

Detailed ways

In the following description, one or more specific details are described to provide a deeper understanding of the examples of the embodiments of the present specification. These embodiments can be obtained without one or more of these specific details, or using other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail so as not to obscure certain aspects of the embodiments.

In the framework of this specification, references to "an embodiment" or "an embodiment" are intended to indicate that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in an embodiment" that may be present in one or more places in this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular configurations, structures, or characteristics may be combined in any appropriate manner.

The headings/references used herein are for convenience only and therefore do not define the scope of protection or the scope of the embodiments.

In the drawings attached hereto, unless the context indicates otherwise, the same components or elements are denoted by the same references/numerals, and the corresponding description will not be repeated for the sake of brevity.

One or more embodiments are directed to a receiver circuit configured to reject spurious pulses SP generated in set and reset signals COMP _N and COMP _P due to unwanted oscillations of a differential signal Vd (e.g., ringing effects caused by common-mode voltage transients applied at the input of the receiver circuit) to improve common-mode transient immunity (CMTI). By way of a detailed description of an exemplary embodiment, reference may first be made to FIG. 8 , which is a timing diagram including exemplary waveforms of signals in a conventional receiver circuit 104 (substantially reproducing the contents of FIG. 7 ). Here, it is shown that the duration Tr of the pulse FP of the set signal COMP _N and the reset signal COMP _P (e.g., the pulse generated at the edge of the clock signal CLK and the edge of the input signal PWM _IN ) that contributes to the correct operation of the set-reset flip-flop 46 (e.g., correct signal decoding) _is generally within a specific range (e.g., between 1ns and 2ns), while the duration Ts of the spurious pulse SP of the set signal COMP _N and the reset signal COMP _P due to common-mode transients and ringing effects _is longer, that is, the duration exceeds the maximum duration of the pulse FP (e.g., higher than 2ns, such as about 10ns). Therefore, one or more embodiments rely on an improved receiver architecture that includes a logic circuit configured to correct the value of the output signal PWM _RX generated by the flip-flop 46 by generating a correct set signal and a correct reset signal when the following conditions are met:

i) the duration of the pulses generated at the outputs of the comparators 42 and 44 (i.e. the pulses of the signals COMP _N and COMP _P ) is higher than a certain threshold, wherein the value of the threshold is higher than the maximum duration _Tr allowed for the functional pulse FP (which indicates that the pulse is indeed a spurious pulse); and

ii) A commutation of the output signal PWM _RX is detected (this indicates that the stray pulse does have to be corrected, since otherwise it would force the output signal PWM _RX to a wrong value).

Thus, one or more embodiments may be directed to a receiver circuit 104' as shown in the circuit block diagram of Fig. 9, wherein components or elements similar to those described with reference to previous figures are denoted by the same or similar reference numerals, and for the sake of brevity, the corresponding description is not repeated. In particular, the receiver circuit 104' comprises a logic circuit 90, which is arranged between the output terminals of the comparators 42, 44 and the input terminals of the set-reset flip-flop 46. The logic circuit 90 receives the "original" set signal COMP _N and reset signal COMP _P , which may be affected by stray pulses, and the reconstructed PWM signal PWM _RX generated by the flip-flop 46. The logic circuit 90 is configured to generate a "correction" set signal _COMP'N and a "correction" reset signal _COMP'P , which are propagated to the flip-flop 46 (where the signal _COMP'N may be complemented, as described above with reference to FIG. 3), and to generate a reconstructed PWM signal PWM _RX that may be free of stray pulses but suitable for properly driving the output switching stages 105, HS, LS so that the output PWM signal PWM _OUT is free of stray pulses, as further discussed below. In particular, one or more embodiments rely on the fact that the signal PWM _RX may include stray pulses, but the duration of such stray pulses is reduced to a value below the propagation delay _Tdelay of the output switching stage so that these pulses do not affect the value of the output PWM signal PWM _OUT .

In particular, the logic circuit 90 is configured to:

detecting the presence of spurious pulses in the signals COMP _N , COMP _P based on the duration of the pulses (e.g., selecting only pulses longer than a threshold value T _count , where T _count is selected to be longer than a maximum duration _Tr of a functional pulse);

discarding stray pulses that do not negatively affect the value of the reconstructed PWM signal PWM _RX (e.g., in the example considered herein, discarding stray pulses of the signal COMP _N that occur while the signal PWM _IN has a high logic value, and stray pulses of the signal COMP _P that occur while the signal PWM _IN has a low logic value); and

In response to detecting a stray pulse in one of the signals COMP _N , COMP _P and the stray pulse is not discarded, a correction pulse is generated in the other of the signals COMP _N , COMP _P , thereby generating a correction set signal COMP' _N and a correction reset signal COMP' _P to force the reconstructed PWM signal PWM _RX to return to its correct value within a time period T _count that is shorter than the propagation delay T _delay of the output switching stage, so that the value of the output PWM signal PWM _OUT does not switch to an erroneous value.

FIG. 10 is an exemplary circuit block diagram of a possible gate-level implementation of logic circuit 90 , and FIG. 11 is a timing diagram including exemplary waveforms of signals in receiver circuit 104 ′, illustrating possible operation of the receiver circuit.

The logic circuit 90 comprises a first asymmetric buffer 91 _P configured to receive the “original” reset signal COMP _P and generate a first detection signal COMP _P,DLY . The signal COMP _P,DLY substantially corresponds to a copy of the signal COMP _P , in which the active edge of the signal (e.g., the falling edge in the example considered herein, in which the reset signal COMP _P is normally high) is delayed by an interval T _count higher than the expected duration _Tr of the functional pulse FP. Thus, as shown in FIG. 11 , the signal COMP _P,DLY indicates a spurious pulse SP of the reset signal COMP _P , as long as a pulse with a duration higher than T _count is propagated with a delayed active edge (e.g., a falling edge) and a nearly unaffected inactive edge (e.g., a rising edge), and a pulse with a duration lower than T _count is not propagated from the signal COMP _P to the signal COMP _P,DLY (e.g., the signal COMP _P,DLY remains at a high logic level during these pulses). In particular, in one or more embodiments, the first asymmetric buffer 91 _P may include a first inverter circuit including a pull-up transistor and a pull-down transistor arranged in series between a logic power supply voltage V _DD and a logic reference voltage V _SS and driven by a signal COMP _P. A capacitor is coupled in parallel to the conduction channel of the pull-down transistor (e.g., between the output node of the inverter circuit and the logic reference voltage V _SS ) to delay an active edge (e.g., a falling edge). An inactive edge (e.g., a rising edge) is kept fast to discharge the capacitor and prepare the buffer for the next detection action. A second inverter circuit is coupled to the output of the first inverter circuit, all thereby generating a signal COMP _P,DLY having the above-described characteristics.

Similarly, the logic circuit 90 includes a second asymmetric buffer 91 _N configured to receive the “original” set signal COMP _N and generate a second detection signal COMP _N,DLY . The signal COMP _N,DLY substantially corresponds to a copy of the signal COMP _N , in which the active edge of the signal (e.g., the falling edge in the example considered herein, in which the set signal COMP _N is normally high) is delayed by an interval T _count . Therefore, as shown in FIG. 11 , the signal COMP _N,DLY indicates a spurious pulse SP of the set signal COMP _N , as long as a pulse with a duration higher than T _count is propagated with a delayed active edge (e.g., a falling edge) and a nearly unaffected inactive edge (e.g., a rising edge), and a pulse with a duration lower than T _count is not propagated from the signal COMP _N to the signal COMP _N,DLY (e.g., the signal COMP _N,DLY remains at a high logic level during these pulses). In particular, in one or more embodiments, the second asymmetric buffer 91 _N may include a first inverter circuit including a pull-up transistor and a pull-down transistor arranged in series between a logic power supply voltage V _DD and a logic reference voltage V _SS and driven by a signal COMP _N. A capacitor is coupled in parallel to the conduction channel of the pull-down transistor (e.g., between the output node of the inverter circuit and the logic reference voltage V _SS ) to delay an active edge (e.g., a falling edge). The inactive edge (e.g., a rising edge) remains fast to discharge the capacitor and prepare the buffer for the next detection action. The second inverter circuit is coupled to the output of the first inverter circuit, and thereby generates a signal COMP _N,DLY having the above-described characteristics.

In addition, the logic circuit 90 includes an edge detector circuit 92, which is coupled to the output of the flip-flop 46 and is configured to generate an edge detection signal ED, which indicates a transition (e.g., an edge) of the reconstructed PWM signal PWM _RX , as shown in FIG11. In particular, the edge detection signal ED can be normally high and can include a low pulse at each occurrence of a transition (e.g., an edge) of the signal PWM _RX . The duration T _ED of such a low pulse can be longer than T _count . In particular, in one or more embodiments, the edge detector circuit 92 can include a delay circuit block configured to generate a copy of the signal PWM _RX delayed by an interval T _ED , an XOR logic gate configured to apply an XOR logic process to the signal PWM _RX and its delayed copy, and an inverter circuit coupled to the output of the XOR logic gate to generate the edge detection signal ED having the above-mentioned characteristics.

In addition, the logic circuit ₉₀ includes a first gated logic gate 93 _P , which is configured to combine the first detection signal COMP _{P, DLY} and the edge detection signal ED to discard stray pulses of the signal COMP _{P, DLY} that do not correspond to the transition _of the reconstructed PWM signal PWM _RX , thereby generating a set correction signal set _new , which indicates a corrective action that must be implemented in the original set signal COMP _N to generate the corrected set signal COMP' _N. In particular, the set correction signal set _new can be normally high and can include a low pulse when the signals COMP _{P, DLY} and ED both have a low pulse. Therefore, in one or more embodiments, the first gated logic gate can include an OR gate 93 _P configured to apply an OR logic process to the signals COMP _{P, DLY} and ED to generate the signal set _new .

Similarly, the logic circuit 90 includes _{a second gating logic gate 93 N configured} to combine the second detection signal COMP _N,DLY and the edge detection signal ED to discard stray pulses of the signal COMP _N,DLY that do not correspond to the transition of the reconstructed PWM signal PWM _RX , thereby generating a reset correction signal reset _new indicating a corrective action _that must be implemented in the original reset signal COMP _P to generate the corrected reset signal COMP' _P. In particular, the reset correction signal reset _new may be normally high and may include a low pulse when both the signals COMP _N,DLY and ED have a low pulse. Therefore, in one or more embodiments, the second gating logic gate may include an OR gate 93 _N configured to apply an OR logic process to the signals COMP _N,DLY and ED to generate the signal reset _new .

In addition, the logic circuit 90 includes a first correction logic gate 94 _P , which is configured to combine the set correction signal set _new and the original set signal COMP _N to add a correction pulse to the signal COMP _{N that} is intended to restore the correct value of the signal PWM _RX after the stray reset pulse, thereby generating a correction set signal COMP' _N. In particular, the correction set signal COMP' _N may be normally high and may include a low pulse corresponding to the pulses of the signals COMP _N and set _new . Therefore, in one or more embodiments, the first correction logic gate 94 _P may include an AND gate 94 _P configured to apply an AND logic process to the signals COMP _N and set _new to generate the signal COMP' _N.

Similarly, the logic circuit 90 includes a second correction logic gate 94 _N , _which is configured to combine the reset correction signal reset _new and the original reset signal COMP _P to add a correction pulse to the signal COMP _P that is intended to restore the correct value of the signal PWM _RX after the stray set pulse, thereby generating a correction reset signal COMP' _P. In particular, the correction reset signal COMP' _P can be normally high and can include low pulses corresponding to the pulses of the signals COMP _P and reset _new . Therefore, in one or more embodiments, the second correction logic gate 94 _N can include an AND gate 94 _N configured to apply an AND logic process to the signals COMP _P and reset _new to generate the signal COMP' _P.

As shown in Fig. 10, the correction signals _COMP'N and _COMP'P are then used as set and reset signals for a set-reset (SR) flip-flop 46 of the receiver 104', as described with reference to Fig. 3. Thus, the flip-flop 46 receives the signal _COMP'N at its clock input terminal _CP (possibly complemented by an inverter stage) and receives the signal _COMP'P at its reset input terminal _CD to generate the reconstructed PWM signal _PWMRX .

Optionally, the first gated logic gate 93 _P may also be configured to receive the signal COMP _P and combine it with the signals COMP _{P, DLY} and ED so that the inactive edge (e.g., rising edge) of the signal COMP _P is quickly propagated to the set correction signal set _new . In fact, as previously discussed, the asymmetric buffer 91 _P is configured to substantially delay (e.g., by an interval T _count ) the active edge (e.g., falling edge) of the signal COMP _P while allowing the inactive edge (e.g., rising edge) to pass without substantial delay. However, if the signal COMP _P is not directly propagated to the gate 93 _P , the inactive edge is propagated via the two cascaded inverter circuits of the asymmetric buffer 91 _P. Alternatively, by propagating the signal COMP _P directly to the gate 93 _P , the propagation delay of the asymmetric buffer 91 _P for the inactive edge can be avoided. Therefore, in one or more embodiments, the first gate control logic gate may include an OR gate 93 _P , and the OR gate 93 _P is configured to apply an OR logic process to the signals COMP _{P, DLY} , COMP _P , and ED to generate the signal set _new . Similarly, optionally, the second gate control logic gate 93 _N may also be configured to receive the signal COMP _N and combine it with the signals COMP _{N, DLY} , and ED so that the inactive edge (e.g., rising edge) of the signal COMP _N is quickly propagated to the reset correction signal reset _new . Therefore, in one or more embodiments, the second gate control logic gate may include an OR gate 93 _N , and the OR gate 93 _N is configured to apply an OR logic process to the signals COMP _{N, DLY} , COMP _N , and ED to generate the signal reset _new .

FIG. 11 is a timing diagram including exemplary waveforms of signals in the receiver circuit 104 ′ of FIG. 10 , which illustrates possible operation of the receiver circuit. Here, by way of example, it is shown that a stray pulse SP1 of the signal COMP _P forces the reconstructed signal PWM _RX to a low logic value (while the signal PWM _RX is expected to remain at a high logic value to replicate the signal PWM _IN ). The stray pulse SP1 is detected by the signal COMP _P,DLY switching to a low logic value due to its duration being longer than T _count . At the same time, the edge detection signal ED also switches to a low logic value because the signal PWM _RX has switched due to the stray pulse. Since the signal COMP _P,DLY indicates the presence of a stray reset pulse, and the signal ED indicates that the signal PWM _RX has changed its state, a correction set pulse CP1 is generated in the signal set _new and propagates to the correction set signal COMP' _N , causing the flip-flop 46 to be set again and the signal PWM _RX to switch to its previous (correct) state again. The signal PWM _RX only maintains the wrong value for an interval T _count which is much lower than the propagation delay T _delay of the pre-driver circuit 105, so that the output PWM _OUT of the pre-driver circuit has no time to switch and is not affected. Moreover, due to the gating action of the signal ED, no correction reset pulse is generated even when a stray pulse SP2 of the signal COMP _N is detected (see the signal reset _new which maintains a high logic value even during SP2), because in this case the signal PWM _RX already has the correct value and the stray pulse SP2 will not corrupt it.

Thus, one or more embodiments may prove advantageous because they provide a receiver circuit with a high level of robustness against common mode noise by using logic circuitry (only) added in the decoding circuitry for correcting spurious signals generated by ringing. Thus, one or more embodiments rely on a simple implementation (e.g., comprising only additional logic gates compared to conventional solutions) that is compatible with conventional transmitter/receiver architectures.

Without affecting the basic principle, with respect to what has been described merely by way of example, the details and embodiments may vary, even significantly, without departing from the scope of protection.

The scope of protection is determined by the appended claims.

A receiver circuit (104') can be summarized as including: a pair of input nodes configured to receive a differential signal (Vd) therebetween, the differential signal (Vd) including a peak of a first polarity and a peak of a second polarity; an output node configured to generate a digital output signal (PWM _RX ) based on the differential signal (Vd); a first comparator circuit (42) configured to receive the differential signal (Vd) and generate an intermediate set signal (COMP _N ), the intermediate set signal (COMP _N ) including a pulse at each peak of the differential signal (Vd) having the first polarity; a second comparator circuit (44) configured to receive the differential signal (Vd) and generate an intermediate reset signal (COMP _P ), the intermediate reset signal (COMP _P ) including a pulse at each peak of the differential signal (Vd) having the second polarity; a logic circuit (90) configured to receive the intermediate set signal (COMP _N ), the intermediate reset signal (COMP _P ) and the digital output signal (PWM RX); _RX ) and is further configured to: detect (92, ED) whether the digital output signal (PWM _RX ) switches between a first logic value and a second logic value; detect (91 _P , COMP _{P , DLY} ) whether the intermediate reset signal (COMP _P ) includes a pulse (SP1, SP3) having a duration greater than a specific time interval (T _count ); generate (93 _P ) a set correction signal (set new ) including pulses when the digital output signal (PWM _RX ) switches between the first logic value and the second logic value and at the same time the intermediate reset signal (COMP _P ) includes a pulse (SP1, SP3) having a duration greater than the specific time interval (T _count ); generate (94 _P ) a correction set signal (COMP' _N ) including pulses of the intermediate set signal (COMP _N ) and pulses of the set correction signal (set _new ); detect (91 _N , COMP _{N , DLY} ) whether the intermediate set signal (COMP _N ) includes a pulse (SP1, SP3) having a duration greater than the specific time interval (T _{count ) ;} ) of the digital output signal (PWM _RX ) when the digital output signal (PWM _RX ) switches between the first logic value and the second logic value and at the same time the intermediate set signal (COMP _N ) includes a pulse (SP2) of a duration greater than the specific time interval (T _count ); and generating ( _{94 N} ) a correction reset signal (COMP' P ) including a pulse of the intermediate reset signal (COMP _P ) and a pulse of the reset correction signal ( _{reset new} ); and an output control circuit (46) configured to receive the correction set signal (COMP' _N ) and the correction reset signal (COMP' _P ), and further configured to assert the digital output signal (PWM _RX ) in response to detecting a pulse in the correction set signal (COMP' _N ), and to de-assert the digital output signal (PWM _RX ) in response to detecting a pulse in the correction reset signal (COMP' _P ).

The logic circuit (90) may include: a first asymmetric buffer circuit (91 _P ) configured to receive the intermediate reset signal (COMP _P ) and generate a first detection signal (COMP P, DLY) by passing an active edge of the intermediate reset signal (COMP _P ) with a delay equal to the specific time interval (T _count ) and passing an inactive edge of the intermediate reset signal (COMP _P ) without substantial delay; a first gating logic gate (93 _P ) configured to pass the first detection signal (COMP _{P, DLY} ) when the digital output signal (PWM _RX ) switches between a first logic value and a second logic value and to shield the first detection signal (COMP _{P, DLY )} otherwise to generate the set correction signal (set _new ); a second asymmetric buffer circuit (91 _N ) configured to receive the intermediate set signal (COMP _N ) and generate a set correction signal (set new) by passing the intermediate set signal (COMP _N ) with a delay equal to the specific time interval (T _count ). ) passes through the active edge of the intermediate set signal (COMP _N ) and passes the inactive edge of the intermediate set signal (COMP N ) without substantial delay to generate a second detection signal (COMP _{N, DLY} ); and a second gating logic gate (93 _N ) is configured to pass the second detection signal (COMP _{N, DLY} ) when the digital output signal (PWM _RX ) switches between the first logic value and the second logic value, and otherwise shield the second detection signal (COMP _{N, DLY} ) to generate the reset correction signal (reset _new ).

The first asymmetric buffer circuit (91 _P ) may include: a first inverter circuit including a first pull-up transistor and a first pull-down transistor alternately driven by the intermediate reset signal (COMP _P ); a first capacitor coupled in parallel to the first pull-down transistor; and a second inverter circuit coupled to the first inverter circuit to generate the first detection signal (COMP _{P, DLY} ); and wherein the second asymmetric buffer circuit (91 _N ) may include: a third inverter circuit including a second pull-up transistor and a second pull-down transistor alternately driven by the intermediate set signal (COMP _N ); a second capacitor coupled in parallel to the second pull-down transistor; and a fourth inverter circuit coupled to the third inverter circuit to generate the second detection signal (COMP _{N, DLY} ).

The logic circuit (90) may include: a first correction logic gate ( _94P ) configured to pass the pulse of the intermediate set signal ( _COMPN ) and the pulse of the set correction signal ( _setnew ) to generate the correction set signal ( _COMP'N ); and a second correction logic gate ( _94N ) configured to pass the pulse of the intermediate reset signal ( _COMPP ) and the pulse of the reset correction signal ( _resetnew ) to generate the correction reset signal ( _COMP'P ).

The logic circuit (90) may include an edge detector circuit (92) configured to receive the digital output signal (PWM _RX ) and generate an edge detection signal (ED), the edge detection signal (ED) including a pulse at each commutation of the digital output signal (PWM _RX ) between a first logic value and a second logic value, wherein the edge detector circuit (92) may include: a delay circuit block configured to receive the digital output signal (PWM _RX ) and propagate the digital output signal (PWM _RX ) with a corresponding delay (T _ED ) to generate a delayed digital output signal; and an XOR gate configured to combine the digital output signal (PWM _RX ) and the delayed digital output signal to generate the edge detection signal (ED), wherein the corresponding delay (T _ED ) may be higher than the specific time interval (T _count ).

The intermediate reset signal (COMP _P ) and the first detection signal (COMP _{P, DLY} ) may be normally high, the active edge of the intermediate reset signal (COMP _P ) may be a falling edge, and the inactive edge of the intermediate reset signal (COMP _P ) may be a rising edge; the intermediate set signal (COMP _N ) and the second detection signal (COMP _{N, DLY} ) may be normally high, the active edge of the intermediate set signal (COMP _N ) may be a falling edge, and the inactive edge of the intermediate set signal (COMP _N ) may be a rising edge; the edge detection signal (ED) may be normally high and include a low pulse at each commutation of the digital output signal (PWM _RX ) between a first logic value and a second logic value; the first gating logic gate (93 _P ) may include an OR gate configured to apply an OR logic process to the first detection signal (COMP _{P, DLY} ) and the edge detection signal (ED) to generate the set correction signal (set _new ); the second gating logic gate (93 _N ) may include an OR gate configured to apply an OR logic process to the second detection signal (COMP _{N, DLY} ) and the edge detection signal (ED) apply OR logic processing to generate the reset correction signal (reset _new ); the first correction logic gate (94 _P ) may include an AND gate configured to apply AND logic processing to the set correction signal (set _new ) and the intermediate set signal (COMP _N ) to generate the correction set signal (COMP' _N ); and the second correction logic gate (94 _N ) may include an AND gate configured to apply AND logic processing to the reset correction signal (reset _new ) and the intermediate reset signal (COMP _P ) to generate the correction reset signal (COMP' _P ).

The first gating logic gate ( _93P ) may also be configured to apply OR logic processing to the intermediate reset signal ( _COMPP ) to generate the set correction signal ( _setnew ), and the second gating logic gate ( _93N ) may also be configured to apply OR logic processing to the intermediate set signal ( _COMPN ) to generate the reset correction signal ( _resetnew ).

The output control circuit may include a set-reset flip-flop (46) having a clock input terminal (C _P ) driven by the correction set signal (COMP' _N ) and a reset input terminal (C _D ) driven by the correction reset signal (COMP' _P ) to generate the digital output signal (PWM _RX ) at a data output terminal (Q) of the set-reset flip-flop (46).

The receiver circuit (104') may include an amplifier circuit (40) configured to receive the differential signal (Vd) and pass an amplified copy of the differential signal (Vd) to the first comparator circuit (42) and the second comparator circuit (44).

The receiver circuit (104') may include a driver circuit, the driver circuit including a half-bridge circuit, the half-bridge circuit being arranged between a positive power supply voltage pin (VH) and a reference power supply voltage pin (VL) and being driven by the digital output signal (PWM _RX ) to generate an output switching signal (PWM _OUT ).

An isolated driver device (10) can be summarized as comprising a first semiconductor die (10a) and a second semiconductor die (10b), wherein the first semiconductor die (10a) comprises: an input pin (101) configured to receive a digital input signal (PWM _IN ); a transmitter circuit (102) configured to receive the digital input signal (PWM _IN ) and generate a pair of complementary digital signals (OUT _P , OUT _N ), wherein a first digital signal (OUT _P ) of the complementary digital signals is a copy of the digital input signal (PWM _IN ) and is generated at a first output node of the transmitter circuit (102), and a second digital signal (OUT _N ) of the complementary digital signals is a copy of the digital input signal (PWM _IN ) and is generated at a first output node of the transmitter circuit (102). ) and is generated at the second output node of the transmitter circuit (102); and a galvanic isolation barrier including a first isolation capacitor (103P) and a second isolation capacitor (103N), the first isolation capacitor (103P) having a first terminal coupled to the first output node of the transmitter circuit (102), the second isolation capacitor (103N) having a first terminal coupled to the second output node of the transmitter circuit (102), so that a differential signal (Vd) is generated between the second terminal of the first isolation capacitor (103P) and the second terminal of the second isolation capacitor (103N), the differential signal (Vd) including a spike of a first polarity at each rising edge of the digital input signal (PWM _IN ) and a spike of a first polarity at each rising edge of the digital input signal (PWM _IN ). ); wherein the second semiconductor die (10b) comprises a receiver circuit (104') according to any of the preceding claims; and wherein a first input node of the receiver circuit (104') is electrically coupled to a second terminal of the first isolation capacitor (103P), and a second input node of the receiver circuit (104') is electrically coupled to a second terminal of the second isolation capacitor (103N) to receive the differential signal (Vd).

An electronic system can be summarized as comprising a processing unit and an isolated driver device (10), the processing unit being configured to generate the digital input signal (PWM _IN ) received by the isolated driver device (10).

A method of decoding a differential signal (Vd) into a digital output signal (PWM _RX ), the method can be summarized as comprising: receiving a differential signal (Vd) comprising a peak of a first polarity and a peak of a second polarity; generating an intermediate set signal (COMP _N ), the intermediate set signal (COMP _N ) comprising a pulse at each peak of the differential signal (Vd) having the first polarity; generating an intermediate reset signal (COMP _P ), the intermediate reset signal (COMP _P ) comprising a pulse at each peak of the differential signal (Vd) having the second polarity; detecting (92, ED) whether the digital output signal (PWM _RX ) switches between a first logic value and a second logic value; detecting (91 _P , COMP _{P , DLY} ) whether the intermediate reset signal (COMP _P ) comprises a pulse (SP1, SP3) having a duration greater than a specific time interval (T _count ); generating (93 _P ) a reset signal (COMP P ) when the digital output signal (PWM _RX ) switches between the first logic value and the second logic value and the intermediate reset signal (COMP _{P )} is reset to zero; ) includes a pulse (SP1, SP3) with a duration longer than the specific time interval (T _count ); generates (94 _P ) a correction set signal (COMP' N ) including pulses of the intermediate set signal (COMP _N ) and pulses of the set correction signal (set _new ); detects (91 _N , COMP _{N , DLY )} whether the intermediate set signal (COMP _N ) includes a pulse (SP2) with a duration longer than the specific time interval (T _count ); generates (93 _N ) a reset correction signal (reset new ) including pulses when the digital output signal (PWM _RX ) switches between the first logic value and the second logic value and at the same time the intermediate set signal (COMP _N ) includes a pulse (SP2) with a duration longer than the specific time interval ( _{T count} ); generates (94 _N ) a correction reset signal (COMP' _P ) including pulses of the intermediate reset signal (COMP _P ) and pulses of the reset correction signal (reset _new ); ); and asserting the digital output signal (PWM _RX ) in response to detecting a pulse in the correction set signal (COMP' _N ), and de-asserting the digital output signal (PWM _RX ) in response to detecting a pulse in the correction reset signal (COMP' _P ).

In light of the above detailed description, these and other changes can be made to the embodiments. Generally, in the following claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be understood to include all possible embodiments and the full range of equivalents to which these claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims (20)

1. A device of a receiver circuit, the receiver circuit comprising: a pair of input nodes configured to receive a differential signal therebetween, the differential signal comprising a spike of a first polarity and a spike of a second polarity; an output node configured to generate a digital output signal according to the differential signal; a first comparator circuit configured to receive the differential signal and generate an intermediate set signal, the intermediate set signal comprising a pulse at each peak of the differential signal having the first polarity; a second comparator circuit configured to receive the differential signal and generate an intermediate reset signal, the intermediate reset signal comprising a pulse at each peak of the differential signal having the second polarity; a logic circuit configured to receive the intermediate set signal, the intermediate reset signal, and the digital output signal, and generate a correction set signal and a correction reset signal; and An output control circuit is configured to receive the correction set signal and the correction reset signal, and is further configured to assert the digital output signal based on the correction set signal and the correction reset signal. 2. The device circuit of claim 1 , wherein the output circuit is configured to assert the digital output signal in response to detecting a pulse in the correction set signal, and to de-assert the digital output signal in response to detecting a pulse in the correction reset signal. 3. The device according to claim 2, wherein the logic circuit is configured to: detecting whether the digital output signal switches between a first logic value and a second logic value; detecting whether the intermediate reset signal includes a pulse having a duration greater than a specific time interval; generating a set correction signal including a pulse when the digital output signal switches between the first logic value and the second logic value and simultaneously the intermediate reset signal includes a pulse having a duration greater than the specific time interval; generating a correction setting signal including pulses of the intermediate setting signal and pulses of the setting correction signal; detecting whether the intermediate set signal includes a pulse having a duration longer than the specific time interval; generating a reset correction signal including a pulse when the digital output signal switches between the first logic value and the second logic value and simultaneously the intermediate set signal includes a pulse having a duration greater than the specific time interval; and A correction reset signal including pulses of the intermediate reset signal and pulses of the reset correction signal is generated. 4. The device according to claim 3, wherein the logic circuit comprises: a first asymmetric buffer circuit configured to receive the intermediate reset signal and generate a first detection signal by passing an active edge of the intermediate reset signal with a delay equal to the specific time interval and passing an inactive edge of the intermediate reset signal without a substantial delay; a first gating logic gate configured to pass the first detection signal when the digital output signal switches between the first logic value and the second logic value, and to shield the first detection signal otherwise, so as to generate the setting correction signal; a second asymmetric buffer circuit configured to receive the intermediate set signal and generate a second detection signal by passing an active edge of the intermediate set signal with a delay equal to the specific time interval and passing an inactive edge of the intermediate set signal without a substantial delay; and The second gating logic gate is configured to pass the second detection signal when the digital output signal switches between the first logic value and the second logic value, and to shield the second detection signal otherwise, so as to generate the reset correction signal. 5. The device of claim 4, wherein the first asymmetric buffer circuit comprises: a first inverter circuit comprising a first pull-up transistor and a first pull-down transistor alternately driven by the intermediate reset signal; a first capacitor coupled in parallel to the first pull-down transistor; and a second inverter circuit, coupled to the first inverter circuit, to generate the first detection signal; And wherein the second asymmetric buffer circuit comprises: a third inverter circuit, comprising a second pull-up transistor and a second pull-down transistor alternately driven by the intermediate set signal; a second capacitor coupled in parallel to the second pull-down transistor; and A fourth inverter circuit is coupled to the third inverter circuit to generate the second detection signal. 6. The device of claim 4, wherein the logic circuit comprises: a first correction logic gate configured to pass the pulse of the intermediate setting signal and the pulse of the setting correction signal to generate the correction setting signal; and The second correction logic gate is configured to pass the pulse of the intermediate reset signal and the pulse of the reset correction signal to generate the correction reset signal. 7. The device of claim 6, wherein the logic circuit comprises an edge detector circuit configured to receive the digital output signal and generate an edge detection signal, the edge detection signal comprising a pulse at each commutation of the digital output signal between a first logic value and a second logic value, wherein the edge detector circuit comprises: a delay circuit block configured to receive the digital output signal and propagate the digital output signal with a corresponding delay to generate a delayed digital output signal; and an XOR gate configured to combine the digital output signal and the delayed digital output signal to generate the edge detection signal, Wherein the corresponding delay is higher than the specific time interval. 8. The device according to claim 7, wherein: The intermediate reset signal and the first detection signal are normally high, the active edge of the intermediate reset signal is a falling edge, and the inactive edge of the intermediate reset signal is a rising edge; The intermediate setting signal and the second detection signal are normally high, the active edge of the intermediate setting signal is a falling edge, and the inactive edge of the intermediate setting signal is a rising edge; The edge detection signal is normally high and includes a low pulse at each commutation of the digital output signal between a first logic value and a second logic value; The first gating logic gate includes an OR gate configured to apply an OR logic process to the first detection signal and the edge detection signal to generate the set correction signal; The second gating logic gate includes an OR gate configured to apply an OR logic process to the second detection signal and the edge detection signal to generate the reset correction signal; The first correction logic gate comprises an AND gate configured to apply an AND logic process to the set correction signal and the intermediate set signal to generate the correction set signal; and The second correction logic gate includes an AND gate configured to apply an AND logic process to the reset correction signal and the intermediate reset signal to generate the correction reset signal. 9. The device according to claim 8, wherein The first gating logic gate is further configured to apply an OR logic process to the intermediate reset signal to generate the set correction signal, and The second gating logic gate is further configured to apply an OR logic process to the intermediate set signal to generate the reset correction signal. 10. The device of claim 3, wherein the output control circuit comprises a set-reset flip-flop having a clock input terminal driven by the correction set signal and a reset input terminal driven by the correction reset signal to generate the digital output signal at a data output terminal of the set-reset flip-flop. 11. The device of claim 3, comprising an amplifier circuit configured to receive the differential signal and pass an amplified copy of the differential signal to the first comparator circuit and the second comparator circuit. 12. The device of claim 3, comprising a driver circuit, the driver circuit comprising a half-bridge circuit, the half-bridge circuit being arranged between a positive power supply voltage pin and a reference power supply voltage pin and being driven by the digital output signal to generate an output switching signal. 13. The device of claim 1, comprising an isolated driver device, the isolated driver device comprising: A first semiconductor die comprising: An input pin configured to receive a digital input signal; a transmitter circuit configured to receive the digital input signal and: generating a first complementary digital signal at a first output node, the first complementary digital signal being a replica of the digital input signal; and generating a second complementary digital signal at a second output node, wherein the second complementary digital signal is a complementary signal of the digital input signal; a galvanic isolation barrier comprising a first isolation capacitor having a first terminal coupled to the first output node of the transmitter circuit and a second isolation capacitor having a first terminal coupled to the second output node of the transmitter circuit, whereby a differential signal is generated between the second terminal of the first isolation capacitor and the second terminal of the second isolation capacitor, the differential signal comprising a spike of a first polarity at each rising edge of the digital input signal and a spike of a second polarity at each falling edge of the digital input signal; and A second semiconductor die includes the receiver circuit, wherein a first input node of the receiver circuit is electrically coupled to a second terminal of the first isolation capacitor and a second input node of the receiver circuit is electrically coupled to a second terminal of the second isolation capacitor to receive the differential signal. 14. The device of claim 13, comprising a processing unit configured to generate the digital input signal received by the isolation driver device. 15. A method for decoding a differential signal into a digital output signal, the method comprising: receiving the differential signal; generating an intermediate setting signal based on the differential signal; generating an intermediate reset signal based on the differential signal; generating a set correction signal based on the digital output signal and the intermediate reset signal; generating a corrected setting signal based on the intermediate setting signal and the setting correction signal; generating a reset correction signal based on the digital output signal and the intermediate set signal; generating a correction reset signal based on the intermediate reset signal and the reset correction signal; and The digital output signal is generated based on the correction set signal and the correction reset signal; the digital output signal is asserted in response to detecting a pulse in the correction set signal, and the digital output signal is de-asserted in response to detecting a pulse in the correction reset signal. 16. The method of claim 15, wherein the differential signal comprises a spike of a first polarity and a spike of a second polarity, the method comprising: generating the intermediate set signal having a pulse at each peak of the differential signal having the first polarity; and The intermediate reset signal is generated to have a pulse at each peak of the differential signal having the second polarity. 17. The method according to claim 16, comprising: detecting whether the digital output signal switches between a first logic value and a second logic value; detecting whether the intermediate reset signal includes a pulse having a duration greater than a specific time interval; generating the set correction signal including a pulse when the digital output signal switches between the first logic value and the second logic value and simultaneously the intermediate reset signal includes a pulse having a duration greater than the specific time interval; generating the corrected set signal including pulses of the intermediate set signal and pulses of the set correction signal; detecting whether the intermediate set signal includes a pulse having a duration longer than the specific time interval; generating the reset correction signal having a pulse when the digital output signal switches between the first logic value and the second logic value and at the same time the intermediate set signal includes a pulse having a duration greater than the specific time interval; generating the correction reset signal including pulses of the intermediate reset signal and pulses of the reset correction signal; and The digital output signal is asserted in response to detecting a pulse in the correction set signal, and the digital output signal is de-asserted in response to detecting a pulse in the correction reset signal. 18. A receiver circuit comprising: A differential input including a first input node and a second input node; a first comparator circuit having an inverting input coupled to the first input node, and a non-inverting input coupled to the second input node; a second comparator circuit having an inverting input coupled to the second input node, and a non-inverting input coupled to the first input node; a logic circuit having a first input coupled to the output of the first comparator and a second input coupled to the output of the second comparator; and A flip-flop having a first input coupled to the first output of the logic circuit, a second input coupled to the second output of the logic circuit, and an output terminal, wherein the logic circuit includes a third input coupled to the output of the flip-flop. 19. The receiver circuit of claim 18, wherein the logic circuit comprises: A first inverter; A second inverter; a first OR gate including a first input coupled to the first input of the logic circuit, a second input coupled to the third input of the logic circuit, and a third input coupled to the output of the first inverter; and A second OR gate includes a first input coupled to the second input of the logic circuit, a second input coupled to the third input of the logic circuit, and a third input coupled to the output of the second inverter. 20. The receiver circuit of claim 19, wherein the logic circuit comprises: a first AND gate having a first input coupled to the output of the first OR gate, a second input coupled to the second input of the logic circuit, and an output corresponding to the first output of the logic circuit; and A second AND gate has a first input coupled to the output of the second OR gate, a second input coupled to the first input of the logic circuit, and an output corresponding to the second output of the logic circuit.