CN118157681B - Column-level low-error single-slope analog-to-digital conversion circuit, analog-to-digital converter and electronic equipment - Google Patents
Column-level low-error single-slope analog-to-digital conversion circuit, analog-to-digital converter and electronic equipment Download PDFInfo
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- H03M1/12—Analogue/digital converters
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Abstract
The invention provides a column-level low-error single-slope analog-to-digital conversion circuit, an analog-to-digital converter and electronic equipment, and relates to the field of integrated circuits. Comprising a plurality of cell groups and an on-chip phase-locked loop. Each unit group is electrically connected with a front-stage circuit arranged on one column in the array in a one-to-one correspondence manner. Each cell group comprises two latches, a counter and an encoder. A latch is electrically connected to the on-chip phase-locked loop, the pre-stage circuit, and the encoder. The counter is electrically connected with the on-chip phase-locked loop, the pre-stage circuit and the other latch. The output end of the encoder is electrically connected with another latch, and the other latch outputs the digital quantity obtained by quantization to the outside of the chip. The invention can not cause error code when the thickness quantization is consistent, improves the precision of quantization result, and reduces quantization nonlinearity caused by uneven quantization step length. The combination of the consistency of the thickness quantization does not cause error codes, so that the precision of the quantization result is improved on the whole, and the requirement of higher precision is met.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a column-level low-error single-slope analog-to-digital conversion circuit, an analog-to-digital converter, and an electronic device.
Background
At present, the thermal infrared imager has wide application in the thermal imaging fields such as medical imaging, monitoring, night vision and the like. In recent years, a read-out circuit (ROIC) with an on-chip analog-to-digital converter (ADC) has a shorter analog signal path than conventional analog readout due to its better noise performance and reduced system complexity.
With the development of science and technology, the readout circuit of the on-chip analog-to-digital converter has a larger-scale array structure at the same time of miniaturization. In general, when a column-level analog-to-digital conversion mode is adopted by a traditional large-scale array readout circuit, a single-slope analog-to-digital conversion circuit is adopted, but the single-slope analog-to-digital conversion often means that low power consumption and high precision cannot be compatible. I.e. consume a large amount of power consumption to obtain high precision, or consume less power consumption, but the precision is naturally lower.
Therefore, there is a need to provide a large-scale array readout circuit with low power consumption and high precision.
Disclosure of Invention
In view of the foregoing, the present invention has been made to provide a column-level low-error single-slope analog-to-digital conversion circuit, an analog-to-digital converter, and an electronic apparatus that solve or partially solve the foregoing problems.
The first aspect of the embodiment of the invention provides a column-level low-error single-slope analog-to-digital conversion circuit, which is applied to a large-scale array reading circuit and comprises a plurality of unit groups and an on-chip phase-locked loop, wherein the on-chip phase-locked loop comprises a phase-locked loop unit and a trigger unit;
Each unit group in the plurality of unit groups is electrically connected with a front-stage circuit arranged on one column in the array in a one-to-one correspondence manner;
One end of the phase-locked loop unit receives a high-frequency main clock signal, and the other end of the phase-locked loop unit is electrically connected with the input end of the trigger unit;
the output end of the trigger unit is electrically connected with each unit group;
each unit group comprises an N-bit latch, an M-bit counter, an encoder and an L-bit latch;
One input end of the N-bit latch is electrically connected with the output end of the trigger unit, the other input end of the N-bit latch is electrically connected with the front-stage circuit, and the output end of the N-bit latch is electrically connected with the input end of the encoder;
One input end of the M-bit counter is electrically connected with the output end of the trigger unit, the other input end of the M-bit counter is electrically connected with the front-stage circuit, and the output end of the M-bit counter is electrically connected with the input end of the L-bit latch and the input end of the encoder respectively;
The output end of the encoder is electrically connected with the input end of the L-bit latch, and the output end of the L-bit latch outputs the quantized digital quantity to the outside of the chip;
the value of N is determined by the number of bits of the on-chip phase-locked loop output signal, the value of L is determined by the requirement of quantization precision, and the value of M is determined by the value of L and the value of N together.
Optionally, the on-chip phase-locked loop is configured to generate a second delayed clock signal based on the high frequency master clock signal and transmit to a plurality of the cell groups;
Wherein the phase-locked loop unit is configured to generate a first delayed clock signal based on the high frequency master clock signal and transmit the first delayed clock signal to the flip-flop unit;
The trigger unit performs frequency division operation on the first delay clock signal to obtain the second delay clock signal and transmits the second delay clock signal to a plurality of unit groups;
the lowest bit signal in the second delay clock signal is independently transmitted to the M-bit counter;
the remaining second delayed clock signals, except the least significant bit signal, are transferred to the N-bit latch.
Optionally, the pre-stage circuit comprises a comparator;
the comparator comprises two input ends;
the two input ends are respectively configured to receive sampling signals, one input end is electrically connected with the single slope signal generation module, the other input end receives the single slope signal, and the sampling signals are signals obtained by sampling one column in the array;
The comparator is configured to generate a comparison signal according to the comparison result of the sampling signal and the single slope signal and transmit the comparison signal to the N-bit latch and the M-bit counter respectively.
Optionally, the N-bit latch is configured to obtain phases of the remaining second delayed clock signals based on the comparison signal, and form corresponding N-bit code values according to the phases and transmit the N-bit code values to the encoder.
Optionally, the M-bit counter is configured to obtain a period count of the lowest bit signal based on the comparison signal, form a corresponding M-bit code value according to the period count, and transmit the M-bit code value to the L-bit latch, and transmit the lowest bit code value of the M-bit code value to the encoder;
and the signal frequency corresponding to the lowest bit code value of the M-bit code value is the same as the frequency of the lowest bit signal.
Optionally, the encoder is configured to generate a corresponding binary code value based on the N-bit code value and a lowest bit code value of the M-bit code value for transmission to the L-bit latch.
Optionally, the L-bit latch is configured to perform synthesis processing on the M-bit code value and the binary code value, obtain the digital quantity, and output off-chip.
Alternatively, L is greater than M, and L is equal to or not equal to N;
N is equal to or different from M.
A second aspect of an embodiment of the present invention provides an analog-to-digital converter, comprising a column-level low-error single-slope analog-to-digital conversion circuit according to any one of the first aspects.
A third aspect of an embodiment of the invention provides an electronic device comprising an analog-to-digital converter as described in the second aspect.
The invention provides a column-level low-error single-slope analog-to-digital conversion circuit which is applied to a large-scale array reading circuit and comprises a plurality of unit groups and an on-chip phase-locked loop. The on-chip phase-locked loop includes a phase-locked loop unit and a flip-flop unit. Each unit group in the plurality of unit groups is electrically connected with a front-stage circuit arranged on one column in the array in a one-to-one correspondence manner, namely, each column is electrically connected with one unit group through one front-stage circuit.
One end of the phase-locked loop unit in the on-chip phase-locked loop receives a high-frequency main clock signal, the other end of the phase-locked loop unit is electrically connected with the input end of the trigger unit, and the output end of the trigger unit is electrically connected with each unit group.
Each cell group includes an N-bit latch, an M-bit counter, an encoder, and an L-bit latch. One input end of the N-bit latch is electrically connected with the on-chip phase-locked loop, the other input end of the N-bit latch is electrically connected with the front-stage circuit, and the output end of the N-bit latch is electrically connected with the input end of the encoder. One input end of the M-bit counter is electrically connected with the on-chip phase-locked loop, the other input end of the M-bit counter is electrically connected with the front-stage circuit, and the output end of the M-bit counter is electrically connected with the input end of the L-bit latch and the input end of the encoder respectively.
The output end of the encoder is electrically connected with the input end of the L-bit latch, and the output end of the L-bit latch outputs the quantized digital quantity to the outside of the chip. The value of N is determined by the number of bits of the output signal of the on-chip phase-locked loop, the value of L is determined by the requirement of quantization precision, and the value of M is determined by the value of L and the value of N together.
The invention provides a low-error single-slope analog-digital conversion circuit of a column level, creatively provides a structure of a unit group, and utilizes the structures of a latch and an encoder in the unit group to realize fine quantization by matching with a counter and realize coarse quantization by combining with the counter. The first delay clock signal generates the second delay clock signal through frequency division, so that the frequency of the lowest-order signal of the second delay clock signal is the same as the frequency of the signal corresponding to the lowest-order code value of the counter, and the phase delay between the lowest-order signal of the first delay clock signal and the signal corresponding to the lowest-order code value of the counter is eliminated. Therefore, the signal to be measured cannot fall in the delay range, so that when the lowest bit of the coarse quantization counter jumps, the fine quantization is also jumped at the same time, error code cannot be caused by consistency of the coarse quantization and the fine quantization, and the precision of the quantization result is improved.
And the inaccurate 50% duty ratio of the first delay signal is divided by two to obtain the signal with the accurate 50% duty ratio, namely the duty ratio of the second delay signal is 50%, so that the problem of uneven fine quantization step length is solved, and the quantization nonlinearity caused by uneven quantization step length is reduced. The combination of the consistency of the thickness quantization can not cause error codes, so that the precision of the quantization result is improved on the whole, the requirement of higher precision is met, and the practicability is higher.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a conventional large-scale array readout circuit;
FIG. 2 is a diagram of a 16-bit (CK 0-CK 15) encoding scheme and counter clock timing diagram for a prior art circuit architecture;
FIG. 3 is a schematic diagram of an exemplary column-level low-error single-slope analog-to-digital conversion circuit according to an embodiment of the present invention;
FIG. 4 is a diagram showing the 16-bit (CK 0'-CK 15') encoding scheme and counter clock timing for the proposed circuit architecture in an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The inventor finds that when the column-level analog-to-digital conversion mode is adopted in the traditional large-scale array readout circuit, a single-slope analog-to-digital conversion circuit is adopted, but the single-slope analog-to-digital conversion is often low in power consumption and high in precision and cannot be compatible. I.e. consume a large amount of power consumption to obtain high precision, or consume less power consumption, but the precision is naturally lower.
For example, with reference to the schematic architecture of a conventional large-scale array readout circuit shown in fig. 1. For each column in the array, the sampling unit samples a signal (typically, a voltage signal or an analog quantity) on the column to which the sampling unit is electrically connected to obtain a sampling signal V SH, and transmits the sampling signal V SH to the comparator, where the non-inverting terminal of the comparator is electrically connected to the single ramp signal generating module (not shown in fig. 1) and receives the single ramp signal V RAMP.
The comparator compares the sampling signal V SH with the single slope signal V RAMP to obtain a comparison signal CMP OUT and transmits the comparison signal CMP OUT to the counter, the counter continuously counts the comparison signal CMP OUT, the memory continuously samples and stores the count code value of the counter, and finally the digital quantity D OUT corresponding to the sampling signal is output to the outside of the chip.
As can be seen from fig. 1, the conventional column-level single-slope analog-to-digital converter needs to implement a counter at the column level. Each column has a counter, a memory, and both are continuously active. In the case of a fixed quantization time, the frequency of the clock signal determines the quantization accuracy. The high-frequency clock signal is difficult to transmit in the large-array-scale column-level circuit, and because of interference factors such as parasitic capacitance and the like which are unavoidable in the large-array-scale column-level circuit, the high-frequency clock signal can be distorted and deformed along with the continuous transmission, and the quantization precision is reduced. In order to prevent signal distortion and distortion of the high frequency clock, a large amount of power consumption is required. And a counter implementing a high frequency clock signal in a single column also means a huge power consumption. And therefore power consumption and accuracy are difficult to be compatible.
Since the high frequency clock is difficult to transmit and the quantization time of SSADC (single slope analog to digital converter) tends to be severe, this also results in insufficient quantization accuracy of SSADC. One solution to this problem is to use a method of adding a high-order counter to a low-order TDC to implement a high-speed and high-precision analog-to-digital converter. I.e. coarse quantization is achieved with a counter and fine quantization is achieved with a latch plus encoder (as such achieving the TDC function). However, since the high and low bits adopt different counting methods, such a circuit architecture can cause errors in code values, resulting in lower accuracy of quantization results.
The inventors have further studied and found that the above problem occurs because the segmented TDC is liable to cause bit errors due to the inconsistency of coarse and fine quantization at the time of the lowest bit transition of the coarse quantization counter due to the difference of the transmission paths of the counter clock and the multi-phase delay clock.
Taking the 16-bit (CK 0-CK 15) encoding scheme and the counter clock timing diagram of the prior circuit architecture shown in FIG. 2 as an example, there is a delay between the lowest bit CNT <0> of the coarse quantization counter and the lowest bit CK0 of the multi-phase delay clock signal, in the worst case, if the signal to be tested falls within the delay range, CNT <0> is flipped, but CK0 is unchanged, the bit number of the error code is as high as five bits, and the result of the error code directly affects the lower 5 bits of the overall quantization result.
Furthermore, as can be seen from fig. 2, the duty cycle of the multi-phase delay clock signal is not exactly 50%, because the multi-phase delay clock signal is generated by the on-chip phase locked loop, and the circuit structure of the on-chip phase locked loop itself causes a problem that the fine quantization step is not uniform, thereby affecting the linearity of the fine quantization.
Therefore, the problem that the delay exists between the lowest bit CNT <0> of the coarse quantization counter and the lowest bit CK0 in the multi-phase delay clock signal or the error code is caused, and the problem that the duty ratio of the multi-phase delay clock signal is not exactly 50% and the fine quantization step length is uneven so as to influence the fine quantization linearity generally results in lower precision of the quantization result of the analog-digital converter which adopts the method of the high-order counter and the low-order TDC to realize high speed and high precision.
In order to solve the problems, the inventor creatively provides a column-level low-error single-slope analog-to-digital conversion circuit, an analog-to-digital converter and electronic equipment. The technical scheme provided by the invention is explained and illustrated in detail below.
The column-level low-error single-slope analog-to-digital conversion circuit is particularly suitable for a large-scale array reading circuit, and comprises a plurality of unit groups and an on-chip phase-locked loop. The on-chip phase-locked loop includes a phase-locked loop unit and a flip-flop unit. Each unit group in the plurality of unit groups is electrically connected with a front-stage circuit arranged on one column in the array in a one-to-one correspondence manner, namely, each column is electrically connected with one unit group through one front-stage circuit. For an on-chip phase-locked loop, one end of a phase-locked loop unit receives a high-frequency main clock signal, the other end of the phase-locked loop unit is electrically connected with the input end of a trigger unit, and the output end of the trigger unit is electrically connected with each unit group. The on-chip phase locked loop is not one per column, but only needs to be single.
Each of the plurality of cell groups includes an N-bit latch, an M-bit counter, an encoder, and an L-bit latch. The N-bit latch has two input ends, one of which is electrically connected with the on-chip phase-locked loop, the other of which is electrically connected with the front-stage circuit, and the output end of the N-bit latch is electrically connected with the input end of the encoder.
The M-bit counter also has two input ends, one of which is electrically connected with the on-chip phase-locked loop, the other of which is electrically connected with the front-stage circuit, and the output end of the M-bit counter is electrically connected with the input end of the L-bit latch and the input end of the encoder respectively.
The output end of the encoder is electrically connected with the input end of the L-bit latch, and the output end of the L-bit latch outputs the quantized digital quantity to the outside of the chip.
For N, M, L, the value of N is determined by the number of bits of the output signal of the on-chip phase-locked loop, the value of L is determined by the requirement of quantization precision, and the value of M is determined by the value of L and the value of N together. For example, the number of bits of the output signal of the on-chip phase-locked loop is 8 bits, the value of N is 8-1=7 bits (because the rest of the second delayed clock signals except the lowest bit signal of the second delayed clock signal are transmitted to the 7-bit latch), the quantization precision is 18 bits, the value of L is 18, and the value of M is determined by the value of L18 and the value of N, if the value of N is 7, the corresponding output bit number of the encoder is 3, the value of M is 18-3=15, i.e. the value of M is 15. The value of M is explained and illustrated in more detail below, and is not described in detail.
In order to solve the problems of distortion and deformation of a high-frequency clock signal in the transmission process and low accuracy of a quantization result of a circuit architecture, an on-chip phase-locked loop is firstly arranged. It should be noted that, in some existing circuit structures, a phase-locked loop may be already provided or a structure capable of implementing a phase-locked loop function may be used, so that the structure or the phase-locked loop may be utilized, and an on-chip phase-locked loop is not required to be additionally provided, thereby indirectly saving cost and device occupation layout.
The on-chip phase-locked loop is configured to generate a delayed clock signal based on the high frequency master clock signal and transmit the delayed clock signal to the plurality of cell groups, i.e., to process the high frequency master clock signal to generate a corresponding second delayed clock signal. The phase-locked loop unit is configured to generate a first delayed clock signal based on a high-frequency master clock signal and transmit the first delayed clock signal to the trigger unit, that is, there is a delay between the lowest-order signal of the first delayed clock signal generated by the phase-locked loop unit and the lowest-order signal of the M-bit counter. The flip-flop unit is preferably formed by a D flip-flop, which performs frequency division operation on the first delayed clock signal to obtain a second delayed clock signal and transmits the second delayed clock signal to the plurality of cell groups. The frequency between the lowest-order signal of the second delayed clock signal after frequency division operation and the signal of the lowest order of the M-bit counter is the same, and no delay exists between the lowest-order signal and the signal, namely, the delay is eliminated.
The least significant bit of the generated second delayed clock signals is transferred to the M-bit counter alone, and the remaining second delayed clock signals except the least significant bit are transferred to the N-bit latch. For example, if the corresponding first delayed clock signal is CK0-CK15, then the second delayed signal is defined as CK0' -CK15', the lowest bit signal CK0' is transmitted to the M-bit counter alone, and the remaining second delayed clock signals CK1' -CK15' are transmitted to the N-bit latch.
The pre-stage circuit can be realized by using a comparator, wherein the comparator comprises two input ends, one of the two input ends is respectively configured to receive a sampling signal, the other input end is electrically connected with a single slope signal generating module and is used for receiving a single slope signal, and the sampling signal is obtained by sampling one column in the array. Typically, the sampling unit obtains and transmits the signal to the inverting terminal of the comparator, and the single ramp signal is received by the non-inverting terminal of the comparator.
The comparator is configured to generate a comparison signal according to the comparison result of the sampling signal and the single ramp signal and transmit the comparison signal to the N-bit latch and the M-bit counter respectively.
The N-bit latch is configured to derive phases of the remaining second delayed clock signals based on the comparison signal, e.g. the remaining second delayed clock signals are CK1'-CK15', then the N-bit latch is configured to derive respective phases of CK1'-CK15' based on the comparison signal and form corresponding N-bits, i.e. 15-bit code values, from the respective phases of CK1'-CK15' for transmission to the encoder.
The encoder is configured to generate a corresponding binary code value based on the N-bit code value and the lowest bit code value of the M-bit code value for transmission to the L-bit latch. Since the encoder outputs a binary code value based on the N-bit code value, the encoder needs to decide how many bit code values it converts into how many bit binary code values according to the value of n+1. For example, N is 15, and the lowest bit code value of the M-bit counter code value is also transmitted to the encoder, so the encoder corresponds to a binary code value of 4, i.e., the encoder is a 16-4 encoder, and, assuming N is 31 (the second delay clock signal is 32 bits), the encoder corresponds to a binary code value of 5, i.e., the encoder is a 32-5 encoder, according to the 15+1=16 structure. I.e. n+1=2 W, W is the number of bits of the binary code value.
The M-bit counter is configured to obtain the period of the lowest bit signal based on the comparison signal, i.e. the M-bit counter counts the period of the lowest bit signal, and forms a corresponding M-bit code value according to the obtained period count for transmission to the L-bit latch, and transmits the lowest bit code value of the M-bit code value to the encoder. The value of N is determined by the number of bits of the output signal of the on-chip pll, the value of L is determined by the quantization precision requirement, and the value of M is determined by both the value of L and the value of N, since the value of L is determined by the quantization precision requirement, that is, the quantization precision requirement is 8 bits, then l=8, and the quantization precision requirement is 16 bits, then l=16.
And the L-bit latch is configured to synthesize the M-bit code value and the binary code value to obtain a digital quantity and output the digital quantity out of the chip. Thus l=m+ the number of bits of the binary code value, i.e. m=l-the number of bits of the binary code value. It is known that L is greater than M and that L is equal to or different from N, and that N is equal to or different from M. For example, if l=16 and n=15, the encoder is a 16-4 encoder, the number of bits of the binary code value is 4, and if m=12, if l=16 and n=7, the encoder is an 8-3 encoder, the number of bits of the binary code value is 3, and if m=13, the rest of the cases are not repeated.
In the overall structure, each unit group can be understood as a counter-plus-TDC circuit formed by an M-bit counter, an N-bit latch, an L-bit latch and an encoder. This is because the use of a single counter in a conventional configuration results in high power consumption, and therefore the present invention employs a column-level counter and a TDC divide signal, which can significantly reduce the clock frequency of the counter, thereby greatly reducing the power consumption of the counter relative to the conventional configuration.
In order to better understand the structure of the above-mentioned column-level low-error single-slope analog-to-digital conversion circuit, referring to a schematic structural diagram of an exemplary column-level low-error single-slope analog-to-digital conversion circuit shown in fig. 3, for simplicity of illustration, fig. 3 is exemplarily shown with n=15, m=12, and l=16 as examples, and the condition of greater quantization accuracy requirement is obtained by simple reasoning with reference to the structure shown in fig. 3, which is not repeated.
In fig. 3, V TH represents a sampling signal, V P represents a single ramp signal, and both are transmitted into the comparator as two input signals of the comparator in the preceding stage circuit. The comparator generates a comparison signal V O according to the comparison result of the sampling signal V TH and the single slope signal V P.
MCK in fig. 3 represents a master clock signal that generates a second delayed clock signal CK0'-CK15' through an On-chip phase-locked loop On-chip DLL (including a phase-locked loop unit and a flip-flop unit, not specifically identified for simplicity of illustration), wherein the remaining second delayed clock signals CK1'-CK15' except the lowest bit CK0 'are transmitted to the 15-bit Latch in the upper left corner of the dummy frame, and the lowest bit CK0' of the second delayed clock signal is separately transmitted to the 12-bit Counter in the lower left corner of the dummy frame.
The 15-bit Latch in the upper left corner of the virtual frame processes the delayed clock signals CK1'-CK15' to obtain respective phases, and forms corresponding code values O F <1:15> according to the respective phases, and transmits the corresponding code values O F to the 16-4 encoder 16-4Decoder in the upper right corner of the virtual frame. The 12-bit Counter at the left lower corner in the virtual frame counts the period of the lowest bit CK0' of the delayed clock signal, forms a corresponding code value CNT <0:11> according to the period counting result, transmits the code value CNT <0> to the 16-bit Latch at the right lower corner in the virtual frame, and transmits the lowest bit code value CNT <0> of the 12-bit code value to the 16-4 encoder 16-4Decoder.
The code value O F <1:16> and CNT <0> are processed by the 16-4 encoder 16-4Decoder in the upper right corner of the dummy frame to obtain the corresponding binary code value Dout F <0:3>, which is also transmitted to the 16-bit Latch in the lower right corner of the dummy frame.
And finally, synthesizing the code value CNT <0:11> and the binary code value Dout F <0:3> by a 16-bit Latch at the right lower corner in the virtual frame to form a digital quantity OUT <0:15> corresponding to a target column adoption signal (which is an analog quantity) and outputting the digital quantity OUT outside the chip.
Referring to the 16-bit (CK 0'-CK 15') encoding scheme and counter clock timing diagram of the circuit architecture of the present invention shown in FIG. 4, the timing diagram of FIG. 2 is incorporated herein for better comparison. The upper Traditional Coding Method is the 16-bit (CK 0-CK 15) encoding scheme under the existing circuit architecture, and the lower Proposed Coding Method is the 16-bit (CK 0'-CK 15') encoding scheme under the circuit architecture of the present invention
As can be seen from fig. 4, the frequency between the lowest bit signal CK0' of the second delayed clock signal and the signal of the lowest bit CNT <0> of the 12-bit counter is the same, and there is no delay, i.e. the delay is eliminated. The lowest bit CK0' of the new delay clock can be replaced with the lowest bit CNT <0> of the counter for decoding to control the bit error within 1 bit. And, although the duty ratio of the multi-phase first delay clocks CK0-CK15 is not exactly 50%, the period of CK0-CK15 is 8ns, so after the flip-flop unit performs the frequency division, the duty ratio of the new delay clocks CK0'-CK15' is 50%, thereby reducing the quantization nonlinearity caused by the uneven quantization step.
Through the structure, the whole column-level low-error single-slope analog-to-digital conversion circuit realizes quantization by using one unit group for each column in the array. The structure of two latches and the encoder is utilized in the unit group, the fine quantization is realized by matching with the counter, and the coarse quantization realized by combining with the single slope signal improves the quantization precision and meets the requirement of high precision. By adopting the architecture of the column-level counter and the TDC frequency division signal, the clock frequency of the counter is obviously reduced, so that the power consumption of the counter part is greatly reduced. Thereby achieving the high-precision quantization requirement on the basis of realizing lower power consumption.
Based on the column-level low-error single-slope analog-to-digital conversion circuit, the embodiment of the invention also provides an analog-to-digital converter, which comprises the column-level low-error single-slope analog-to-digital conversion circuit.
Based on the column-level low-error single-slope analog-to-digital conversion circuit, the embodiment of the invention also provides electronic equipment, which comprises the analog-to-digital converter.
Through the embodiment, the column-level low-error single-slope analog-to-digital conversion circuit is applied to a large-scale array reading circuit and comprises a plurality of unit groups and an on-chip phase-locked loop. The on-chip phase-locked loop includes a phase-locked loop unit and a flip-flop unit. Each unit group in the plurality of unit groups is electrically connected with a front-stage circuit arranged on one column in the array in a one-to-one correspondence manner, namely, each column is electrically connected with one unit group through one front-stage circuit.
One end of the phase-locked loop unit in the on-chip phase-locked loop receives a high-frequency main clock signal, the other end of the phase-locked loop unit is electrically connected with the input end of the trigger unit, and the output end of the trigger unit is electrically connected with each unit group.
Each cell group includes an N-bit latch, an M-bit counter, an encoder, and an L-bit latch. One input end of the N-bit latch is electrically connected with the on-chip phase-locked loop, the other input end of the N-bit latch is electrically connected with the front-stage circuit, and the output end of the N-bit latch is electrically connected with the input end of the encoder. One input end of the M-bit counter is electrically connected with the on-chip phase-locked loop, the other input end of the M-bit counter is electrically connected with the front-stage circuit, and the output end of the M-bit counter is electrically connected with the input end of the L-bit latch and the input end of the encoder respectively.
The output end of the encoder is electrically connected with the input end of the L-bit latch, and the output end of the L-bit latch outputs the quantized digital quantity to the outside of the chip. The value of N is determined by the number of bits of the output signal of the on-chip phase-locked loop, the value of L is determined by the requirement of quantization precision, and the value of M is determined by the value of L and the value of N together.
The invention provides a low-error single-slope analog-digital conversion circuit of a column level, creatively provides a structure of a unit group, and utilizes the structures of a latch and an encoder in the unit group to realize fine quantization by matching with a counter and realize coarse quantization by combining with the counter. The first delay clock signal generates the second delay clock signal through frequency division, so that the frequency of the lowest-order signal of the second delay clock signal is the same as the frequency of the signal corresponding to the lowest-order code value of the counter, and the phase delay between the lowest-order signal of the first delay clock signal and the signal corresponding to the lowest-order code value of the counter is eliminated. Therefore, the signal to be measured cannot fall in the delay range, so that when the lowest bit of the coarse quantization counter jumps, the fine quantization is also jumped at the same time, error code cannot be caused by consistency of the coarse quantization and the fine quantization, and the precision of the quantization result is improved.
And the inaccurate 50% duty ratio of the first delay signal is divided by two to obtain the signal with the accurate 50% duty ratio, namely the duty ratio of the second delay signal is 50%, so that the problem of uneven fine quantization step length is solved, and the quantization nonlinearity caused by uneven quantization step length is reduced. The combination of the consistency of the thickness quantization does not cause error codes, so that the precision of the quantization result is improved on the whole, and the requirement of higher precision is met.
Meanwhile, the quantization is realized by using a separate counter structure for each single column in the traditional large-scale array, so that the clock frequency of the counter is obviously reduced, and the power consumption of a counter part is greatly reduced. Therefore, the high-precision quantification requirement is achieved on the basis of low power consumption, and the method has high practicability.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are to be protected by the present invention.
Claims (9)
1. The column-level low-error single-slope analog-to-digital conversion circuit is characterized by being applied to a large-scale array reading circuit, and comprises a plurality of unit groups and an on-chip phase-locked loop, wherein the on-chip phase-locked loop comprises a phase-locked loop unit and a trigger unit;
Each unit group in the plurality of unit groups is electrically connected with a front-stage circuit arranged on one column in the array in a one-to-one correspondence manner;
One end of the phase-locked loop unit receives a high-frequency main clock signal, and the other end of the phase-locked loop unit is electrically connected with the input end of the trigger unit;
the output end of the trigger unit is electrically connected with each unit group;
each unit group comprises an N-bit latch, an M-bit counter, an encoder and an L-bit latch;
One input end of the N-bit latch is electrically connected with the output end of the trigger unit, the other input end of the N-bit latch is electrically connected with the front-stage circuit, and the output end of the N-bit latch is electrically connected with the input end of the encoder;
One input end of the M-bit counter is electrically connected with the output end of the trigger unit, the other input end of the M-bit counter is electrically connected with the front-stage circuit, and the output end of the M-bit counter is electrically connected with the input end of the L-bit latch and the input end of the encoder respectively;
The output end of the encoder is electrically connected with the input end of the L-bit latch, and the output end of the L-bit latch outputs the quantized digital quantity to the outside of the chip;
Wherein, the value of N is determined by the number of bits of the output signal of the on-chip phase-locked loop, the value of L is determined by the requirement of quantization precision, and the value of M is determined by the value of L and the value of N together;
The pre-stage circuit comprises a comparator;
the comparator comprises two input ends;
the two input ends are respectively configured to receive sampling signals, one input end is electrically connected with the single slope signal generation module, the other input end receives the single slope signal, and the sampling signals are signals obtained by sampling one column in the array;
The comparator is configured to generate a comparison signal according to the comparison result of the sampling signal and the single slope signal and transmit the comparison signal to the N-bit latch and the M-bit counter respectively.
2. The column-level low-error single-slope analog-to-digital conversion circuit of claim 1, wherein said on-chip phase-locked loop is configured to generate a second delayed clock signal based on said high-frequency master clock signal and transmit to a plurality of said groups of cells;
Wherein the phase-locked loop unit is configured to generate a first delayed clock signal based on the high frequency master clock signal and transmit the first delayed clock signal to the flip-flop unit;
The trigger unit performs frequency division operation on the first delay clock signal to obtain the second delay clock signal and transmits the second delay clock signal to a plurality of unit groups;
the lowest bit signal in the second delay clock signal is independently transmitted to the M-bit counter;
the remaining second delayed clock signals, except the least significant bit signal, are transferred to the N-bit latch.
3. The column-level low-error single-slope analog-to-digital conversion circuit of claim 2, wherein the N-bit latch is configured to derive phases of the remaining second delayed clock signals based on the comparison signal and form corresponding N-bit code values from the phases for transmission to the encoder.
4. The column-level low-error single-slope analog-to-digital conversion circuit of claim 3, wherein the M-bit counter is configured to obtain a cycle count of the lowest bit signal based on the comparison signal, form a corresponding M-bit code value according to the cycle count, transmit the M-bit code value to the L-bit latch, and transmit the lowest bit code value of the M-bit code value to the encoder;
and the signal frequency corresponding to the lowest bit code value of the M-bit code value is the same as the frequency of the lowest bit signal.
5. The column-level low-error single-slope analog-to-digital conversion circuit of claim 4, wherein the encoder is configured to generate a corresponding binary code value for transmission to the L-bit latch based on the N-bit code value and a lowest bit code value of the M-bit code value.
6. The column-level low-error single-slope analog-to-digital conversion circuit of claim 5, wherein said L-bit latch is configured to synthesize said M-bit code value and said binary code value, obtain said digital quantity, and output off-chip.
7. The column-level low-error single-slope analog-to-digital conversion circuit of claim 1, wherein L is greater than M and L is equal to or different from N;
N is equal to or different from M.
8. An analog to digital converter comprising a column level low error single slope analog to digital conversion circuit as claimed in any of claims 1 to 7.
9. An electronic device comprising an analog-to-digital converter as claimed in claim 8.
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| CN114726375A (en) * | 2022-03-09 | 2022-07-08 | 北方广微科技有限公司 | Analog-to-digital converter and control method thereof |
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