CN118157436B - A power clamp circuit - Google Patents
A power clamp circuit Download PDFInfo
- Publication number
- CN118157436B CN118157436B CN202410159767.2A CN202410159767A CN118157436B CN 118157436 B CN118157436 B CN 118157436B CN 202410159767 A CN202410159767 A CN 202410159767A CN 118157436 B CN118157436 B CN 118157436B
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- power supply
- supply tube
- voltage
- circuit
- resistor
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- 238000001514 detection method Methods 0.000 claims abstract description 33
- 239000003990 capacitor Substances 0.000 claims description 17
- 230000015556 catabolic process Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0016—Control circuits providing compensation of output voltage deviations using feedforward of disturbance parameters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Measurement Of Current Or Voltage (AREA)
- Electronic Switches (AREA)
Abstract
The embodiment of the application provides a power clamping circuit, when the voltage of the second end of a second power supply tube is larger than a preset threshold voltage, the voltage of the first end of the second power supply tube is reduced by the detection circuit flowing through the first resistor after the detection circuit is conducted to generate current, and then the voltage of the second end of the second power supply tube is reduced.
Description
Technical Field
Embodiments of the present application relate to clamping circuits, and more particularly to a power clamping circuit.
Background
When using a power supply to supply power to other devices, the voltage required by the power supply to supply power to the devices is required, as shown in fig. 1, if the voltage of the power supply needs to be controlled in a required voltage range, the circuit of fig. 1 is subject to two factors, namely (1) the breakdown voltage of the zener diode may be different under different processes, (2) the PMOS devices with low on voltage and the zener diode need to be used in a matched manner, the PMOS devices with low on voltage of different process platforms need to be additionally provided with an additional mask, and the voltage of the circuit in the prior art is reduced when the circuit is turned off from M3 to M4, so that a new scheme is proposed based on the above problems.
Disclosure of Invention
The embodiment of the application aims to alleviate or solve the problems in the prior art.
The embodiment of the application provides a power clamping circuit, which comprises a biasing circuit, a first power supply tube, a second power supply tube, a charge pump and a detection circuit, wherein the biasing circuit is connected with the first power supply tube;
the output end of the bias circuit is connected with the first end of the first power supply tube, and the second end of the first power supply tube is connected with the input end of the charge pump;
The output end of the charge pump is connected with the first end of a second power supply tube through a first resistor, and the second end of the second power supply tube is connected with the voltage output circuit;
The input end of the bias circuit, the third end of the first power supply tube and the third end of the second power supply tube are respectively connected with a power supply, and the bias circuit and the charge pump are respectively connected with a grounding end;
one end of the detection circuit is connected with a common end between the voltage output circuit and the second end of the second power supply tube, and the other end of the detection circuit is connected with the common end between the first resistor and the first end of the second power supply tube;
when the voltage of the second end of the second power supply tube is larger than a preset threshold voltage, the detection circuit is conducted to generate current and then flows through the first resistor to reduce the voltage of the first end of the second power supply tube, and then the voltage of the second end of the second power supply tube is reduced.
As a preferred embodiment of the present application, a second resistor is serially arranged on a circuit where the bias circuit is located so as to stabilize the voltage output by the power supply;
And a common end between the second resistor and the bias circuit is connected with the first end of the first power supply tube.
As a preferred embodiment of the present application, the bias circuit is composed of a plurality of NMOS tubes or PMOS tubes which are mutually connected in series.
As a preferred embodiment of the present application, the circuit further includes a first protection circuit;
One end of the first protection circuit is connected with the common end between the output end of the charge pump and the first resistor, and the other end of the first protection circuit is connected with the grounding end.
As a preferred embodiment of the present application, the first protection circuit includes a first capacitor and a zener diode;
one end of the first capacitor and one end of the zener diode are connected with a common end between the output end of the charge pump and the first resistor;
The other end of the first capacitor and the other end of the zener diode are both connected with the grounding end.
As a preferred embodiment of the present application, the detection circuit includes a third resistor, a detection branch and a current mirror sequentially connected in series;
The first end of the third resistor is connected with the common end between the second end of the second power supply tube and the voltage output circuit;
the second end of the third resistor is connected with the current mirror through a detection branch, and the current mirror is connected with a common end between the first resistor and the first end of the second power supply tube;
The current mirror is also connected with a grounding end.
As a preferred embodiment of the present application, a second protection circuit is further disposed between the current mirror and the common terminal between the first resistor and the first terminal of the second power supply tube.
As a preferred embodiment of the present application, the detection branch includes NMOS transistors that are serially connected to each other.
As a preferred embodiment of the present application, the voltage output circuit includes a second capacitor.
Compared with the prior art, when the voltage of the second end of the second power supply tube is larger than the preset threshold voltage, the detection circuit conducts the generated current and then divides the voltage through the first resistor so as to reduce the voltage of the first end of the second power supply tube and further reduce the voltage of the second end of the second power supply tube.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. Some specific embodiments of the application will be described in detail hereinafter by way of example and not by way of limitation with reference to the accompanying drawings. The same reference numbers in the drawings denote the same or similar parts or portions, and it will be understood by those skilled in the art that the drawings are not necessarily drawn to scale, in which:
FIG. 1 is a block diagram of a prior art power clamp circuit;
FIG. 2 is a graph of output voltage variation in the prior art;
FIG. 3 is a block diagram of a power clamp circuit according to an embodiment of the present application.
Detailed Description
In order to enable those skilled in the art to better understand the present application, the following description will make clear and complete descriptions of the technical solutions according to the embodiments of the present application with reference to the accompanying drawings. It will be apparent that the described embodiments are merely some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
As shown in fig. 1, in a power clamp circuit provided in the prior art, M1 and M2 are low on voltage Vth PMOS, M3 is high voltage PMOS, M4 is high voltage NMOS, breakdown voltage Vz of zener diode is 5.6V, when VIN < vz+vth (M1), M3 is turned on, clamping voltage vcamp is approximately equal to power supply voltage input voltage VIN, after VIN > vz+vth (M1), zener diode D2 breaks down, M1 and M2 turn on, resulting in M3 turn off, at which time zener diode D1 breaks down, clamping voltage VCLAMP is finally clamped at Vz-Vth (M4), and output voltage can be guaranteed to be lower than 6V;
However, this scheme is limited by two factors, (1) the breakdown voltage of the zener diode may be different in different processes, and (2) the PMOS device with low on voltage needs to be used in combination with the zener diode, and additional masks are required to be added to the PMOS device with low on voltage in different process platforms.
The prior art circuit will have a voltage drop when M3 turns off to M4 turns off (see fig. 2), and a new solution is proposed based on the above-mentioned problem.
As shown in fig. 3, the embodiment of the application provides a power clamp circuit, which comprises a bias circuit 01, a first power supply tube M15, a second power supply tube M16, a charge pump 02 and a detection circuit 03;
In the embodiment of the present application, the first power supply tube M15 and the second power supply tube M16 are NMOS tubes.
The output end of the bias circuit 01 is connected with the grid electrode of the first power supply tube M15, and the source electrode of the first power supply tube M15 is connected with the input end of the charge pump 02;
The output end of the charge pump 02 is connected with the grid electrode of a second power supply tube M16 through a first resistor R5, and the source electrode of the second power supply tube M16 is connected with the voltage output circuit;
the input end of the bias circuit 01, the drain electrode of the first power supply tube M15 and the drain electrode of the second power supply tube M16 are respectively connected with a power supply, and the bias circuit 01 and the charge pump 02 are respectively connected with a grounding end;
one end of the detection circuit 03 is connected with a common end between the voltage output circuit and the source electrode of the second power supply tube M16, and the other end of the detection circuit 03 is connected with a common end between the first resistor R5 and the gate electrode of the second power supply tube M16;
when the source voltage of the second power supply tube M16 is greater than the preset threshold voltage, the detection circuit 03 is turned on to generate a current and then flows through the first resistor R5 to reduce the voltage of the gate of the second power supply tube M16, thereby reducing the source voltage of the second power supply tube M16.
In the present application, the charge pump 02 includes the switch S1A, S2A, S3B, S B and the flying capacitor C5, when in the charge phase of the charge pump 02, the switches S1A and S2A are turned on, the switches S3B and S4B are turned off to charge the flying capacitor C5, when in the discharge phase of the charge pump 02, the switches S3B and S4B are turned on, the switches S1A and S2A are turned off to charge the capacitor C4 through the flying capacitor C5, and the source of the first power supply tube M15 is connected to the gate of the second power supply tube M16 through the charge pump 02 to supply power to the voltage output circuit.
According to the embodiment of the application, the first power supply tube M15 is controlled to be at the working point by the bias circuit 01, the working point is that the grid voltage of the first power supply tube M15 is enabled to be VDDL through the output voltage of the first power supply tube M15, then the VDDL is boosted through the charge pump 02, the output voltage of the charge pump 02 is transmitted to the voltage output circuit through the second power supply tube M16, the size of the source voltage of the second power supply tube M16 is detected through the detection circuit 03, if the source voltage of the second power supply tube M16 is larger, the detection circuit 03 conducts generated current and then conducts the generated current to conduct voltage division through the first resistor R5, so that the voltage of the grid electrode of the second power supply tube M16 is reduced, and the source voltage of the second power supply tube M16 is reduced. Preferably, the bias circuit 01 is composed of a plurality of NMOS (M5-M8) or PMOS (M5-M8) tubes which are mutually connected in series.
In a preferred embodiment of the present application, a second resistor R4 is serially arranged on the circuit where the bias circuit 01 is located so as to stabilize the voltage output by the power supply, and a common terminal between the second resistor R4 and the bias circuit 01 is connected to the first terminal of the first power supply tube M15.
As a preferred embodiment of the present application, the circuit further includes a first protection circuit 04;
One end of the protection circuit 04 is connected with a common end between the output end of the charge pump 02 and the first resistor R5, and the other end of the first protection circuit 04 is connected with a grounding end.
Further, the protection circuit 04 includes a first capacitor C5 and a zener diode D3;
One end of the first capacitor C5 and one end of the zener diode D3 are connected with a common end between the output end of the charge pump 02 and the first resistor R5, and the other end of the first capacitor C5 and the other end of the zener diode D3 are connected with a grounding end.
In the embodiment of the application, the output voltage of the charge pump 02 is transmitted to the voltage output circuit through the second power supply tube M16, the magnitude of the source voltage of the second power supply tube M16 is detected by the detection circuit 03, and if the source voltage of the second power supply tube M16 is larger, the detection circuit 03 is conducted to generate current and then flows through the first resistor R5 to reduce the gate voltage of the M16, so that the purpose of stabilizing the output voltage is achieved.
As a preferred embodiment of the present application, the detection circuit 03 includes a third resistor R6, a detection branch, and a current mirror sequentially connected in series;
The first end of the third resistor R6 is connected with the common end between the second end of the second power supply tube M16 and the voltage output circuit, a second protection circuit is further arranged between the current mirror and the common end between the first resistor R5 and the first end of the second power supply tube M16, and the current mirror is further connected with the grounding end.
In the embodiment of the application, the output voltage of the charge pump 02 is transmitted to the voltage output circuit through the second power supply tube M16, the magnitude of the source voltage of the second power supply tube M16 is detected by the detection circuit 03, if the source voltage of the second power supply tube M16 exceeds the preset threshold voltage, the detection branch is turned on, the current mirror mirrors the current, and then the current is divided by the first resistor R5, so as to reduce the voltage of the grid electrode of the second power supply tube M16, and further reduce the source voltage of the second power supply tube M16. In the embodiment of the application, as the second power supply tube M16 and the first resistor R5 are in a high voltage region, the current mirror is in a low voltage region, the current mirror can be protected by the high voltage protection circuit M13, the high voltage protection circuit is an NMOS tube M13, and the current mirror is composed of NMOS tubes M9 and M14.
Preferably, the detection branch comprises NMOS tubes (M9-M12) which are arranged in series with each other.
As a preferred embodiment of the present application, the voltage output circuit includes a second capacitor C3.
The output voltage is filtered by the second capacitor C3.
When the voltage v_amp of the voltage output circuit is increased to M9, M10, M11 and M12, the voltage drop generated on R5 by the voltage v_amp of the second power supply tube M16 will decrease (vgate=vz- (Vclamp-4 x Vth 2) R5/R6), wherein Vth2 is the on voltage of M9, M10, M11 and M12, vz is the breakdown voltage of zener diode D3, and the voltage Vclamp size of the voltage output circuit is set to be approximately equal to Vin, when Vin increases to cause the voltage Vclamp of the voltage output circuit to rise to M9, M10, M11 and M12, the voltage v_amp of the voltage output circuit will decrease (vgate=vz-4 x Vth 2) on the voltage v_5/R6), and when Vth1 is not in the voltage drop of the voltage output circuit is detected in the current embodiment, as in the voltage detection scheme of the application, the voltage of the voltage output circuit is not shown in the voltage detection scheme 1, the voltage drop of the voltage detection circuit is turned off when Vth1 is implemented in the voltage detection circuit.
It should be noted that the above embodiments are merely for illustrating the technical solution of the present application and not for limiting the same, and although the present application has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that the technical solution described in the above embodiments may be modified or some or all of the technical features may be equivalently replaced, and these modifications or substitutions do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the present application.
Claims (6)
1. A power clamp circuit is characterized by comprising a bias circuit, a first power supply tube, a second power supply tube, a charge pump, a detection circuit and a voltage output circuit;
The bias circuit comprises four NMOS tubes connected in series, the grid electrode and the drain electrode of each NMOS tube are connected with each other, the grid electrode and the drain electrode of the uppermost NMOS tube in the bias circuit are connected with the grid electrode of the first power supply tube and one end of the second resistor, the other end of the second resistor is connected with the drain electrode of the first power supply tube, and the source electrode of the lowermost NMOS tube is grounded;
The first power supply tube source electrode is connected with the charge pump input end, the charge pump output end is connected with the second power supply tube grid electrode through a first resistor, the second power supply tube source electrode is connected with the voltage output circuit, the second power supply tube drain electrode is connected with a power supply, and the charge pump is also connected with a grounding end;
The detection circuit comprises a third resistor, a detection branch and a current mirror which are sequentially connected in series, wherein a first end of the third resistor is connected with a source electrode of the second power supply tube, a second end of the third resistor is connected with the current mirror through the detection branch, the current mirror is also connected with a common end between the first resistor and a grid electrode of the second power supply tube, and the current mirror is also connected with a grounding end;
When the source voltage of the second power supply tube is larger than the preset threshold voltage, the detection circuit is conducted to generate current and then flows through the first resistor to reduce the voltage of the grid electrode of the second power supply tube, and then the source voltage of the second power supply tube is reduced.
2. The power clamp of claim 1, wherein the bias circuit is comprised of a plurality of PMOS transistors in series with each other.
3. The power clamp of claim 1, wherein the circuit further comprises a first protection circuit;
One end of the first protection circuit is connected with the common end between the output end of the charge pump and the first resistor, and the other end of the first protection circuit is connected with the grounding end.
4. The power clamp of claim 3, wherein the first protection circuit includes a first capacitor and a zener diode;
one end of the first capacitor and one end of the zener diode are connected with a common end between the output end of the charge pump and the first resistor;
The other end of the first capacitor and the other end of the zener diode are both connected with the grounding end.
5. The power clamp of claim 1, wherein a second protection circuit is further provided between the current mirror and a common terminal between the first resistor and the gate of the second supply tube.
6. The power clamp of claim 1, wherein said voltage output circuit includes a second capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410159767.2A CN118157436B (en) | 2024-02-04 | 2024-02-04 | A power clamp circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410159767.2A CN118157436B (en) | 2024-02-04 | 2024-02-04 | A power clamp circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118157436A CN118157436A (en) | 2024-06-07 |
| CN118157436B true CN118157436B (en) | 2025-02-21 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410159767.2A Active CN118157436B (en) | 2024-02-04 | 2024-02-04 | A power clamp circuit |
Country Status (1)
| Country | Link |
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| CN (1) | CN118157436B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103401229A (en) * | 2013-07-04 | 2013-11-20 | 西安电子科技大学 | Voltage triggering static discharge clamping circuit with feedback strengthening effect |
| CN113708606A (en) * | 2021-08-19 | 2021-11-26 | 珠海智融科技有限公司 | PMOS access switch control circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050035795A1 (en) * | 2003-07-08 | 2005-02-17 | Liu Chi Fai | Circuit for optimizing zener diode bias current |
| JP2009104455A (en) * | 2007-10-24 | 2009-05-14 | Rohm Co Ltd | Clamp circuit, overvoltage protection circuit using the same, and electronic equipment using the same |
-
2024
- 2024-02-04 CN CN202410159767.2A patent/CN118157436B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103401229A (en) * | 2013-07-04 | 2013-11-20 | 西安电子科技大学 | Voltage triggering static discharge clamping circuit with feedback strengthening effect |
| CN113708606A (en) * | 2021-08-19 | 2021-11-26 | 珠海智融科技有限公司 | PMOS access switch control circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118157436A (en) | 2024-06-07 |
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