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CN118156156A - Package structure and method for forming the same - Google Patents

Package structure and method for forming the same Download PDF

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Publication number
CN118156156A
CN118156156A CN202410233661.2A CN202410233661A CN118156156A CN 118156156 A CN118156156 A CN 118156156A CN 202410233661 A CN202410233661 A CN 202410233661A CN 118156156 A CN118156156 A CN 118156156A
Authority
CN
China
Prior art keywords
layer
chip
package
forming
functional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202410233661.2A
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Chinese (zh)
Inventor
赵强
刘涛
王长文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangyin Changdian Advanced Packaging Co Ltd
Original Assignee
Jiangyin Changdian Advanced Packaging Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangyin Changdian Advanced Packaging Co Ltd filed Critical Jiangyin Changdian Advanced Packaging Co Ltd
Priority to CN202410233661.2A priority Critical patent/CN118156156A/en
Publication of CN118156156A publication Critical patent/CN118156156A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention relates to a packaging structure and a forming method thereof. The package structure includes: packaging a substrate; the packaging body is located on the packaging substrate, the packaging body comprises a plastic sealing layer, a first rerouting layer, a functional chip and a bridging chip, the functional chip is located on one side of the first rerouting layer, the bridging chip is located on one side of the first rerouting layer, the functional chip and the bridging chip are electrically connected with the first rerouting layer, the bridging chip is electrically connected with the packaging substrate, and the plastic sealing layer at least covers the functional chip and the bridging chip. The invention shortens the connection distance between the functional chip and the bridging chip, ensures the integrity of signal transmission in the packaging structure, and is beneficial to reducing the size of the packaging substrate and the design complexity of the packaging substrate.

Description

Package structure and method for forming the same
Technical Field
The present disclosure relates to integrated circuit manufacturing, and more particularly, to a package structure and a method for forming the same.
Background
With the continuous development of semiconductor technology, miniaturization of dimensions, high integration of structures and functions have become a trend of semiconductor components. In order to meet the demands of high integration and downsizing, a three-dimensional stacked packaging technology has become a mainstream packaging technology. In order to obtain a package structure with better performance, the number of chips integrated in the package structure is continuously increased, and the size of the package structure is continuously increased. A package substrate for carrying the chip and transmitting control signals to the chip or extracting signals from the chip is also generally provided in the package structure. However, as the number of chips integrated in the package structure increases, the length of the connection line between the chip and the passive component in the package substrate increases, which not only results in an increase in the difficulty of signal transmission between the chip and the passive component in the package substrate, but also results in a more complex wiring structure in the package substrate, thereby increasing the difficulty of the manufacturing process of the package structure. In addition, as the number of chips in the package structure increases, the size of the package body formed by the plurality of chips and the plastic package material also increases, and the package body with a large size has larger warpage, which forms a great challenge for welding between the package body and the package substrate, especially the welding difficulty between the edge of the package body and the package substrate increases, thereby reducing the manufacturing efficiency and the manufacturing yield of the package structure.
Therefore, how to increase the integration level of the package structure and shorten the length of the connecting wire in the package structure, so as to improve the signal transmission effect inside the package structure, reduce the manufacturing difficulty of the package structure, and improve the manufacturing efficiency and the manufacturing yield of the package structure at the same time is a technical problem to be solved currently.
Disclosure of Invention
The invention provides a packaging structure and a forming method thereof, which are used for shortening the length of a connecting wire in the packaging structure while increasing the integration level of the packaging structure so as to improve the signal transmission effect in the packaging structure, reduce the manufacturing difficulty of the packaging structure and improve the manufacturing efficiency and the manufacturing yield of the packaging structure.
According to some embodiments, the present invention provides a package structure, comprising:
packaging a substrate;
The packaging body is located on the packaging substrate, the packaging body comprises a plastic sealing layer, a first rerouting layer, a functional chip and a bridging chip, the functional chip is located on one side of the first rerouting layer, the bridging chip is located on one side of the first rerouting layer, the functional chip and the bridging chip are electrically connected with the first rerouting layer, the bridging chip is electrically connected with the packaging substrate, and the plastic sealing layer at least covers the functional chip and the bridging chip.
In some embodiments, the package further comprises:
The first passive element is positioned between the first rewiring layer and the packaging substrate, the first passive element is electrically connected with the first rewiring layer, and the plastic packaging layer coats the first passive element;
The functional chips and the bridge chips are distributed on two opposite sides of the first rewiring layer along a first direction, the bridge chips and the first passive elements are distributed along a second direction, and the first direction is intersected with the second direction.
In some embodiments, the package further comprises:
The second passive element is positioned between the bridging chip and the packaging substrate and is electrically connected with the bridging chip, and the plastic sealing layer coats the second passive element;
The third passive element is positioned between the first passive element and the packaging substrate, and is electrically connected with the first passive element, and the plastic packaging layer coats the third passive element.
In some embodiments, the package further comprises:
The first conductive connecting column is positioned on the packaging substrate, one end of the first conductive connecting column is electrically connected with the first rewiring layer, and the other end of the first conductive connecting column is electrically connected with the packaging substrate.
In some embodiments, the plastic layer comprises:
the first plastic layer is positioned on one side of the first rewiring layer, which is away from the packaging substrate, and at least coats the functional chip;
the second plastic layer is positioned between the first rewiring layer and the packaging substrate, at least coats the bridging chip, and the modulus of the second plastic layer is higher than that of the first rewiring layer.
In some embodiments, further comprising:
and the heat dissipation layer is covered on the surface of the functional chip, which is away from the first rewiring layer.
In some embodiments, the functional chips and the bridge chips are distributed on opposite sides of the first rewiring layer along a first direction;
The package body comprises a plurality of functional chips which are arranged at least along a second direction, the functional chips are electrically connected with the first rewiring layer, and the first direction is intersected with the second direction.
According to other embodiments, the present invention further provides a method for forming a package structure, including the following steps:
forming a package body, wherein the package body comprises a plastic sealing layer, a first rerouting layer, and functional chips and bridging chips which are positioned on two opposite sides of the first rerouting layer, the functional chips and the bridging chips are electrically connected with the first rerouting layer, and the plastic sealing layer at least covers the functional chips and the bridging chips;
and connecting the packaging body to a packaging substrate, so that the bridging chip is positioned between the first rewiring layer and the packaging substrate, and electrically connecting the bridging chip and the packaging substrate.
In some embodiments, the specific steps of forming the package include:
Forming a first rerouting layer comprising a first surface and a second surface distributed relatively along a first direction;
connecting the functional chip to the first surface of the first rewiring layer;
Forming a first plastic layer which is positioned on the first surface of the first rewiring layer and at least covers the functional chip;
Connecting the bridge chip to the second surface of the first rewiring layer;
And forming a second plastic sealing layer which is positioned on the second surface of the first re-wiring layer and at least coats the bridge chip, wherein the modulus of the second plastic sealing layer is higher than that of the first re-wiring layer, and the first plastic sealing layer and the second plastic sealing layer are jointly used as the plastic sealing layer.
In some embodiments, the specific step of attaching the functional chip to the first surface of the first redistribution layer comprises:
forming a first conductive bump on the first surface of the first redistribution layer;
Forming a second conductive bump on the front surface of the functional chip;
electrically connecting the first conductive bump and the second conductive bump in a direction of the front surface of the functional chip toward the first rewiring layer;
a first adhesive layer is formed that fills between the functional chip and the first surface of the first redistribution layer.
In some embodiments, the bridge chip includes a third surface and a fourth surface opposite the third surface; the specific step of connecting the bridge chip to the second surface of the first redistribution layer includes:
Forming a third conductive bump on the second surface of the first redistribution layer;
Forming a fourth conductive bump on the third surface of the bridge chip;
Electrically connecting the third conductive bump and the fourth conductive bump in a direction of the third surface of the bridge chip toward the second surface of the first redistribution layer;
a second adhesive layer is formed that fills between the bridge chip and the second surface of the first redistribution layer.
In some embodiments, before electrically connecting the third conductive bump and the fourth conductive bump in a direction of the third surface of the bridge chip toward the second surface of the first redistribution layer, further comprising the steps of:
first conductive connection pillars are formed on the second surface of the first redistribution layer.
In some embodiments, the method further comprises the steps of:
Forming a fifth conductive bump on the second surface of the first redistribution layer;
forming a sixth conductive bump on a fifth surface of the first passive element;
Electrically connecting the fifth conductive bump and the sixth conductive bump in a direction of the fifth surface of the first passive element toward the second surface of the first redistribution layer;
A third adhesive layer is formed that fills between the first passive element and the second surface of the first redistribution layer.
In some embodiments, before forming a second molding layer that is located on the second surface of the first redistribution layer and encapsulates at least the bridge chip, the method further comprises the steps of:
connecting a second passive element to a surface of the bridge chip facing away from the first rewiring layer;
and forming a second conductive connecting column on the surface of the second passive element, which is away from the bridge chip.
In some embodiments, the step of connecting the package to a package substrate such that the bridge chip is located between the first redistribution layer and the package substrate, and electrically connecting the bridge chip to the package substrate comprises:
providing a packaging substrate;
and electrically connecting the first conductive connecting column and the packaging substrate in the direction of the fourth surface of the bridge chip facing the packaging substrate, and electrically connecting the second conductive connecting column and the packaging substrate.
In some embodiments, the method further comprises the steps of:
and forming a heat dissipation layer on the surface of the functional chip, which is away from the first rewiring layer.
According to the packaging structure and the forming method thereof, the bridge chip and the functional chip are integrated in the packaging body, so that the physical distance between the functional chip and the bridge chip is shortened, the electric connection distance between the functional chip and the bridge chip is shortened, the integrity of signal transmission in the packaging structure of the functional chip is ensured, and the signal transmission effect in the packaging structure is improved; secondly, the functional chip is directly and electrically connected with the bridging chip through the first rewiring layer, so that the connection distance between the functional chip and the bridging chip is shortened, and the integrity of signal transmission between the functional chip and the bridging chip is further ensured; and thirdly, by integrating the bridge chip inside the packaging body, the occupation of the space of the packaging substrate is reduced, the size of the packaging substrate is reduced, the design complexity of the packaging substrate is reduced, and the whole manufacturing cost of the packaging structure is reduced. In addition, the plastic sealing layer at least coats the functional chip and the bridging chip on the two opposite sides of the first rewiring layer, so that the degree of mismatch of thermal expansion coefficients on the two opposite sides of the first rewiring layer is reduced, the warping of the package body in the thermal process is reduced, the stable connection between the package body and the package substrate is ensured, and the manufacturing efficiency and the manufacturing yield of the package structure are improved.
Drawings
FIG. 1 is a schematic cross-sectional view of a package structure according to an embodiment of the present invention;
FIG. 2 is a schematic top view of a portion of another package structure according to an embodiment of the present invention;
FIG. 3 is a flow chart of a method for forming a package structure according to an embodiment of the present invention;
Fig. 4-14 are schematic process structures of the embodiment of the present invention in forming the package structure.
Detailed Description
The following describes in detail the package structure and the forming method thereof with reference to the drawings.
In this embodiment, a package structure is provided, and fig. 1 is a schematic cross-sectional view of a package structure according to an embodiment of the present invention. As shown in fig. 1, the package structure includes:
A package substrate 10;
The packaging body is located on the packaging substrate 10, and comprises a plastic sealing layer 19, a first rerouting layer 20, a functional chip 12 located on one side, away from the packaging substrate 10, of the first rerouting layer 20, and a bridge chip 15 located on one side, facing the packaging substrate 10, of the first rerouting layer 20, wherein the functional chip 12 and the bridge chip 15 are electrically connected with the first rerouting layer 20, the bridge chip 15 is electrically connected with the packaging substrate 10, and the plastic sealing layer 19 at least covers the functional chip 12 and the bridge chip 15.
In particular, the package substrate 10 may be, but is not limited to, a printed circuit board. The package substrate 10 includes a package substrate top surface and a package substrate bottom surface that are relatively distributed along the first direction D1. The package body is connected to the top surface of the package substrate, a plurality of solder balls 11 are arranged on the bottom surface of the package substrate, a second redistribution layer is arranged in the package substrate 10, the package body is electrically connected with the solder balls 11 through the second redistribution layer in the package substrate 10, and control signals from the outside are transmitted into the package body through the solder balls 11 and the second redistribution layer. The functional chip 12 in the package is electrically connected to the package substrate 10 through the first redistribution layer 20 and the bridge chip 15 in sequence. In one example, the functional chip 12 is flip-chip mounted on the first redistribution layer 20. For example, the first redistribution layer 20 includes a first surface facing the functional chip 12, and a second surface opposite to the first surface along the first direction D1. The first surface of the first re-wiring layer 20 has a first conductive bump thereon, the surface of the functional chip 12 facing the first re-wiring layer 20 has a second conductive bump thereon, and the first conductive bump is soldered with the second conductive bump. In an example, a first adhesive layer 211 is further filled between the functional chip 12 and the first redistribution layer 20 to enhance the connection strength between the functional chip 12 and the first redistribution layer 20. The second surface of the first redistribution layer 20 may further be provided with a third conductive bump, the surface of the bridge chip 15 facing the first redistribution layer 20 is provided with a fourth conductive bump, and the third conductive bump is soldered with the fourth conductive bump. In an example, a second adhesive layer is further filled between the bridge chip 15 and the first redistribution layer 20 to enhance the connection strength between the bridge chip 15 and the first redistribution layer 20. The plastic layer 19 encapsulates at least the functional chip 12 and the bridge chip 15. In one example, the material of the plastic layer 19 may include an epoxy molding compound. In one example, passive devices are integrated within the bridge chip 15. The package structure further comprises a heat dissipation cover 14 located on the package substrate 10, the package body is located in a cavity surrounded by the heat dissipation cover 14, and the heat dissipation cover 14 is used for dissipating heat of the package body. In an example, the material of the heat dissipating cover 14 may be a metal material.
In this embodiment, the first redistribution layer 20 and the bridge chip 15 are integrated in the package, and the functional chip 12 and the bridge chip 15 are disposed on opposite sides of the first redistribution layer 20, and the functional chip 12 and the bridge chip 15 are electrically connected through the first redistribution layer 20, so that first, the physical distance between the functional chip 12 and the bridge chip 15 is shortened, and thus, the electrical connection distance between the functional chip and the bridge chip is shortened, the integrity of signal transmission inside the functional chip package structure is ensured, and therefore, the signal transmission effect inside the package structure is improved; secondly, the functional chip 12 is directly electrically connected with the bridge chip 15 through the first redistribution layer 20, thereby further shortening the electrical connection distance between the functional chip 12 and the bridge chip 15; again, by integrating the bridge chip 15 inside the package body, the occupation of the package substrate space is reduced, which is conducive to downsizing the package substrate and reducing the complexity of the package substrate design, thereby realizing the reduction of the overall manufacturing cost of the package structure. In this embodiment, the plastic layer 19 at least encapsulates the functional chip 12 and the bridge chip 15, that is, the plastic layer 19 is distributed on two opposite sides of the first redistribution layer 20, so as to reduce the degree of mismatch of thermal expansion coefficients of two opposite sides of the first redistribution layer, reduce warpage of the package in a thermal process, ensure stable connection between the package and the package substrate, and improve manufacturing efficiency and manufacturing yield of the package structure.
In some embodiments, the functional chips 12 and the bridge chips 15 are distributed on opposite sides of the first redistribution layer 20 along a first direction D1;
The package body includes a plurality of functional chips 12 arranged at least along a second direction D2, and the functional chips 12 are electrically connected to the first redistribution layer 20, and the first direction D1 intersects the second direction D2.
For example, as shown in fig. 1, the package body includes a plurality of functional chips 12 arranged at intervals along at least the second direction D2, and each functional chip 12 is electrically connected to the first redistribution layer 20, so as to further increase the integration of the package structure and expand the functions of the package structure. The plurality of functional chips 12 are electrically connected to the bridge chip 15 through the first redistribution layer 20, so that each functional chip 12 can be electrically connected to the package substrate 10 through the bridge chip 15, and also can be electrically connected to each functional chip 12 through the bridge chip 15. In one example, the plurality of functional chips 12 are identical in structure. In another example, the plurality of functional chips 12 are structurally different to achieve different functions. The plural numbers described in this embodiment mode refer to two or more.
In some embodiments, the package further comprises:
A first passive component 16 located between the first redistribution layer 20 and the package substrate 10, where the first passive component 16 is electrically connected to the first redistribution layer 20, and the plastic layer 19 encapsulates the first passive component 16;
The functional chips 12 and the bridge chips 15 are distributed on two opposite sides of the first redistribution layer 20 along a first direction D1, the bridge chips 15 and the first passive components 16 are arranged along a second direction D2, and the first direction D1 intersects the second direction D2.
Specifically, the first passive component 16 is further disposed between the first redistribution layer 20 and the package substrate 10, and the first passive component 16 and the bridge chip 15 are arranged along the second direction D2. The plurality of first passive elements 16 are electrically connected to the plurality of functional chips 12 through the first redistribution layer 20, respectively, and the first passive elements 16 are electrically connected to the package substrate 10, so that each of the functional chips 12 can be electrically connected to the package substrate 10 through the first redistribution layer 20 and the first passive elements 16. In one example, the first passive component 16 includes a plurality of passive components (i.e., passive devices) therein. The first direction D1 perpendicularly intersects or obliquely intersects the second direction D2.
In some embodiments, the package further comprises:
The second passive component 17 is located between the bridge chip 15 and the package substrate 10, and the second passive component 17 is electrically connected with the bridge chip 15, and the plastic package layer encapsulates the second passive component;
The third passive component 18 is located between the first passive component 16 and the package substrate 10, and the third passive component 18 is electrically connected to the first passive component 16, and the plastic layer 19 encapsulates the third passive component 18.
For example, the second passive component 17 is located between the bridge chip 15 and the package substrate 10 and is electrically connected to the bridge chip 15 through conductive adhesive (e.g. conductive silver adhesive), and the third passive component 18 is located between the first passive component 16 and the package substrate 10 and is electrically connected to the first passive component 16 through conductive adhesive (e.g. conductive silver adhesive). By providing the second passive element 17 and the third passive element 18, on one hand, the bridge chip 15 and the package substrate 10 can be directly and electrically connected through the second passive element, and the first passive element 16 and the package substrate 10 can be directly and electrically connected through the third passive element 18, so that no other circuit trace is required, and the length of the circuit trace in the package structure is further shortened; on the other hand, it is also possible to dispose a part of the passive elements within the second passive element 17 and the third passive element 18, thereby contributing to simplification of the structures of the first passive element 16 and the bridge chip 15, thereby further simplifying the manufacturing process of the package structure while ensuring stable electrical connection of the functional chip 12 and the package substrate 10.
In some embodiments, the package further comprises:
The first conductive connection post 22 is located on the package substrate 10, and one end of the first conductive connection post 22 is electrically connected with the first redistribution layer 20, and the other end of the first conductive connection post is electrically connected with the package substrate 10, so as to realize electrical connection between the first redistribution layer 20 and the package substrate 10. In one example, the material of the first conductive connection post 22 is a metal material, such as metallic copper. In an example, the surface of the first conductive connection post 22 facing the package substrate 10 is further provided with a first connection bump 23 and a first solder joint 24 located on the first connection bump 23, and the first solder joint 24 is soldered to the package substrate 10.
In some embodiments, the plastic layer 19 includes:
A first plastic layer 191 located on a side of the first redistribution layer 20 away from the package substrate 10, where the first plastic layer 191 at least covers the functional chip 12;
The second plastic layer 192 is located between the first redistribution layer 20 and the package substrate 10, and the second plastic layer 192 at least covers the bridge chip 15, and the elastic modulus of the second plastic layer 192 is higher than that of the first redistribution layer 20.
The elastic modulus of the second plastic layer 192 in this embodiment refers to the ratio between the stress and the strain of the second plastic layer 192 in the stressed state. The elastic modulus of the first redistribution layer 20 refers to a ratio between stress and strain of the first redistribution layer 20 in a stressed state. In this embodiment, the elastic modulus of the second plastic layer 192 is set to be higher than the elastic modulus of the first redistribution layer 20, so that the second plastic layer 192 can support the first redistribution layer 20 and the functional chip 12, thereby improving the stability of the package. By providing the first plastic sealing layer 191 and the second plastic sealing layer 192 on the opposite sides of the first redistribution layer 20, the degree of mismatch of the thermal expansion coefficients of the opposite sides of the first redistribution layer 20 can be reduced, so that the warpage of the package body in the thermal process is reduced, and stable soldering between the package body and the package substrate 10 is ensured. In one example, the material of the first plastic layer 191 is the same as the material of the second plastic layer 192. In another example, the material of the first plastic layer 191 is different from the material of the second plastic layer 192. A fourth adhesive layer 212 may be further disposed between the second plastic layer 192 and the package substrate 10 to enhance the connection strength between the package body and the package substrate 10.
In some embodiments, the package structure further comprises:
and the heat dissipation layer is covered on the surface of the functional chip 12, which is away from the first rewiring layer 20.
For example, as shown in fig. 1, the heat dissipation layer includes a first heat dissipation layer 131 covering a surface of the functional chip 12 facing away from the first redistribution layer 20 and a second heat dissipation layer 132 covering a surface of the first heat dissipation layer 131. By the combined stack of the first heat dissipation layer 131 and the second heat dissipation layer 132, the heat dissipation effect of the heat dissipation layer on the functional chip 12 is enhanced. In an example, the material of the first heat dissipation layer 131 and the material of the second heat dissipation layer 132 are both metal materials, and the material of the first heat dissipation layer 131 is different from the material of the second heat dissipation layer 132, for example, the material of the first heat dissipation layer 131 is metal copper or metal silver, and the material of the second heat dissipation layer 132 is metal indium.
Fig. 2 is a schematic top view of a portion of another package structure according to an embodiment of the present invention. The present embodiment is described taking the example that the bridge chip 15 and the functional chip 12 are disposed on opposite sides of the first redistribution layer 20. In other embodiments, the bridge chip 15 and the functional chip 12 may also be disposed on the same side of the first redistribution layer 20, as shown in fig. 2, to further reduce the thickness of the package.
The embodiment also provides a method for forming the package structure, fig. 3 is a flowchart of a method for forming the package structure in the embodiment of the invention, and fig. 4 to fig. 14 are schematic process structures of the embodiment of the invention in the process of forming the package structure. A schematic view of the package structure formed in this embodiment may be seen in fig. 1. As shown in fig. 1 and fig. 3 to fig. 14, the method for forming the package structure includes the following steps:
Step S31, forming a package body, wherein the package body comprises a plastic sealing layer 19, a first rerouting layer 20, and a functional chip 12 and a bridge chip 15 which are positioned on two opposite sides of the first rerouting layer 20, the functional chip 12 and the bridge chip 15 are electrically connected with the first rerouting layer 20, and the plastic sealing layer 19 at least covers the functional chip 12 and the bridge chip 15;
Step S32, connecting the package to the package substrate 10, such that the bridge chip 15 is located between the first redistribution layer 20 and the package substrate 10, and electrically connecting the bridge chip 15 and the package substrate 10.
In some embodiments, the specific steps of forming the package include:
forming a first re-wiring layer 20, the first re-wiring layer 20 including a first surface 201 and a second surface 202 that are relatively distributed along a first direction D1, as shown in fig. 4;
Connecting the functional chip 12 to the first surface 201 of the first redistribution layer 20, as shown in fig. 5;
Forming a first plastic layer 191 on the first surface 201 of the first redistribution layer 20 and at least covering the functional chip 12, as shown in fig. 5;
connecting the bridge chip 15 to the second surface 202 of the first redistribution layer 20, as shown in fig. 8;
a second plastic layer 192 is formed on the second surface 202 of the first redistribution layer 20 and at least covers the bridge chip 15, the modulus of the second plastic layer 192 is higher than that of the first redistribution layer 20, and the first plastic layer 191 and the second plastic layer 192 together serve as the plastic layer 19, as shown in fig. 11.
In other embodiments, the functional chip 12 may also be connected first on a carrier plate (e.g., a glass carrier plate). Next, the first rewiring layer 20 is formed on the surface of the functional chip facing away from the carrier plate. After that, the bridge chip 15 is connected to the side of the first redistribution layer 20 facing away from the functional chip 12. After forming the second plastic layer 192 for plastic packaging the bridge chip 15, the carrier is removed, and the first plastic layer 191 for plastic packaging the functional chip 12 is formed, thereby obtaining the structure shown in fig. 11.
In some embodiments, the specific steps of connecting the functional chip 12 to the first surface 201 of the first redistribution layer 20 include:
forming a first conductive bump 40 on the first surface 201 of the first redistribution layer 20, as shown in fig. 4;
forming a second conductive bump 50 on the front surface of the functional chip 12, as shown in fig. 5;
electrically connecting the first conductive bump 40 and the second conductive bump 50 in a direction of the front surface of the functional chip 12 toward the first rewiring layer 20;
a first adhesive layer 211 is formed to fill between the functional chip 12 and the first surface 201 of the first redistribution layer 20, as shown in fig. 5.
For example, a layer of laser release material is coated on the carrier 41, and a metal material (e.g., metallic aluminum, metallic titanium, or metallic copper) is deposited on the surface of the laser release material as a sacrificial metal layer. Next, a high-density wiring layer and a dielectric layer covering the high-density wiring layer are formed on the surface of the sacrificial metal layer, and the high-density wiring layer and the dielectric layer are used together as the first re-wiring layer 20. The surface of the first redistribution layer 20 facing the carrier 41 is the second surface 202, and the surface of the first redistribution layer 20 facing away from the carrier 41 is the first surface 201. In an example, the carrier 41 may be a glass carrier. Thereafter, the first conductive bump 40 may be formed on the first surface 201 of the first re-wiring layer 20 using an electroplating process, as shown in fig. 4. The material of the first conductive bump 40 may be metallic copper, metallic nickel or metallic gold. After forming the second conductive bump 50 on the front surface of the functional chip 12, a first soldering assisting layer 51 is coated on the surface of the second conductive bump 50, and the second conductive bump 50 is soldered with the first conductive bump 40 by adopting a hot pressing process. Then, an underfill (unref ill) is filled between the functional chip 12 and the first surface 201 of the first redistribution layer 20, forming the first adhesive layer 211 between the functional chip 12 and the first redistribution layer 20. Next, the functional chip 12 is encapsulated by an encapsulation process, so as to form the first encapsulation layer 191, and the surface of the first encapsulation layer 191 facing away from the first redistribution layer 20 is higher than the functional chip 12, as shown in fig. 5.
In some embodiments, the bridge chip 15 includes a third surface and a fourth surface opposite the third surface; the specific steps of attaching the bridge chip 15 to the second surface 202 of the first redistribution layer 20 include:
Forming a third conductive bump 70 on the second surface 202 of the first redistribution layer 20;
forming a fourth conductive bump 80 on the third surface of the bridge chip 15;
Electrically connecting the third conductive bump 70 and the fourth conductive bump 80 in a direction of the third surface of the bridge chip 15 toward the second surface 202 of the first re-wiring layer 20;
A second adhesive layer 84 is formed that fills between the bridge chip 15 and the second surface 202 of the first redistribution layer 20, as shown in fig. 8.
In some embodiments, before electrically connecting the third conductive bump 70 and the fourth conductive bump 80 in a direction in which the third surface of the bridge chip 15 faces the second surface 202 of the first redistribution layer 20, the method further includes the steps of:
first conductive connection pillars 22 are formed on the second surface 202 of the first redistribution layer 20, as shown in fig. 7.
In some embodiments, the method for forming a package structure further includes the steps of:
forming a fifth conductive bump 71 on the second surface 202 of the first redistribution layer 20;
Forming a sixth conductive bump 82 on the fifth surface of the first passive element 16;
Electrically connecting the fifth conductive bump 71 and the sixth conductive bump 82 in a direction of the fifth surface of the first passive component 16 toward the second surface 202 of the first redistribution layer 20, as shown in fig. 8;
A third adhesive layer 85 is formed that fills between the first passive component 16 and the second surface 202 of the first redistribution layer 20, as shown in fig. 8.
For example, the carrier 41 is removed by laser bonding, and the sacrificial metal layer is etched away to expose the second surface 202 of the first redistribution layer 20, as shown in fig. 6. The third conductive bump 70, the fifth conductive bump 71 and the first conductive connection post 22 are formed on the second surface 202 of the first re-wiring layer 20 by a plating process or the like, as shown in fig. 7. In an example, the material of the third conductive bump 70 and the fifth conductive bump 71 may be nickel-gold alloy, and the heights of the third conductive bump 70 and the fifth conductive bump 71 (e.g., the height along the first direction D1) are the same, for example, each 3 micrometers. The material of the first conductive connection post 22 may be metallic copper, and the height of the first conductive connection post 22 (e.g., the height along the first direction D1) is greater than or equal to 100 micrometers. In an example, the distance between the first conductive connecting post 22 and the third conductive bump 70 and the distance between the first conductive connecting post 22 and the fifth conductive bump 71 are greater than or equal to 500 micrometers, facilitating subsequent soldering operations (e.g., subsequent operations of soldering the bridge chip and the first passive component).
Thereafter, the fourth conductive bump 80 is formed on the third surface of the bridge chip 15, and a first non-conductive film (e.g., a first insulating film) is formed to cover the surface of the bridge chip 15 and expose the fourth conductive bump 80. A sixth conductive bump 82 is formed on the fifth surface of the first passive element 16, and a second non-conductive film is formed that covers the surface of the first passive element 16 and exposes the sixth conductive bump 82. In an example, the thickness of the bridge chip 15 (e.g. the thickness along the first direction D1) and the thickness of the first passive component 16 (e.g. the thickness along the first direction D1) are both greater than or equal to 30 micrometers, and the height of the fourth conductive bump 80 and the height of the sixth conductive bump 82 are both 10 micrometers to 15 micrometers, so as to further shorten the electrical connection distance inside the package structure. Then, a second solder resist layer 81 is applied on the surface of the fourth conductive bump 80, and a third solder resist layer 83 is applied on the surface of the sixth conductive bump 82. Next, the third conductive bump 70 and the fourth conductive bump 80 are electrically connected in a direction in which the third surface of the bridge chip 15 faces the second surface 202 of the first redistribution layer 20, and the fifth conductive bump 71 and the sixth conductive bump 82 are electrically connected in a direction in which the fifth surface of the first passive component 16 faces the second surface 202 of the first redistribution layer 20. Next, a second adhesive layer 84 is formed to fill between the bridge chip 15 and the second surface 202 of the first redistribution layer 20, and a third adhesive layer 85 is formed to fill between the first passive component 16 and the second surface 202 of the first redistribution layer 20, as shown in fig. 8.
In some embodiments, before forming the second molding layer 192 that is located on the second surface 202 of the first redistribution layer 20 and wraps at least the bridge chip 15, the method further includes the steps of:
connecting a second passive component 17 to the surface of the bridge chip 15 facing away from the first redistribution layer 20, as shown in fig. 9;
second conductive connecting posts 92 are formed on the surface of the second passive component 17 facing away from the bridge chip 15, as shown in fig. 9.
For example, the second passive component 17 is connected to the surface of the bridge chip 15 facing away from the first redistribution layer 20 (i.e. the fourth surface of the bridge chip 15) by a first conductive adhesive layer 91, and the third passive component 18 is connected to the surface of the first passive component 16 facing away from the first redistribution layer 20 (i.e. the sixth surface of the first passive component 16, which is opposite to the fifth surface) by a second conductive adhesive layer 93. In one example, the thickness of the second passive element 17 and the thickness of the third passive element 18 are each greater than or equal to 30 microns. Thereafter, a second conductive connection post 92 is formed on the surface of the second passive element 17 facing away from the bridge chip 15 by electroplating or the like, and a third conductive connection post 94 is formed on the surface of the third passive element 18 facing away from the first passive element 16, as shown in fig. 9. In one example, the second conductive connection posts 92 are the same height as the third conductive connection posts 94, e.g., 30 microns.
In some embodiments, the step of connecting the package body to the package substrate 10 such that the bridge chip 15 is located between the first redistribution layer 20 and the package substrate 10, and electrically connecting the bridge chip 15 and the package substrate 10 includes:
providing a package substrate 10;
The fourth surface of the bridge chip 15 is electrically connected to the first conductive connection post 22 and the package substrate 10 in a direction toward the package substrate 10, and electrically connected to the second conductive connection post 92 and the package substrate 10, as shown in fig. 14.
For example, the second molding layer 192 is formed by molding or film pressing to cover the bridge chip 15, the first passive component 16, the second passive component 17, the third passive component 18, the first conductive connecting post 22, the second conductive connecting post 92, and the third conductive connecting post 94, as shown in fig. 10. In one example, the modulus of the second plastic layer 192 is higher than the modulus of the first redistribution layer 20, and the coefficient of thermal expansion of the second plastic layer 192 is lower than the coefficient of thermal expansion of the first redistribution layer 20. The material of the second plastic layer 192 may be a mixed material including a resin and filler particles. Next, a part of the second plastic layer 192 and a part of the first conductive connection post 22, the second conductive connection post 92, and the third conductive connection post 94 may be removed by grinding, and the first conductive connection post 22, the second conductive connection post 92, and the third conductive connection post 94 are exposed after grinding, as shown in fig. 11, and the remaining height of the second conductive connection post 92 and the third conductive connection post 94 after grinding is greater than or equal to 5 micrometers, so as to ensure stable connection with the package substrate.
Next, a first connection bump 23 and a first solder joint 24 located on the first connection bump 23 are formed on a surface of the first conductive connection post 22 facing away from the first redistribution layer 20, a second connection bump 120 and a second solder joint 121 located on the second connection bump 120 are formed on a surface of the second conductive connection post 92 facing away from the first redistribution layer 20, and a third connection bump 122 and a third solder joint 123 located on the third connection bump 122 are formed on a surface of the third conductive connection post 94 facing away from the first redistribution layer 20, as shown in fig. 12. Wherein the diameter of the first welding point 24 is 10 micrometers larger than the diameter of the first conductive connecting post 22, the diameter of the second welding point 121 is 10 micrometers larger than the diameter of the second conductive connecting post 92, and the diameter of the third welding point 123 is 10 micrometers larger than the diameter of the third conductive connecting post 94, so as to increase the contact area between the package body and the package substrate 10 and reduce the stress between the package body and the package substrate 10. In one example, the height of the first pad 24, the height of the second pad 121, and the height of the third pad 123 are all 50 micrometers to 70 micrometers.
In some embodiments, the method for forming a package structure further includes the steps of:
a heat dissipation layer is formed on a surface of the functional chip 12 facing away from the first redistribution layer 20, as shown in fig. 14.
For example, a portion of the first plastic layer 191 is removed by grinding, so as to expose a surface of the functional chip 12 facing away from the first redistribution layer 20, as shown in fig. 13. Next, a plurality of metal materials are deposited on the surface of the functional chip 12 facing away from the first redistribution layer 20 by sputtering, so as to form a first heat dissipation layer 131, as shown in fig. 13. Then, the first solder joint 24, the second solder joint 121 and the third solder joint 123 are soldered on the package substrate 10, and a fourth adhesive layer 122 is formed to fill between the second plastic layer 192 and the package substrate 10, as shown in fig. 14. Solder balls 11 are formed on the surface of the package substrate 10 facing away from the package body, and a second heat dissipation layer 132 is formed on the surface of the first heat dissipation layer 131. Next, the heat dissipating cover 14 is connected to the package substrate 10, so that the package is located in the cavity surrounded by the heat dissipating cover 14, as shown in fig. 14.
According to the packaging structure and the forming method thereof, the bridge chip and the functional chip are integrated in the packaging body, so that the physical distance between the functional chip and the bridge chip is shortened, the electric connection distance between the functional chip and the bridge chip is shortened, the integrity of signal transmission in the packaging structure is ensured, and the signal transmission effect in the packaging structure is improved; secondly, the functional chip is directly and electrically connected with the bridging chip through the first rewiring layer, so that the connection distance between the functional chip and the bridging chip is shortened, and the integrity of signal transmission between the functional chip and the bridging chip is further ensured; and thirdly, by integrating the bridge chip inside the packaging body, the occupation of the space of the packaging substrate is reduced, the size of the packaging substrate is reduced, the design complexity of the packaging substrate is reduced, and the whole manufacturing cost of the packaging structure is reduced. In addition, the plastic sealing layer in the embodiment at least coats the functional chip and the bridging chip on two opposite sides of the first rewiring layer, so that the degree of mismatch of thermal expansion coefficients on two opposite sides of the first rewiring layer is reduced, the warping of the package body in the thermal process is reduced, the stable connection of the package body and the package substrate is ensured, and the manufacturing efficiency and the manufacturing yield of the package structure are improved.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.

Claims (15)

1. A package structure, comprising:
packaging a substrate;
The packaging body is located on the packaging substrate, the packaging body comprises a plastic sealing layer, a first rerouting layer, a functional chip and a bridging chip, the functional chip is located on one side of the first rerouting layer, the bridging chip is located on one side of the first rerouting layer, the functional chip and the bridging chip are electrically connected with the first rerouting layer, the bridging chip is electrically connected with the packaging substrate, and the plastic sealing layer at least covers the functional chip and the bridging chip.
2. The package structure of claim 1, wherein the package further comprises:
the first passive element is positioned between the first rewiring layer and the packaging substrate, the first passive element is electrically connected with the first rewiring layer, and the plastic packaging layer coats the first passive element; the functional chips and the bridge chips are distributed on two opposite sides of the first rewiring layer along a first direction, the bridge chips and the first passive elements are distributed along a second direction, and the first direction is intersected with the second direction.
3. The package structure of claim 2, wherein the package further comprises:
The second passive element is positioned between the bridging chip and the packaging substrate and is electrically connected with the bridging chip, and the plastic sealing layer coats the second passive element;
The third passive element is positioned between the first passive element and the packaging substrate, and is electrically connected with the first passive element, and the plastic packaging layer coats the third passive element.
4. The package structure of claim 1, wherein the plastic layer comprises:
the first plastic layer is positioned on one side of the first rewiring layer, which is away from the packaging substrate, and at least coats the functional chip;
the second plastic layer is positioned between the first rewiring layer and the packaging substrate, at least coats the bridging chip, and the modulus of the second plastic layer is higher than that of the first rewiring layer.
5. The package structure of claim 1, further comprising:
and the heat dissipation layer is covered on the surface of the functional chip, which is away from the first rewiring layer.
6. The package structure of claim 1, wherein the functional chip and the bridge chip are distributed on opposite sides of the first redistribution layer along a first direction;
The package body comprises a plurality of functional chips which are arranged at least along a second direction, the functional chips are electrically connected with the first rewiring layer, and the first direction is intersected with the second direction.
7. The method for forming the packaging structure is characterized by comprising the following steps:
forming a package body, wherein the package body comprises a plastic sealing layer, a first rerouting layer, and functional chips and bridging chips which are positioned on two opposite sides of the first rerouting layer, the functional chips and the bridging chips are electrically connected with the first rerouting layer, and the plastic sealing layer at least covers the functional chips and the bridging chips;
and connecting the package body to a package substrate, so that the bridge chip is positioned between the first rewiring layer and the package substrate, and electrically connecting the bridge chip and the package substrate.
8. The method of forming a package according to claim 7, wherein the forming the package comprises:
Forming a first rerouting layer comprising a first surface and a second surface distributed relatively along a first direction;
connecting the functional chip to the first surface of the first rewiring layer;
Forming a first plastic layer which is positioned on the first surface of the first rewiring layer and at least covers the functional chip;
Connecting the bridge chip to the second surface of the first rewiring layer;
And forming a second plastic sealing layer which is positioned on the second surface of the first re-wiring layer and at least coats the bridge chip, wherein the modulus of the second plastic sealing layer is higher than that of the first re-wiring layer, and the first plastic sealing layer and the second plastic sealing layer are jointly used as the plastic sealing layer.
9. The method of claim 8, wherein the step of attaching the functional chip to the first surface of the first redistribution layer comprises:
forming a first conductive bump on the first surface of the first redistribution layer;
Forming a second conductive bump on the front surface of the functional chip;
electrically connecting the first conductive bump and the second conductive bump in a direction of the front surface of the functional chip toward the first rewiring layer;
a first adhesive layer is formed that fills between the functional chip and the first surface of the first redistribution layer.
10. The method of forming a package structure of claim 8, wherein the bridge chip includes a third surface and a fourth surface opposite the third surface; the specific step of connecting the bridge chip to the second surface of the first redistribution layer includes:
Forming a third conductive bump on the second surface of the first redistribution layer;
Forming a fourth conductive bump on the third surface of the bridge chip;
Electrically connecting the third conductive bump and the fourth conductive bump in a direction of the third surface of the bridge chip toward the second surface of the first redistribution layer;
a second adhesive layer is formed that fills between the bridge chip and the second surface of the first redistribution layer.
11. The method of forming a package structure of claim 10, further comprising, before electrically connecting the third conductive bump and the fourth conductive bump in a direction in which the third surface of the bridge chip faces the second surface of the first redistribution layer, the steps of:
first conductive connection pillars are formed on the second surface of the first redistribution layer.
12. The method of forming a package structure of claim 11, further comprising the steps of:
Forming a fifth conductive bump on the second surface of the first redistribution layer;
forming a sixth conductive bump on the fifth surface of the first passive element;
Electrically connecting the fifth conductive bump and the sixth conductive bump in a direction of the fifth surface of the first passive element toward the second surface of the first redistribution layer;
A third adhesive layer is formed that fills between the first passive element and the second surface of the first redistribution layer.
13. The method of forming a package structure of claim 11, further comprising, prior to forming a second molding layer on the second surface of the first redistribution layer and encapsulating at least the bridge chip, the steps of:
connecting a second passive element to a surface of the bridge chip facing away from the first rewiring layer;
and forming a second conductive connecting column on the surface of the second passive element, which is away from the bridge chip.
14. The method of claim 13, wherein the step of connecting the package to a package substrate such that the bridge chip is located between the first redistribution layer and the package substrate, and electrically connecting the bridge chip to the package substrate comprises:
providing a packaging substrate;
and electrically connecting the first conductive connecting column and the packaging substrate in the direction of the fourth surface of the bridge chip facing the packaging substrate, and electrically connecting the second conductive connecting column and the packaging substrate.
15. The method of forming a package structure of claim 7, further comprising the steps of:
and forming a heat dissipation layer on the surface of the functional chip, which is away from the first rewiring layer.
CN202410233661.2A 2024-03-01 2024-03-01 Package structure and method for forming the same Pending CN118156156A (en)

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CN202410233661.2A CN118156156A (en) 2024-03-01 2024-03-01 Package structure and method for forming the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202410233661.2A CN118156156A (en) 2024-03-01 2024-03-01 Package structure and method for forming the same

Publications (1)

Publication Number Publication Date
CN118156156A true CN118156156A (en) 2024-06-07

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Family Applications (1)

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Country Link
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