CN118155573A - LED backlight driving method for realizing image black insertion under variable refresh rate - Google Patents
LED backlight driving method for realizing image black insertion under variable refresh rate Download PDFInfo
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3406—Control of illumination source
- G09G3/342—Control of illumination source using several illumination sources separately controlled corresponding to different display panel areas, e.g. along one dimension such as lines
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Abstract
The invention discloses an LED backlight assembly suitable for realizing image black insertion under variable refresh rate, comprising: the LED backlight assembly is divided into a plurality of backlight partitions, and when the display is performed at a first refresh rate, LED current control periods of the corresponding backlight partitions in a vertical synchronization signal Vsync period T at the first refresh rate are divided into a first duration T 1 and a second duration T 2, and T 1+T2 =T; the LED current in the first period T 1 is set to a first current value, and the LED current in the second period T 2 is set to a second current value; when the liquid crystal panel displays at the second refresh rate, the LED current control periods of the backlight partitions corresponding to the vertical synchronization signal Vsync period T' at the second refresh rate are divided into a first period T 1, a second period T 2, and a third period T 3; and has T 1+T2+T3 = T'; the LED current in the third period of time T 3 is set to a third current value.
Description
Technical Field
The invention relates to the technical field of image display, in particular to an LED backlight assembly and a driving method suitable for realizing image black insertion under a variable refresh rate.
Background
Every time a Liquid Crystal Display (LCD) displays a frame of image, the Liquid crystal molecules are turned over, and a high refresh rate can cause a user to see a blurred smear when playing a fast dynamic picture, which affects the customer experience. The conventional black insertion technology (BFI, black Frame Inertion) is to insert a black frame between two normal frames to cover up the residual image of the image ash, so as to complete the operation of eliminating the smear and improve the appearance of people. The conventional black insertion method requires the response time of the liquid crystal display to be fast enough, otherwise, the black insertion frame is easily perceived by human eyes, and flicker can occur.
Variable Refresh Rate (VRR) REFRESH RATE is a new technology for display panels to allow the refresh rate of the display panel to be adaptively changed based on the current processing speed of a video provider, such as a Graphics Processing Unit (GPU). Thus, the problems of tearing effect, image residues and other visual effects when the GPU cannot timely output the image frames are avoided. The display of the variable refresh rate enables the user to experience better, and particularly for game players, the variable refresh rate signal enables the game picture texture to be higher, so that the problems of picture lag, clamping and frame tearing can be reduced or eliminated.
Based on the features of the BFI technology and the VRR technology, in the prior art, it becomes difficult to obtain a better display effect by implementing the black insertion technology under the variable refresh rate display panel. In the synchronous backlight control scheme, the backlight control signal is synchronized with a vertical synchronization signal (Vsync, which is a pulse signal applied between two frames, indicating the end of a previous frame and the start of a new frame, i.e., the frequency of the vertical synchronization signal is kept consistent with the picture refresh rate) of an input image; therefore, since the length of the frame period (i.e., the period of the vertical synchronization signal Vsync) is variable, performing the BFI in different frame periods will cause the backlight partition currents of the backlight control signal to be inconsistent, and the continuously varying backlight partition currents will generate backlight flicker, thereby allowing the user to feel the image flicker. Thus, implementing the black insertion technique at a variable refresh rate can easily cause backlight flicker in addition to the brightness degradation caused by the black insertion technique itself.
Therefore, there is a need in the art for a new LED backlight control technique that enables the black insertion technique to be implemented simultaneously at a variable refresh rate and achieves a good display effect, i.e., that is capable of maintaining a high brightness of the image while avoiding backlight flicker.
Disclosure of Invention
The invention aims to provide an LED backlight assembly and a control method suitable for realizing image black insertion under a variable refresh rate, and based on the LED backlight assembly and the backlight control method, the black insertion technology can be implemented at the same time under the variable refresh rate, a better display effect can be obtained, namely, the image can be kept to have higher brightness, and backlight flickering is avoided.
Based on the technical purpose, the invention provides an LED backlight driving method suitable for realizing image black insertion under a variable refresh rate, which comprises the following steps:
dividing the LED backlight assembly into a plurality of backlight partitions, wherein each backlight partition corresponds to a pixel partition of a liquid crystal panel, and a plurality of rows of liquid crystal pixels are contained in each pixel partition;
When the liquid crystal panel displays at a first refresh rate, LED current control periods of the backlight partitions corresponding to the vertical synchronization signal Vsync period T at the first refresh rate are divided into a first period T 1 and a second period T 2, and T 1+T2 =t;
The LED current of the first duration T 1 is a first current value I 1, and the LED current of the second duration T 2 is a second current value I 2;
the second current value is a frame current value I Led of the frame display picture;
The first current value I 1 is simultaneously satisfied: the first current value I 1 is set to be greater than zero and less than the second current value I 2; while the first current value I 1 is set to be less than the first threshold value;
When the liquid crystal panel displays at the second refresh rate, the LED current control periods of the backlight partitions corresponding to the vertical synchronization signal Vsync period T' at the second refresh rate are divided into a first period T 1, a second period T 2, and a third period T 3; and has T 1+T2+T3 = T';
The LED current of the third duration T 3 is a third current I 3; the value range of the third current I 3 is the average current + -current floating value delta I;
the average current is a current value corresponding to a frame average current value or a frame average brightness;
the first refresh rate is greater than the second refresh rate.
In one embodiment, the first refresh rate is the highest refresh rate of the variable refresh rate settings.
In one embodiment, the first threshold is 1/2, 1/4, 1/16, 1/32, 1/64 or 1/128 of the current value corresponding to the highest brightness.
In one embodiment, the current floating value Δi is 10%, 15%, 20% of the current value corresponding to the frame average current value or the frame average luminance.
In one embodiment, when the liquid crystal panel displays at the third refresh rate, the vertical synchronization signal Vsync period t″ at the third refresh rate is divided into a plurality of identical vertical synchronization signal Vsync sub-periods t″ sub, and the LED current control periods of the respective backlight partitions corresponding to each of the vertical synchronization signal Vsync sub-periods t″ sub are each divided into a first period T 1, a second period T 2, and a third period T 3. And has a T 1+T2+T3＝T"sub.
One or more embodiments of the present invention may have the following advantages over the prior art:
The invention realizes the picture black inserting technology under the state of variable refresh rate by controlling the LED current in different time periods in the period of the vertical synchronous signal, and simultaneously ensures the brightness stability of the display picture and no flicker of backlight.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention, without limitation to the invention. In the drawings:
FIG. 1 is a schematic diagram of an LED backlight partition structure of the present invention;
FIG. 2 is a schematic diagram showing the correspondence between LED backlight partitions and liquid crystal pixel partitions according to the present invention;
FIG. 3 is a timing diagram of the LED backlight partition control at a first refresh rate according to a first embodiment of the present invention;
FIG. 4 is a timing diagram of the LED backlight partition control at a second refresh rate according to the first embodiment of the present invention;
FIG. 5 is a timing diagram of the LED backlight partition control at a third refresh rate according to a second embodiment of the present invention;
Fig. 6 is a timing diagram of the LED backlight partition control at the second refresh rate according to the third embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent.
It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present.
Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Example 1
As shown in fig. 1, the LED backlight assembly of the present invention is divided into n-line backlight partitions according to the requirements of the present invention, and is synchronized with the refresh direction of the image signal of the display panel, from top to bottom, 1-line backlight partition, 2-line backlight partition to the lowest n-line backlight partition. The value of n can be formulated according to the requirement of LED backlight control, namely, the higher n indicates that the more backlight partitions are, the more accurate the LED backlight control is, and the higher the component cost is.
As shown in fig. 2, the LED backlight assembly of the present invention is disposed below the liquid crystal panel, each backlight partition corresponds to a pixel partition of the liquid crystal panel, and the pixel partition includes a plurality of rows of liquid crystal pixels, for example, the pixel resolution of the liquid crystal panel is 2560×1440, i.e. 2K resolution, and the number of backlight partitions is n=40 rows, then the number of rows of liquid crystal pixels corresponding to each backlight partition is 1440/40=36, i.e. the 1 st row of backlight partition corresponds to the first 36 rows of liquid crystal pixels, the 2 nd row of backlight partition corresponds to the second 36 rows of liquid crystal pixels, and so on.
As can be seen from the characteristics of the liquid crystal panel, in the liquid crystal partition mode of the present embodiment, when one frame of display image is displayed, all the rows of liquid crystal pixels in each pixel partition need to be turned over, and the consumed time is the same. If the pixel is set in a pixel area, the time from the beginning of the inversion of the first row of liquid crystal pixels to the end of the inversion of the last row of liquid crystal pixels in the pixel area is t, and if the 2K resolution is still used, 40 backlight areas are taken as an example, namely, the time from the beginning of the inversion of the 1 st row of liquid crystal pixels to the end of the inversion of the 36 th row of liquid crystal pixels in the pixel area is t. In the present invention, the value of t is the same in all backlight partitions.
In order to solve the problem of simultaneously implementing variable refreshing and image black insertion technology under the effect of ensuring brightness of a display image and no image flicker, the embodiment aims to solve the technical problem of controlling a backlight LED to perform black insertion within the time period t. To achieve the technical object, the present embodiment provides the following LED backlight control method.
As shown in fig. 3, when the display panel operates at the first refresh rate, the period of the vertical synchronization signal Vsync is T. In this embodiment, the first refresh rate is the highest refresh rate in the variable refresh rate of the display panel, for example, the variable refresh rate setting of the display panel includes a plurality of options of 180Hz, 165Hz, 144Hz, 120Hz, 75Hz, and 60Hz, and the first refresh rate in this embodiment refers to 180Hz. Accordingly, the period of the vertical synchronization signal Vsync at the first refresh rate is T, which is also the minimum value at the plurality of refresh rates.
In this embodiment, LED current control periods of the backlight partitions corresponding to the vertical synchronization signal Vsync period T at the first refresh rate are divided into a first period T 1 and a second period T 2, and there is a first period T 1 +a second period T 2 =the vertical synchronization signal Vsync period T.
The LED current of the first duration T 1 is a first current value I 1, and the LED current of the second duration T 2 is a second current value I 2. The second current value is a frame current value I Led of the frame display picture. In this embodiment, in order to implement the black insertion of the picture within the first time period T 1, the first current value I 1 needs to be set smaller than the second current value I 2 within the second time period T 2, so as to implement the black insertion effect. In this embodiment, the first current value I 1 satisfies the following two conditions at the same time:
1. The first current value I 1 is set to be greater than zero and less than the second current value I 2;
2. The first current value I 1 is set to be smaller than a first threshold value; the first threshold is 1/2, 1/4, 1/16, 1/32, 1/64 or 1/128 of the current value corresponding to the highest brightness.
By setting the first current value I 1, the LED backlight is prevented from being completely turned off in the first duration, so that the flicker of a picture which can be perceived by human eyes is prevented.
For different backlight partitions, since the number of rows of pixels is the same, the first time period T 1 and the second time period T 2 are both fixed and the first time period T 1 is from the start time of the inversion of the first row of liquid crystal pixels in the pixel partition corresponding to the backlight partition to the end time of the inversion of the last row of liquid crystal pixels in the backlight partition. Or the first time period T 1 is ended in advance or ended in a delayed manner when all the pixel liquid crystals of all the rows in the pixel partition are turned over according to the requirement. I.e., T 1 may be set to be greater than T or less than T. The time periods except the first time period T 1 are the second time period T 2 within the duration range of the vertical synchronization signal Vsync period T.
As can be seen from the above technical means, in this embodiment, in the first refresh rate (the highest refresh rate), when the liquid crystal molecules of the plurality of rows of liquid crystal pixels of the pixel partition corresponding to each backlight partition are in the inversion state, the backlight LED current is set to be in the low current state, that is, the image black insertion is realized.
In this embodiment, the first duration T 1 may not strictly correspond to the time from the start of the turning of the first row of liquid crystal pixels in the pixel partition corresponding to the backlight partition to the time from the completion of the turning of the last row of liquid crystal pixels in the backlight partition according to the actual situation, that is, the first duration T 1 may select the time at which the turning of the pixels in the liquid crystal partition is most intense, that is, the duration T is less than the duration T, and the first duration T 1 may also exceed the duration T, that is, the black inserting duration is longer than the liquid crystal turning duration. Meanwhile, the first time period may be set outside the liquid crystal inversion time zone.
In this embodiment, the first duration T 1 may be greater than the second duration T 2 and may be equal to or less than the second duration T 2, that is, the time relationship between the first duration T 1 and the second duration T 2 is mainly limited by the first duration T 1 +the second duration T 2 =the vertical synchronization signal Vsync period T. When the first time period T 1 is determined according to the case, the second time period T 2 is also determined.
And after the liquid crystal molecules are turned over, the backlight LEDs are lightened to realize picture display, and at the moment, the input current of the backlight LEDs is the frame current I Led determined by the frame picture display data.
The second period T 2 may be divided into a plurality of periods and discontinuous, i.e., may be distributed on both sides of the first period T 1 within the period T of the vertical synchronization signal Vsync.
It should be noted that, at the first refresh rate, the inversion deadline of the nth pixel partition is not necessarily just cut off at the next frame Vsync; the nth pixel partition deadline may exceed the next frame Vsync at a high refresh rate. It is understood that there is a delay between the Vsync signal and the actual picture output, i.e., when pictures are continuously output.
As shown in fig. 4, LED current control periods of the respective backlight partitions corresponding to the vertical synchronization signal Vsync period T' at the second refresh rate (not the highest refresh rate) in the present embodiment are each divided into a first period T 1, a second period T 2, and a third period T 3. And there is a first period T 1 + a second period T 2 + a third period T 3 = vertical synchronization signal Vsync period T'.
The first time period T 1 under the second refresh rate is a determined first time period T 1 under the first refresh rate, and the first time period T 1 is a time period from a start of turning of the first row of liquid crystal pixels in the pixel partition corresponding to the backlight partition to a time period of finishing turning of the last row of liquid crystal pixels in the backlight partition.
The second duration T 2 at the second refresh rate is the determined second duration T 2 at the first refresh rate. Likewise, in the vertical synchronization signal Vsync period T' at the second refresh rate, the periods except for the first period T 1 and the second period T 2 are both the third period T 3. The third period T 3 may be discontinuous, i.e., may be located at both sides of the period T' of the vertical synchronization signal Vsync.
Likewise, in the period T' of the vertical synchronization signal Vsync at the second refresh rate, the LED current of the first period T 1 is zero, and the LED current of the second period T 2 is the frame current I Led. The LED current for the third period of time T 3 is a third current I 3. The value range of the third current I 3 is a frame average current value I avg ±a first current floating value Δi 1, that is, the value range of the third current I 3 is [ I avg-ΔI1,Iavg+ΔI1 ], and the frame average current I avg is expressed as:
the first current floating value Δi 1 is 10%, 15%, 20% of the frame average current I avg.
In this embodiment, the third current value I 3 is in a range of current values I 'avg ±second current floating value Δi 2 corresponding to the frame average luminance, and the second current floating value Δi 2 is 10%, 15%, 20% of the frame average luminance current I' avg.
In this embodiment, the first duration T 1 and the second duration T 2 determined at the first refresh rate are reserved in the second refresh rate, so as to ensure that the influence of the black frame insertion on the brightness is consistent. Meanwhile, the LED current of the third duration T 3 is set to be close to the frame average current I avg, and the frame average current I avg is consistent with the frame average current in the period T of the vertical synchronization signal Vsync of the first refresh rate, so that the consistency of the brightness of the pictures at different refresh rates is ensured, and the backlight flicker phenomenon is eliminated.
Example 2
In this embodiment, on the basis of the foregoing embodiment 1, a backlight LED current control strategy at a third refresh rate is added, and as shown in fig. 5, the third refresh rate is also the non-highest refresh rate in the variable refresh rates.
The vertical synchronization signal Vsync period t″ at the third refresh rate is divided into a plurality of identical vertical synchronization signal Vsync sub-periods T "sub, and the LED current control periods of the respective backlight partitions corresponding to each of the vertical synchronization signal Vsync sub-periods T" sub are each divided into a first period T 1, a second period T 2, and a third period T 3. And there is a first period T 1 + a second period T 2 + a third period T 3 = vertical synchronization signal Vsync sub-period T "sub. Wherein the third time period T 3 may be zero.
The first time period T 1 under the third refresh rate is the determined first time period T 1 under the first refresh rate, and the first time period T 1 is from the start time of the turning of the first row of liquid crystal pixels in the pixel partition corresponding to the backlight partition to the time of the finishing of the turning of the last row of liquid crystal pixels in the backlight partition. And the first time length T 1 may be set to be greater than T or less than T. But the first period of time should cover the period of time during which the liquid crystal in the pixel region is most flipped.
The second duration T 2 at the third refresh rate is the determined second duration T 2 at the first refresh rate. Likewise, in the vertical synchronization signal Vsync sub-period t″ sub at the third refresh rate, the periods except for the first period T 1 and the second period T 2 are both the third period T 3.
Likewise, in the vertical synchronization signal Vsync subperiod t″ sub at the third refresh rate, the first current value I 1 satisfies both of the following two conditions:
1. The first current value I 1 is set to be greater than zero and less than the second current value I 2;
2. The first current value I 1 is set to be smaller than a first threshold value; the first threshold is 1/2, 1/4, 1/16, 1/32, 1/64 or 1/128 of the current value corresponding to the highest brightness.
The LED current for the second period T 2 is the frame current I Led.
The LED current for the third period of time T 3 is a third current I 3. The value range of the third current I 3 is a frame average current value I avg ±a first current floating value Δi 1, that is, the value range of the third current I 3 is [ I avg-ΔI1,Iavg+ΔI1 ], and the frame average current I avg is expressed as:
the first current floating value Δi 1 is 10%, 15%, 20% of the frame average current I avg.
In this embodiment, the third current value I 3 is in a value range of I ' avg ±second current floating value Δi 2 corresponding to the frame average luminance, that is, the third current I 3 is in a value range of I ' avg-ΔI2,I'avg+ΔI2 ], and the second current floating value Δi 2 is 10%, 15%, 20% of the frame average luminance current I ' avg.
In this embodiment, the backlight LED current control can be achieved by frequency doubling for lower refresh rates (e.g., below 70 Hz).
Example 3
In this embodiment, on the basis of embodiment 1, LED current control periods of the respective backlight partitions corresponding to the vertical synchronization signal Vsync period T' at the second refresh rate are each divided into a first period T 1, a second period T 2, and a third period T 3. And there is a first period T 1 + a second period T 2 + a third period T 3 = vertical synchronization signal Vsync period T'.
And the distribution of the first duration T 1, the second duration T 2, and the third duration T 3 in the vertical synchronization signal Vsync period T' at the second refresh rate may be adjusted. For example, as shown in fig. 6, in the vertical synchronization signal Vsync period T' at the second refresh rate, the liquid crystal inversion period corresponds to the first period T 1, then the third period T3 is output, and finally the second period T 2 is output. The technical effect of this embodiment is the same as in example 1.
In this embodiment, the first period T 1 does not correspond to the liquid crystal inversion period, and the first period T 1, the second period T 2, and the third period T 3 may be distributed in any manner in the period T' of the vertical synchronization signal Vsync at the second refresh rate. When the first period T 1 does not correspond to the liquid crystal inversion period, the black insertion effect becomes poor, but backlight flicker can still be eliminated.
The present invention may be any possible integrated technology level system, method and/or computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to perform the various aspects of the invention.
A computer readable storage medium may be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a Static Random Access Memory (SRAM), a portable compact disc read-only memory (CD-ROM), a Digital Versatile Disc (DVD), a memory stick, a floppy disk, a mechanical coding device such as a punch card or a protrusion structure in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer-readable storage medium, as used herein, should not be construed as a transitory signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse through a fiber optic cable), or an electrical signal transmitted through a wire.
The computer readable program instructions described herein may be downloaded from a computer readable storage medium to a corresponding computing/processing device or to an external computer or external storage device via a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers and/or edge servers. The network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.
Computer readable program instructions for performing operations of the present invention can be assembler instructions, instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source code or object code written in any combination of one or more programming languages and procedural programming languages. The computer readable program instructions may be executed entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer, partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, electronic circuitry, including, for example, programmable logic circuitry, field Programmable Gate Arrays (FPGAs), or Programmable Logic Arrays (PLAs), may perform aspects of the invention by utilizing state information of computer-readable program instructions to execute the computer-readable program instructions to personalize the electronic circuitry.
Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.
These computer readable program instructions may be provided to a processor of a computer, or other programmable data processing apparatus, to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having the instructions stored therein includes an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, with some or all of the blocks being time-wise overlapped, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Embodiments of the present application are described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (devices) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only a specific embodiment of the present invention, and the scope of the present invention is not limited thereto, and any person skilled in the art should modify or replace the present invention within the technical specification described in the present invention.
Claims (10)
1. A driving method of an LED backlight assembly adapted to implement image black insertion at a variable refresh rate, the LED backlight assembly comprising:
dividing the LED backlight assembly into a plurality of backlight partitions, wherein each backlight partition corresponds to a pixel partition of a liquid crystal panel, and a plurality of rows of liquid crystal pixels are contained in each pixel partition;
When the liquid crystal panel displays at a first refresh rate, LED current control periods of the backlight partitions corresponding to the vertical synchronization signal Vsync period T at the first refresh rate are divided into a first period T 1 and a second period T 2, and T 1+T2 =t;
The LED current of the first duration T 1 is a first current value I 1, and the LED current of the second duration T 2 is a second current value I 2;
the second current value is a frame current value I Led of the frame display picture;
The first current value I 1 is simultaneously satisfied: the first current value I 1 is set to be greater than zero and less than the second current value I 2; while the first current value I 1 is set to be less than the first threshold value;
When the liquid crystal panel displays at the second refresh rate, the LED current control periods of the backlight partitions corresponding to the vertical synchronization signal Vsync period T' at the second refresh rate are divided into a first period T 1, a second period T 2, and a third period T 3; and has T 1+T2+T3 = T';
The LED current of the third duration T 3 is a third current I 3; the value range of the third current I 3 is the average current + -current floating value delta I;
the average current is a current value corresponding to a frame average current value or a frame average brightness;
the first refresh rate is greater than the second refresh rate.
2. The driving method of an LED backlight assembly according to claim 1, wherein the liquid crystal pixels within the pixel section are identical.
3. The method of driving an LED backlight assembly of claim 1, wherein the first refresh rate is a highest refresh rate of the variable refresh rate settings.
4. The driving method of an LED backlight assembly according to claim 1, wherein the first threshold is 1/2, 1/4, 1/16, 1/32, 1/64 or 1/128 of a current value corresponding to the highest luminance.
5. The method of driving an LED backlight assembly according to claim 1, wherein the current floating value Δi is 10%, 15%, 20% of an average luminance current corresponding to a frame average current or a frame average luminance.
6. The driving method of an LED backlight assembly according to claim 1, wherein when the liquid crystal panel displays at a third refresh rate, the vertical synchronization signal Vsync period t″ at the third refresh rate is divided into a plurality of identical vertical synchronization signal Vsync sub-periods T "sub, and the LED current control periods of the respective backlight partitions corresponding to each of the vertical synchronization signal Vsync sub-periods T" sub are each divided into a first period T 1, a second period T 2, and a third period T 3. And has a T 1+T2+T3＝T"sub.
7. The driving method of an LED backlight assembly according to claim 1, wherein the second period T 2 or the third period T 3 is discontinuous in a vertical synchronization signal period.
8. The driving method of an LED backlight assembly according to claim 1, wherein the first, second and third periods T 1, T 2 and T 3 are not arranged in a fixed order within a period of the vertical synchronization signal at the second or third refresh rate.
9. An LED backlight panel characterized in that the LED backlight panel performs backlight control using the driving method according to one of claims 1 to 8.
10. A display panel, characterized in that the display panel comprises the LED backlight panel according to claim 9 or the backlight control is performed using the driving method of the LED backlight assembly according to any one of claims 1 to 8.
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| CN202410436731.4A Active CN118116340B (en) | 2024-02-04 | 2024-04-12 | LED backlight driving method capable of simultaneously realizing variable refresh rate and image black insertion display |
| CN202410586653.6A Pending CN118366408A (en) | 2024-02-04 | 2024-05-13 | LED backlight assembly capable of realizing image black insertion under variable refresh rate and control method |
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| CN202410586653.6A Pending CN118366408A (en) | 2024-02-04 | 2024-05-13 | LED backlight assembly capable of realizing image black insertion under variable refresh rate and control method |
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| CN118116340B (en) | 2024-12-06 |
| CN118116340A (en) | 2024-05-31 |
| CN118366408A (en) | 2024-07-19 |
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