CN118152302B - Dynamic partitioning method and device for data storage area of memory on FPGA (field programmable Gate array) chip - Google Patents

Abstract

The invention discloses a method and a device for dynamically dividing a data storage area of an on-chip memory of an FPGA, which relate to the technical field of FPGAs, wherein the on-chip memory is an on-chip nonvolatile memory and comprises the data storage area, and the method comprises the following steps: determining a division mode selected by a user based on the region dynamic division signal; when the division mode selected by the user is dynamic division, acquiring a dynamic demarcation address set by the user; the data storage area is divided into a configuration data area and a user data area according to the dynamic demarcation address. The invention can dynamically divide the configuration data area and the user data area according to the user requirement, so that the user can use the nonvolatile memory on the FPGA chip more flexibly, and the use scene of the FPGA chip is increased.

Description

Method and device for dynamically dividing data storage area of FPGA on-chip memory

Technical Field

The present invention belongs to the field of FPGA technology, and in particular relates to a method and a device for dynamically dividing data storage areas of an on-chip memory of an FPGA.

Background Art

Most FPGA (Field Programmable Gate Array) devices are based on SRAM (Static Random-Access Memory) structure. The programming information is lost immediately after power failure. Each time the power is turned on, the programming information needs to be loaded into the configuration SRAM inside the FPGA chip. After completing this configuration process, the FPGA chip can start working according to the user's design.

At present, the configuration methods of FPGA mainly include: active configuration, passive configuration and JTAG (Joint Test Action Group) configuration, among which the active configuration method needs to use off-chip non-volatile memory or FPGA on-chip non-volatile memory to implement. When using FPGA on-chip non-volatile memory for active configuration, the on-chip non-volatile memory is generally divided into multiple areas, such as function information area, configuration data area and user data area. Different commands can be used to read, write, erase and other operations on different areas of the on-chip non-volatile memory.

Since the amount of user programming information changes with the user's design, the space occupied when the programming information is stored in the on-chip non-volatile memory will also change. In the prior art, when dividing the configuration data area and the user data area of the on-chip non-volatile memory, one method is to use a method of dividing into fixed areas, that is, dividing the configuration data area and the user data area into fixed areas. At this time, it is necessary to select an on-chip non-volatile memory with a capacity greater than the sum of the capacities of the configuration data area and the user data area. If the user does not need to store data in the user data area when using it, the area will be wasted; another method is to expand the configuration data area of the on-chip non-volatile memory by occupying a part of the user data area, but when there is less programming information and more user data or the user wants to use the entire area of the on-chip non-volatile memory to store user data, it is impossible to provide enough space.

Summary of the invention

In order to solve the above problems existing in the prior art, the present invention provides a method and device for dynamically dividing the data storage area of the on-chip memory of an FPGA. The technical problem to be solved by the present invention is achieved by the following technical solutions:

In a first aspect, the present invention provides a method for dynamically partitioning a data storage area of an on-chip memory of an FPGA, wherein the on-chip memory is an on-chip non-volatile memory, comprising a data storage area;

The method comprises:

Determine the division method selected by the user based on the dynamic area division signal;

When the partitioning method selected by the user is dynamic partitioning, the dynamic boundary address set by the user is obtained;

The data storage area is divided into a configuration data area and a user data area according to the dynamic boundary address.

In one embodiment of the present invention, the on-chip non-volatile memory further includes a function information area, the FPGA includes an FPGA configuration module, and the FPGA configuration module includes an on-chip non-volatile memory control module;

The step of determining the division method selected by the user based on the area dynamic division signal includes:

After the FPGA is powered on, the on-chip non-volatile memory control module is used to read the dynamic area division signal from the functional information area;

The division method selected by the user is determined according to the area dynamic division signal.

In one embodiment of the present invention, the division method includes dynamic division and fixed division;

The step of determining the division method selected by the user according to the area dynamic division signal comprises:

When the area dynamic division signal is 0, it indicates that the division method selected by the user is fixed division;

When the area dynamic division signal is 1, it indicates that the division method selected by the user is dynamic division.

In one embodiment of the present invention, when the division mode selected by the user is dynamic division, the step of obtaining the dynamic boundary address set by the user includes:

The dynamic demarcation address is read from the function information area using the on-chip non-volatile memory control module.

In one embodiment of the present invention, the step of dividing the data storage area into a configuration data area and a user data area according to the dynamic boundary address includes:

An area in the on-chip non-volatile memory with an address less than or equal to the dynamic demarcation address is divided into a configuration data area, and an area in the on-chip non-volatile memory with an address greater than the dynamic demarcation address is divided into a user data area.

In one embodiment of the present invention, after the step of determining the division method selected by the user based on the dynamic area division signal, the method further includes:

When the division method selected by the user is fixed division, the area in the address range of 16'h0000~16'h2fff in the on-chip non-volatile memory is divided into a configuration data area, and the area in the address range of 16'h3000~16'h3fff in the on-chip non-volatile memory is divided into a user data area.

In a second aspect, the present invention further provides a device for dynamically dividing data storage areas of an on-chip memory of an FPGA, wherein the on-chip memory is an on-chip non-volatile memory, comprising a data storage area;

The device comprises:

A determination module, used to determine the division method selected by the user based on the area dynamic division signal;

The acquisition module is used to acquire the dynamic boundary address set by the user when the division mode selected by the user is dynamic division;

The partitioning module is used to partition the data storage area into a configuration data area and a user data area according to the dynamic boundary address.

Compared with the prior art, the present invention has the following beneficial effects:

The present invention provides a method and device for dynamically dividing the data storage area of an FPGA on-chip memory. When dividing, firstly, the division method selected by the user is determined based on the regional dynamic division signal. When the division method selected by the user is dynamic division, the dynamic boundary address set by the user is obtained, and finally the data storage area is divided into a configuration data area and a user data area according to the dynamic boundary address. The present invention can dynamically divide the configuration data area and the user data area according to user needs, so that the user can use the FPGA on-chip non-volatile memory more flexibly, and increase the use scenarios of the FPGA chip.

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

1 is a flow chart of a method for dynamically partitioning data storage areas in an FPGA on-chip memory provided by an embodiment of the present invention;

2 is a schematic diagram of a method for dynamically dividing data storage areas of an on-chip non-volatile memory provided by an embodiment of the present invention;

3 is a schematic diagram of a fixed partitioning method of an on-chip non-volatile memory data storage area provided by an embodiment of the present invention;

FIG. 4 is a schematic diagram of a structure of a device for dynamically dividing data storage areas in an on-chip memory of an FPGA provided by an embodiment of the present invention.

DETAILED DESCRIPTION

The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

Fig. 1 is a flow chart of a method for dynamically dividing data storage areas of an FPGA on-chip memory provided by an embodiment of the present invention. Referring to Fig. 1, an embodiment of the present invention provides a method for dynamically dividing data storage areas of an FPGA on-chip memory, wherein the on-chip memory is an on-chip non-volatile memory, including a data storage area;

The above methods include:

S1. Determine the division method selected by the user based on the dynamic area division signal;

S2. When the partitioning method selected by the user is dynamic partitioning, obtaining the dynamic boundary address set by the user;

S3. Divide the data storage area into a configuration data area and a user data area according to the dynamic boundary address.

It should be understood that the amount of user programming information varies with the user design. If the user uses fewer FPGA logic resources during design, the amount of programming information data will also be smaller. On the contrary, if the user uses more FPGA logic resources during design or uses EBR (Embedded Block RAM), the amount of programming information data will be larger. Therefore, when the programming information is stored in the on-chip non-volatile memory, the space occupied will also change.

In this embodiment, the FPGA on-chip non-volatile memory includes a data storage area, and the data storage area further includes a configuration data area and a user data area, wherein the configuration data area is used to store user programming information, and the user data area is used to store other user data. Optionally, the user selects the division method of the configuration data area and the user data area in the on-chip non-volatile memory through the supporting software of the FPGA. If the dynamic division method is selected, the user needs to set the dynamic boundary address at the same time; then, the software generates corresponding read and write commands, and stores the division method, dynamic boundary address and other information set by the user in the form of a regional dynamic division signal to the FPGA on-chip non-volatile memory. Therefore, when dividing the data storage area of the FPGA on-chip non-volatile memory, the division method selected by the user can be determined by the regional dynamic division signal.

It should be noted that user programming information refers to the information contained in the configuration bitstream file when the user converts the designed code into the configuration bitstream file through the supporting software of the FPGA. The process of writing the user programming information in the configuration bitstream file into the configuration SRAM using the corresponding interface of the FPGA is called "configuration". Generally speaking, there are many configuration methods, one of which is to use the on-chip non-volatile memory. At this time, the user programming information in the configuration bitstream file needs to be stored in the configuration data area of the on-chip non-volatile memory.

Optionally, in steps S2 to S3, when the division method selected by the user is dynamic division, a dynamic boundary address set by the user is obtained, so that the data storage area is divided into two parts, a configuration data area and a user data area, according to the dynamic boundary address.

It can be seen that the method for dynamically dividing the data storage area of the FPGA on-chip memory provided by the present invention can dynamically divide the configuration data area and the user data area according to user needs, allowing users to use the FPGA on-chip non-volatile memory more flexibly and increasing the use scenarios of the FPGA chip.

Furthermore, the on-chip non-volatile memory further includes a function information area, the FPGA includes an FPGA configuration module, and the FPGA configuration module includes an on-chip non-volatile memory control module;

In step S1, the step of determining the division method selected by the user based on the area dynamic division signal includes:

S101, after the FPGA is powered on, using the on-chip non-volatile memory control module to read the dynamic area division signal from the function information area;

S102: Determine the division method selected by the user according to the regional dynamic division signal.

In this embodiment, the on-chip non-volatile memory also includes a functional information area. After the user sets the division method through the supporting software of the FPGA, the software generates read and write commands for the functional information area, and stores the division method and other information set by the user in the form of a dynamic regional division signal in the functional information area of the on-chip non-volatile memory.

After the FPGA is powered on, the configuration process starts, and the FPGA configuration module can use the on-chip non-volatile memory control module to read the area dynamic division signal from the functional information area and make a judgment.

Figure 2 is a schematic diagram of a dynamic partitioning method of an on-chip non-volatile memory data storage area provided by an embodiment of the present invention, and Figure 3 is a schematic diagram of a fixed partitioning method of an on-chip non-volatile memory data storage area provided by an embodiment of the present invention. Please refer to Figures 2-3. In this embodiment, the partitioning method includes dynamic partitioning and fixed partitioning;

The step of dynamically dividing the signal according to the region and determining the division method selected by the user comprises:

When the area dynamic division signal is 0, it means that the division method selected by the user is fixed division;

When the area dynamic division signal is 1, it means that the division method selected by the user is dynamic division.

Please continue to refer to FIG. 2 . When the division mode selected by the user is dynamic division, the step of obtaining the dynamic boundary address set by the user includes:

The dynamic demarcation address is read from the function information area using the on-chip non-volatile memory control module.

Further, the step of dividing the data storage area into a configuration data area and a user data area according to the dynamic boundary address includes:

An area in the on-chip nonvolatile memory with an address less than or equal to the dynamic demarcation address is divided into a configuration data area, and an area in the on-chip nonvolatile memory with an address greater than the dynamic demarcation address is divided into a user data area.

Specifically, when it is determined that the division method selected by the user is a dynamic division method, the area in the on-chip non-volatile memory whose address is less than or equal to the dynamic boundary address is divided into a configuration data area, that is, when the FPGA configuration module receives relevant commands for reading and writing the configuration data area, it will only perform read and write operations on the area in the on-chip non-volatile memory whose address is less than or equal to the dynamic boundary address; at the same time, the area in the on-chip non-volatile memory whose address is greater than the dynamic boundary address is divided into a user data area, that is, when the FPGA configuration module receives relevant commands for reading and writing the user data area, it will only perform read and write operations on the area in the on-chip non-volatile memory whose address is greater than the boundary address.

Optionally, after the step of determining the division method selected by the user based on the dynamic area division signal, the method further includes:

When the partitioning method selected by the user is fixed partitioning, the area in the address range of 16'h0000~16'h2fff in the on-chip non-volatile memory is divided into the configuration data area, and the area in the address range of 16'h3000~16'h3fff in the on-chip non-volatile memory is divided into the user data area.

Specifically, if the division method selected by the user is a fixed division method, then the area in the on-chip non-volatile memory with an address range of 16’h0000~16’h2fff is divided into the configuration data area. When the FPGA configuration module receives the relevant command to read and write the configuration data area, it only performs read and write operations on the area in the on-chip non-volatile memory with an address range of 16’h0000~16’h2fff. At the same time, the area in the on-chip non-volatile memory with an address range of 16’h3000~16’h3fff is divided into the user data area. When the FPGA configuration module receives the relevant command to read and write the user data area, it only performs read and write operations on the area in the on-chip non-volatile memory with an address range of 16’h3000~16’h3fff.

Fig. 4 is a schematic diagram of a structure of a device for dynamically dividing data storage areas of an FPGA on-chip memory provided by an embodiment of the present invention. As shown in Fig. 4, an embodiment of the present invention further provides a device for dynamically dividing data storage areas of an FPGA on-chip memory, wherein the on-chip memory is an on-chip non-volatile memory, including a data storage area;

The above device comprises:

A determination module 410, configured to determine a division method selected by a user based on a dynamic area division signal;

The acquisition module 420 is used to acquire the dynamic boundary address set by the user when the division mode selected by the user is dynamic division;

The partitioning module 430 is used to partition the data storage area into a configuration data area and a user data area according to the dynamic boundary address.

It can be seen from the above embodiments that the beneficial effects of the present invention are:

The present invention provides a method and device for dynamically dividing the data storage area of an FPGA on-chip memory. When dividing, the division method selected by the user is first determined based on the regional dynamic division signal. When the division method selected by the user is dynamic division, the dynamic boundary address set by the user is obtained, and finally the data storage area is divided into a configuration data area and a user data area according to the dynamic boundary address. The present invention can dynamically divide the configuration data area and the user data area according to user needs, so that the user can use the FPGA on-chip non-volatile memory more flexibly, and increase the use scenarios of the FPGA chip.

In the description of the present invention, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims (4)

1. A method for dynamically partitioning data storage areas of an on-chip memory of an FPGA, characterized in that the on-chip memory is an on-chip non-volatile memory, comprising a data storage area; The method comprises: Determine the division method selected by the user based on the dynamic area division signal; When the partitioning method selected by the user is dynamic partitioning, the dynamic boundary address set by the user is obtained; Dividing the data storage area into a configuration data area and a user data area according to the dynamic boundary address; The on-chip non-volatile memory further includes a function information area, the FPGA includes an FPGA configuration module, and the FPGA configuration module includes an on-chip non-volatile memory control module; The step of determining the division method selected by the user based on the area dynamic division signal includes: After the FPGA is powered on, the on-chip non-volatile memory control module is used to read the dynamic area division signal from the functional information area; Determining the division method selected by the user according to the area dynamic division signal; Wherein, the division method includes dynamic division and fixed division; The step of determining the division method selected by the user according to the area dynamic division signal comprises: When the area dynamic division signal is 0, it indicates that the division method selected by the user is fixed division; When the area dynamic division signal is 1, it indicates that the division method selected by the user is dynamic division; When the partitioning method selected by the user is dynamic partitioning, the step of obtaining the dynamic boundary address set by the user includes: The dynamic boundary address is read from the functional information area using the on-chip non-volatile memory control module; wherein the division method set by the user and the dynamic boundary address are pre-stored in the FPGA on-chip non-volatile memory in the form of the dynamic division signal of the area through the read and write commands of the functional information area. 2. The method for dynamically dividing the data storage area of the FPGA on-chip memory according to claim 1, characterized in that the step of dividing the data storage area into a configuration data area and a user data area according to the dynamic boundary address comprises: An area in the on-chip non-volatile memory with an address less than or equal to the dynamic demarcation address is divided into a configuration data area, and an area in the on-chip non-volatile memory with an address greater than the dynamic demarcation address is divided into a user data area. 3. The method for dynamically dividing the data storage area of the FPGA on-chip memory according to claim 1, characterized in that after the step of determining the division method selected by the user based on the area dynamic division signal, it also includes: When the division method selected by the user is fixed division, the area in the address range of 16'h0000~16'h2fff in the on-chip non-volatile memory is divided into a configuration data area, and the area in the address range of 16'h3000~16'h3fff in the on-chip non-volatile memory is divided into a user data area. 4. A device for dynamically dividing data storage areas of an on-chip memory of an FPGA, characterized in that the on-chip memory is an on-chip non-volatile memory, comprising a data storage area; The device comprises: A determination module, used to determine the division method selected by the user based on the area dynamic division signal; The acquisition module is used to acquire the dynamic boundary address set by the user when the division mode selected by the user is dynamic division; A partitioning module, used for partitioning the data storage area into a configuration data area and a user data area according to the dynamic boundary address; The on-chip non-volatile memory further includes a function information area, the FPGA includes an FPGA configuration module, and the FPGA configuration module includes an on-chip non-volatile memory control module; The determination module is specifically used to: after the FPGA is powered on, use the on-chip non-volatile memory control module to read the dynamic area division signal from the functional information area; and determine the division method selected by the user according to the dynamic area division signal; Wherein, the division method includes dynamic division and fixed division; The step of determining the division method selected by the user according to the area dynamic division signal comprises: When the area dynamic division signal is 0, it indicates that the division method selected by the user is fixed division; When the area dynamic division signal is 1, it indicates that the division method selected by the user is dynamic division; The acquisition module is used to use the on-chip non-volatile memory control module to read the dynamic boundary address from the functional information area; wherein the division method set by the user and the dynamic boundary address are pre-stored in the FPGA on-chip non-volatile memory in the form of the area dynamic division signal through the read and write commands of the functional information area.