CN118136680B - Double-carrier LDMOS device and manufacturing method - Google Patents

Abstract

The invention relates to the technical field of semiconductors, and provides a double-carrier LDMOS device and a manufacturing method thereof. Comprising the following steps: the semiconductor device comprises a substrate, a buried oxide layer, an N-type drift region, a positive grid, a P-type source region, a P-type drain region, a P-type body region, an N-type source region, an N-type drain region and a back grid, wherein the buried oxide layer is formed on the upper surface of the substrate, the bottom of the P-type source region is connected with the N-type drift region and the buried oxide layer, the bottom of the P-type drain region is connected with the N-type drift region and the buried oxide layer, the N-type source region is connected with the P-type body region, and the N-type drain region is connected with the N-type drift region. The P-type source region, the P-type drain region, the N-type drift region and the back gate form a PLDMOS structure, so that a P-type channel is formed at the bottom of the N-type drift region; the N-type source region, the N-type drain region, the N-type drift region, the P-type body region and the positive grid electrode form an NLDMOS structure, so that an N-type channel is formed on the surface of the P-type body region. The invention simultaneously utilizes the flow of holes in the P-type channel and electrons in the N-type channel to reduce the specific on-resistance of the device.

Description

Dual-carrier LDMOS device and manufacturing method

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to a dual-carrier LDMOS device and a manufacturing method thereof.

Background technique

LDMOS (Lateral Double-diffusion Metal Oxide Semiconductor) is a typical power MOS device. LDMOS devices have the characteristics of high operating frequency, high linearity and low noise, and are widely used in high-frequency and high-power transmission systems. For LDMOS, breakdown voltage (Breakdown Voltage, BV) and specific on-resistance (Specific On-resistance, R _{on, sp} ) are the main technical indicators. There are two conventional technical methods to increase the breakdown voltage of LDMOS: increasing the length of the drift region of the device and reducing the doping concentration of the drift region. However, these two methods will lead to an increase in the effective conduction area and resistivity of the device, respectively, and ultimately increase the specific on-resistance of the device. Therefore, the research on LDMOS mainly focuses on how to solve the contradiction between high breakdown voltage and low specific on-resistance. With the development of the electronics industry, the mainstream technology of traditional LDMOS optimization can no longer meet the growing performance requirements of LDMOS. Proposing a new LDMOS structure has become an urgent problem to be solved.

Summary of the invention

The present invention provides a dual-carrier LDMOS device and a manufacturing method thereof, which solves the contradictory relationship between the breakdown voltage and the specific on-resistance of the LDMOS device and effectively reduces the specific on-resistance of the device.

The present invention provides a dual-carrier LDMOS device, comprising: a substrate, a buried oxide layer, an N-type drift region, a gate oxide layer, a positive gate, a P-type source region, a P-type drain region, a P-type body region, an N-type source region, an N-type drain region, and a back gate;

The buried oxide layer is formed on the upper surface of the substrate, the N-type drift region is formed on the surface of the buried oxide layer, and the back gate is formed on the lower surface of the substrate;

The bottom of the P-type source region is connected to the N-type drift region and the buried oxide layer, the bottom of the P-type drain region is connected to the N-type drift region and the buried oxide layer, the N-type source region is connected to the P-type body region, and the N-type drain region is connected to the N-type drift region;

The P-type source region, the P-type drain region, the N-type drift region and the back gate form a PLDMOS structure, so that a P-type channel is formed at the bottom of the N-type drift region;

The N-type source region, the N-type drain region, the N-type drift region, the P-type body region and the positive gate constitute an NLDMOS structure, so that an N-type channel is formed on the surface of the P-type body region.

In the embodiment of the present invention, the upper portion of the P-type source region is connected to the N-type source region, and the upper portion of the P-type drain region is connected to the N-type drain region.

In the embodiment of the present invention, the P-type body region includes a lateral region and a longitudinal region, the lateral region of the P-type body region is connected to the P-type source region, and the longitudinal region of the P-type body region is connected to the gate oxide layer.

In the embodiment of the present invention, the thickness of the N-type drift region between the lateral region of the P-type body region and the buried oxide layer is 100-300 nm.

In an embodiment of the present invention, the substrate is a silicon-on-insulator substrate, which includes an insulating layer, a buried oxide layer and a top silicon layer, and the buried oxide layer of the silicon-on-insulator substrate serves as the buried oxide layer of the dual-carrier LDMOS device.

In an embodiment of the present invention, the carriers of the P-type channel are holes, and the number of carriers in the hole channel is controlled by changing the voltage of the back gate;

The carriers of the N-type channel are electrons, and the number of carriers in the electron channel is controlled by changing the voltage of the positive gate.

In the embodiment of the present invention, the P-type source region and the P-type drain region are P-type heavily doped regions, and the doping concentration is greater than 1×10 ¹⁸ cm ^-3 ;

The N-type source region and the N-type drain region are N-type heavily doped regions, and the doping concentration is greater than 1×10 ¹⁸ cm ^-3 ;

The P-type body region is a P-type lightly doped region, and the doping concentration is less than 1×10 ¹⁶ cm ^-3 ;

The N-type drift region is an N-type lightly doped region, and the doping concentration is less than 1×10 ¹⁶ cm ^-3 .

Another aspect of the present invention provides a method for manufacturing a dual-carrier LDMOS device, comprising:

forming an N-type lightly doped region on the upper surface of the substrate having the buried oxide layer;

Ion implantation is performed in the N-type lightly doped region to form a P-type source region, a P-type drain region, a P-type body region, an N-type source region, an N-type drain region and an N-type drift region; wherein the bottom of the P-type source region is connected to the N-type drift region and the buried oxide layer, the bottom of the P-type drain region is connected to the N-type drift region and the buried oxide layer, the N-type source region is connected to the P-type body region, and the N-type drain region is connected to the N-type drift region;

A gate oxide layer and a positive gate are formed above the N-type drift region and the P-type body region, and the N-type source region, the N-type drain region, the N-type drift region, the P-type body region and the positive gate constitute an NLDMOS structure;

A back gate is formed on the lower surface of the substrate, and a P-type source region, a P-type drain region, an N-type drift region and the back gate constitute a PLDMOS structure.

In an embodiment of the present invention, an N-type lightly doped region is formed on the upper surface of a substrate having a buried oxide layer, including: using a silicon substrate on an insulating layer, doping the top silicon of the silicon substrate on the insulating layer to form the N-type lightly doped region.

In an embodiment of the present invention, ion implantation is performed in the N-type lightly doped region, including:

Performing P-type ion implantation in a first predetermined region of the N-type lightly doped region to form a P-type source region, a P-type drain region and a P-type body region;

N-type ion implantation is performed in a second predetermined region of the N-type lightly doped region to form an N-type source region and an N-type drain region, and the remaining N-type lightly doped region serves as an N-type drift region.

The dual-carrier LDMOS device of the present invention comprises two structures, PLDMOS and NLDMOS. In the PLDMOS structure, by applying a negative voltage to the back gate, positive charges are generated at the bottom of the N-type drift region to form a hole channel (P-type channel), and the hole current flows from the P-type source region to the P-type drain region; in the NLDMOS structure, by applying a positive voltage to the positive gate, negative charges are induced on the surface of the P-type body region to form an electron channel (N-type channel), and the electron current flows from the N-type source region to the N-type drain region. The present invention forms a P-type channel and an N-type channel, and simultaneously utilizes the flow of holes in the P-type channel and the flow of electrons in the N-type channel to realize device conduction, thereby effectively reducing the specific on-resistance of the device.

Other features and advantages of the technical solution of the present invention will be described in detail in the specific implementation section below.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

FIG1 is a schematic structural diagram of a dual-carrier LDMOS device provided in an embodiment of the present invention;

2 is a schematic diagram of a channel formed by a dual-carrier LDMOS device provided in an embodiment of the present invention;

3 is a comparison diagram of the specific on-resistance of the dual-carrier LDMOS provided by an embodiment of the present invention and the conventional LDMOS;

4a to 4g are schematic diagrams of structures formed in various steps of the method for manufacturing a dual-carrier LDMOS device provided in an embodiment of the present invention.

Description of Reference Numerals

10-substrate, 11-buried oxide layer, 12-N-type drift region, 13-gate oxide layer, 14-positive gate,

15-P type source region, 16-P type drain region, 17-P type body region, 18-N type source region, 19-N type drain region,

20-source, 21-drain, 22-back gate.

Detailed ways

In order to make the technical solutions and advantages of the embodiments of the present invention more clearly understood, the exemplary embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

In the present invention, unless otherwise clearly specified and limited, the terms such as "connected", "connected", "connected" and the like should be understood in a broad sense, for example, it can be a mechanical connection, an electrical connection or mutual communication; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

The embodiment of the present invention provides a dual-carrier LDMOS device, comprising: a substrate, a buried oxide layer, an N-type drift region, a gate oxide layer, a positive gate, a P-type source region, a P-type drain region, a P-type body region, an N-type source region, an N-type drain region and a back gate. The buried oxide layer is formed on the upper surface of the substrate, the N-type drift region is formed on the surface of the buried oxide layer, the back gate is formed on the lower surface of the substrate, the bottom of the P-type source region is connected to the N-type drift region and the buried oxide layer, the bottom of the P-type drain region is connected to the N-type drift region and the buried oxide layer, the N-type source region is connected to the P-type body region, and the N-type drain region is connected to the N-type drift region. The P-type source region, the P-type drain region, the N-type drift region and the back gate form a PLDMOS structure, so that a P-type channel is formed at the bottom of the N-type drift region; the N-type source region, the N-type drain region, the N-type drift region, the P-type body region and the positive gate form an NLDMOS structure, so that an N-type channel is formed on the surface of the P-type body region.

The dual-carrier LDMOS device of the present invention includes two structures, PLDMOS and NLDMOS. In the PLDMOS structure, by applying a negative voltage to the back gate, positive charges are generated at the bottom of the N-type drift region to form a hole channel (P-type channel), and the hole current flows from the P-type source region to the P-type drain region; in the NLDMOS structure, by applying a positive voltage to the positive gate, negative charges are induced on the surface of the P-type body region to form an electron channel (N-type channel), and the electron current flows from the N-type source region to the N-type drain region. The present invention forms a P-type channel and an N-type channel, and at the same time uses the flow of holes in the P-type channel and the flow of electrons in the N-type channel to realize device conduction, effectively reducing the specific on-resistance of the device. The technical solution of the present invention is described in detail below through specific embodiments.

FIG1 is a schematic diagram of the structure of a dual-carrier LDMOS device provided by an embodiment of the present invention. As shown in FIG1 , the dual-carrier LDMOS device of the present embodiment includes: a substrate 10, a buried oxide layer 11, an N-type drift region 12, a gate oxide layer 13, a positive gate 14, a P-type source region 15, a P-type drain region 16, a P-type body region 17, an N-type source region 18, an N-type drain region 19, and a back gate. The buried oxide layer 11 is formed on the upper surface of the substrate 10, the N-type drift region 12 is formed on the surface of the buried oxide layer 11, the back gate is formed on the lower surface of the substrate 10, the bottom of the P-type source region 15 is connected to the N-type drift region 12 and the buried oxide layer 11, the bottom of the P-type drain region 16 is connected to the N-type drift region 12 and the buried oxide layer 11, the N-type source region 18 is connected to the P-type body region 17, and the N-type drain region 19 is connected to the N-type drift region 12. The P-type source region 15 , the P-type drain region 16 , the N-type drift region 12 and the back gate constitute a PLDMOS structure, and the N-type source region 18 , the N-type drain region 19 , the N-type drift region 12 , the P-type body region 17 and the positive gate 14 constitute a NLDMOS structure.

The upper portion of the P-type source region 15 is connected to the N-type source region 18, and the upper portion of the P-type drain region 16 is connected to the N-type drain region 19. The P-type body region 17 includes a lateral region and a longitudinal region, the lateral region of the P-type body region 17 is connected to the P-type source region 15, and the longitudinal region of the P-type body region is connected to the gate oxide layer 13. The thickness of the N-type drift region between the lateral region of the P-type body region 17 and the buried oxide layer 11 is 100-300nm.

One side of the N-type source region 18 is connected to the P-type source region 15, and the other side and the bottom of the N-type source region 18 are connected to the P-type body region. A source electrode 20 is formed above the P-type source region 15 and the N-type source region 18, and a drain electrode 21 is formed above the P-type drain region 16 and the N-type drain region 19. The P-type source region 15 and the N-type source region 18 constitute the source region of the device, and the P-type drain region 16 and the N-type drain region 19 constitute the drain region of the device. The source region and the source electrode 20 form an ohmic contact, and the drain region and the drain electrode 21 form an ohmic contact. The material of the source electrode 20, the drain electrode 21 and the back gate 22 is selected from metal aluminum.

As shown in FIG2 , the N-type source region, the N-type drain region, the N-type drift region, the P-type body region and the positive gate constitute the NLDMOS structure. A positive bias is applied to the positive gate 14, and a large amount of induced negative charge accumulation is generated on the surface of the P-type body region 17 through the NLDMOS structure to form an N-type electron conductive channel. The P-type source region, the P-type drain region, the N-type drift region and the back gate constitute the PLDMOS structure. A negative bias is applied to the back gate 22, and a large amount of induced positive charge accumulation is generated at the bottom of the N-type drift region 12 through the PLDMOS structure to form a P-type hole conductive channel. Since NLDMOS and PLDMOS share the source-drain structure, the total channel current of the device includes the electron current of NLDMOS and the hole current of PLDMOS, and the device has a low specific on-resistance. The carriers of the P-type channel are holes, and the number of carriers in the hole channel is controlled by changing the voltage of the back gate. The carriers of the N-type channel are electrons, and the number of carriers in the electron channel is controlled by changing the voltage of the positive gate.

FIG3 is a comparison diagram of the specific on-resistance of the dual-carrier LDMOS provided by an embodiment of the present invention and the conventional LDMOS. As shown in FIG3, under the condition that the bias voltage of the positive gate is set to 10.0 V and the bias voltage of the back gate is set to -10.0 V, the drain voltage is 0V~3V, the drain current is 0A~0.0014A, and the specific on-resistance of the dual-carrier LDMOS device is 58 mΩ·mm ^2. Compared with the specific on-resistance of 96.8 mΩ·mm ² of the conventional LDMOS device under the same working conditions, it decreases by 40%. This result proves that the dual-carrier LDMOS device of the present invention has better conduction performance than the conventional LDMOS device structure.

In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate, which has an insulating layer, a buried oxide layer and a top silicon layer. The buried oxide layer of the SOI can be directly used as the buried oxide layer 11 of the dual-carrier LDMOS device. The top silicon of the SOI can be doped to form an N-type drift region, a P-type body region, a P-type source region, a P-type drain region, an N-type source region, an N-type drain region and other regions.

In another embodiment, the substrate 10 is a lightly doped support substrate with a doping concentration less than 1×10 ¹⁵ cm ^-3 , and the material includes but is not limited to silicon, germanium, and III-V compounds. The material of the buried oxide layer 11 is silicon dioxide. The material of the gate oxide layer 13 is silicon dioxide, and the material of the positive gate layer 14 is polysilicon.

In one embodiment, the N-type drift region 12 is an N-type lightly doped region, and the doping concentration is less than 1×10 ¹⁶ cm ⁻³ ;

The P-type source region 15 and the P-type drain region 16 are P-type heavily doped regions, and the doping concentration is greater than 1×10 ¹⁸ cm ^-3 ;

The P-type body region 17 is a P-type lightly doped region, and the doping concentration is less than 1×10 ¹⁶ cm ^-3 ;

The N-type source region 18 and the N-type drain region 19 are N-type heavily doped regions, and the doping concentration is greater than 1×10 ¹⁸ cm ⁻³ .

The embodiment of the present invention also provides a method for manufacturing the dual-carrier LDMOS device, the method comprising the following steps:

forming an N-type lightly doped region on the upper surface of the substrate having the buried oxide layer;

Ion implantation is performed in the N-type lightly doped region to form a P-type source region, a P-type drain region, a P-type body region, an N-type source region, an N-type drain region and an N-type drift region; wherein the bottom of the P-type source region is connected to the N-type drift region and the buried oxide layer, the bottom of the P-type drain region is connected to the N-type drift region and the buried oxide layer, the N-type source region is connected to the P-type body region, and the N-type drain region is connected to the N-type drift region;

A gate oxide layer and a positive gate are formed above the N-type drift region and the P-type body region, and the N-type source region, the N-type drain region, the N-type drift region, the P-type body region and the positive gate constitute an NLDMOS structure;

A back gate is formed on the lower surface of the substrate, and a P-type source region, a P-type drain region, an N-type drift region and the back gate constitute a PLDMOS structure.

In the above steps, a silicon-on-insulator (SOI) substrate may be used. The SOI substrate has an insulating layer, a buried oxide layer, and a top silicon layer. The top silicon layer of the SOI substrate is doped to form an N-type lightly doped region.

In the above steps, ion implantation is performed in the N-type lightly doped region, including: performing P-type ion implantation in a first predetermined area of the N-type lightly doped region to form a P-type source region, a P-type drain region and a P-type body region, performing N-type ion implantation in a second predetermined area of the N-type lightly doped region to form an N-type source region and an N-type drain region, and the remaining N-type lightly doped region serves as an N-type drift region.

In a specific example, a manufacturing method of a dual-carrier LDMOS device using a P-type silicon-on-insulator (SOI) substrate is as follows:

(1) As shown in FIG. 4a , the silicon substrate on the insulating layer includes a supporting substrate 10, a buried oxide layer 11 and a semiconductor layer (top silicon) on the buried oxide layer 11. The top silicon is doped to form an N-type drift region 12. The doping method is diffusion or ion implantation.

(2) As shown in FIG4b , a gate oxide layer 13 is deposited on the N-type drift region 12 by thermal oxidation, atomic layer deposition or sputtering. A polysilicon front gate layer 14 is deposited on the gate oxide layer 13 by low pressure chemical vapor deposition (LPCVD);

(3) As shown in FIG. 4 c , a P-type source region 15 , a P-type drain region 16 and a P-type body region 17 are doped on the surface of the N-type drift region 12 by ion implantation;

(4) As shown in FIG. 4d , the surface of the P-type body region 17 is doped to form an N-type source region 18 ; the surface of the N-type drift region 12 is doped to form an N-type drain region 19 , and the doping method is ion implantation;

(5) As shown in FIG. 4 e , the gate oxide layer 13 on the surfaces of the P-type source region 15 , the P-type drain region 16 , the N-type source region 18 , and the N-type drain region 19 is etched, and the polysilicon on the surfaces of the P-type source region 15 , the P-type drain region 16 , the N-type source region 18 , the N-type drain region 19 , and the N-type drift region 12 is etched to form a positive gate 14 , and the etching method is wet etching or reactive plasma etching;

(6) As shown in FIG. 4 f , a source electrode 18 is formed on the P-type source region 15 and the N-type source region 18 , and a drain electrode 18 is formed on the P-type drain region 16 and the N-type drain region 19 , and the formation method is: atomic layer deposition, evaporation or sputtering;

(7) As shown in FIG. 4g , a back gate 22 is formed on the lower surface of the supporting substrate 10 by atomic layer deposition, evaporation or sputtering.

The dual-carrier LDMOS device provided by the present invention is relatively simple in structure and can significantly reduce the specific on-resistance of the device. The manufacturing process of the device is relatively low in complexity and can be integrated with the CMOS process.

Although preferred embodiments of the present invention have been described, additional changes and modifications may be made to these embodiments by those skilled in the art once the basic inventive concepts are known. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention. Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims (8)

1. A dual carrier LDMOS device, comprising: the device comprises a substrate, a buried oxide layer, an N-type drift region, a gate oxide layer, a positive gate, a P-type source region, a P-type drain region, a P-type body region, an N-type source region, an N-type drain region and a back gate;

the buried oxide layer is formed on the upper surface of the substrate, the N-type drift region is formed on the surface of the buried oxide layer, and the back grid is formed on the lower surface of the substrate;

The bottom of the P-type source region is connected with the N-type drift region and the buried oxide layer, the bottom of the P-type drain region is connected with the N-type drift region and the buried oxide layer, the N-type source region is connected with the P-type body region, and the N-type drain region is connected with the N-type drift region;

The upper part of the P-type source region is connected with the N-type source region, and the upper part of the P-type drain region is connected with the N-type drain region;

The P-type body region comprises a transverse region and a longitudinal region, the transverse region of the P-type body region is connected with the P-type source region, and the longitudinal region of the P-type body region is connected with the gate oxide layer;

the P-type source region, the P-type drain region, the N-type drift region and the back gate form a PLDMOS structure, so that a P-type channel is formed at the bottom of the N-type drift region;

And the N-type source region, the N-type drain region, the N-type drift region, the P-type body region and the positive grid electrode form an NLDMOS structure, so that an N-type channel is formed on the surface of the P-type body region.

2. The dual carrier LDMOS device of claim 1, wherein a thickness of the N-type drift region between the lateral region of the P-type body region and the buried oxide layer is 100-300 nm.

3. The dual carrier LDMOS device of claim 1, wherein the substrate is a silicon-on-insulator substrate comprising an insulator layer, a buried oxide layer, and a top layer silicon, the buried oxide layer of the silicon-on-insulator substrate acting as the buried oxide layer of the dual carrier LDMOS device.

4. The dual carrier LDMOS device of claim 1 wherein carriers of the P-type channel are holes and the number of carriers of the hole channel is controlled by varying the voltage of the back-gate;

the carriers of the N-type channel are electrons, and the number of the carriers of the electron channel is controlled by changing the voltage of the positive grid electrode.

5. The dual carrier LDMOS device of claim 1 wherein the P-type source and P-type drain regions are P-type heavily doped regions having a doping concentration greater than 1 x 10 ¹⁸cm^-3;

The N-type source region and the N-type drain region are N-type heavily doped regions, and the doping concentration is more than 1 multiplied by 10 ¹⁸cm^-3;

the P type body region is a P type lightly doped region, and the doping concentration is less than 1 multiplied by 10 ¹⁶cm^-3;

The N-type drift region is an N-type lightly doped region, and the doping concentration is less than 1 multiplied by 10 ¹⁶cm^-3.

6. A method of fabricating a dual carrier LDMOS device, comprising:

Forming an N-type lightly doped region on the upper surface of the substrate with the buried oxide layer;

Ion implantation is carried out on the N-type lightly doped region to form a P-type source region, a P-type drain region, a P-type body region, an N-type source region, an N-type drain region and an N-type drift region; the bottom of the P-type source region is connected with the N-type drift region and the buried oxide layer, the bottom of the P-type drain region is connected with the N-type drift region and the buried oxide layer, the N-type source region is connected with the P-type body region, the N-type drain region is connected with the N-type drift region, the upper part of the P-type source region is connected with the N-type source region, the upper part of the P-type drain region is connected with the N-type drain region, the P-type body region comprises a transverse region and a longitudinal region, and the transverse region of the P-type body region is connected with the P-type source region;

Forming a gate oxide layer and a positive gate above the N-type drift region and the P-type body region, wherein a longitudinal region of the P-type body region is connected with the gate oxide layer, and the N-type source region, the N-type drain region, the N-type drift region, the P-type body region and the positive gate form an NLDMOS structure;

and forming a back grid electrode on the lower surface of the substrate, wherein the P-type source region, the P-type drain region, the N-type drift region and the back grid electrode form a PLDMOS structure.

7. The method of manufacturing a dual carrier LDMOS device as set forth in claim 6, wherein forming an N-type lightly doped region on an upper surface of the substrate having the buried oxide layer comprises:

And doping the top silicon of the insulating layer silicon substrate by adopting the insulating layer silicon substrate to form an N-type lightly doped region.

8. The method of manufacturing a dual carrier LDMOS device of claim 6, wherein the performing an ion implantation in the N-type lightly doped region to form a P-type source region, a P-type drain region, a P-type body region, an N-type source region, an N-type drain region, and an N-type drift region comprises:

P-type ion implantation is carried out in a first preset area of the N-type lightly doped area, so that a P-type source area, a P-type drain area and a P-type body area are formed;

And performing N-type ion implantation in a second preset area of the N-type lightly doped region to form an N-type source region and an N-type drain region, wherein the rest N-type lightly doped region is used as an N-type drift region.