CN118132488B - Signal frame generation method, device, electronic device and storage medium - Google Patents
Signal frame generation method, device, electronic device and storage medium Download PDFInfo
- Publication number
- CN118132488B CN118132488B CN202410242717.0A CN202410242717A CN118132488B CN 118132488 B CN118132488 B CN 118132488B CN 202410242717 A CN202410242717 A CN 202410242717A CN 118132488 B CN118132488 B CN 118132488B
- Authority
- CN
- China
- Prior art keywords
- node
- address
- target
- signal frame
- nodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 64
- 230000005540 biological transmission Effects 0.000 claims abstract description 44
- 238000004590 computer program Methods 0.000 claims description 13
- 238000012795 verification Methods 0.000 claims description 9
- 230000003111 delayed effect Effects 0.000 claims description 8
- 125000004122 cyclic group Chemical group 0.000 claims description 6
- 238000012545 processing Methods 0.000 abstract description 6
- 238000001514 detection method Methods 0.000 abstract description 5
- 238000004891 communication Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000012546 transfer Methods 0.000 description 4
- 238000003780 insertion Methods 0.000 description 3
- 230000037431 insertion Effects 0.000 description 3
- 101150075681 SCL1 gene Proteins 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 101150111792 sda1 gene Proteins 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008929 regeneration Effects 0.000 description 1
- 238000011069 regeneration method Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/404—Coupling between buses using bus bridges with address mapping
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Quality & Reliability (AREA)
- Computer Hardware Design (AREA)
- Small-Scale Networks (AREA)
Abstract
本发明提供一种信号帧生成方法、装置、电子设备及存储介质，涉及数据传输技术领域，该方法包括：获取所述目标节点对应的目标层的总线的帧结构；所述帧结构包括地址段；所述地址段包括所述多层总线中每层总线的节点的节点地址；所述节点地址包括所述节点的地址和所述节点的指令类型；基于各所述节点的地址和所述节点的指令类型，生成信号帧。通过各节点的地址和节点的指令类型，实现I2C总线分层传输的信号帧结构的生成，同时，能够支持大规模检测单元的需求，进而实现分层传输的过程中对数据的转发和处理，提升传输效率。
The present invention provides a signal frame generation method, device, electronic device and storage medium, which relate to the technical field of data transmission. The method comprises: obtaining the frame structure of the bus of the target layer corresponding to the target node; the frame structure comprises an address segment; the address segment comprises the node address of the node of each layer of the bus in the multi-layer bus; the node address comprises the address of the node and the instruction type of the node; based on the address of each node and the instruction type of the node, a signal frame is generated. Through the address of each node and the instruction type of the node, the signal frame structure of I2C bus hierarchical transmission is generated, and at the same time, the needs of large-scale detection units can be supported, thereby realizing the forwarding and processing of data in the process of hierarchical transmission, and improving the transmission efficiency.
Description
Technical Field
The present invention relates to the field of data transmission technologies, and in particular, to a signal frame generating method, a device, an electronic device, and a storage medium.
Background
The integrated circuit (Inter-INTEGRATED CIRCUIT, I 2 C) bus is a serial bus having a total of two bi-directional data lines, serial clock line (Serial Clock Line, SCL) and serial data line (SERIAL DATA LINE, SDA), respectively. In a multi-host system, there may be multiple host-initiated buses transmitting data at the same time. To avoid confusion, the I 2 C bus must arbitrate through the bus to determine which host is controlling the bus.
However, how to generate the signal frame structure of the I 2 C bus hierarchical transmission is a technical problem to be solved.
Disclosure of Invention
The invention provides a signal frame generation method, a device, electronic equipment and a storage medium, which are used for solving the problem of how to generate a signal frame structure of hierarchical transmission of an I 2 C bus.
The invention provides a signal frame generation method, which is applied to a target node of a layered transmission structure, wherein the layered transmission structure comprises a plurality of layers of buses, and each layer of bus corresponds to a plurality of nodes, and the method comprises the following steps:
the method comprises the steps of obtaining a frame structure of a bus of a target layer corresponding to a target node, wherein the frame structure comprises an address segment, wherein the address segment comprises a node address of a node of each layer of bus in the multi-layer bus, and the node address comprises the address of the node and an instruction type of the node;
a signal frame is generated based on the address of each of the nodes and the instruction type of the node.
According to the signal frame generating method provided by the invention, the address segment further comprises a Cyclic Redundancy Check (CRC), the signal frame is generated based on the address of each node and the instruction type of the node, and the method comprises the following steps:
Matching the address of the node corresponding to the target node in each node with the preset address of the target node;
Under the condition that the address of the node corresponding to the target node in each node is not matched with the preset address of the target node, the target node is switched into an idle state;
And under the condition that the addresses of the nodes corresponding to the target node and the preset addresses of the target node are matched, checking the CRC and the preset CRC of the target node to obtain a checking result, wherein the checking result is used for indicating that the CRC and the preset CRC are correct or incorrect, and generating the signal frame based on the checking result.
According to the signal frame generating method provided by the invention, the signal frame is generated based on the verification result, and the signal frame generating method comprises the following steps:
Inserting an ending symbol at a cascading port of the target node under the conditions of the CRC and the preset CRC error;
judging whether the addresses of other nodes except the target node in the nodes are target addresses or not under the condition that the CRC and the preset CRC are correct;
and generating the signal frame based on the judging result.
According to the signal frame generation method provided by the invention, the signal frame is generated based on the judgment result, and the signal frame generation method comprises the following steps:
Generating the signal frame based on the address of each node, the instruction type of the node and the CRC when the addresses of other nodes except the target node in the nodes are all the target addresses;
Setting the address of a node with a first address which is not the target address in other nodes as the target address under the condition that at least one address of other nodes except the target node exists in the nodes, replacing the address which is not the target address in the nodes except the first address to obtain a replaced address segment, generating the signal frame based on the replaced address segment, and forwarding the signal frame to the next layer through a cascade port of the target node.
According to the signal frame generating method provided by the invention, after the frame structure of the bus of the target layer corresponding to the target node is obtained, the method further comprises:
forwarding the frame structure to a cascading port of the target node;
And forwarding the generated signal frame to any node of the next layer through the cascade port under the condition that at least one address of other nodes except the target node in the nodes is not the target address.
According to the signal frame generating method provided by the invention, in the process of transmitting the signal frame to any node of the next layer, the signal frame is transmitted on the first falling edge of the serial clock line SCL, and the time for transmitting the signal frame is delayed by one SCL period.
The signal frame generation method provided by the invention comprises a first layer bus, a second layer bus, a third layer bus and a fourth layer bus, wherein the addresses of nodes of the first layer bus represent access addresses, the addresses corresponding to the second layer bus, the third layer bus and the fourth layer bus respectively represent forwarding addresses corresponding to the frame structure, and a first node in the nodes corresponds to the fourth layer bus, a second node corresponds to the third layer bus, a third node corresponds to the second layer bus and a fourth node corresponds to the first layer bus.
The invention also provides a signal frame generating device, which is applied to a target node of a layered transmission structure, wherein the layered transmission structure comprises a plurality of layers of buses, each layer of bus corresponds to a plurality of nodes, and the device comprises:
The system comprises an acquisition module, a frame structure and a command type acquisition module, wherein the acquisition module is used for acquiring a frame structure of a bus of a target layer corresponding to the target node, the frame structure comprises an address segment, the address segment comprises a node address of a node of each layer of bus in the multi-layer bus, and the node address comprises the address of the node and the command type of the node;
and the generation module is used for generating a signal frame based on the address of each node and the instruction type of the node.
The invention also provides an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the signal frame generation method as described above when executing the program.
The present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a signal frame generation method as described in any of the above.
The invention also provides a computer program product comprising a computer program which when executed by a processor implements a signal frame generation method as described in any one of the above.
The signal frame generation method, the device, the electronic equipment and the storage medium provided by the invention are used for acquiring the frame structure of the bus of the target layer corresponding to the target node, wherein the frame structure comprises an address segment, the address segment comprises the node address of the node of each layer of bus in the multi-layer bus, the node address comprises the address of the node and the instruction type of the node, and the signal frame is generated based on the address of each node and the instruction type of the node. The generation of the signal frame structure of the hierarchical transmission of the I 2 C bus is realized through the address of each node and the instruction type of the node, and meanwhile, the requirement of a large-scale detection unit can be supported, so that the forwarding and processing of data in the hierarchical transmission process are realized, and the transmission efficiency is improved.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of a signal frame generating method according to the present invention;
FIG. 2 is a schematic diagram of sequential logic provided by the present invention;
FIG. 3 is a second flowchart of a signal frame generating method according to the present invention;
Fig. 4 is a schematic structural diagram of a signal frame generating device provided by the present invention;
Fig. 5 is a schematic structural diagram of an electronic device provided by the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
For purposes of clarity in describing various embodiments of the application, the relevant background is presented.
The data signals transmitted by the I 2 C bus are broad, including both address signals and true data signals. After the start signal a slave address is included, the data transfer direction bit (R/T) is denoted by "0" for the host to send data (T) and "1" for the host to receive data (R). Each data transfer ends with a termination signal generated by the host, but if the host wishes to continue occupying the bus for a new data transfer, the start signal may be sent out immediately to address another slave without generating a termination signal.
The number of nodes (e.g., the number of terminals) to which the I 2 C bus can be connected is relatively small, and cannot meet the requirements of a large-scale detection unit (e.g., the terminals), and cannot cope with hierarchical transmission.
In view of the foregoing, the present application provides a signal frame generating method, where the structure of a signal frame is a hierarchical transmission structure corresponding to an I 2 C bus, and a frame structure corresponding to the hierarchical transmission structure, that is, a frame structure used in the I 2 C bus. The structure of the signal frame generated by the application can meet the requirement that the signal frame is forwarded to the node of the next layer for processing through the node of each layer in the layered transmission process, and the transmission efficiency is improved.
The signal frame generation method of the present invention is described below with reference to fig. 1 to 3.
Fig. 1 is a schematic flow chart of a signal frame generating method provided in the present invention, as shown in fig. 1, applied to a target node of a hierarchical transmission structure, where the hierarchical transmission structure includes a multi-layer bus, and each layer of bus corresponds to a plurality of nodes, and the method includes steps 101-102,
Step 101, obtaining a frame structure of a bus of a target layer corresponding to the target node, wherein the frame structure comprises an address segment, the address segment comprises a node address of a node of each layer of bus in the multi-layer bus, and the node address comprises the address of the node and an instruction type of the node.
It should be noted that, the signal frame generating method provided by the present invention is suitable for a scenario of hierarchical data transmission of a large-scale array, and the execution subject of the method may be a signal frame generating device, for example, an electronic device, or a control module in the signal frame generating device for executing the signal frame generating method.
Specifically, the node comprises a main interface, a standby interface and a cascade interface which is used for forwarding to the node at the next layer, wherein the cascade interface provides a bus at the next layer, and the bus is connected with the main interface or the standby interface of the node at the next layer. The target node is any node of each layer of bus in the hierarchical transmission structure.
The target node obtains a frame structure of a bus of a target layer corresponding to the target node, wherein the frame structure comprises an address segment, the address segment comprises a node address of a node of each layer of bus in the multi-layer bus, and the node address comprises the address of the node and an instruction type of the node. The frame structure may be a read data frame or a write data frame, and the frame structure may further include a start symbol S, a data segment, a redundancy bit R, and an end symbol P, wherein the frame structure of the write data frame may further include a placeholder bit field, wherein the placeholder bit field ranges from 0 to 6 bits.
Table 1 shows a frame structure of a write data frame, which includes a start symbol S, an address segment, a data segment, redundancy bits R and an end symbol P, wherein the redundancy bits range from 0 bits to 3 bits.
TABLE 1 frame Structure of write data frame
| S | Address field | Data segment | Redundancy bits | P |
Table 2 shows the frame structure of the read data frame, which includes a start symbol S, an address field, a placeholder, a data field, redundancy bits R and an end symbol P, wherein the range of the placeholder bit field is 0-6 bits.
TABLE 2 frame structure of read data frame
| S | Address field | Space bit | Data segment | Redundancy bits | P |
Wherein S represents a start symbol, S is a falling edge of SCL high level and SDA, P is an end symbol, and P is a rising edge of SCL high level and SDA. The end of the address segment and the end of the data segment of the frame structure can be inserted with CRC-8 check, the CRC check of the address segment and the data segment adopts the same algorithm, wherein the generating polynomial of the algorithm is selected as x 8+x2 +x+1, the initial value is calculated as 0, and the result is not inverted.
Optionally, the address segment includes a node address of a node of each layer of the multi-layer bus, the node address including an address of the node and an instruction type of the node. Table 3 shows the structure of address field, which includes address D, type, address C, type, address B, type1, address A, R/W, len, read/write start address, and CRC, as shown in Table 3.
TABLE 3 Structure of address field
Where address a represents the address of the access node (first tier node), address B, address C, and address D represent addresses forwarded to tier 2 to 4 nodes. Note that, in each 8-bit node address, the upper 7 bits represent the address of the node, and the last bit (8 th bit) represents the instruction type (type [3:0 ]). The type [0] contained in the address A field is a read-write flag, wherein high level read and low level write are performed. The 3 different bits in Type [3:1] represent different instruction types.
Instruction Type [3:1] means that 111 denotes register read/write, 101 denotes channel switch (Type [0] =1, timing with register read instruction), and 000 denotes state group read (Type [0] =1, timing with register read instruction).
The data length Len is the content length of the data segment to be transmitted later, and the Len field includes CRC (bytes). The Len field is used to determine what data is to be output after the CRC field of the data when the data is read.
Optionally, the multi-layer bus includes a first layer bus, a second layer bus, a third layer bus and a fourth layer bus, where addresses of nodes of the first layer bus represent access addresses, addresses corresponding to the second layer bus, the third layer bus and the fourth layer bus respectively represent forwarding addresses corresponding to the frame structure, and a first node corresponds to the fourth layer bus, a second node corresponds to the third layer bus, a third node corresponds to the second layer bus and a fourth node corresponds to the first layer bus.
Specifically, the multi-layer buses include a first-layer bus, a second-layer bus, a third-layer bus and a fourth-layer bus, wherein the address of a node of the first-layer bus represents an access address, for example, the address a of a node a (i.e., a fourth node) of the first-layer bus represents an access address, and the addresses corresponding to the second-layer bus, the third-layer bus and the fourth-layer bus respectively represent forwarding addresses corresponding to the frame structure, for example, the address B of a node B (i.e., a third node) of the second-layer bus, the address C of a node C (i.e., a second node) of the third-layer bus, and the address D of a node D (i.e., a first node) of the fourth-layer bus represent forwarding addresses corresponding to the frame structure, i.e., the address B, the address C and the address D represent forwarding addresses to the 2 to 4-layer nodes.
Step 102, generating a signal frame based on the address of each node and the instruction type of the node.
Specifically, a signal frame may be generated based on the address of each node and the instruction type of the node.
The signal frame generation method provided by the invention comprises the steps of obtaining a frame structure of a bus of a target layer corresponding to a target node, wherein the frame structure comprises an address segment, the address segment comprises a node address of a node of each layer of bus in a multi-layer bus, the node address comprises the address of the node and the instruction type of the node, and the signal frame is generated based on the address of each node and the instruction type of the node. The generation of the signal frame structure of the hierarchical transmission of the I 2 C bus is realized through the address of each node and the instruction type of the node, and meanwhile, the requirement of a large-scale detection unit can be supported, so that the forwarding and processing of data in the hierarchical transmission process are realized, and the transmission efficiency is improved.
Optionally, the address field further includes a cyclic redundancy check CRC, and the specific implementation manner of step 102 includes:
(1) And matching the address of the node corresponding to the target node in each node with the preset address of the target node.
Specifically, the address of the node corresponding to the target node in each node is matched with the preset address of the target node. For example, the target node is node a, and each node is node a to node D, as shown in table 3. And the target node A matches the address of the node corresponding to the target node A in each node with the preset address of the target node.
(2) And under the condition that the address of the node corresponding to the target node in each node is not matched with the preset address of the target node, the target node is switched into an idle state.
Specifically, under the condition that the address of the node corresponding to the target node in each node is not matched with the preset address of the target node (i.e. the address is not matched), the target node is switched into an IDLE state (IDLE), waits for the next transmission, and the cascade port insertion terminator of the target node ends the data forwarding.
(3) And under the condition that the addresses of the nodes corresponding to the target node and the preset addresses of the target node are matched, checking the CRC and the preset CRC of the target node to obtain a checking result, wherein the checking result is used for indicating that the CRC and the preset CRC are correct or incorrect, and generating the signal frame based on the checking result.
Specifically, under the condition that the addresses of the nodes corresponding to the target node and the preset addresses of the target node are matched (namely, the addresses are matched), the CRC and the preset CRC of the target node are checked, namely, the CRC and the preset CRC are matched, a check result can be obtained, wherein the check result is used for indicating that the CRC and the preset CRC are correct or incorrect, and a signal frame can be generated based on the check result.
Optionally, the generating the signal frame based on the verification result includes:
(a) And inserting an ending symbol at a cascading port of the target node under the condition of the CRC and the preset CRC error.
Specifically, under the conditions of CRC and preset CRC error, the cascade port insertion ending symbol of the target node ends the data forwarding.
(B) And under the condition that the CRC and the preset CRC are correct, judging whether the addresses of other nodes except the target node in the nodes are all target addresses, and generating the signal frame based on a judging result.
Specifically, the target address is 0x7f. And under the condition that the CRC and the preset CRC are correct, judging whether the addresses of other nodes except the target node in each node are all target addresses. For example, as shown in table 3, the target node is node a, each node is node a to node D, and it is determined whether addresses of node B to node D other than node a in node a to node D are all 0x7f. Based on the judgment result, a signal frame may be further generated.
Optionally, the generating the signal frame based on the determination result includes:
1) And generating the signal frame based on the address of each node, the instruction type of the node and the CRC when the addresses of other nodes except the target node in the nodes are all the target addresses, wherein the signal frame is processed by the target node.
Specifically, under the condition that the addresses of other nodes except the target node in each node are all target addresses, a signal frame can be generated based on the addresses of the nodes, the instruction type of the node and the CRC, wherein the signal frame is processed by the target node, and an ending symbol is inserted into a cascade port of the target node A to end the data forwarding. For example, table 4 shows the structure of the address segment obtained by the target node a, as shown in table 4, the target node is node a, each node is node a to node D, and if the addresses of node B to node D except node a in node a to node D are all 0x7f, a signal frame can be generated based on the addresses of node a to node D, the instruction type of the node and the CRC, wherein the signal frame is processed by the target node a.
TABLE 4 Structure of address field acquired by target node A
2) Setting the address of a node with a first address which is not the target address in other nodes as the target address under the condition that at least one address which is not the target address exists in other nodes except the target node in the nodes, replacing the address which is not the target address in other nodes except the first address to obtain a replaced address segment, generating the signal frame based on the replaced address segment, and forwarding the signal frame to the next layer through a cascade port of the target node.
Specifically, when at least one address of other nodes except the target node is not the target address, the address of the node with the first address being not the target address in the other nodes can be set as the target address, and the other addresses which are not the target address in the other nodes except the first address are replaced, namely, the other nodes which are not the target address in the other nodes except the first address are replaced according to the descending order of the layer number corresponding to the first address, so as to obtain a replaced address segment, a signal frame is generated based on the replaced address segment, and the signal frame is forwarded to the next layer by a cascade port of the target node, namely, the data is transmitted transparently.
For example, as shown in table 3, the target node is node a, each node is node a to node D, if it is determined that all the addresses from node B to node D except node a in node a to node D are not 0x7f, then the address of node D whose first address is not 0x7f in node B to node D is set to 0x7f, and the addresses from node C to node a are replaced by node D to node B, and table 5 is the address segment structure after the replacement corresponding to the target node a, as shown in table 5.
TABLE 5 address segment structure after replacement for target node A
As shown in Table 5, type [3:0] in the address field remains unchanged, type [0] being R/W. The 7bit position of address D is filled with 0x7f at the concatenation port, and the positions of address C to address a are replaced by addresses D to B, respectively.
Optionally, after the obtaining the frame structure of the bus of the target layer corresponding to the target node, the method further includes:
And forwarding the generated signal frame to any node of the next layer by the cascade port under the condition that at least one address of other nodes except the target node in the nodes is not the target address.
Specifically, after the target node obtains the frame structure of the bus of the target layer corresponding to the target node, the target node forwards the frame structure to the cascade port of the target node immediately. It should be noted that (1) in the case where the address of the node corresponding to the target node and the preset address of the target node do not match in each node, or (2) in each node the address of the node corresponding to the target node and the preset address of the target node match, but the CRC and the preset CRC check are wrong, or (3) in the case where the address of the node corresponding to the target node and the preset address of the target node match in each node, and the CRC and the preset CRC check are correct, but in each node the addresses of other nodes except the target node are both target addresses, although the target node forwards the frame structure to the tandem port, the session with the next layer node is ended due to the fact that the terminator is inserted in the tandem port later, and no influence is generated on the next layer node.
And forwarding the generated signal frame to any node of the next layer through the cascade port under the condition that at least one address of other nodes except the target node in each node is not the target address.
Optionally, in transmitting the signal frame to any node of the next layer, the signal frame is transmitted on the first falling edge of the serial clock line SCL, and the time of transmitting the signal frame is delayed by one SCL period.
Specifically, in the process that the cascade port of the target node transmits a signal frame to any node of the next layer, the signal frame is transmitted on the falling edge of the SCL, and the time for transmitting the signal frame is delayed by one SCL period. Fig. 2 is a schematic diagram of sequential logic provided in the present invention, as shown in fig. 2, SCL1 and SDA1 are frame structures of buses received by a target node, and SCL2 and SDA2 are signal frames forwarded by the target node to the next layer. In contrast to SDA1 and SDA2, the forwarded SDA2 is sent on the first falling edge of SCL1, delayed by one cycle of SCL 1. The SDA data is a signal frame.
For the end of each frame of data, in order to coordinate with the regeneration delay of the data, a redundancy bit R is inserted after each frame of data, and after the data frame is forwarded, the redundancy bit is removed. After the end symbol is detected, the end symbol is synchronized with an internal clock and outputted.
Each time a data frame is forwarded, the data frame is delayed by one beat, i.e. by one SCL period, the terminator needs a rising edge, and the redundancy bits are filled with "0". For the layered transmission of the four-layer structure, there are three middle layers, and at most three redundant bits are added.
For read-back data of a read command (read data frame), the data transfer back to the host may be delayed by 0-6 bits. When forwarding the data frame, filling the redundant bit 0 into the part after the CRC is transmitted, wherein the range of the redundant bit is 0-3 bits.
The signal frame generation method of the present application is illustrated below.
For example, the host accesses the nodes of the second layer bus in the hierarchical transmission, and the format of the address field of the data frame structure of the target node a of the bus of the first layer is shown in table 6, and table 6 is the address field structure of the data frame structure of the target node a.
TABLE 6 Address segment Structure of data frame Structure of target node A
Wherein, the first 0x7f corresponds to the address of the node D, the second 0x7f corresponds to the address of the node C, and the addresses B which are not 0x7f exist in the nodes D, C and B, so the target node a does not process the instruction (data frame), and the instruction is transparently transmitted to the second layer through the cascade port of the target node a with the address a.
Table 7 is an address field structure of a data frame structure forwarded by a cascade port of the target node a, and as shown in table 7, the address of the address B is set to 0x7f, and then the address a is replaced by the address B. The first three addresses of the address field of the second layer are all 0x7f, and the node with the address of the address B processes the subsequent data, and the cascade port is not forwarded to the next layer.
TABLE 7 Address segment Structure of data frame Structure forwarded by the tandem Port of target node A
Fig. 3 is a schematic flow chart of the signal frame generating method provided in the present invention, as shown in fig. 3, applied to a target node of a hierarchical transmission structure, where the hierarchical transmission structure includes a plurality of buses, each of the buses corresponds to a plurality of nodes, and the method includes steps 301 to 309,
Step 301, obtaining a frame structure of a bus of a target layer corresponding to a target node, wherein the frame structure comprises an address segment, a data segment and a CRC (cyclic redundancy check), the address segment comprises a node address of a node of each layer of bus in the multi-layer bus, and the node address comprises the address of the node and an instruction type of the node.
Step 302, the target node forwards the frame structure to the cascade port of the target node.
Step 303, the target node matches the address of the node corresponding to the target node in each node with the preset address of the target node.
Step 304, under the condition that the address of the node corresponding to the target node in each node is not matched with the preset address of the target node, the target node is switched into an idle state to wait for the next transmission, and the cascade port insertion ending symbol of the target node ends the data forwarding.
Step 305, checking the CRC and the preset CRC of the target node when the address of the corresponding node of the target node matches with the preset address of the target node.
And 306, inserting an ending symbol at the cascade port of the target node under the conditions of CRC and preset CRC check errors.
Step 307, judging whether the addresses of other nodes except the target node in each node are all target addresses if the CRC and the preset CRC are correct.
In step 308, when the addresses of the nodes other than the target node are all target addresses, a signal frame is generated based on the addresses of the nodes, the instruction type of the node, and the CRC, and the signal frame is processed by the target node and an ending symbol is inserted into the cascade port of the target node.
Step 309, setting the address of the node whose first address is not the target address in the other nodes as the target address and replacing the other addresses which are not the target address in the other nodes except the first address to obtain a replaced address segment, generating a signal frame based on the replaced address segment, and forwarding the signal frame to the next layer from the cascade port of the target node.
The signal frame generation method provided by the application is easier to support large-scale units by layered transmission and setting different bus numbers on each layer. The method and the system can realize the forwarding and processing of the signal frames of the data correctly by the nodes in the layered transmission process only by using the signal frames generated by the application at the host, thereby improving the transmission efficiency.
The signal frame generating device provided by the invention is described below, and the signal frame generating device described below and the signal frame generating method described above can be referred to correspondingly to each other.
Fig. 4 is a schematic structural diagram of a signal frame generating device provided in the present invention, as shown in fig. 4, applied to a target node of a hierarchical transmission structure, where the hierarchical transmission structure includes a plurality of buses, each of the buses corresponds to a plurality of nodes, and the signal frame generating device 400 includes:
The acquisition module 401 is configured to acquire a frame structure of a bus of a target layer corresponding to the target node, where the frame structure includes an address field, where the address field includes a node address of a node of each layer of buses in the multi-layer bus, where the node address includes an address of the node and an instruction type of the node;
A generating module 402, configured to generate a signal frame based on an address of each of the nodes and an instruction type of the node.
The signal frame generating device provided by the invention is used for generating a signal frame by acquiring a frame structure of a bus of a target layer corresponding to a target node, wherein the frame structure comprises an address segment, the address segment comprises a node address of a node of each layer of bus in a multi-layer bus, the node address comprises the address of the node and the instruction type of the node, and the signal frame is generated based on the address of each node and the instruction type of the node. The generation of the signal frame structure of the hierarchical transmission of the I 2 C bus is realized through the address of each node and the instruction type of the node, and meanwhile, the requirement of a large-scale detection unit can be supported, so that the forwarding and processing of data in the hierarchical transmission process are realized, and the transmission efficiency is improved.
Optionally, the address segment further includes a cyclic redundancy check CRC, and the generating module 402 is specifically configured to:
Matching the address of the node corresponding to the target node in each node with the preset address of the target node;
Under the condition that the address of the node corresponding to the target node in each node is not matched with the preset address of the target node, the target node is switched into an idle state;
And under the condition that the addresses of the nodes corresponding to the target node and the preset addresses of the target node are matched, checking the CRC and the preset CRC of the target node to obtain a checking result, wherein the checking result is used for indicating that the CRC and the preset CRC are correct or incorrect, and generating the signal frame based on the checking result.
Optionally, the generating module 402 is further configured to:
Inserting an ending symbol at a cascading port of the target node under the conditions of the CRC and the preset CRC error;
judging whether the addresses of other nodes except the target node in the nodes are target addresses or not under the condition that the CRC and the preset CRC are correct;
and generating the signal frame based on the judging result.
Optionally, the generating module 402 is further configured to:
Generating the signal frame based on the address of each node, the instruction type of the node and the CRC when the addresses of other nodes except the target node in the nodes are all the target addresses;
Setting the address of a node with a first address which is not the target address in other nodes as the target address under the condition that at least one address of other nodes except the target node exists in the nodes, replacing the address which is not the target address in the nodes except the first address to obtain a replaced address segment, generating the signal frame based on the replaced address segment, and forwarding the signal frame to the next layer through a cascade port of the target node.
Optionally, after the acquiring the frame structure of the bus of the target layer corresponding to the target node, the signal frame generating apparatus 400 further includes:
A first forwarding module, configured to forward the frame structure to a cascade port of the target node;
and the second forwarding module is used for forwarding the generated signal frame to any node of the next layer through the cascade port under the condition that at least one address of other nodes except the target node in the nodes is not the target address.
Optionally, in transmitting the signal frame to any node of the next layer, the signal frame is transmitted on the first falling edge of the serial clock line SCL, and the time of transmitting the signal frame is delayed by one SCL period.
Optionally, the multi-layer bus includes a first layer bus, a second layer bus, a third layer bus and a fourth layer bus, where addresses of nodes of the first layer bus represent access addresses, addresses corresponding to the second layer bus, the third layer bus and the fourth layer bus respectively represent forwarding addresses corresponding to the frame structure, and a first node corresponds to the fourth layer bus, a second node corresponds to the third layer bus, a third node corresponds to the second layer bus and a fourth node corresponds to the first layer bus.
Fig. 5 is a schematic physical structure of an electronic device according to the present invention, as shown in fig. 5, the electronic device 500 may include a processor (processor) 510, a communication interface (Communications Interface) 520, a memory (memory) 530, and a communication bus 540, where the processor 510, the communication interface 520, and the memory 530 complete communication with each other through the communication bus 540. Processor 510 may invoke logic instructions in memory 530 to perform a method of signal frame generation comprising obtaining a frame structure of a bus of a target layer corresponding to the target node, the frame structure comprising an address field, the address field comprising a node address of a node of each layer of the multi-layer bus, the node address comprising an address of the node and an instruction type of the node, and generating a signal frame based on the address of each of the nodes and the instruction type of the node.
Further, the logic instructions in the memory 530 described above may be implemented in the form of software functional units and may be stored in a computer-readable storage medium when sold or used as a stand-alone product. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. The storage medium includes a U disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, an optical disk, or other various media capable of storing program codes.
In another aspect, the present invention also provides a computer program product, where the computer program product includes a computer program, where the computer program is capable of being stored on a non-transitory computer readable storage medium, and where the computer program, when executed by a processor, is capable of executing a signal frame generating method provided by the methods described above, where the method includes obtaining a frame structure of a bus of a target layer corresponding to the target node, where the frame structure includes an address field, where the address field includes a node address of a node of each layer of the multi-layer bus, where the node address includes an address of the node and an instruction type of the node, and where a signal frame is generated based on the address of each of the nodes and the instruction type of the node.
In yet another aspect, the present invention further provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the method for generating a signal frame provided by the methods described above, the method comprising obtaining a frame structure of a bus of a target layer corresponding to the target node, the frame structure comprising an address field, the address field comprising a node address of a node of each layer of the multi-layer bus, the node address comprising an address of the node and an instruction type of the node, and generating a signal frame based on the address of each of the nodes and the instruction type of the node.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
It should be noted that the above-mentioned embodiments are merely for illustrating the technical solution of the present invention, and not for limiting the same, and although the present invention has been described in detail with reference to the above-mentioned embodiments, it should be understood by those skilled in the art that the technical solution described in the above-mentioned embodiments may be modified or some technical features may be equivalently replaced, and these modifications or substitutions do not make the essence of the corresponding technical solution deviate from the spirit and scope of the technical solution of the embodiments of the present invention.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410242717.0A CN118132488B (en) | 2024-03-04 | 2024-03-04 | Signal frame generation method, device, electronic device and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410242717.0A CN118132488B (en) | 2024-03-04 | 2024-03-04 | Signal frame generation method, device, electronic device and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118132488A CN118132488A (en) | 2024-06-04 |
| CN118132488B true CN118132488B (en) | 2024-12-10 |
Family
ID=91245368
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410242717.0A Active CN118132488B (en) | 2024-03-04 | 2024-03-04 | Signal frame generation method, device, electronic device and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118132488B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5796605A (en) * | 1996-07-02 | 1998-08-18 | Sun Microsystems, Inc. | Extended symmetrical multiprocessor address mapping |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3274624B2 (en) * | 1997-05-13 | 2002-04-15 | 甲府日本電気株式会社 | Timing controller for multi-tier bus system |
| US6874052B1 (en) * | 2000-09-29 | 2005-03-29 | Lucent Technologies Inc. | Expansion bridge apparatus and method for an I2C bus |
| DE102016123400B3 (en) * | 2016-01-19 | 2017-04-06 | Elmos Semiconductor Aktiengesellschaft | Single-wire light control bus with several levels |
| CN106506713B (en) * | 2016-10-09 | 2019-04-12 | 三明学院 | Mix isomery serial communication system and dynamic device allocation address approach |
-
2024
- 2024-03-04 CN CN202410242717.0A patent/CN118132488B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5796605A (en) * | 1996-07-02 | 1998-08-18 | Sun Microsystems, Inc. | Extended symmetrical multiprocessor address mapping |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118132488A (en) | 2024-06-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20240296088A1 (en) | Memory error detection | |
| KR101093857B1 (en) | System, method and apparatus for transmitting data and data mask bits with a shared error bit code in a common frame | |
| US7836378B2 (en) | System to detect and identify errors in control information, read data and/or write data | |
| JP4917671B2 (en) | Data transmission method between master device and slave device | |
| EP3566138B1 (en) | Transaction identification synchronization | |
| TWI417891B (en) | Memory mirroring apparatus and method | |
| US7206891B2 (en) | Multi-port memory controller having independent ECC encoders | |
| US20170288705A1 (en) | Shared memory with enhanced error correction | |
| CN114328316A (en) | DMA controller, SOC system and data carrying method based on DMA controller | |
| CN105843549A (en) | Memory device and method for executing error detection protocol | |
| US20170212800A1 (en) | System and method for performing bus transactions | |
| JPH0691511B2 (en) | Signal check device | |
| CN118132488B (en) | Signal frame generation method, device, electronic device and storage medium | |
| US20200319969A1 (en) | Method for checking address and control signal integrity in functional safety applications, related products | |
| CN103838638B (en) | Calibration method and device for FPGA plug-in storage | |
| CN108664362B (en) | Memory mirror image processing method, memory controller and user equipment | |
| CN107748704A (en) | The method and device that memory mirror based on FPGA is realized | |
| US6799293B2 (en) | Sparse byte enable indicator for high speed memory access arbitration method and apparatus | |
| JP4546380B2 (en) | Crossbar switch, information processing apparatus, and transfer method | |
| CN106940684A (en) | A kind of method and device pressed than feature data | |
| US11726944B2 (en) | Transaction layer circuit of PCIe and operation method thereof | |
| CN117336169B (en) | Configuration method, device, chip, switch and medium of Ethernet flow table | |
| CN118092819B (en) | Data reading method, flash memory, device and storage medium | |
| US20240248858A1 (en) | Serial bus communication without read indication | |
| CN113454611B (en) | Method for verifying the integrity of address and control signals, and related products |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |