CN118118029B - A sensor signal conversion device for a pre-alignment machine - Google Patents
A sensor signal conversion device for a pre-alignment machine Download PDFInfo
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Abstract
本发明公开了一种预对准机的传感器信号转换装置。该装置包括：信号输出模块、信号转换模块及解析模块；所述信号输出模块，用于输出预对准机的传感器信号至所述信号转换模块；所述信号转换模块，用于将所述传感器信号转换为传感器转换信号，并输出至所述解析模块；所述解析模块，用于解析所述传感器转换信号。本方案实现了传感器的信号高速转换，以提高现场解析模块的适配度，保证现场解析模块的稳定运行。
The present invention discloses a sensor signal conversion device for a pre-alignment machine. The device comprises: a signal output module, a signal conversion module and an analysis module; the signal output module is used to output the sensor signal of the pre-alignment machine to the signal conversion module; the signal conversion module is used to convert the sensor signal into a sensor conversion signal and output it to the analysis module; the analysis module is used to analyze the sensor conversion signal. This solution realizes high-speed conversion of sensor signals to improve the adaptability of the on-site analysis module and ensure the stable operation of the on-site analysis module.
Description
Technical Field
The embodiment of the invention relates to a pre-alignment technology of a pre-alignment machine, in particular to a sensor signal conversion device of the pre-alignment machine.
Background
The wafer is a wafer with a single crystal structure, different wafer crystal directions have different chemical, electrical and physical characteristics, the wafer is provided with a notch or a trimming edge as a visual reference of the crystal directions, and the semiconductor analysis module transmits the wafer to the precise moving platform for processing and measurement at a specific angle by identifying the notch or the trimming edge of the wafer. Along with the development of semiconductor technology, before the equipment processes and measures the wafer, the wafer is prealigned by a wafer prealigner so as to realize high-speed automatic production and measurement, and the transmission precision and the production efficiency of the semiconductor equipment are directly affected by the performance of the prealigner.
At present, a pre-alignment machine commonly adopts a sensor to detect the edge of a wafer, and detects the shielding signal change of the wafer to the sensor by rotating the wafer, so as to calculate the circle center coordinate and the notch direction of the wafer. At present, sensor manufacturers for measuring the circle center coordinates and the notch directions of wafers at home and abroad have diversified internal principles, and different types of sensors have certain difference in application scenes, namely different types of signals detected by different sensors, because the on-site semiconductor analysis module is fixed, the on-site semiconductor analysis module cannot detect the edges of the wafers of different types of sensors, and thus the stable operation of the on-site semiconductor analysis module cannot be ensured, therefore, a sensor signal replacement scheme of the prealignment machine is necessary to be studied so as to ensure the stable operation of the on-site semiconductor analysis module.
Disclosure of Invention
The invention provides a sensor signal conversion device of a prealignment machine, which realizes high-speed signal conversion of a sensor so as to improve the adaptation degree of a semiconductor analysis module on site and ensure the stable operation of the semiconductor analysis module.
In order to achieve the above purpose, the embodiment of the invention provides a sensor signal conversion device of a prealignment machine, which comprises a signal output module, a signal conversion module and an analysis module;
the signal output module is used for outputting a sensor signal to the signal conversion module;
The signal conversion module is used for converting the sensor signal into a sensor conversion signal and outputting the sensor conversion signal to the analysis module;
the analysis module is used for analyzing the sensor conversion signal.
Optionally, the signal output module comprises a first type signal output module, the signal conversion module comprises a first conversion module, and the analysis module comprises a first analysis module:
The first conversion module is used for converting the voltage signals output by the first type signal output module into pixel photosensitive signals and outputting the pixel photosensitive signals to the first analysis module so that the first analysis module can analyze the pixel photosensitive signals;
the signal output module comprises a second class signal output module, the signal conversion module comprises a second conversion module, and the analysis module comprises a second analysis module;
The second conversion module is configured to convert the pixel photosensitive signal output by the second type signal output module into a voltage signal, and output the voltage signal to the second analysis module, so that the second analysis module performs analysis processing according to the voltage signal.
The first conversion module comprises a clock generation unit, a first logic control unit, a first shift counting unit, a first DA conversion unit and a first comparison unit;
the clock generation unit is used for generating a pixel photosensitive signal storage clock and a pixel photosensitive signal shift clock;
The first logic control unit is used for reading and generating a counting clock and a clear clock according to the pixel photosensitive signal storage clock and the pixel photosensitive signal shifting clock, wherein the counting clock is synchronous with the pixel photosensitive signal shifting clock;
the first shift counting unit is used for counting and accumulating according to the counting clock, outputting accumulated count to the first DA conversion unit, and counting and resetting according to the resetting clock;
The first DA conversion unit is used for converting the accumulated count into a sawtooth analog voltage signal;
The first comparison unit is configured to output a pixel photosensitive signal according to the sawtooth analog voltage signal and the analog voltage signal output by the analog voltage signal output unit, so that the first analysis module analyzes the pixel photosensitive signal, where the sawtooth analog voltage signal has the same period as the pixel photosensitive signal storage clock, and the pixel photosensitive signal is synchronous with the pixel photosensitive signal shift clock.
Optionally, the first type signal output module further includes a digital voltage signal output unit;
the first conversion module further comprises a second DA conversion unit;
The second DA conversion unit is used for converting the digital voltage signal output by the digital voltage signal output unit into an analog voltage signal, and outputting the analog voltage signal to the first comparison unit;
The first comparison unit is also used for outputting a pixel photosensitive signal according to the sawtooth analog voltage signal and the analog voltage signal output by the second DA conversion unit.
Optionally, the second conversion module comprises a second logic control unit, a threshold setting unit, a second comparison unit, a second shift counting unit and a trigger;
the second class signal output module comprises a pixel photosensitive signal output unit;
The second logic control unit is used for generating a pixel photosensitive signal storage clock and a pixel photosensitive signal shift clock, and controlling the pixel photosensitive signal output unit to generate a pixel photosensitive signal according to the pixel photosensitive signal storage clock and the pixel photosensitive signal shift clock;
The threshold setting unit is used for generating a voltage threshold;
The second comparison unit is used for outputting a binarization signal according to the pixel photosensitive signal and the voltage threshold value and outputting the binarization signal to the second logic control unit;
the second logic control unit is further configured to generate a count stop clock according to the pixel photosensitive signal shift clock and the binarization signal when the binarization signal is detected;
The second shift counting unit is used for carrying out count accumulation according to the pixel photosensitive signal shift clock, stopping counting when the count stop clock is detected, and outputting count accumulation;
The second logic control unit is further configured to generate a data output trigger clock according to the pixel photosensitive signal storage clock, where a rising edge of the pixel photosensitive signal storage clock is synchronous with a rising edge of the data output trigger clock;
The data output trigger clock is used for generating a pixel photosensitive signal storage clock according to the pixel photosensitive signal and the data output trigger clock, wherein the rising edge of the pixel photosensitive signal storage clock is synchronous with the falling edge of the data output trigger clock;
The trigger is used for outputting the count accumulation as a digital voltage signal to the second analysis module when receiving the data output trigger clock so as to enable the second analysis module to analyze the digital voltage signal;
The second shift counting unit is further used for resetting the count accumulation according to the clearing clock.
Optionally, the second conversion module further comprises a third DA conversion unit;
The third DA conversion unit is configured to convert the digital voltage signal into an analog voltage signal, so that the second analysis module analyzes the analog voltage signal.
According to the embodiment of the invention, the sensor signal is output to the signal conversion module through the signal output module, the signal conversion module converts the sensor signal into the sensor conversion signal and outputs the sensor conversion signal to the analysis module, and the analysis module analyzes the sensor conversion signal, so that the scheme realizes high-speed conversion of the sensor signal, improves the adaptation degree of the field analysis module and ensures the stable operation of the field analysis module.
Drawings
Fig. 1 is a schematic structural diagram of a sensor signal conversion device of a pre-alignment machine according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a voltage signal output measurement of a wafer edge according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a pixel photosensitive signal output measurement wafer edge according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a sensor signal conversion device of another pre-alignment machine according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a sensor signal conversion device of another pre-alignment machine according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a specific structure of a first conversion module according to an embodiment of the present invention;
fig. 7 is a waveform diagram of a pixel photosensitive signal storage clock Px, a pixel photosensitive signal shift clock Pt, a sawtooth analog voltage signal (0-Vref), an analog voltage signal V, and a pixel photosensitive signal CCDsig according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of another embodiment of a first conversion module;
fig. 9 is a schematic diagram of a specific structure of a second conversion module according to an embodiment of the present invention;
Fig. 10 is a waveform diagram of a pixel photosensitive signal storing clock Px, a pixel photosensitive signal shifting clock Pt, a pixel photosensitive signal CCDsig, a binarization signal Cmpsig, a count stop clock CLK1, a data output trigger clock CLK2, and a clear clock CLR2 according to an embodiment of the present invention;
fig. 11 is a schematic diagram of a specific structure of another second conversion module according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Fig. 1 is a schematic structural diagram of a sensor signal conversion device of a pre-alignment machine according to an embodiment of the present invention, where the device, as shown in fig. 1, includes a signal output module 10, a signal conversion module 20, and an analysis module 30, where the signal output module 10 is configured to output a sensor signal of the pre-alignment machine to the signal conversion module 20, the signal conversion module 20 is configured to convert the sensor signal into a sensor conversion signal and output the sensor conversion signal to the analysis module 30, and the analysis module 30 is configured to analyze the sensor conversion signal.
The existing prealignment machine can adopt different types of sensors to detect the edge of a wafer, detect the shielding signal change of the wafer to the sensors by rotating the wafer, calculate the circle center coordinates and the notch direction of the wafer, and the on-site analysis module outputs an adjustment signal according to the calculated circle center coordinates and the notch direction of the wafer and the offset between the circle center coordinates and the notch direction of the preset wafer so as to adjust the wafer;
The different types of sensors can comprise silicon photocells, phototriodes and linear CCD sensors, the different types of sensors are not particularly limited, the internal principle that the different types of sensors detect the edge of a wafer is not needed, the output sensor signals are different, and the field analysis module only can analyze specific sensor signals, so that the sensor signals output by the different types of sensors are converted through the signal conversion module 20 and are output to the analysis module 30, the field analysis module can directly analyze the sensor conversion signals, and the circle center coordinates and the notch direction of the wafer can be calculated, so that the stable operation of the field analysis module is ensured.
It will be understood that the actual field analysis module 30 may be any other type of analysis module, and the signal conversion module 20 may convert different sensor signals into other types of analysis modules, so as to meet the analysis of the field analysis modules 30 of different types, and the type of the field analysis module 30 is not limited in this embodiment.
Considering that the pre-alignment sensor at present mainly has two output interfaces, one is voltage signal output, fig. 2 is a schematic diagram of the principle of measuring the edge of a wafer by using the voltage signal output provided by the embodiment of the invention, as shown in fig. 2, the principle is that the blocking distance L of the wafer B is converted into voltage in equal proportion to output (i.e. L1), namely, the blocking distance/detection range=output voltage/reference voltage. Fig. 3 is a schematic diagram of a pixel photosensitive signal output measuring wafer edge, as shown in fig. 3, by using an array sensor C to detect the edge of a wafer B, a light excitation unit C1 in the array sensor C irradiates the wafer B, each photosensitive unit C2 corresponds to a register, a photosensitive value of each photosensitive unit is stored in the corresponding register during detection, photosensitive information (e.g. l 2) of each photosensitive unit is obtained through reading the register, and then the photosensitive information is processed to obtain edge position information;
meanwhile, the types of the existing on-site analysis modules are also considered to be different, one is usually an analysis module for analyzing voltage signals, and the other is usually an analysis module for analyzing pixel photosensitive signals;
In the following, the mutual conversion of the two sensor signals is specifically described, and the two sensor signals are respectively analyzed by different analysis modules after the mutual conversion, and optionally, in some embodiments, fig. 4 is a schematic structural diagram of a sensor signal conversion device of another prealignment machine provided by the embodiment of the present invention, as shown in fig. 4, the signal output module 10 includes a first type signal output module 11, the signal conversion module 20 includes a first conversion module 21, the analysis module 30 includes a first analysis module 31, and the first conversion module 21 is configured to convert a voltage signal output by the first type signal output module 11 into a pixel photosensitive signal and output the pixel photosensitive signal to the first analysis module 31 so that the first analysis module 31 performs analysis processing according to the pixel photosensitive signal;
the first type signal output module 11 may convert the blocking distance of the wafer into voltage by using an equal proportion and output the voltage, so as to determine the edge position of the wafer, the first analyzing module 31 is a module for analyzing the pixel photosensitive signals, that is, determining the edge position information according to the photosensitive information of each photosensitive unit, and the first converting module 21 may convert the voltage signal into the pixel photosensitive signals, so that the first type analyzing module 31 may determine the edge position according to the pixel photosensitive signals.
Or in other embodiments, fig. 5 is a schematic structural diagram of a sensor signal conversion device of another pre-alignment machine according to an embodiment of the present invention, where, as shown in fig. 5, the signal output module 10 includes a second type signal output module 12, the signal conversion module 20 includes a second conversion module 22, the analysis module 30 includes a second analysis module 32, and the second conversion module 22 is configured to convert a pixel photosensitive signal output by the second type signal output module 12 into a voltage signal and output the voltage signal to the second analysis module 32 so that the second analysis module 32 performs an analysis process according to the voltage signal.
The second-type signal output module 12 may be a linear CCD sensor, where the linear CCD sensor uses the photosensitive information pixel photosensitive signals of each photosensitive unit to obtain edge position information, the second-type analyzing module 32 is a module that analyzes the voltage signals, that is, determines the edge position information according to the voltage signals, and converts the pixel photosensitive signals into the voltage signals through the second converting module 22, so that the second-type analyzing module can analyze and determine the edge position according to the voltage signals.
Optionally, based on the foregoing embodiment, the first conversion module 21 and the second conversion module 22 are further refined, and fig. 6 is a schematic diagram of a specific structure of the first conversion module according to the embodiment of the present invention;
Fig. 7 is a waveform diagram of a pixel photosensitive signal storing clock Px, a pixel photosensitive signal shifting clock Pt, a sawtooth analog voltage signal (0-Vref), an analog voltage signal V, and a pixel photosensitive signal CCDsig according to an embodiment of the present invention, wherein as shown in fig. 6-7, the first type signal output module 11 includes an analog voltage signal output unit 111, and the first conversion module 21 includes a clock generating unit 211, a first logic control unit 212, a first shifting count unit 213, a first DA conversion unit 214, and a first comparison unit 215;
A clock generation unit 211 for generating a pixel photosensitive signal holding clock Px and a pixel photosensitive signal shift clock Pt;
The first logic control unit 212 is configured to read and generate a count clock CLK and a clear clock CLR according to the pixel photosensitive signal storage clock Px and the pixel photosensitive signal shift clock Pt, where the count clock CLK is synchronous with the pixel photosensitive signal shift clock Pt;
The first shift counting unit 213 is configured to count and accumulate according to the count clock CLK, and output an accumulated count to the first DA conversion unit 214;
A first DA conversion unit 214 for converting the accumulated count into a sawtooth analog voltage signal (0-Vref);
the first comparing unit 215 is configured to output a pixel photosensitive signal CCDsig according to the sawtooth analog voltage signal (0-Vref) and the analog voltage signal V output by the analog voltage signal output unit, so that the first analyzing module 31 analyzes the pixel photosensitive signal, where the sawtooth analog voltage signal (0-Vref) has the same period as the pixel photosensitive signal storing clock Px, and the pixel photosensitive signal CCDsig is synchronous with the pixel photosensitive signal shifting clock Pt.
The first logic control unit 211 may be GAL22V10D, the first shift count unit 213 may be SN74LV4040A, the first DA conversion unit 214 may be composed of two chips, DAC902 and OPA2680, and the first comparison unit 215 may be TLV3201;
The conversion principle of converting an analog voltage signal into a pixel photosensitive signal is described below with reference to a specific clock, specifically, with reference to fig. 7, the first comparing unit 215 outputs a square wave signal V ' according to a sawtooth analog voltage signal (0-Vref) and an analog voltage signal V, the period of the square wave signal V ' is the same as the period of the pixel photosensitive signal storage clock Px, the position of the square wave signal V ' turned high and low is the position of the pixel photosensitive signal shift clock Pt corresponding to the ith photosensitive unit (the square wave signal V ' and the pixel photosensitive signal are essentially the same type of signal), and the first analyzing module 31 can directly analyze the position of the wafer edge through the position of the pixel photosensitive signal shift clock Pt corresponding to the ith photosensitive unit, so that the position of the wafer edge can be analyzed by analyzing the position of the square wave signal V ' turned high and low, i.e. determining the position of the pixel photosensitive signal shift clock Pt corresponding to the ith photosensitive unit.
Optionally, fig. 8 is a schematic diagram of a specific structure of another first conversion module according to an embodiment of the present invention, where, as shown in fig. 8, the first type signal output module 11 further includes a digital voltage signal output unit 112;
The first conversion module 21 further includes a second DA conversion unit 216, a second DA conversion unit 216 for converting the digital voltage signal output from the digital voltage signal output unit 112 into an analog voltage signal, and further for outputting the analog voltage signal to the first comparison unit 215, and the first comparison unit 215 further outputs a pixel photosensitive signal according to the sawtooth analog voltage signal and the analog voltage signal output from the second DA conversion unit 216. When the digital voltage signal output unit 112 outputs a digital voltage signal, the second DA conversion unit 216 can convert the digital voltage signal into an analog voltage signal, and the first comparison unit 215 outputs a pixel photosensitive signal according to the sawtooth analog voltage signal and the analog voltage signal, so as to meet the conversion requirements of other scenes.
Optionally, fig. 9 is a schematic diagram of a specific structure of a second conversion module according to an embodiment of the present invention, fig. 10 is a waveform diagram of a pixel photosensitive signal storage clock Px, a pixel photosensitive signal shift clock Pt, a pixel photosensitive signal CCDsig, a binarization signal Cmpsig, a count stop clock CLK1, a data output trigger clock CLK2, and a clear clock CLR2 according to an embodiment of the present invention, and as shown in fig. 9-10, the second conversion module 22 includes a second logic control unit 221, a threshold setting unit 222, a second comparing unit 223, a second shift counting unit 224, and a trigger 225;
the second type signal output module 12 includes a pixel photosensitive signal output unit 121;
The second logic control unit 221 is configured to generate a pixel photosensitive signal storage clock Px and a pixel photosensitive signal shift clock Pt, and control the pixel photosensitive signal output unit 121 to generate a pixel photosensitive signal CCDsig according to the pixel photosensitive signal storage clock Px and the pixel photosensitive signal shift clock Pt;
a threshold setting unit 222 for generating a voltage threshold V Threshold value ;
the second comparing unit 223 is configured to output a binarized signal Cmpsig according to the pixel photosensitive signal CCDsig and the voltage threshold V Threshold value , and output a binarized signal Cmpsig to the second logic control unit 221;
the second logic control unit 221 is further configured to generate a count stop clock CLK1 according to the pixel photosensitive signal shift clock Pt and the binarization signal Cmpsig when the binarization signal Cmpsig is detected;
A second shift counting unit 224 for performing count accumulation according to the pixel photosensitive signal shift clock Pt, stopping counting when the count stop clock CLK1 is detected, and outputting the count accumulation;
The second logic control unit 221 is further configured to generate a data output trigger clock CLK2 according to the pixel photosensitive signal storage clock Px, where a rising edge of the pixel photosensitive signal storage clock Px is synchronous with a rising edge of the data output trigger clock CLK2;
the pixel photosensitive signal storage clock is also used for generating a cleaning clock CLR2 according to the pixel photosensitive signal storage clock Px and the data output trigger clock CLK2, wherein the rising edge of the cleaning clock CLR2 is synchronous with the falling edge of the data output trigger clock CLK 2;
a flip-flop 225 for outputting the count accumulation as the digital voltage signal Q to the second parsing module 32 to cause the second parsing module 32 to parse the digital voltage signal Q when receiving the data output trigger clock CLK 2;
The second shift count unit 224 is further configured to zero the count accumulation according to the clear clock CLR 2.
The second logic control unit 221 may be GAL22V10D, the second comparing unit 223 may be TLV3201, the second shift count unit 224 may be SN74LV4040A, and the trigger 225 may be SN74hc374;
with continued reference to fig. 10, specifically, since the level inversion time of the pixel photosensitive signal CCDsig is the edge position of the wafer, that is, the position corresponding to the pixel photosensitive signal shift clock Pt corresponding to the ith photosensitive unit analyzes the position of the edge of the wafer, in this embodiment, the second comparing unit 223 outputs the binarized signal Cmpsig according to the pixel photosensitive signal CCDsig and the voltage threshold V Threshold value , and the level inversion time of the binarized signal Cmpsig corresponds to the level inversion time of the pixel photosensitive signal CCDsig, that is, the position corresponding to the pixel photosensitive signal shift clock Pt corresponding to the ith photosensitive unit, that is, the detection time of the edge position of the wafer can be determined by the level inversion time on the binarized signal Cmpsig;
When the binarization signal Cmpsig is detected, the second logic control unit 221 generates a count stop clock CLK1 according to the pixel photosensitive signal shift clock Pt and the binarization signal Cmpsig, the second shift count unit 224 performs count accumulation according to the pixel photosensitive signal shift clock Pt, stops counting when the count stop clock CLK1 is detected, and outputs the count accumulation;
The second logic control unit 221 generates the data output trigger clock CLK2 according to the pixel photosensitive signal storage clock Px at the same time, and the trigger 225 outputs the count accumulation as the digital voltage signal Q to the second analyzing module 32 when receiving the data output trigger clock CLK2, so that the second analyzing module 32 analyzes the digital voltage signal Q, thereby determining the wafer edge position.
And after the data output trigger clock CLK2 ends, the second logic control unit 221 generates the clear clock CLR2, and the second shift count unit 224 clears the count accumulation according to the clear clock CLR2, to prepare for the next cycle count.
Optionally, fig. 11 is a schematic diagram of a specific structure of another second conversion module according to an embodiment of the present invention, and as shown in fig. 11, the second conversion module 22 further includes a third DA conversion unit 226, and the third DA conversion unit 226 is configured to convert a digital voltage signal (Dn) into an analog voltage signal (exemplarily, dn/1024×vmax) so that the second analysis module 32 analyzes the analog voltage signal. The third DA conversion unit 226 may be added to meet the conversion requirement of the second parsing module 32 for parsing the output analog voltage signal.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
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