CN118116929A - Integrated circuit structure and method for manufacturing high voltage field effect transistor - Google Patents

Abstract

The IC structure includes: a semiconductor substrate; an isolation structure formed in the semiconductor substrate to define an active region surrounded by the isolation member; a first well of a first conductivity type formed in the semiconductor substrate; a neutral region formed in the semiconductor substrate and laterally surrounding the first well; a second well of a second conductivity type formed on the semiconductor substrate and laterally surrounding the neutral region, the second conductivity type being opposite to the first conductivity type; a source electrode disposed on the second well of the semiconductor substrate; a drain electrode disposed on the first well of the semiconductor substrate; and a gate structure interposed between the source and the drain. The gate structure engages the first well, the neutral region, and the second well of the semiconductor substrate. The source, drain and gate structures are configured as FETs. Embodiments of the present application also relate to methods of fabricating high voltage field effect transistors.

Description

Integrated circuit structure and method for manufacturing high voltage field effect transistor

Technical Field

Embodiments of the present application provide integrated circuit structures and methods for manufacturing high voltage field effect transistors.

Background technique

The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each of which has smaller and more complex circuits than the previous generation. In the process of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometric size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by improving production efficiency and reducing related costs. Such shrinking also increases the complexity of IC processing and manufacturing, and in order to achieve these advances, similar developments in IC processing and manufacturing are required. For example, high voltage field effect transistors (FETs) for high voltage applications face various challenges, including breakdown voltage, on-state channel resistance, drain saturation current, off-state current, signal-to-noise ratio, etc. Therefore, although traditional high voltage FETs are generally sufficient to meet their intended purposes, they are not satisfactory in every aspect.

Summary of the invention

Some embodiments of the present application provide an integrated circuit (IC) structure, comprising: a semiconductor substrate; an isolation structure formed in the semiconductor substrate to define an active area surrounded by the isolation component; a first well of a first conductivity type formed in the semiconductor substrate; a neutral region formed in the semiconductor substrate and laterally surrounding the first well; a second well of a second conductivity type formed on the semiconductor substrate and laterally surrounding the neutral region, the second conductivity type being opposite to the first conductivity type; a source disposed on the second well of the semiconductor substrate; a drain disposed on the first well of the semiconductor substrate; and a gate structure interposed between the source and the drain, the gate structure joining the first well, the neutral region and the second well of the semiconductor substrate, wherein the source, the drain and the gate structure are configured as a first field effect transistor (FET).

Some other embodiments of the present application provide an integrated circuit (IC) structure, comprising: a semiconductor substrate; a shallow trench isolation (STI) component formed in the semiconductor substrate to define an active area surrounded by the shallow trench isolation component; a first well of a first conductivity type, disposed on the semiconductor substrate; a neutral region, disposed on the semiconductor substrate and laterally surrounding the first well; a second well of a second conductivity type, disposed on the semiconductor substrate and laterally surrounding the neutral region, the second conductivity type being opposite to the first conductivity type; and a first field effect transistor (FET) and a second field effect transistor, formed on the semiconductor substrate, wherein the first field effect transistor comprises a first source disposed on the second well, a drain disposed on the first well, and a first gate structure between the first source and the drain, the first gate structure being bonded to the first well, the neutral region, and the second well, and the second field effect transistor comprises a second source disposed on the second well, the drain, and a second gate structure between the second source and the drain, the second gate structure being bonded to the first well, the neutral region, and the second well.

Some other embodiments of the present application provide a method for manufacturing a high-voltage field effect transistor, comprising: forming a first well of a first conductivity type in a semiconductor substrate; forming a second well of a second conductivity type on the semiconductor substrate, so that the second well laterally surrounds the first well and is separated from the first well by a neutral region between the first well and the second well, the second conductivity type being opposite to the first conductivity type; forming an active area surrounded by an isolation structure having an uneven thickness, wherein the active area includes a planar active area and a fin active area; forming a source in the second well; forming a drain in the first well; and forming a gate structure between the source and the drain, the gate structure being arranged on the first well, the neutral region and the second well.

BRIEF DESCRIPTION OF THE DRAWINGS

When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

1A is a top view of an integrated circuit (IC) structure having one or more FET devices according to some embodiments of the present disclosure;

FIG. 1B is a cross-sectional view of the IC structure of FIG. 1A according to some embodiments of the present disclosure;

FIG. 2A is a partial top view of an IC structure according to some embodiments of the present disclosure;

FIG. 2B is a partial cross-sectional view of the IC structure of FIG. 2A according to some embodiments of the present disclosure;

FIG. 3A is a top view of an IC structure according to some embodiments of the present disclosure;

3B is a partial cross-sectional view of the IC structure of FIG. 3A according to some embodiments of the present disclosure;

FIG. 4A is a top view of an IC structure according to some embodiments of the present disclosure;

FIG. 4B is a partial top view of an IC structure according to some embodiments of the present disclosure;

FIG. 4C is a partial cross-sectional view of the IC structure of FIG. 4A (or FIG. 4B ) according to some embodiments of the present disclosure;

4D is a partial cross-sectional view of the IC structure of FIG. 4A (or FIG. 4B ) according to some embodiments of the present disclosure;

FIG5A is a partial top view of an IC structure according to some embodiments of the present disclosure;

FIG5B is a partial top view of an IC structure according to some embodiments of the present disclosure;

6A, 6B, 6C, 6D, 6E, 6F, and 6G are partial top views of IC structures constructed according to various embodiments of the present disclosure; and

FIG. 7 is a flow chart of a method of fabricating an IC structure according to some embodiments of the present disclosure.

Detailed ways

The following disclosure provides many different embodiments or examples for realizing different features. Reference numerals and/or characters may be repeated in each example described herein. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between each disclosed embodiment and/or configuration. In addition, the specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted to form, and may also include an embodiment in which an additional component may be formed between the first component and the second component, so that the first component and the second component may not be in direct contact. In addition, in the disclosed embodiments, a component formed on another component, connected to and/or coupled to another component may include an embodiment in which the component is directly contacted to form, and may also include an embodiment in which the additional component formed between the components may not be in direct contact.

In addition, the present disclosure may repeat reference numerals and/or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and/or configurations discussed. In addition, in the following embodiments of the present disclosure, a component formed on another component, connected to and/or coupled to another component may include an embodiment in which the components are directly contacted, and may also include an embodiment in which an additional component is formed between the components so that the components may not be directly contacted. In addition, spatial relative terms such as "lower", "upper", "horizontal", "vertical", "above", "above", "below", "below", "upward", "downward", "top", "bottom" and their derivatives (e.g., "horizontally", "downward", "upward", etc.) are used to easily understand the relationship between one component and another component of the embodiments of the present disclosure. Spatial relative terms are intended to cover different orientations of devices including components. In addition, when "about", "approximately", etc. are used to describe a numerical value or a numerical range, the term is intended to cover a numerical value within a reasonable range including the numerical value, such as within +/-10% of the numerical value or other values understood by those skilled in the art. For example, the term "about 5nm" covers a size range from 4.5nm to 5.5nm.

The disclosed embodiments generally relate to integrated circuit (IC) structures and methods of manufacturing the same, and more particularly to high voltage field effect transistor (FET) structures. In various embodiments, the IC structures include planar FET structures and multi-gate devices, such as FETs formed on fin active areas, and nanosheet structures with multiple channels stacked vertically on each other in an effort to improve gate control by increasing gate-channel coupling, reduce off-state current, and reduce short channel effects (SCE).

The disclosed FET structure is formed on a planar active area as a planar FET device, and is optionally formed on a three-dimensional (3D) structure, such as a multi-gate FET device. Examples of multi-gate devices include fin field effect transistors (FinFETs) having a fin structure and a multi-bridge channel (MBC). The MBC transistor has a gate structure that can extend partially or completely around the channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel region, the MBC transistor can also be referred to as a gate-around transistor (SGT) or a gate-all-around (GAA) transistor having multiple channel members stacked vertically. The IC structure may include other suitable device structures, such as fork-piece FETs and complementary FET (CFET) structures. According to various embodiments of the present disclosure, the IC structure and its manufacturing method are described in detail together.

FIG. 1A is a top view of an IC structure 100 having one or more FETs, and FIG. 1B is a cross-sectional view of the IC structure 100 constructed according to various embodiments along the dashed line AA'. In the present embodiment, the FET of the IC structure 100 is designed for high voltage applications and is therefore also referred to as a high voltage FET (HVFET). In the disclosed embodiment of the IC structure 100, one or more n-type FETs (nFETs) are provided as examples for illustration. However, it is not intended to be limiting, and the IC structure 100 may additionally or optionally include one or more p-type FETs (pFETs). In FIGS. 1A and 1B, the IC structure 100 includes two field effect transistors configured side by side, particularly sharing a common drain.

IC structure 100 includes substrate 102. Substrate 102 is a semiconductor substrate. Semiconductor substrate 102 includes silicon. In some other embodiments, substrate 102 includes germanium, silicon germanium, or other suitable semiconductor materials. Alternatively, substrate 102 may be made of some other suitable elemental semiconductors, such as diamond or germanium; suitable compound semiconductors, such as silicon carbide, indium arsenide, or indium phosphide; or suitable alloy semiconductors, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide.

According to various embodiments, the substrate 102 may include buried layers, such as an N-type buried layer (NBL), a P-type buried layer (PBL), and a buried dielectric layer including a buried oxide (BOX) layer. In the disclosed embodiments, the substrate 102 includes a P-type doped region 104 located at a deep level of the substrate 102. The p-type dopant includes boron, gallium, indium, other suitable p-type dopants, or a combination thereof. Therefore, the P-type doped region 104 is also referred to as a deep P-well 104. In some embodiments, the substrate 102 may include a BOX layer below the deep P-well 104. The deep P-well 104 may be formed by ion implantation, and the BOX layer may be formed by a method called isolation by implantation of oxygen (SIMOX).

The substrate 102 also includes an N-well region (or simply N-well) 106 (also referred to as a high voltage N-well or HVNW) and a P-well region (or simply P-well) 108 formed above the deep P-well 104. The P-well 108 is configured to surround and enclose the N-well 106 in a top view, as shown in FIG. 1A. The N-well 106 and the P-well 108 are formed by a suitable method, such as ion implantation with appropriate dopants, implantation energies, and doping doses to achieve the desired doping type, doping level, doping thickness, and doping concentration. In the top view as shown in FIG. 1A, according to the disclosed embodiments, the P-well 108 surrounds and encloses the N-well 106. The P-well 108 is doped with a P-type dopant such as boron, and the N-well 106 is doped with an N-type dopant such as phosphorus. In another embodiment, the N-well 106 and the P-well 108 can be formed by any suitable procedure having multiple processing steps, such as forming a patterned mask by a photolithography process and patterning, applying an ion implantation process to the substrate 102 through the opening of the patterned mask, and then removing the patterned mask. In the disclosed embodiment, the N-well 106 is used as a drift region of the nFET to be formed, and the P-well 108 provides a channel 122 of the nFET.

In addition, a neutral region 120 is inserted between the N-well 106 and the P-well 108, such that in the top view, the neutral region 120 surrounds and encloses the N-well 106, and the P-well 108 surrounds and encloses the neutral region 120, as shown in FIG1A. The neutral region 120 is designed to improve the performance of the IC structure 100, especially the performance of the high voltage FET, which includes increasing the breakdown voltage, reducing the resistance of the HVFET in the on state, and reducing the current of the HVFET in the off state.

The neutral region 120 is a region of the semiconductor substrate 102 without dopants. This can be achieved by a suitable method, such as redesigning the photomask used to form the N-well 106 and the P-well 108 so that the neutral region 120 is not implanted. The neutral region 120 includes an inner edge that continuously contacts the N-well 106 and an outer edge that continuously contacts the P-well 108. The neutral region 120 spans the width W between the N-well 106 and the P-well 108. The width W is appropriately designed based on theoretical analysis and experiments. As pointed out above, the disclosed neutral region 120 brings benefits, such as increased breakdown voltage and reduced leakage current. However, the neutral region 120 also affects other factors, such as increasing parasitic capacitance, which in turn affects switching behavior and reduces frequency response. Therefore, the design of the neutral region 120 needs to consider various factors to achieve the desired performance improvement while minimizing any potential disadvantages. In the disclosed embodiment, the width W is in the range between 0.01 μm and 5 μm.

The IC structure 100 also includes an isolation structure 110 formed on the substrate 102, thereby defining an active area 112, which is a semiconductor surface area for an active device (such as a FET) to be formed thereon. In the IC structure 100 shown in FIG. 1B, the active area 112 is planar, fin-shaped, or a combination thereof (also referred to as a hybrid active area). The fin-shaped active area is a three-dimensional (3D) active area to increase the coupling between the channel and the gate. However, it is not intended to be limiting. The active area can have any suitable profile, such as other suitable 3D profiles.

The isolation structure 110 includes one or more dielectric materials and provides separation and isolation between the various devices formed on the active area 112. The isolation structure 110 can be formed by any suitable method and can have any suitable geometry, such as a stepped profile with different thicknesses, which will be described in further detail later. In the disclosed embodiment, the isolation structure 110 includes a shallow trench isolation (STI) component (also represented by the reference numeral 110) formed on the substrate 102. In some embodiments, the STI component 110 is formed by a suitable procedure, which includes patterning to form a trench, filling the trench with a dielectric material, and polishing to remove excess dielectric material and flatten the top surface. The patterning process includes a photolithography process, etching, and may also include forming a patterned hard mask. One or more etching processes are performed on the substrate 102 through the opening of the soft mask or hard mask (which is formed by patterning and etching by photolithography). According to some embodiments, the formation of the STI component 110 is further described below.

In the present example, a hard mask is deposited on the substrate 102 and patterned by a photolithography process. The hard mask includes a dielectric material (such as silicon oxide, silicon nitride, silicon oxynitride) and/or other suitable materials (such as metal oxides). In an embodiment, the hard mask includes a silicon oxide film and a silicon nitride film. The hard mask can be formed by thermal growth, atomic layer deposition (ALD), chemical vapor deposition (CVD), high density plasma CVD (HDP-CVD), other suitable deposition processes, or combinations thereof.

A photoresist layer (or resist) for defining the isolation structure 110 may be formed on the hard mask. The resist layer includes a photosensitive material that causes the layer to undergo a property change when exposed to light, such as ultraviolet (UV) light, deep ultraviolet (DUV) light, or extreme ultraviolet (EUV) light. This property change can be used to selectively remove exposed or unexposed portions of the resist layer by the development process described. This process of forming a patterned resist layer is also referred to as a photolithography process.

In one embodiment, the patterned resist layer is to leave the portion of the photoresist material disposed above the substrate 102 by the photolithography process. After the patterned resist, an etching process is performed on the substrate 102 to open the hard mask, so that the pattern is transferred from the resist layer to the hard mask. After the patterned hard mask, the remaining resist layer can be removed. The photolithography process includes spin-coating the resist layer, soft baking of the resist layer, mask alignment, exposure, post-exposure baking, developing the resist layer, rinsing and drying (e.g., hard baking). Alternatively, the photolithography process can be realized, supplemented or replaced by other suitable methods such as maskless lithography, electron beam writing and ion beam writing. The etching process of the patterned hard mask can include wet etching, dry etching or a combination thereof. The etching process can include multiple etching steps. For example, the silicon oxide film in the hard mask can be etched by a diluted hydrofluoric solution, and the silicon nitride film in the hard mask can be etched by a phosphoric acid solution.

Then, an etching process may follow to etch portions of the substrate 102 that are not covered by the patterned hard mask. The patterned hard mask is used as an etching mask during the etching process to pattern the substrate 102. The etching process may include any suitable etching technique, such as dry etching, wet etching, and/or other etching methods (e.g., reactive ion etching (RIE)). In some embodiments, the etching process includes multiple etching steps using different etching chemicals, designed to etch the substrate to form a groove with a specific groove profile for improving device performance and pattern density. In some instances, the semiconductor material of the substrate 102 may be etched by a dry etching process using a fluorine-based etchant. In particular, the etching process applied to the substrate 102 is controlled so that the substrate 102 is partially etched. This can be achieved by controlling the etching time or by controlling other etching parameters. After the etching process, the active area 112 is defined on the substrate 102 and extends above the isolation structure 110.

One or more dielectric materials are filled in the trenches to form the STI features 110. Suitable dielectric materials for filling the trenches include semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, fluorinated quartz glass (FSG), low-K dielectric materials, and/or combinations thereof. In various embodiments, the dielectric material is deposited using a HDP-CVD process, a sub-atmospheric pressure CVD (SACVD) process, a high aspect ratio process (HARP), a flowable CVD (FCVD), and/or a spin coating process.

The deposition of the dielectric material may be followed by a chemical mechanical polishing/planarization (CMP) process to remove excess dielectric material and planarize the top surface of the semiconductor structure. The CMP process may use the hard mask layer as a polishing stop layer to prevent polishing of the semiconductor substrate 102. In some embodiments, the CMP process completely removes the hard mask. Alternatively, the hard mask may be removed by an etching process. However, in further embodiments, portions of the hard mask remain after the CMP process.

In some embodiments, the method further includes forming the fin active region 112 by a suitable method, such as etching back the STI structure 110, so that the STI component 110 is recessed and the active region 112 extends above the STI component 110. The etch-back process uses one or more etching steps (such as dry etching, wet etching, or a combination thereof) to selectively etch back the STI component 110. For example, when the STI component 110 is a silicon oxide component, a wet etching process using hydrofluoric acid can be used for etching. Optionally, the fin active region 112 is formed by epitaxially growing one or more semiconductor materials so that the fin active region 112 extends above the STI component 110.

In some embodiments, the STI feature 110 includes various regions with different thicknesses and is designed to reduce leakage current. This will be described in further detail later, such as in FIGS. 2A , 2B , 3A , and 3B .

The active regions 112 are spaced apart from each other. The active regions 112 may have an elongated shape oriented longitudinally along a first direction (X direction). The second direction (Y direction) is orthogonal to the X direction. The X-axis and the Y-axis define the top surface of the substrate 102. The STI feature 110 includes two extensions to define three active regions: a first active region, a second active region, and a third active region, which is shown in FIG. 1A and more clearly shown in FIG. 2A.

Specifically, the first active region 112 is formed directly on the N-well 106 and is disposed within the N-well 106. The first active region spans between two extensions of the STI component 110 along the X direction. The second active region 112 is disposed on one side (such as the left side) of the first active region 112 and extends from the STI component 110 along the X direction over the N-well 106, the neutral region 120, and the P-well 108. The third active region 112 is disposed on the other side (such as the right side) of the first active region 112 and extends from the STI component 110 along the X direction over the N-well 106, the neutral region 120, and the P-well 108. As noted above, the active region 112 may be a mixed active region including a planar active region and a fin active region.

One or more FETs are formed on the active region 112. The FETs include a source component (or simply source) 114, a drain component (or simply drain) 116, and a gate structure 118 between the source 114 and the drain 116. The source 114 and the drain 116 are formed in the substrate 102, and the gate structure 118 is formed on the substrate 102. In the disclosed embodiment shown in FIGS. 1A and 1B , the IC structure 100 includes two nFETs (FET-I and FET-II) that share a common drain 116.

The gate structure 118 includes a gate stack, which may further include a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes one or more dielectric materials, such as silicon oxide, a high-k dielectric material, other suitable dielectric materials, or a combination thereof. In some embodiments, the gate dielectric layer includes one or more high-k dielectric materials, and may further include an interface layer (such as silicon oxide) between the channel and the high-k dielectric material. The high-k dielectric material may include a metal oxide, a metal nitride, such as LaO, AlO, ZrO, TiO, Ta ₂ O ₅ , Y ₂ O ₃ , SrTiO ₃ (STO), BaTiO ₃ (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO ₃ (BST), Al ₂ O ₃ , Si ₃ N ₄ , oxynitride (SiON) or other suitable high-k dielectric materials. The interfacial layer may include silicon oxide, silicon nitride, silicon oxynitride, and/or other suitable materials. The interfacial layer may be formed by a suitable method, such as atomic layer deposition (ALD), CVD, ozone oxidation, etc. The high-k dielectric layer is deposited on the interfacial layer (if the interfacial layer exists) by a suitable technique, such as ALD, CVD, metal organic CVD (MOCVD), PVD, thermal oxidation, combinations thereof, and/or other suitable techniques.

The gate electrode includes one or more conductive materials, such as doped polysilicon, metals, or metal alloys. The metal in the gate electrode includes aluminum, copper, tungsten, ruthenium, cobalt, nickel, metal silicide, other suitable metal-containing conductive materials, or combinations thereof. In some embodiments, the gate electrode may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, Cu, W, any suitable material, or combinations thereof.

In some embodiments, the gate electrode includes other materials, such as work function metals, which are used to reduce the threshold voltage of the corresponding FET. The work function metal used in the gate electrode is different from that of n-type FET (nFET) and p-type FET (pFET), and can therefore be formed separately. The work function (WF) metal layer includes a conductive layer of a metal or metal alloy having an appropriate work function, so that the corresponding FET is enhanced by its device performance. For pFET and nFET, the work function metal layer is different, respectively referred to as n-type WF metal and p-type WF metal. The selection of WF metal depends on the FET to be formed on the active area. For example, n-type WF metal and p-type WF metal are formed in corresponding gate stacks, respectively. In particular, n-type WF metal includes a metal having a first work function, so that the threshold voltage of the relevant nFET is reduced. The n-type WF metal is close to the work function of the silicon conduction band energy (Ec) or lower, presenting easier electron escape. For example, the n-type WF metal has a work function of about 4.2eV or less. The p-type WF metal includes a metal having a second work function, so that the threshold voltage of the relevant pFET is reduced. The p-type WF metal has a work function close to the silicon valence band energy (Ev) or higher, and presents a strong electron binding energy to the nucleus. For example, the p-type work function metal has a WF of about 5.2eV or higher. In some embodiments, the n-type WF metal includes tantalum (Ta). In other embodiments, the n-type WF metal includes titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), or a combination thereof. In other embodiments, the n-type WF metal includes Ta, TiAl, TiAlN, tungsten nitride (WN), or a combination thereof. The n-type WF metal may include various metal-based films as stacked parts for optimizing device performance and processing integration. In some embodiments, the p-type WF metal includes titanium nitride (TiN) or tantalum nitride (TaN). In other embodiments, the p-metal includes TiN, TaN, tungsten nitride (WN), titanium aluminum (TiAl), or a combination thereof. The p-type WF metal may include various metal-based films as stacked parts for optimizing device performance and processing integration. The work function metal is deposited by a suitable technique, such as physical vapor deposition (PVD) or ALD.

The gate structure 118 may also include a gate sidewall component (or gate spacer) formed on the sidewall of the gate electrode. The gate spacer provides isolation between the gate electrode and the source/drain component, and can be used to offset the subsequently formed source/drain component, and can be used to design or modify the source/drain structure profile. The gate spacer may include any suitable dielectric material, such as semiconductor oxides, semiconductor nitrides, semiconductor carbides, semiconductor oxynitrides, other suitable dielectric materials and/or combinations thereof. The gate spacer may have multiple films, such as two films (silicon oxide film and silicon nitride film) or three films (silicon oxide film; silicon nitride film; and silicon oxide film). The formation of the gate spacer includes deposition and anisotropic etching, such as dry etching.

The formation of the gate structure 118 includes depositing various gate materials and patterning the deposited gate materials using a process including photolithography and etching. In some embodiments, the gate structure 118 can be formed by a gate replacement process, in which a dummy gate structure is formed and replaced at a later stage, such as after forming the source 114 and the drain 116, to avoid undesirable effects of thermal processing on the gate structure 118.

In some embodiments, the gate structure 118 is segmented to have multiple segments for various manufacturing benefits, such as adjusting pattern density and improving process (such as CMP) uniformity. In the disclosed embodiment, the gate structure 118 for the first nFET (FET-I) includes: a first segment, between the drain 116 and the STI feature 110; and a second segment, between the source 114 and the STI feature 110. In a further embodiment, the first segment of the gate structure 118 is formed for manufacturing benefits and is floating, which means that it is not configured to be biased and does not serve as the gate of the first nFET. The second segment of the gate structure 118 is configured to be connected to a power signal line so that it is biased as a functional gate of the first nFET. Due to the different functions of the first segment and the second segment of the gate structure 118, the first segment and the second segment can be designed to have different sizes. For example, the second segment can have a size along the X direction that is larger than the size of the first segment. Specifically, the second segment of the gate structure 118 is bonded to the P-well 108, the neutral region 120, and the N-well 106. The second segment of the gate structure 118 is capacitively coupled to the P-well 108, thereby controlling the channel 122 of the first nFET. The channel 122 is the portion of the P-well 108 that is located below the second segment of the gate structure 118. The second nFET (FET-II) is similar to the first nFET in terms of layout and configuration. For example, the gate structure of the second nFET also includes two segments, one segment is floating and is disposed between the drain 116 and the STI feature 110; and the other segment is biased and is disposed between the drain 116 and the source 114.

The source 114 and the drain 116 are semiconductor components doped with appropriate dopants. For example, in the embodiment shown in FIGS. 1A and 1B , an nFET is formed, and the source 114 and the drain 116 are doped with an N-type dopant, such as phosphorus. This is merely illustrative and is not intended to be limiting. It should be understood that one or more pFETs may be formed alternatively or additionally. For a pFET, the source 114 and the drain 116 are doped with a p-type dopant. In addition, the doped wells 106 and 108 are exchanged for a P-type well and an N-type well, respectively.

In some embodiments, the source 114 and drain 116 are formed by diffusion or ion implantation. In some embodiments, the source 114 and drain 116 are formed by a process that includes: etching the substrate 102 to form source/drain (S/D) grooves in the S/D region; and epitaxially growing one or more semiconductor materials (such as silicon or silicon germanium) to achieve a strain effect with enhanced carrier mobility. In this case, dopants can be introduced into the source 114 and drain 116 during epitaxial growth. In some embodiments, a thermal annealing process may follow to activate the source 114 and drain 116.

In the described embodiment shown in FIGS. 1A and 1B , the IC structure 100 includes two nFETs arranged side by side with a common drain 116. As shown in FIG. 1B , the source 114, the drain 116, and the portion of the gate structure 118 located to the left of the drain 116 (such as the second segment) on the left constitute a first nFET (FET-I); and the source 114, the drain 116, and the portion of the gate structure 118 located to the right of the drain 116 on the right constitute a second nFET (FET-II). The first nFET and the second nFET share the common drain 116. Specifically, the common drain 116 is formed in the N-well 106, and the source 114 is formed in the P-well 108.

In particular, the IC structure 100 is designed with various components to enhance circuit performance, as further described below with reference to FIGS. 1A and 1B and other figures. The IC structure 100 includes a neutral region 120 surrounding and enclosing the N-well 106. This can be achieved by the layout of the N-well 106 and the P-well 108 without the need for additional processing costs and ion implantation. For example, a photomask defining the N-well 106 and a photomask defining the P-well 108 are designed to have a shape and size such that when they are formed on the substrate 102 by ion implantation using a photomask during ion implantation. The width W of the neutral region 120 depends on other device dimensions and is designed to enhance the performance of the IC structure 100. In the disclosed embodiment, the width W of the neutral region 120 is in a range between 0.01 μm and 5 μm.

The N-well 106 serves as a drift region, which is a region responsible for controlling the voltage in the device. In a FET, the drift region is the region between the source and drain where the electric field is high enough to cause electrons to drift toward the drain. The drift region is typically made of a lightly doped material with a low impurity concentration. In a high voltage FET, the drift region is designed to handle high voltages and minimize the electric field strength, thereby preventing breakdown.

When the FET is turned on, the portion of the P-well 108 underlying the corresponding gate structure 118 serves as a channel 122 for current to flow from the source 114 to the drain 116 .

IC structure 100 includes STI features 110 formed in N-well 106 designed for high voltage applications. In some embodiments, STI features 110 in N-well 106 are designed to have a ring surrounding drain 116.

The gate structure 118 is designed as a segmented structure with multiple segments. The segments of the gate structure 118 for one FET are electrically biased to the same power line to control the corresponding FET. In some embodiments, the segments of the gate structure 118 are longitudinally oriented along the Y direction. For example, the gate structure 118 in the first nFET (FET-I) includes a first segment disposed between the drain 116 and the STI component 110 and a second segment disposed between the source 114 and the STI component 110. The first segment and the second segment of the gate structure 118 are sandwiched by the STI component 110. In the disclosed example, the gate structure 118 in the first nFET (FET-I) has a similar segmented structure. The gate structure 118 in the second nFET (FET-II) includes a third segment disposed between the drain 116 and the STI component 110 and a fourth segment disposed between the corresponding source 114 and the STI component 110. The two segments of the gate structure 118 in the second nFET are sandwiched by the STI component 110.

The disclosed IC structure 100 is designed to effectively distribute the electric field and optimize parameters and enhance performance, such as increased breakdown voltage, reduced on-state channel resistance, and reduced off-state channel current. In addition, the STI feature 110 includes a stepped structure with different portions having different thicknesses; and the active region 112 is designed to have a hybrid structure including a fin active region and a planar active region, which will be further described below with reference to other figures.

FIG2A is a top view of an IC structure 130 having one or more high voltage FETs, and FIG2B is a partial cross-sectional view of the IC structure 130 constructed according to various embodiments, taken along the dashed line AA' of FIG2A. FIG3A is a top view of the IC structure 130, and FIG3B is a partial cross-sectional view of the IC structure 130 constructed according to various embodiments, taken along the dashed line AA' of FIG3A. In particular, for simplicity, FIG2A and FIG2B only show the STI features 110 and the active region 112. For simplicity, the gate structure is not shown in FIG3B.

In the disclosed embodiment, an n-type FET structure having one or more n-type FETs (nFETs) is provided as an example for illustration. However, it is not intended to be limiting, and the IC structure 130 may additionally or optionally include a p-type FET structure having one or more p-type FETs. The IC structure 130 is similar to the IC structure 100 in FIGS. 1A and 1B. For simplicity, similar components and features are not repeated. However, the STI component 110 in the IC structure 130 is designed differently. Specifically, the STI component 110 is non-planar and includes a stepped profile designed to prevent leakage. As shown in FIG. 2B, the STI component 110 surrounding the active area includes three regions with different heights: a first region 110A with a first thickness H1, a second region (also referred to as a transition region) 110B with a varying height, and a third region 110C with a height H1+H2. The STI component 110 in the transition region 110B gradually increases from a height H1 to a height H1+H2. H2 is in the range between 0.01 μm and 5 μm. Parameter H1 is optimized for its effectiveness. Exceeding the range (larger or smaller) is either costly or inefficient. The first region 110A spans dimension L1, the second region 110B spans dimension L2, and the third region 110C spans dimension L3 along the Y direction. According to some embodiments, dimension L2+L3 is in the range between 0.01 μm and 5 μm.

3A and 3B , transition region 110B of STI feature 110 is aligned with Nwell 106 such that transition region 110B contacts and surrounds Nwell 106. According to some embodiments, a distance D between gate structure 118 and transition region 110B ranges between 0.01 μm and 5 μm along the Y direction.

FIG4A is a top view of an IC structure 150 having one or more high voltage FETs, and FIG4B is a partial top view of an IC structure 150 constructed according to various embodiments. FIG4C is a partial cross-sectional view of the IC structure 150 taken along the dashed line AA' of FIG4A (or FIG4B); and FIG4D is a partial cross-sectional view of the IC structure 150 constructed according to various embodiments taken along the dashed line BB' of FIG4A (or FIG4B). Specifically, for simplicity, FIG4B, FIG4C, and FIG4D only show the STI features 110 and the active regions 112.

IC structure 150 includes an n-type FET structure having one or more nFETs, such as two nFETs sharing a common drain. IC structure 150 is similar to IC structure 130 in structure. For simplicity, similar components and features are not repeated. For example, STI feature 110 includes a stepped profile with different regions of different thicknesses. However, IC structure 150 includes an active area 112 having a planar active area and a fin active area. A planar active area is an active area having a top planar surface, while a fin active area is a cluster of active areas, each having side and top surfaces that collectively contribute to coupling between a corresponding gate and a channel.

As shown in FIG. 4B , the IC structure 150 includes three active regions 112, a left active region, a center active region, and a right active region. In the disclosed embodiment, those active regions 112 have a hybrid structure that also includes a planar active region 112P and a fin active region 112F, as shown in FIG. 4C and FIG. 4D . Specifically, as shown in FIG. 4D , along the X direction, the center active region 112 includes a first planar active region 112P between two portions of the STI component 110. The left active region 112 includes a second planar active region 112P disposed on the side of the STI component 110 in the first nFET and a first fin active region 112F disposed on the side of the second planar active region 112P in the first nFET. The right active region 112 includes a third planar active region 112P disposed on the side of the STI component 110 in the second nFET and a second fin active region 112F disposed on the side of the third planar active region 112P in the second nFET. In other words, each of the left active region 112 and the right active region 112 is mixed.

As shown in FIG. 4C , along the Y direction, the active region 112 includes a planar active region 112P between two portions of the STI feature 110 , and a fin active region 112F is disposed on a region outside the P-well 108 (not shown in FIG. 4A ).

A common drain 116 is formed in the first planar active region 112P. A source 114 of the first nFET is formed on the first fin active region 112F. A source 114 of the second nFET is formed on the second fin active region 112F. A gate structure 118 for each nFET (specifically, a second segment as a functional gate) is partially formed on the fin active region 112F and partially formed on the planar active region 112P, which will be described in further detail below with reference to FIGS. 5A , 5B, and 6A to 6G.

5A is a partial top view of an IC structure 150; FIG. 5B is a partial top view of an IC structure 150; and FIG. 6A to FIG. 6G are partial top views of an IC structure 150 constructed according to various embodiments. Specifically, for simplicity, FIG. 5A shows only the STI feature 110 and the active region 112; FIG. 5B shows only the STI feature 110, the active region 112, the source 114, the drain 116, and the gate 118; and FIG. 6A to FIG. 6G show the portion of the active region 112, the source 114, the drain 116, and the gate structure 118 within the dashed box 160 of FIG. 5B.

5A is similar to FIG. 4B and shows an active region 112. However, FIG. 5A further shows a planar active region 112P and a fin active region 112F of the active region 112. Specifically, the fin active region 112F and the planar active region 112P have an interface 152, which may not be a straight line in the top view.

FIG5B is similar to FIG5A , but further illustrates a source 114, a drain 116, and a gate structure 118. It can be seen that a common drain 116 is formed on the planar active region 112P, a source 114 is formed on the fin active region 112F, and a gate structure 118 is formed over the fin active region 112F and the planar active region 112P. In FIG5B , the gate structure 118 is illustrated by a transparent box of dashed lines so that the planar active region and the fin active region below can be seen. It should be noted that the segment of the gate structure 118 located above the central active region 112 is floating and is not shown in FIG5B for simplicity.

Furthermore, the interface 152 between the planar active region 112P and the fin active region 112F overlaps the gate structure 118 and may be any suitable geometry in top view, which is further illustrated in FIGS. 6A to 6G according to various embodiments.

In FIG. 6A , the active region 112 is shown in a top view. The drain 116 is formed on the planar active region 112P; the source 114 is formed on the fin active region 112F; and the gate structure 118 is partially formed on the fin active region 112F and partially formed on the planar active region 112P. The interface 152 between the planar active region 112P and the fin active region 112F overlaps the gate structure 118 and is a straight line in the top view. In FIG. 6B , the interface 152 is a curve in the top view. The interface 152 can have any suitable geometry, such as those shown in FIGS. 6C to 6G . By adjusting the geometry of the interface 152 between the planar active region 112P and the fin active region 112F, the high voltage FET is further adjusted to have enhanced performance, including increased breakdown voltage and reduced leakage current.

7 is a flow chart of a method 200 for fabricating an IC structure 100 having one or more high voltage FETs according to some embodiments. The method 200 includes an operation 202 by forming various doped wells, such as a p-type doped well 104, an N-well 106, and a p-well 108, on a substrate 102. The various doped wells are formed by a suitable method, such as ion implantation, diffusion, other suitable methods, or a combination thereof. In the disclosed embodiment, the p-type doped well 104 is formed at a deep level using ion implantation and photolithography processes. In a further embodiment, a hard mask is formed by a procedure including: forming an implantation mask layer (such as silicon oxide); and performing a photolithography process and etching to pattern the mask layer with an opening that defines an area for the p-type doped well 104. Ion implantation is performed to introduce a p-type dopant, such as boron, to form the p-type doped well 104.

The n-well 106 and the p-well 108 are similarly formed. However, the implantation depth is less than the p-type doped well 104, so that the n-well 106 and the p-well 108 are formed above the p-type doped well 104. In addition, the n-well 106 and the p-well 108 are defined such that the gap where the p-well 108 surrounds the n-well 106 defines a neutral region 120 that is not doped.

The method 200 includes an operation 204, by forming active regions 112 on a substrate 102, and isolating structures 110 surrounding the active regions 112 to separate the active regions 112 from each other. The substrate 102 is a semiconductor substrate. In some embodiments, the substrate 102 is a silicon substrate or other suitable semiconductor substrate. In some embodiments, the isolation structure 110 is a shallow trench isolation (STI) structure. In various embodiments, the active region 112 includes a planar active region, a fin active region, other suitable active regions (such as an active region with multiple channels stacked vertically, such as a full-all-around gate structure), or a combination thereof. In the disclosed embodiment, the active region includes a planar active region 112P and a fin active region 112F. In some embodiments, the method of forming the STI structure 110 and the active regions 112P and 112F includes: photolithography and etching to pattern the substrate to form the fin active region 112F and the trench; depositing one or more dielectric materials to fill in the trench; and performing chemical mechanical polishing (CMP) to flatten the top surface. The method may further include etching to recess the filled dielectric material to form the STI structure 110. In some embodiments, the etching process recesses the filled dielectric material applied only to the fin active region 112F, such as by a procedure including forming a mask layer covering the planar active region 112P; and etching to recess the dielectric material within the fin active region 112F. In particular, the interface between the planar active region 112P and the fin active region 112F overlaps the gate structure 118 and may be a straight line in top view, as shown in FIG. 6A, or alternatively may be a curved line in top view, such as those shown in FIGS. 6C to 6G.

The method 200 includes an operation 206 by forming a gate structure over the active regions 112F and 112P. The gate structure is formed on the active region and is located above the channel region. The gate structure includes a gate stack and a gate spacer disposed on the sidewalls of the gate stack. In some embodiments, the gate stacks are functional gate stacks each including a gate dielectric layer (such as a high-K dielectric material) and a gate electrode (such as one or more metals). In some embodiments, the gate stacks are dummy gate stacks including polysilicon and are replaced by functional gate stacks at a later stage. Specifically, when forming the gate stacks, the gate material is patterned to have various segments, such as shown in Figures 1A and 1B.

The gate stack 118 includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. In the present embodiment, the gate dielectric layer includes a high-k dielectric material, and the gate electrode includes a metal or a metal alloy. In some examples, the gate dielectric layer and the gate electrode each may include a plurality of sublayers. The high-k dielectric material may include a metal oxide, a metal nitride, such as LaO, AlO, ZrO, TiO, Ta ₂ O ₅ , Y ₂ O ₃ , SrTiO ₃ (STO), BaTiO ₃ (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO ₃ (BST), Al ₂ O ₃ , Si ₃ N ₄ , oxynitride (SiON) or other suitable dielectric materials. The gate electrode may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, Cu, W, Ru, Co or any suitable conductive material. In some embodiments, different metal materials are used for nFET and pFET devices with corresponding work functions to enhance device performance. The gate dielectric layer may also include an interface layer sandwiched between the high-k dielectric material layer and the corresponding fin active region 106. The interface layer may include silicon oxide, silicon nitride, silicon oxynitride and/or other suitable materials. The interface layer is deposited by a suitable method, such as ALD, CVD, ozone oxidation, etc. The high-k dielectric layer is deposited on the interface layer (if the interface layer exists) by a suitable technique, such as ALD, CVD, metal organic CVD (MOCVD), PVD, thermal oxidation, combinations thereof and/or other suitable techniques.

The gate electrode may include a variety of conductive materials. In some embodiments, the gate electrode includes a capping layer, a barrier layer, a work function metal layer, another barrier layer and a filling metal layer. In a further embodiment, the capping layer includes titanium nitride, tantalum nitride or other suitable materials formed by a suitable deposition technique such as ALD. The barrier layer includes titanium nitride, tantalum nitride or other suitable materials formed by a suitable deposition technique such as ALD. The work function metal layer includes a conductive layer of a metal or metal alloy having a suitable work function, so that the corresponding FET is enhanced by its device performance. For the pFET and nFET in the second region, the work function (WF) metal layer is different in composition, and is respectively referred to as a p-type WF metal and an n-type WF metal. In particular, the n-type WF metal is a metal having a first work function, so that the threshold voltage of the relevant nFET is reduced. The n-type WF metal is close to the silicon conduction band energy (Ec) or lower work function, presenting easier electron escape. For example, the n-type WF metal has a work function of about 4.2eV or less. The p-type WF metal is a metal having a second work function, so that the threshold voltage of the relevant pFET is reduced. The p-type WF metal has a work function close to the silicon valence band energy (Ev) or higher, and presents a strong electron binding energy to the nucleus. For example, the p-type work function metal has a WF of about 5.2eV or higher. In some embodiments, the n-type WF metal includes tantalum (Ta). In other embodiments, the n-type WF metal includes titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), or a combination thereof. In other embodiments, the n-metal includes Ta, TiAl, TiAlN, tungsten nitride (WN), or a combination thereof. In some embodiments, the p-type WF metal includes titanium nitride (TiN) or tantalum nitride (TaN). In other embodiments, the p-metal includes TiN, TaN, tungsten nitride (WN), titanium aluminum (TiAl), or a combination thereof. The work function metal is deposited by a suitable technique, such as PVD. The n-type WF metal or the p-type WF metal may include various metal-based films as stacked parts for optimizing device performance and processing compatibility. In various embodiments, the fill metal layer includes aluminum, tungsten, copper, or other suitable metals. The fill metal layer is deposited by a suitable technique, such as PVD or plating. The gate stack is formed by a suitable method, such as a procedure including deposition and patterning using photolithography processes and etching.

The gate spacer may include any suitable dielectric material, such as semiconductor oxide, semiconductor nitride, semiconductor carbide, semiconductor oxynitride, other suitable dielectric materials and/or combinations thereof. The spacer may have multiple films, such as two films (silicon oxide film and silicon nitride film) or three films (silicon oxide film; silicon nitride film; and silicon oxide film). The formation of the spacer may include deposition and anisotropic etching, such as dry etching.

The method 200 includes an operation 208 by forming a source component 114 and a drain component 116 on the active area, such as the source 114 and the common drain 116 shown in Figures 1A and 1B. In some embodiments, the source 114 is formed on the fin active area 112F, and the drain 116 is formed on the planar active area 112P. The source 114 and the drain 116 are formed by any suitable method, such as ion implantation, diffusion, epitaxial growth, or a combination thereof. In the disclosed embodiment, the source 114 and the drain 116 are formed by selective epitaxial growth for strain effects with enhanced carrier mobility and device performance. In some embodiments, the source 114 and the drain 116 are formed by one or more epitaxial (epi) processes, thereby growing Si components, SiGe components, SiC components, and/or other suitable components in a crystalline state on the active area. Optionally, before the epitaxial growth, an etching process is applied to recess the source/drain region. Suitable epitaxial processes include CVD deposition techniques (e.g., vapor phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy, and/or other suitable processes). The epitaxial process may use gaseous and/or liquid precursors that interact with the composition of the substrate. In some embodiments, adjacent source/drain electrodes may be grown to merge together to provide an increased contact area and reduce contact resistance. This may be achieved by controlling the epitaxial growth process.

The source 114 and drain 116 may be doped in situ during the epitaxial process by introducing doping substances, including: p-type dopants, such as boron or _BF2 ; n-type dopants, such as phosphorus or arsenic; and/or other suitable dopants, including combinations thereof. If the source 114 and drain 116 are not doped in situ, an implantation process is performed to introduce the corresponding dopants into the source and drain. In an embodiment, the source 114 and drain 116 in the nFET include SiC or Si doped with phosphorus, while those in the pFET include Ge or SiGe doped with boron. In some other embodiments, the raised source and drain include more than one semiconductor material layer. For example, a silicon germanium layer is epitaxially grown on the substrate in the source/drain region, and a silicon layer is epitaxially grown on the silicon germanium layer. One or more annealing processes may be performed thereafter to activate the source and drain. Suitable annealing processes include rapid thermal annealing (RTA), laser annealing processes, other suitable annealing techniques, or combinations thereof.

The method 200 may include other manufacturing processes 210 implemented before, during, or after the operations described above. For example, the method 200 may include an operation of forming a protective layer on top of the gate stack 108 to protect the gate stack 110 from loss during subsequent processing. The protective layer may include a suitable material different from the dielectric material of the ILD layer to achieve etching selectivity during the etching process of forming the contact opening. In some embodiments, the protective layer includes silicon nitride. In other examples, the method 200 includes forming an interconnect structure on the semiconductor substrate 102 to connect various FETs and other devices into a circuit. The interconnect structure includes contacts, vias, and metal lines formed by suitable processes. In copper interconnects, the conductive components include copper and may also include a barrier layer. The copper interconnect structure is formed by a damascene process. The damascene process includes: depositing an ILD layer; patterning the ILD layer to form a groove; depositing various materials (such as a barrier layer and copper); and performing a CMP process. The damascene process may be a single damascene process or a dual damascene process. The deposition of copper may include PVD to form a seed layer and plating to form a bulk copper on the copper seed layer. Other metals, such as ruthenium, cobalt, tungsten or aluminum, can be used to form an interconnect structure. In some embodiments, before filling the conductive material in the contact hole, silicide can be formed on the source 114 and the drain 116 to further reduce the contact resistance. The silicide includes silicon and a metal, such as titanium silicide, tantalum silicide, nickel silicide or cobalt silicide. The silicide can be formed by a process called self-aligned silicide (or self-aligned polysilicide). The process includes metal deposition, annealing to react the metal with silicon, and etching to remove unreacted metal. In some other embodiments, some other metals, such as ruthenium or cobalt, can be used for contacts and/or through holes.

The disclosed embodiments provide an IC structure having one or more HVFET devices and a method for manufacturing the same. As described above, the IC structure includes various components that enhance the performance of the HVFET device, including the neutral region 120, the hybrid active region, the stepped profile of the STI component 110, the segmented gate structure 118, and various geometries of the interface between the fin active region 112F and the planar active region 112P. Various components are implemented in the disclosed IC structure to achieve enhanced performance, including increased breakdown voltage, reduced leakage current, and increased current in the on state. In addition, the HVFET device of the IC structure can be formed on a planar active region, a fin active region, or formed to have other three-dimensional FET structures, such as a nanostructure with multiple channels stacked vertically, such as a full-ring gate (GAA) structure, or a CFET structure with nFETs and pFETs stacked vertically on each other.

In one exemplary aspect, the disclosed embodiments provide an embodiment of an integrated circuit (IC) structure. The IC structure includes: a semiconductor substrate; an isolation structure formed in the semiconductor substrate to define an active area surrounded by an isolation component; a first well of a first conductivity type formed in the semiconductor substrate; a neutral region formed in the semiconductor substrate and laterally surrounding the first well; a second well of a second conductivity type formed on the semiconductor substrate and laterally surrounding the neutral region, the second conductivity type being opposite to the first conductivity type; a source disposed on the second well of the semiconductor substrate; a drain disposed on the first well of the semiconductor substrate; and a gate structure between the source and the drain. The gate structure engages the first well, the neutral region, and the second well of the semiconductor substrate. The source, the drain, and the gate structure are configured as a first field effect transistor (FET).

In another exemplary aspect, the disclosed embodiments provide an embodiment of an integrated circuit (IC) structure. The IC structure includes: a semiconductor substrate; a shallow trench isolation (STI) component formed in the semiconductor substrate to define an active area surrounded by the STI component; a first well of a first conductivity type, disposed on the semiconductor substrate; a neutral region, disposed on the semiconductor substrate and laterally surrounding the first well; a second well of a second conductivity type, disposed on the semiconductor substrate and laterally surrounding the neutral region, the second conductivity type being opposite to the first conductivity type; and a first field effect transistor (FET) and a second FET, formed on the semiconductor substrate. The first FET includes a first source disposed on the second well, a drain disposed on the first well, and a first gate structure between the first source and the drain. The first gate structure is bonded to the first well, the neutral region, and the second well. The second FET includes a second source disposed on the second well, a drain, and a second gate structure between the second source and the drain. The second gate structure is bonded to the first well, the neutral region, and the second well.

In another exemplary aspect, the disclosed embodiment provides an embodiment of a method for manufacturing a high voltage field effect transistor. The method includes: forming a first well of a first conductivity type in a semiconductor substrate; forming a second well of a second conductivity type on the semiconductor substrate, so that the second well laterally surrounds the first well and is separated from the first well by a neutral region between the first well and the second well, the second conductivity type is opposite to the first conductivity type; forming an active area surrounded by an isolation structure with a non-uniform thickness, wherein the active area includes a planar active area and a fin active area; forming a source in the second well; forming a drain in the first well; and forming a gate structure between the source and the drain, the gate structure being disposed on the first well, the neutral region, and the second well.

Some embodiments of the present application provide an integrated circuit (IC) structure, comprising: a semiconductor substrate; an isolation structure formed in the semiconductor substrate to define an active area surrounded by the isolation component; a first well of a first conductivity type formed in the semiconductor substrate; a neutral region formed in the semiconductor substrate and laterally surrounding the first well; a second well of a second conductivity type formed on the semiconductor substrate and laterally surrounding the neutral region, the second conductivity type being opposite to the first conductivity type; a source disposed on the second well of the semiconductor substrate; a drain disposed on the first well of the semiconductor substrate; and a gate structure interposed between the source and the drain, the gate structure joining the first well, the neutral region and the second well of the semiconductor substrate, wherein the source, the drain and the gate structure are configured as a first field effect transistor (FET).

In some embodiments, the isolation component is a shallow trench isolation (STI) component, the shallow trench isolation (STI) component including a portion formed in the first well and disposed between the source and the drain. In some embodiments, the shallow trench isolation component has a non-uniform structure, the non-uniform structure including a first segment of a first thickness, a second segment of a second thickness, and a transition segment connecting the first segment and the second segment of the shallow trench isolation component; the second thickness is greater than the first thickness; and the transition segment of the shallow trench isolation component has a varying thickness and overlaps with the neutral region in a top view. In some embodiments, the gate structure includes a first segment and a second segment interposed by the portion of the shallow trench isolation component, wherein the first segment of the gate structure is directly disposed on the neutral region and spans between the source and the portion of the shallow trench isolation component in a first direction, the second segment of the gate structure is directly disposed on the first well and spans between the portion of the shallow trench isolation component and the drain, the first segment is configured to be electrically connected to a power signal line, and the second segment of the gate structure is configured to be floating. In some embodiments, the first segment and the second segment of the gate structure are longitudinally oriented along a second direction orthogonal to the first direction; and the first segment of the gate structure partially overlaps the first well and the second well in the top view. In some embodiments, the integrated circuit structure further comprises: a deep well of the second conductivity type, wherein the source and the drain are doped components of the first conductivity type, and the first well and the second well are disposed on the deep well and overlap the deep well in the top view. In some embodiments, the active area comprises a planar active area and a fin active area. In some embodiments, the planar active area and the fin active area comprise an interface having a curve in the top view. In some embodiments, the source is formed on the fin active area; the drain is formed on the planar active area; and the gate structure is formed on the planar active area and the fin active area and overlaps the interface of the planar active area and the fin active area in the top view. In some embodiments, the source has a plurality of portions formed on the fin active area, respectively. In some embodiments, the gate structure is a first gate structure and the source is a first source, wherein the integrated circuit structure further includes: a second source, disposed in the second well of the semiconductor substrate; and a second gate structure, interposed between the second source and the drain, the gate structure joining the first well, the neutral region and the second well of the semiconductor substrate, wherein the second source, the drain and the second gate structure are configured as a second field effect transistor.

Some other embodiments of the present application provide an integrated circuit (IC) structure, comprising: a semiconductor substrate; a shallow trench isolation (STI) component formed in the semiconductor substrate to define an active area surrounded by the shallow trench isolation component; a first well of a first conductivity type, disposed on the semiconductor substrate; a neutral region, disposed on the semiconductor substrate and laterally surrounding the first well; a second well of a second conductivity type, disposed on the semiconductor substrate and laterally surrounding the neutral region, the second conductivity type being opposite to the first conductivity type; and a first field effect transistor (FET) and a second field effect transistor, formed on the semiconductor substrate, wherein the first field effect transistor comprises a first source disposed on the second well, a drain disposed on the first well, and a first gate structure between the first source and the drain, the first gate structure being bonded to the first well, the neutral region, and the second well, and the second field effect transistor comprises a second source disposed on the second well, the drain, and a second gate structure between the second source and the drain, the second gate structure being bonded to the first well, the neutral region, and the second well.

In some embodiments, the shallow trench isolation feature further comprises: a first portion formed in the first well and disposed between the first source and the drain, and a second portion formed in the first well and disposed between the second source and the drain. In some embodiments, the first gate structure comprises a first segment and a second segment sandwiched by the first segment of the shallow trench isolation feature; the second gate structure comprises a third segment and a fourth segment sandwiched by the second segment of the shallow trench isolation feature; the first segment of the first gate structure is directly disposed on the neutral region and spans between the first source and the first segment of the shallow trench isolation feature along a first direction; the second segment of the first gate structure is directly disposed on the first well and spans between the first segment of the shallow trench isolation feature and the drain; the third segment of the second gate structure is directly disposed on the neutral region and spans between the second source and the second segment of the shallow trench isolation feature along the first direction; the fourth segment of the second gate structure is directly disposed on the first well and spans between the second segment of the shallow trench isolation feature and the drain; and the second segment of the first gate structure and the fourth segment of the second gate structure are configured to be floating. In some embodiments, the active region includes a first planar active region, a second planar active region, a third planar active region, a first fin active region, and a second fin active region; the first planar active region spans between the first portion and the second portion of the shallow trench isolation component, and the drain is formed on the first planar active region; the second planar active region spans between the first fin active region and the first portion of the shallow trench isolation component, and contacts the first fin active region with a first curved interface, and the first source is disposed on the first fin active region; and the third planar active region spans between the second fin active region and the second portion of the shallow trench isolation component, and contacts the second fin active region with a second curved interface, and the second source is disposed on the second fin active region. In some embodiments, the shallow trench isolation component includes a first segment of a first thickness, a second segment of a second thickness, and a transition segment connecting the first segment and the second segment of the shallow trench isolation component; the second thickness is greater than the first thickness; and the transition segment of the shallow trench isolation component has a varying thickness and overlaps with the neutral region in a top view.

Some other embodiments of the present application provide a method for manufacturing a high-voltage field effect transistor, comprising: forming a first well of a first conductivity type in a semiconductor substrate; forming a second well of a second conductivity type on the semiconductor substrate, so that the second well laterally surrounds the first well and is separated from the first well by a neutral region between the first well and the second well, the second conductivity type being opposite to the first conductivity type; forming an active area surrounded by an isolation structure having an uneven thickness, wherein the active area includes a planar active area and a fin active area; forming a source in the second well; forming a drain in the first well; and forming a gate structure between the source and the drain, the gate structure being arranged on the first well, the neutral region and the second well.

In some embodiments, forming the active region includes forming the isolation structure in a semiconductor substrate; forming the isolation structure includes forming a shallow trench isolation (STI) component; the shallow trench isolation component includes a first segment of a first thickness, a second segment of a second thickness, and a transition segment connecting the first segment and the second segment of the shallow trench isolation component, the second thickness being greater than the first thickness; and the transition segment of the shallow trench isolation component has a varying thickness and overlaps with the neutral region in a top view. In some embodiments, forming the active region includes forming a first planar active region, a second planar active region, and a fin active region; the source is disposed on the fin active region; the drain is disposed on the first planar active region; and the gate structure is disposed on the second planar active region and the fin active region. In some embodiments, the second planar active region and the fin active region include a curved interface; and the gate structure overlaps with the curved interface of the planar active region and the fin active region in a top view.

The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and/or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims (10)

1. An integrated circuit (IC) structure, comprising: Semiconductor substrate; an isolation structure formed in the semiconductor substrate so as to define an active area surrounded by the isolation feature; A first well of a first conductivity type is formed in the semiconductor substrate; a neutral region formed in the semiconductor substrate and laterally surrounding the first well; a second well of a second conductivity type formed on the semiconductor substrate and laterally surrounding the neutral region, the second conductivity type being opposite to the first conductivity type; A source electrode, disposed on the second well of the semiconductor substrate; a drain electrode disposed on the first well of the semiconductor substrate; and A gate structure is disposed between the source and the drain, the gate structure engaging the first well, the neutral region, and the second well of the semiconductor substrate, wherein the source, the drain, and the gate structure are configured as a first field effect transistor (FET). 2. The integrated circuit structure of claim 1, wherein the isolation feature is a shallow trench isolation (STI) feature, the shallow trench isolation (STI) feature including a portion formed in the first well and disposed between the source and the drain. 3. The integrated circuit structure according to claim 2, wherein: The shallow trench isolation component has a non-uniform structure, and the non-uniform structure includes a first section of a first thickness, a second section of a second thickness, and a transition section connecting the first section and the second section of the shallow trench isolation component; the second thickness is greater than the first thickness; and The transition section of the shallow trench isolation feature has a varying thickness and overlaps the neutral region in a top view. 4. The integrated circuit structure of claim 2, wherein the gate structure comprises a first segment and a second segment sandwiched by the portion of the shallow trench isolation feature, wherein: The first segment of the gate structure is disposed directly on the neutral region and spans between the source and the portion of the shallow trench isolation feature along a first direction, The second section of the gate structure is disposed directly on the first well and spans between the portion of the shallow trench isolation feature and the drain, The first segment is configured to be electrically connected to a power signal line, and The second segment of the gate structure is configured to be floating. 5. The integrated circuit structure according to claim 4, wherein: The first segment and the second segment of the gate structure are longitudinally oriented along a second direction orthogonal to the first direction; and The first segment of the gate structure partially overlaps the first well and the second well in the top view. 6. The integrated circuit structure according to claim 1, further comprising: a deep well of the second conductivity type, wherein: The source and the drain are doped features of the first conductivity type, and The first well and the second well are disposed on the deep well and overlap with the deep well in a top view. 7 . The integrated circuit structure of claim 1 , wherein the active region comprises a planar active region and a fin active region. 8 . The integrated circuit structure of claim 7 , wherein the planar active region and the fin active region include an interface having a curve in a top view. 9. An integrated circuit (IC) structure comprising: Semiconductor substrate; a shallow trench isolation (STI) feature formed in the semiconductor substrate to define an active area surrounded by the shallow trench isolation feature; A first well of a first conductivity type is disposed on the semiconductor substrate; a neutral region disposed on the semiconductor substrate and laterally surrounding the first well; a second well of a second conductivity type disposed on the semiconductor substrate and laterally surrounding the neutral region, the second conductivity type being opposite to the first conductivity type; and A first field effect transistor (FET) and a second field effect transistor are formed on the semiconductor substrate, wherein: The first field effect transistor includes a first source disposed on the second well, a drain disposed on the first well, and a first gate structure between the first source and the drain, the first gate structure being bonded to the first well, the neutral region, and the second well, and The second field effect transistor includes a second source disposed on the second well, the drain, and a second gate structure between the second source and the drain, wherein the second gate structure is bonded to the first well, the neutral region, and the second well. 10. A method for manufacturing a high voltage field effect transistor, comprising: forming a first well of a first conductivity type in a semiconductor substrate; forming a second well of a second conductivity type on the semiconductor substrate so that the second well laterally surrounds the first well and is separated from the first well by a neutral region between the first well and the second well, the second conductivity type being opposite to the first conductivity type; forming an active area surrounded by an isolation structure having a non-uniform thickness, wherein the active area includes a planar active area and a fin active area; forming a source in the second well; forming a drain in the first well; and A gate structure is formed between the source and the drain, and the gate structure is disposed on the first well, the neutral region, and the second well.