CN118116893A - Semiconductor packaging structure and forming method thereof - Google Patents

Abstract

A semiconductor package structure and a method for forming the same are provided. The semiconductor package structure includes a semiconductor substrate, a conductive pad on the semiconductor substrate, and a passivation layer on the semiconductor substrate and the conductive pad. The passivation layer exposes a portion of the top surface of the conductive pad. The semiconductor package structure also includes: a conductive adhesive layer on the conductive pad, and a dielectric layer on the passivation layer and the conductive adhesive layer. The dielectric layer exposes a portion of the conductive adhesive layer. The semiconductor package structure also includes: a redistribution layer RDL structure on the dielectric layer and electrically connected to the conductive pad through the conductive adhesive layer. The semiconductor package structure also includes: a bump structure on the RDL structure.

Description

Semiconductor packaging structure and method for forming the same

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on and claims priority to U.S. Provisional Application No. 63/385,441 filed on November 30, 2022, the entire contents of which are incorporated herein by reference.

Technical Field

The present invention relates to a semiconductor package structure and a method for forming the same, and more particularly, to a semiconductor package structure having improved adhesion between components and a method for forming the same.

Background technique

Integrated circuit (IC) devices are manufactured in semiconductor wafers and separated into individual chips. Afterwards, these chips are assembled into packages for use in electronic products. Semiconductor packaging provides a structure to support the chip and protect the chip from environmental influences. The semiconductor package also provides electrical connections to the chip.

Although existing semiconductor packages have been adequate for their intended purposes, they are not completely satisfactory in all aspects. For example, when an external circuit such as a printed circuit board (PCB) is bonded to a semiconductor package structure, bonding stress through solder balls to the bottom of a metal layer (such as a Cu redistribution layer) in direct contact with a conductive pad can cause delamination between the metal layer and the conductive pad. Therefore, there are still some problems to be overcome with respect to semiconductor package structures in the field of semiconductor integrated circuit technology.

Summary of the invention

Some embodiments of the present invention provide a semiconductor packaging structure. An exemplary embodiment of a semiconductor packaging structure includes a semiconductor substrate, a conductive pad on the semiconductor substrate, and a passivation layer on the semiconductor substrate and the conductive pad. The passivation layer exposes a portion of the top surface of the conductive pad. The semiconductor packaging structure also includes: a conductive adhesive layer on the conductive pad, and a dielectric layer on the passivation layer and the conductive adhesive layer. The dielectric layer exposes a portion of the conductive adhesive layer. The semiconductor packaging structure also includes: a redistribution layer (RDL) structure, which is on the dielectric layer and electrically connected to the conductive pad through the conductive adhesive layer. The semiconductor packaging structure also includes: a bump structure on the redistribution layer (RDL) structure.

Some embodiments of the present invention provide a method for forming a semiconductor package structure. First, a semiconductor substrate is provided. A conductive pad is formed on the semiconductor substrate, and a passivation layer is formed on the semiconductor substrate and the conductive pad. The passivation layer exposes a portion of the top surface of the conductive pad. The method for forming a semiconductor package also includes: forming a conductive adhesive layer on the conductive pad. The method for forming a semiconductor package also includes: forming a dielectric layer on the passivation layer and the conductive adhesive layer, wherein the dielectric layer exposes a portion of the top surface of the conductive adhesive layer. The method for forming a semiconductor package also includes forming a redistribution layer (RDL) structure on the dielectric layer, and the redistribution layer (RDL) structure is electrically connected to the conductive pad through the conductive adhesive layer. The method for forming a semiconductor package also includes: forming a bump structure above the redistribution layer (RDL) structure.

The embodiments are described in detail below with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention may be more fully understood by reading the following detailed description and examples with reference to the accompanying drawings, in which:

1A , 1B, 1C, 1D, 1E, 1F, 1G, 1H, and 1I are cross-sectional views of intermediate stages of a method of forming a semiconductor package structure according to some embodiments of the present invention.

FIG. 2 is a cross-sectional view of an intermediate stage of a semiconductor package structure according to some embodiments of the present invention.

3A , 3B, 3C, 3D, and 3E are cross-sectional views of intermediate stages of a method of forming a semiconductor package structure according to some embodiments of the present invention.

Detailed ways

The following description is the best mode for implementing the present invention. The purpose of this description is to illustrate the general principles of the present invention and should not be construed as limiting. The scope of the present invention is determined by the appended claims.

The inventive concept will be described in full with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are shown. From the exemplary embodiments that will be described in more detail below with reference to the accompanying drawings, the advantages and features of the inventive concept and the methods for implementing them will become apparent. However, it should be noted that the inventive concept is not limited to the following exemplary embodiments and can be implemented in various forms. Therefore, exemplary embodiments are provided only to disclose the inventive concept and to let those skilled in the art know the scope of the inventive concept. Moreover, the illustrated drawings are only schematic and non-restrictive. In the accompanying drawings, for the purpose of illustration, the sizes of some elements may be exaggerated rather than drawn to scale. In the practice of the present invention, the sizes and relative sizes do not correspond to the actual sizes.

The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, the singular terms "one", "a kind of" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. Similarly, it should be understood that when an element such as a layer, a region or a substrate is referred to as being "on" another element, it can be directly on another element, or there can be an intermediate element. On the contrary, the term "directly" means that there is no intermediate element. It should be understood that the terms "include", "comprise", "include" and/or "include" specify the existence of stated features, characteristics, steps, operations, elements and/or parts when used in this article, but do not exclude the existence or addition of one or more other features, characteristics, steps, operations, elements, components and/or their groups.

In addition, for ease of description, spatially relative terms can be used here to describe the relationship between an element or feature and another element or feature, as shown in the figure. In addition to the orientation shown in the figure, spatially relative terms are intended to include different orientations of the device in use or operation. It should be understood that although the terms first, second, third, etc. can be used to describe various elements here, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present invention, the first element in some embodiments can be referred to as the second element in other embodiments. Explanatory embodiments of various aspects of the inventive concept explained and shown here include their complementary counterparts. Throughout the specification, the same or similar reference numerals or reference numbers represent the same or similar elements.

Some embodiments of the present disclosure are described. It should be noted that additional processes may be provided before, during, and/or after the stages described in these embodiments. Some of the stages described may be replaced or eliminated for different embodiments. Additional features may be added to the semiconductor package. Some of the features described below may be replaced or eliminated for different embodiments. Although some embodiments discuss processes performed in a specific order, these processes may be performed in another logical order.

According to some embodiments of the present invention, a semiconductor package structure and a method for forming the same are described below to improve adhesion between components. In some embodiments, a conductive adhesive layer is formed between a conductive pad on a semiconductor substrate and a metal layer such as a redistribution layer (RDL). By adding a conductive adhesive layer between the conductive pad and the metal layer, the contact area between the conductive pad and the metal layer can be expanded. According to an embodiment, the adhesion between the conductive pad and the conductive adhesive layer is stronger than the adhesion between the conductive pad and the metal layer, thereby preventing delamination between the conductive pad and the metal layer.

The following provides one of the multiple methods of forming a semiconductor package structure according to some embodiments of the present invention. It should be noted that the present disclosure is not limited to the exemplary package structures and formation methods provided herein. Those structures and processes described below are only used to provide examples of configuration and manufacture of semiconductor packages.

1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H and 1I are cross-sectional views of intermediate stages of a method of forming a semiconductor package structure according to some embodiments of the present invention. To simplify the figure, only a portion of the semiconductor package structure is depicted in FIG. 1A to FIG. 1I.

1A, a semiconductor substrate 100 is provided. In some embodiments, the semiconductor substrate 100 is a substrate of a semiconductor die. The semiconductor substrate 100 may include a plurality of chip regions A1 and a scribe line region A2 surrounding the chip regions A1 and separating adjacent chip regions A1 from each other. In order to simplify the figure, only two adjacent chip regions A1 and the scribe line region A2 separating these chip regions A1 are depicted as an example.

Semiconductor substrate 100 may be a silicon substrate or another semiconductor substrate. In some embodiments, semiconductor substrate 100 is a silicon wafer to facilitate wafer-level packaging processing. Chip region A1 corresponds to a portion of the wafer after the wafer is cut along scribe lines in scribe line region A2 in subsequent processing.

In some embodiments, circuits (not shown) and device elements (not shown) may be formed within the semiconductor substrate 100, and the circuits may be any type of circuit suitable for a particular application. For example, the circuits and device elements may include one or more N-type metal oxide semiconductor (NMOS) devices and/or one or more P-type metal oxide semiconductor (PMOS) devices, such as transistors, capacitors, resistors, diodes, photodiodes, fuses, etc., which are interconnected to implement one or more functions. Various structures including memory structures, processing structures, sensors, amplifiers, power distribution, input/output circuits, etc. may be used to implement these functions. For a given application, other circuits and device elements may be used appropriately. Various processes are performed to form circuits and device elements, such as deposition, etching, implantation, lithography, annealing, and/or other applicable processes. In some embodiments, circuits and device elements are formed in the semiconductor substrate 100 in the front-end (FEOL).

In addition, the semiconductor substrate 100 has a first surface 100 a and a second surface 100 b opposite to the first surface 100 a. An interconnection structure is formed on the first surface 100 a, and the first surface 100 a may be referred to as an active surface of the semiconductor substrate 100.

In some embodiments, in each chip region A1, a plurality of conductive pads 103 are formed on the semiconductor substrate 100, for example, on the first surface 100a of the semiconductor substrate 100. The conductive pads 103 may be formed above an intermetallic dielectric (IMD) layer (not shown) in the semiconductor substrate 100. The conductive pads 103 are electrically connected to the device elements through various metal lines and vias in the IMD layer. In order to simplify the figure, only one conductive pad 103 in each chip region A1 is shown in the accompanying drawings.

In some embodiments, the conductive pad 103 is configured to be electrically coupled to a bump (e.g., the bump structure 140 in FIG. 1I ) through a conductive trace (e.g., the redistribution layer (RDL) structure 117 in FIG. 1E ) to the conductive pad 103 , such that a circuit inside the semiconductor substrate 100 is connected to a circuit outside the semiconductor substrate 100 through the conductive trace from the conductive pad 103 to the bump.

In some embodiments, the conductive pad 103 may be made of gold (Au), silver (Ag), copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), palladium (Pd) and/or alloys thereof. In some embodiments, the conductive pad 103 is formed by plating or other suitable methods.

In addition, according to some embodiments of the present disclosure, a passivation layer 105 is formed on the semiconductor substrate 100 and the conductive pads 103. The passivation layer 105 partially covers the conductive pads 103. As shown in FIG. 1A , the passivation layer 105 exposes a portion of the top surface 103a of each conductive pad 103. The conductive pads 103 and the passivation layer 105 are formed in a back-end-of-line (BEOL) process.

In some embodiments, the passivation layer 105 is configured to provide electrical insulation and moisture-proof protection for the semiconductor substrate 100, so that the semiconductor substrate 100 is isolated from the surrounding environment. Therefore, the passivation layer 105 can be referred to as a protective insulating layer.

In some embodiments, the passivation layer 105 is made of an inorganic material, such as spin-on glass (SOG), silicon oxide ( _SiOx ), silicon nitride ( _SiNx ), silicon oxynitride (SiON), silicon nitride (SiN) or a combination thereof, or other suitable insulating materials. In some embodiments, the passivation layer 105 can be formed by using vapor deposition, spin coating, or other suitable processes.

In addition, in this exemplary embodiment, the passivation layer 105 includes: openings on the conductive pads 103, such as first openings 106, to expose the conductive pads 103, so as to electrically connect the conductive pads 103 to a circuit outside the semiconductor substrate 100 through a conductive trace. Specifically, as shown in FIG. 1A , each first opening 106 exposes a portion of the top surface 103a of the conductive pad 103.

In some embodiments, each first opening 106 has a virtual center line C1 that divides the first opening 106 into two equal lateral distances along the first direction D1. The center line C1 extends along the second direction D2. The second direction D2 is different from the first direction D1, for example, perpendicular to the first direction D1. In some embodiments, the center line C1 of the first opening 106 can be aligned with the center line (not shown) of the conductive pad 103 below. However, the present disclosure is not limited thereto. In some other embodiments, the first opening 106 can be slightly offset from the conductive pad 103 below.

Furthermore, in some embodiments, the first opening 106 has a first width W1 in the first direction D1. A sufficient width W1 of the first opening 106 increases the contact area between the conductive pad 103 and the conductive adhesive layer 110 (FIG. 1C).

According to some embodiments of the present invention, before a dielectric layer is deposited over the passivation layer 105 and the conductive pad 103, a conductive adhesive layer 110 (FIG. 1C) is formed on the conductive pad 103. The formation of the conductive adhesive layer 110 solves the problem of poor adhesion between the conductive pad 103 and a subsequently formed conductive portion (e.g., a redistribution layer (RDL)). Therefore, during a packaging process and/or a bonding process (e.g., bonding a semiconductor packaging structure to a printed circuit board (PCB)), the conductive adhesive layer 110 prevents delamination between the conductive pad and the conductive portion on the conductive pad.

The conductive adhesive layer 110 may be a single layer structure or a multi-layer structure. In this exemplary embodiment, a conductive adhesive layer including two adhesive films is depicted for illustration. However, the present disclosure is not limited thereto.

1B , in some embodiments, a first adhesive film material 1110 is conformally formed on the passivation layer 105 and the exposed portion of the conductive pad 103. Specifically, the first adhesive film material 1110 covers the passivation layer 105 and the exposed portion of the top surface 103a of the conductive pad 103. In addition, in the first opening 106, the first adhesive film material 1110 deposited on the conductive pad 103 is formed as a liner in the first opening 106 of the passivation layer 105.

Next, in some embodiments, the second adhesive film material 1120 is conformally formed on the first adhesive film material 1110. Specifically, the second adhesive film material 1120 covers the first adhesive film material 1110. The second adhesive film material 1120 is separated from the conductive pad 103 by the first adhesive film material 1110.

The first adhesive film material 1110 and the second adhesive film material 1120 include different conductive materials. In some embodiments, the first adhesive film material 1110 and the second adhesive film material 1120 include copper, titanium, tantalum, titanium nitride, tantalum nitride, etc. or a combination thereof. In an exemplary embodiment, the first adhesive film material 1110 is a titanium-based layer, and the second adhesive film material 1120 is a copper-based layer.

Furthermore, in some embodiments, the first adhesive film material 1110 and the second adhesive film material 1120 are deposited by atomic layer deposition (ALD), sputtering, another physical vapor deposition (PVD) process, etc. In one exemplary embodiment, the first adhesive film material 1110 and the second adhesive film material 1120 are formed by sputtering, thereby obtaining the first adhesive film material 1110 and the second adhesive film material 1120 at a high density.

Furthermore, in some embodiments, the first adhesive film material 1110 and the second adhesive film material 1120 are thin films. Therefore, according to some embodiments of the present disclosure, the profile and form of the material layer (e.g., the first dielectric layer 115 in FIG. 1D ) laminated on the conductive adhesive layer (formed by patterning the first adhesive film material 1110 and the second adhesive film material 1120) will not be substantially changed.

In some embodiments, the thickness of the first adhesive film material 1110 is about 5nm to about 200nm. In some other embodiments, the thickness of the first adhesive film material 1110 is about 10nm to about 100nm. In some embodiments, the thickness of the second adhesive film material 1120 is about 5nm to about 500nm. In some other embodiments, the thickness of the second adhesive film material 1120 is about 20nm to about 200nm. In some embodiments, the total thickness of the first adhesive film material 1110 and the second adhesive film material 1120 is about 10nm to about 700nm. In some embodiments, the total thickness of the first adhesive film material 1110 and the second adhesive film material 1120 is about 30nm to about 300nm. It should be noted that the thickness of the first adhesive film material 1110 and the second adhesive film material 1120 of the present disclosure is not limited to the above exemplary values. The actual values of the thickness of the first adhesive film material 1110 and the second adhesive film material 1120 can be modified and determined according to the design conditions of the actual application.

Next, referring to FIG. 1C , in some embodiments, the second adhesive film material 1120 and the first adhesive film material 1110 are patterned to form a second adhesive film 112 and a first adhesive film 111 , respectively.

In some embodiments, photolithography and etching processes are performed to pattern the second adhesive film material 1120 and the first adhesive film material 1110, thereby removing a portion of the second adhesive film material 1120 and a portion of the first adhesive film material 1110. The remaining portion of the second adhesive film material 1120 is referred to as a second adhesive film 112. The remaining portion of the first adhesive film material 1110 is referred to as a first adhesive film 111. In this exemplary embodiment, the second adhesive film 112 and the first adhesive film 111 are collectively referred to as a conductive adhesive layer 110. The conductive adhesive layer 110 is formed on the conductive pad 103.

1C , in some embodiments, the conductive adhesive layer 110 is in direct contact with the exposed portion of the top surface 103 a of the conductive pad 103 . The conductive adhesive layer 110 is configured as a liner in the first opening 106 of the passivation layer 105 .

In addition, the conductive adhesive layer 110 has a symmetry line C2 in the second direction D2. In some embodiments, the symmetry line C2 may be aligned with a center line C1 of the first opening 106. However, the present disclosure is not limited thereto.

Specifically, in some embodiments, the conductive adhesive layer 110 includes a wing portion 1101, a sidewall portion 1102, and a bottom portion 1103. The portion of the conductive adhesive layer 110 extending to the top surface 1050a of the protrusion 1050 of the passivation layer 105 may be referred to as the wing portion 1101. The wing portion 1101 is physically separated from the conductive pad 103 by the sidewall portion 1102 and the bottom portion 1103. The portion of the conductive adhesive layer 110 extending along the sidewall of the first opening 106 of the passivation layer 105 may be referred to as the sidewall portion 1102. The portion of the conductive adhesive layer 110 formed to directly contact with and cover the top surface 103a of the conductive pad 103 may be referred to as the bottom portion 1103.

In addition, in some embodiments, the lateral dimension (in the first direction D1) of the conductive adhesive layer 110 corresponds to the lateral dimension (in the first direction D1) of the conductive pad 103. For example, the side edge of the wing 1101 of the conductive adhesive layer 110 may be aligned with the side edge 103s of the conductive pad 103 or slightly protrude from the side edge 103s of the conductive pad 103. It is not necessary to form a conductive adhesive layer 110 having a much larger width (in the first direction D1) than the conductive pad 103. However, the present disclosure is not limited thereto. It should be noted that in some embodiments, an exemplary conductive adhesive layer 110 as shown in FIG. 1C is provided for illustrative purposes, and embodiments of the present invention are not limited thereto.

1D , according to some embodiments of the present disclosure, a first dielectric layer 115 is formed on the passivation layer 105 and the conductive adhesive layer 110. The first dielectric layer 115 exposes a portion of the top surface 110a of the conductive adhesive layer 110. Specifically, the first dielectric layer 115 exposes a portion of the top surface 112a of the second adhesive film 112.

In some embodiments, the first dielectric layer 115 and the conductive adhesive layer 110 include different materials. The first dielectric layer 115 is an organic layer, such as a polymer layer. In some embodiments, the first dielectric layer 115 includes polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), epoxy resin, photosensitive material, other suitable polymer materials, or combinations thereof.

In some embodiments, the dielectric material layer may be deposited by a spin coating process, a lamination process, other suitable processes, or a combination thereof. The dielectric material layer is then patterned by photolithography and etching processes to remove portions of the dielectric material layer. For example, a photoresist layer (not shown) may be deposited on the dielectric material layer. Photolithography may be used to pattern the photoresist layer (not shown) to create a mask on the dielectric material layer. The dielectric material layer may be etched to expose portions of the conductive pads 103 below. The remaining portion of the dielectric material layer is referred to as the first dielectric layer 115.

Furthermore, in this exemplary embodiment, the first dielectric layer 115 includes an opening, such as the second opening 116 , to expose the conductive adhesive layer 110 on the conductive pad 103 and thus to electrically connect the conductive pad 103 to a circuit outside the semiconductor substrate 100 through a conductive trace.

In some embodiments, as shown in FIG. 1D , the first opening 106 is larger than the second opening 116. Each second opening 116 is located within the first opening 106 to expose a smaller portion of the top surface 103a of the conductive pad 103. Specifically, in some embodiments, the first opening 106 has a first width W1 in the first direction D1, and the second opening 116 has a second width W2 in the first direction D1. The second width W2 is smaller than the first width W1.

In some embodiments, each second opening 116 has a virtual center line C3 that divides the second opening 116 into two equal lateral distances in the first direction D1. The center line C3 extends along the second direction D2. In some embodiments, the center line C3 of the second opening 116 can be substantially aligned with the center line C1 of the first opening 106. However, the present disclosure is not limited thereto. In some other embodiments, the second opening 116 can be slightly offset from the first opening 106.

Furthermore, in some embodiments, after forming the first dielectric layer 115 having the second opening 116, at least a portion of the conductive adhesive layer 110 is disposed between the first dielectric layer 115 and the passivation layer 105. For example, as shown in FIG. 1D , the wing portion 1101 of the conductive adhesive layer 110 is sandwiched between the first dielectric layer 115 and the passivation layer 105. Therefore, the second opening 116 of the first dielectric layer 115 does not expose the wing portion 1101 of the conductive adhesive layer 110.

In addition, in some embodiments, after forming the first dielectric layer 115, the sidewall portion 1102 of the conductive adhesive layer 110 is completely covered by the first dielectric layer 115. For example, as shown in FIG1D , the sidewall portion 1102 of the conductive adhesive layer 110 is disposed between the first dielectric layer 115 and the passivation layer 105. That is, according to some embodiments of the present disclosure, the second opening 116 of the first dielectric layer 115 does not expose the sidewall portion 1102 of the conductive adhesive layer 110.

Compared to the first dielectric layer 115, the first adhesive film 111 and the second adhesive film 112 are relatively thin, so that the first dielectric layer 115 laminated on the passivation layer 105 and the conductive adhesive layer 110 has a substantially flat top surface 115a, as shown in FIG. 1D. Specifically, in this exemplary embodiment, the portion of the top surface 115a of the first dielectric layer 115 located directly above the wing portion 1101 of the conductive adhesive layer 110 is still flat. Therefore, according to some embodiments of the present invention, although the conductive adhesive layer 110 is formed on the conductive pad 103 before the first dielectric layer 115 is formed on the conductive pad 103, the profile and form of the material layers laminated on the conductive adhesive layer 110 (such as the first dielectric layer 115 and other material layers formed subsequently) will not be significantly changed.

1E, in some embodiments, a redistribution layer (RDL) structure 117 is formed on the first dielectric layer 115. The redistribution layer (RDL) structure 107 is in direct contact with the exposed top surface 110a of the conductive adhesive layer 110. The redistribution layer (RDL) structure 117 is electrically connected to the conductive pad 103 through the conductive adhesive layer 110. The redistribution layer (RDL) structure 117 reroutes the path of the circuit from the conductive pad 103 to the circuit outside the semiconductor substrate 100.

The RDL structure 117 may be a single layer structure or a multi-layer structure. In some embodiments, the RDL structure 117 includes a conductive material such as gold, silver, copper, nickel, tungsten, aluminum, and/or alloys thereof.

1D and 1G , in this exemplary embodiment, the first width W1 of the first opening 106 is greater than the second width W2 of the second opening 116, as described above. Therefore, after forming the redistribution layer (RDL) structure 117, the contact area between the conductive adhesive layer 110 and the conductive pad 103 is greater than the contact area between the redistribution layer (RDL) structure 117 and the conductive adhesive layer 110.

In some embodiments, the redistribution layer (RDL) structure 117 includes a pillar portion 118 (extending along the second direction D2) and a main portion 119 (extending along the first direction D1). The pillar portion 118 is disposed in the second opening 116. For example, each pillar portion 118 completely fills the second opening 116, and the bottom surface 118b of the pillar portion 118 of the redistribution layer (RDL) structure 117 is in direct contact with the top surface 110a of the conductive adhesive layer 110, as shown in FIG. 1E.

Furthermore, in some embodiments, the sidewalls 118s and the bottom surface 118b of each pillar portion 118 of the redistribution layer (RDL) structure 117 are in contact with different material layers. For example, the bottom surface 118b of each pillar portion 118 is in contact with the conductive adhesive layer 110, and the sidewalls 118s of the pillar portion 118 are in contact with the first dielectric layer 115, as shown in FIG. 1E.

In addition, each column portion 118 of the redistribution layer (RDL) structure 117 has a symmetry line C4 in the second direction D2. In some embodiments, the symmetry line C4 of the column portion 118 is substantially aligned with the symmetry line C2 of the conductive adhesive layer 110 below. In other words, the lateral distances (in the first direction D1) between the sidewall portion 1102 of the conductive adhesive layer 110 and the sidewall 118s of the column portion 118 are substantially equal to each other. That is, the each column portion 118 of the redistribution layer (RDL) structure 117 does not deviate from the conductive adhesive layer 110 below. However, the present disclosure is not limited to this. In some other embodiments, the each column portion 118 of the redistribution layer (RDL) structure 117 may deviate slightly from the conductive adhesive layer 110 below. That is, the symmetry line C4 deviates from the symmetry line C2.

According to an embodiment of the present disclosure, by forming a conductive adhesive layer 110 between the conductive pad 103 and the pillar portion 118 of the redistribution layer (RDL) structure 117, the adhesion between the conductive pad 103 and the redistribution layer (RDL) structure 117 can be effectively improved. That is, the adhesion between the conductive pad 103 and the conductive adhesive layer 110 (for example, the first adhesive film 111) is stronger than the adhesion between the conductive pad 103 and the redistribution layer (RDL) structure 117.

In one example, the conductive pad 103 is an aluminum pad, and the redistribution layer (RDL) structure 117 includes copper traces and vias. In a conventional packaging structure, delamination easily occurs at the interface between the copper RDL structure 117 and the aluminum conductive pad 103 during a packaging process and/or a bonding process (e.g., bonding the semiconductor packaging structure to a printed circuit board (PCB)). In some embodiments, a conductive adhesive layer 110 including a titanium film and a copper film (which may be expressed as a "Ti/Cu film") is provided between the aluminum conductive pad 103 and the copper RDL structure 117. The bonding between the aluminum conductive pad 103 and the Ti/Cu conductive adhesive layer 110 is stronger than the bonding between the aluminum conductive pad 103 and the copper RDL structure 117. Therefore, in some embodiments, the redistribution layer (RDL) structure 117 can be well attached to the conductive adhesive layer 110, thereby preventing conventional delamination between the conductive pad 103 and the RDL structure 117.

In some embodiments, after forming the redistribution layer (RDL) structure 117, the chip regions A1 are separated from each other by cutting the scribe line region A2 to form a semiconductor die 10a having the redistribution layer (RDL) structure 117 thereon. The formed semiconductor die may be a system on chip (SOC) integrated circuit die. The SOC integrated circuit die (for example) may include a logic die including a central processing unit (CPU), a graphics processing unit (GPU), a dynamic random access memory (DRAM) controller, or any combination thereof.

In some embodiments, the semiconductor die 10a includes a semiconductor substrate 100, at least one conductive pad 103 on the semiconductor substrate 100, a passivation layer 105 on the semiconductor substrate 100 and exposing a portion of the conductive pad 103, a conductive adhesive layer 110 on the conductive pad 103, a first dielectric layer 115 on the passivation layer 105 and exposing a portion of the conductive adhesive layer 110, and a redistribution layer (RDL) structure 117 on the semiconductor substrate 100.

Next, according to some embodiments of the present invention, semiconductor die 10a may be mounted on another substrate (eg, a carrier substrate) using a pick-and-place process.

1F, in some embodiments, the semiconductor die 10a is mounted on a carrier substrate 200 using an adhesive layer 201. To simplify the figure, only two semiconductor dies 10a mounted on the carrier substrate 200 are shown in the drawing.

The carrier substrate 200 may be made of silicon, glass, ceramic or other suitable materials. The carrier substrate 200 may be a semiconductor wafer, and thus the carrier substrate 200 is sometimes referred to as a carrier wafer. The adhesive layer 201 may be a light-to-heat conversion (LTHC) material layer or include other suitable materials.

Next, in some embodiments, as shown in FIG. 1F , a protective material layer 1200 is formed over the carrier substrate 200 to cover the semiconductor die 10a. Specifically, the protective material layer 1200 surrounds the semiconductor substrate 100, the passivation layer 105, the first dielectric layer 115, and the redistribution layer (RDL) structure 117 that is in direct contact with the conductive adhesive layer 110. Therefore, the semiconductor die 10a is encapsulated by the protective material layer 1200. In some embodiments, the protective material layer 1200 can protect the semiconductor die 10a from environmental influences, thereby preventing the semiconductor die 10a in the subsequently formed semiconductor package structure from being damaged due to stress, chemicals, and moisture.

In some embodiments, the protective material layer 1200 may be a molding compound, which may include a substrate and filler particles in the substrate. The substrate may include a polymer, a resin, an epoxy resin, etc. The substrate may be a carbon-based polymer or an acrylic-based polymer. The filler particles may be particles of a dielectric material such as SiO ₂ , Al ₂ O ₃ , silicon dioxide, iron (Fe) compounds, sodium (Na) compounds, etc., and may have a spherical shape. In some embodiments, the protective material layer 1200 may be formed by a molding process, such as compression molding, transfer molding, or other suitable molding methods.

In one example, the protective material layer 1200 (e.g., epoxy or resin) can be applied while being substantially liquid and can then be cured by a chemical reaction. In addition, the protective material layer 1200 can be a thermally curable polymer or an ultraviolet (UV) curable polymer. The protective material layer 1200 can be applied as a gel or a tough solid that can be formed around the semiconductor die 10a and can then be cured by a thermal curing process or a UV curing process. The protective material layer 1200 can be cured with a mold (not shown).

1G, in some embodiments, after forming the protective material layer 1200, the semiconductor die 10a encapsulated by the protective material layer 1200 is desorbed from the carrier substrate 200. The carrier substrate 200 and the adhesive layer 201 are removed. The second surface 100b of the semiconductor substrate 100 is exposed.

In some embodiments, in the case where the adhesive layer 201 is made of LTHC material, a desorption process is performed by exposing the adhesive layer 201 (shown in FIG. 1F) using laser or UV light. The LTHC material can be decomposed due to the heat generated by the laser or UV light, and thus the carrier substrate 200 is removed from the semiconductor die 10a. Therefore, the second surface 100b of the semiconductor substrate 100 can be exposed from the protective material layer 1200, as shown in FIG. 1G.

In some embodiments, after the carrier substrate 200 is removed by the desorption process, a planarization process such as a chemical mechanical polishing/grinding (CMP) process or a mechanical grinding process is performed on the top surface 1200a of the protective material layer 1200 until the redistribution layer (RDL) structure 117 is exposed from the protective material layer 1200. In one example, the top surface 1200a of the protective material layer 1200 may be ground by a chemical mechanical polishing (CMP) process or other suitable grinding processes.

After the planarization process, the remaining portion of the protective material layer 1200 may be referred to as a mold layer 120, as shown in FIG1G. In some embodiments, the mold layer surrounds the semiconductor substrate 100, the passivation layer 105, the conductive adhesive layer 110, the first dielectric layer 115, and the redistribution layer (RDL) structure 117.

Furthermore, in some embodiments, after performing a planarization process, the mold layer 120 has a flat top surface 120a and a flat bottom surface 120b opposite to the top surface 120a. The top surface 120a of the mold layer 120 is coplanar with a top surface 117a of a redistribution layer (RDL) structure 117. After the carrier substrate 200 is desorbed from the semiconductor die 10a, the bottom surface 120b of the mold layer 120 is coplanar with the second surface 100b of the semiconductor substrate 100.

1H , in some embodiments, according to some embodiments of the present disclosure, a second dielectric layer 125 is formed on a redistribution layer (RDL) structure 117. The second dielectric layer 125 exposes a portion of a top surface 117a of the redistribution layer (RDL) structure. Specifically, the second dielectric layer 125 exposes a portion of a top surface 119a of a main portion 119 of the second dielectric layer 125 (which extends in the first direction D1).

The second dielectric layer 125 and the first dielectric layer 115 can be made of the same material or different materials. In some embodiments, the second dielectric layer 125 is an organic layer, such as a polymer layer. In some embodiments, the second dielectric layer 125 includes polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), epoxy resin, photosensitive material, other suitable polymer materials or combinations thereof.

In some embodiments, the dielectric material layer may be deposited by a spin coating process, a lamination process, other suitable processes, or a combination thereof. The dielectric material layer is then patterned by photolithography and etching processes to remove portions of the dielectric material layer. For example, a photoresist layer (not shown) may be deposited on the dielectric material layer. Photolithography may be used to pattern the photoresist layer (not shown) to produce a mask on the dielectric material layer. The dielectric material layer may be etched to expose portions of the underlying redistribution layer (RDL) structure 117. The remaining portion of the dielectric material layer is referred to as a second dielectric layer 125.

Furthermore, in some embodiments, the second dielectric layer 125 includes an opening, such as a third opening 126, to expose the redistribution layer (RDL) structure 117, and thus is used to electrically connect the conductive pad 103 with a circuit external to the semiconductor substrate 100. In this exemplary embodiment, the circuit external to the semiconductor substrate 100 (e.g., a PCB) is electrically connected to the conductive pad 103 through the bump structure 140 ( FIG. 1I ), the redistribution layer (RDL) structure 117, and the conductive adhesive layer 110 on the conductive pad 103.

In addition, in some embodiments, the third opening 126 of the second dielectric layer 125 is laterally offset from the conductive adhesive layer 110, as shown in FIG. 1H. However, the present disclosure is not limited thereto. In some other embodiments, the third opening 126 of the second dielectric layer 125 may be substantially aligned with the conductive adhesive layer 110.

Furthermore, in some embodiments, the third opening 126 of the second dielectric layer 125 is larger than the second opening 116 of the first dielectric layer 115 (FIG. 1D) that receives the pillar 118 of the redistribution layer (RDL) structure 117. In some embodiments, the third opening 126 of the second dielectric layer 125 is larger than the first opening 106 of the passivation layer 105 (FIG. 1A) in which the conductive adhesive layer 110 is formed. However, the sizes and positions of the third opening 126, the second opening 116, and the first opening 106 may be appropriately adjusted and arranged according to actual needs of the application.

1I, in some embodiments, after forming a second dielectric layer 125 having a third opening 126 on the semiconductor substrate 100, a bump structure 140 is formed on an exposed portion of a top surface 117a of a redistribution layer (RDL) structure 117. In some embodiments, the bump structure 140 may include an under bump metallization (UBM) layer 141 and a solder portion 142. It should be noted that the configuration of the bump structure 140 illustrated in FIG. 1I is provided for example, and the present invention is not limited thereto.

In some embodiments, an under bump metallization (UBM) layer 141 is formed on an exposed portion of a top surface 117a of a redistribution layer (RDL) structure 117, and a solder portion 142 is formed on the UBM layer 141. The solder portion 142 and the UBM layer 141 are collectively referred to as a bump structure 140. The bump structure 140 is electrically connected to the semiconductor substrate 100 through the redistribution layer (RDL) structure 117, the conductive adhesive layer 110, and the conductive pad 103.

In some embodiments, the UBM layer 141 provides a solderable surface that is exposed to receive a solder portion 142 (e.g., a solder bump or other suitable conductive portion). The UBM layer 141 is electrically connected to the conductive pad 103 through the redistribution layer (RDL) structure 117 and the conductive adhesive layer 110. In one example, the UBM layer 141 has a flat bottom surface 141b, and the conductive adhesive layer 110 has a flat bottom surface 110b. As shown in FIG. 1I, the interface between the UBM layer 141 and the redistribution layer (RDL) structure 117 is flat and substantially parallel to the interface between the conductive adhesive layer 110 and the conductive pad 103.

In some embodiments, the UBM layer 141 may include a single layer or a plurality of layers. For example, the UBM layer 141 may include a barrier layer and a seed layer. In order to simplify the figure, the UBM layer 141 including a single layer is described as an example.

In some embodiments, the UBM layer 141 may be made of one or more conductive materials, such as copper (Cu), copper alloy, aluminum (Al), aluminum alloy, tungsten (W), tungsten alloy, titanium (Ti), titanium alloy, tantalum (Ta) or tantalum alloy. In addition, in some embodiments, the UBM layer 141 may also include a copper seed layer (not shown). In some embodiments, the solder portion 142 is a solder bump, a solder ball, a solder paste, etc.

In one example, an under bump metallization (UBM) material layer is formed on the redistribution layer (RDL) structure 117 by a suitable metal deposition operation, such as electroplating or electroless plating, physical vapor deposition (PVD) including sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), thermal evaporation, and electron beam evaporation. Then, a photoresist layer (not shown) is formed above the under bump metallization (UBM) material layer and patterned to form an opening, thereby exposing a desired portion of the top surface of the under bump metallization (UBM) material layer. Solder is then formed in the opening on the under bump metallization (UBM) material layer. The solder can be formed by a suitable metal deposition operation, including electroplating or electroless plating, physical vapor deposition (PVD) including sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), thermal evaporation, and electron beam evaporation. In some embodiments, before depositing the solder, a seed layer (not shown) is deposited on the under bump metallization (UBM) material layer. The photoresist adhesive layer is then removed by using photoresist stripping or other suitable methods. After removing the photoresist layer, the under-bump metallization (UBM) material layer is etched using the solder portion 142 as a mask to form a UBM layer 141. In some embodiments, after removing the photoresist adhesive layer, the solder portion 142 is reflowed to form a smooth hemispherical shape as shown in FIG. 1I. In one example, the solder portion 142 is reflowed by heating the solder to a temperature at which it softens and flows.

In addition, in some other embodiments, one or more metal layers (not shown) may be further formed between the UBM layer 141 and the solder portion 142. For example, a copper-based layer (not shown) may be formed on the UBM layer 141, and a metal column (not shown) having a solderability lower than that of copper may be formed between the copper-based layer and the solder portion 142. The metal column may include nickel, a nickel alloy, or other suitable materials. Because the metal column has a lower solderability than the copper-based layer, the solder may be inhibited from flowing down the side of the metal column during solder reflow.

In addition, in some embodiments, the bump structure 140 on the second dielectric layer 125 can be laterally offset from the pillar portion 118 and the conductive adhesive layer 110, as shown in FIG. 1I. However, the present disclosure is not limited thereto. In some other embodiments, the bump structure 140 can be substantially disposed directly above the pillar portion 118 and the conductive adhesive layer 110.

2 is a cross-sectional view of an intermediate stage of a semiconductor package structure according to some embodiments of the present invention. In this exemplary embodiment, a semiconductor package structure 10P includes a semiconductor substrate 100, a conductive pad 103 on the semiconductor substrate 100, and a passivation layer 105 on the semiconductor substrate 100 and the conductive pad 103. The passivation layer 105 exposes a portion of the top surface 103a of the conductive pad 103. The semiconductor package structure 10P also includes: a conductive adhesive layer 110 on the conductive pad 103, and a first dielectric layer 115 on the passivation layer 105 and the conductive adhesive layer 110. The first dielectric layer 115 exposes a portion of the conductive adhesive layer 110. The semiconductor package structure 10P also includes: a redistribution layer (RDL) structure 117 on the first dielectric layer 115 and the second dielectric layer 125. The RDL structure 117 is electrically connected to the conductive pad 103 through the conductive adhesive layer 110. The semiconductor package structure 10P also includes: a bump structure 140 on the RDL structure 117.

In this exemplary embodiment, a wing portion 1101 of the conductive adhesive layer 110 is formed between the first dielectric layer 115 and the passivation layer 105. The side edge of the wing portion 1101 of the conductive adhesive layer 110 may be, but is not limited to, aligned with the side edge 103s of the conductive pad 103 or slightly protruded from the side edge 103s of the conductive pad 103. According to an embodiment, the conductive adhesive layer 110 prevents delamination due to direct contact between the conductive pad and the conductive portion (e.g., the RDL structure 117) on the conductive pad.

Although a semiconductor die 10a having one conductive pad 103 is depicted in FIGS. 1E to 1I , the semiconductor die 10a may include more conductive pads 103 (e.g., two, three, four, etc.). In addition, although a redistribution layer (RDL) structure 117 in a semiconductor package structure is shown in FIGS. 1E to 1I , the present disclosure is not limited thereto. More redistribution layer (RDL) structures may be formed in the semiconductor package structure, and trace routing may be arranged according to actual requirements of the application. For example, multiple redistribution layer (RDL) structures may be formed to provide a semiconductor package structure having a fan-out structure. The conductive adhesive layer 110 in the embodiment may be applied to any type of semiconductor package structure to prevent delamination between a conductive pad and a conductive portion (e.g., an RDL structure).

3A, 3B, 3C, 3D and 3E are cross-sectional views of intermediate stages of a method for forming a semiconductor package structure according to some embodiments of the present invention. In this exemplary semiconductor package structure, three conductive pads 103 are formed on a semiconductor substrate 100, and two RDL structures are provided on the semiconductor substrate 100 to provide a fan-out structure.

In FIGS. 3A to 3E and FIGS. 1A to 1I , the same or similar reference numerals or reference signs represent the same or similar elements (e.g., components or layers). For the sake of brevity, the description of the same or similar elements in FIGS. 3A to 3E of the following embodiments as those previously described with reference to FIGS. 1A to 1I may be omitted.

3A, in some embodiments, a semiconductor substrate 100 is provided. In some embodiments, a circuit (not shown) and a device element (not shown) may be formed within the semiconductor substrate 100, and the circuit may be any type of circuit suitable for a particular application. Two or more conductive pads may be formed on the semiconductor substrate 100. In this exemplary embodiment, three conductive pads 103 are formed on the semiconductor substrate 100, for example, on the first surface 100a (e.g., active surface) of the semiconductor substrate 100.

In some embodiments, the conductive pad 103 is configured to be electrically coupled to a bump (e.g., the bump structure 140 in FIG. 3E ) through a conductive trace (e.g., the first RDL structure 117 and the second RDL structure 127 in FIG. 3E ) to the conductive pad 103. In some embodiments, the conductive pad 103 may be made of gold (Au), silver (Ag), copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), palladium (Pd), and/or alloys thereof. In some embodiments, the conductive pad 103 is formed by plating or other suitable methods.

In addition, according to some embodiments of the present disclosure, a passivation layer 105 is formed on the semiconductor substrate 100 and the conductive pads 103. The passivation layer 105 partially covers the conductive pads 103. For example, the passivation layer 105 exposes a portion of the top surface 103a of each conductive pad 103. As shown in FIG. 3A, the passivation layer 105 includes three first openings 106 that expose the conductive pads 103.

The passivation layer 105 may include an inorganic material, such as spin-on glass (SOG), silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), silicon oxynitride (SiON), silicon nitride (SiN) or a combination thereof, or other suitable insulating materials. The passivation layer 105 may be formed by depositing the passivation layer using vapor deposition, spin coating, or other suitable processes, and then patterning the passivation layer to form the passivation layer 105 having a plurality of first openings 106.

According to some embodiments of the present disclosure, before a dielectric layer (e.g., the first dielectric layer 115 in FIG. 3B ) is deposited over the passivation layer 105 and the conductive pad 103, a conductive adhesive layer 110 ( FIG. 1C ) is formed on the conductive pad 103. From the conductive pad 103 through the conductive adhesive layer 110 and the conductive trace of the RDL structure to the bump structure 140, a circuit inside the semiconductor substrate 100 is connected to another circuit outside the semiconductor substrate 100.

In some embodiments, the conductive adhesive layer 110 on the conductive pad 103 may include a second adhesive film 112 and a first adhesive film 111. The conductive adhesive layer 110 is in direct contact with the exposed portion of the top surface 103a of the conductive pad 103. The conductive adhesive layer 110 is configured as a liner in the first opening 106 of the passivation layer 105. The conductive adhesive layer 110 has an extension on the passivation layer 105 (e.g., a wing 1101 shown in FIG. 1C ).

The second adhesive film 112 and the first adhesive film 111 include different conductive materials, such as different metal-containing materials. In some embodiments, the first adhesive film 111 and the second adhesive film 112 include copper, titanium, tantalum, titanium nitride, tantalum nitride, etc. or a combination thereof. In an exemplary embodiment, the first adhesive film 111 is a titanium-based layer and the second adhesive film 112 is a copper-based layer.

In an exemplary embodiment, the first adhesive film material and the second adhesive film material may be formed by (but not limited to) sputtering to obtain an adhesive film material with high density. Then, the first adhesive film material and the second adhesive film material are patterned to form the second adhesive film 112 and the first adhesive film 111, respectively.

For the sake of brevity, details of the construction, materials and manufacturing methods of the semiconductor substrate 100, the conductive pad 103, the passivation layer 105 and the conductive adhesive layer 110 in FIG. 3A are similar to those described above with reference to FIGS. 1A to 1C and are not repeated here.

Next, referring to FIG. 3B , in some embodiments, according to some embodiments of the present disclosure, a first dielectric layer 115 is formed on the passivation layer 105 and the conductive adhesive layer 110. The first dielectric layer 115 exposes a portion of the top surface 110a of the conductive adhesive layer 110. In some embodiments, the wing portion 1101 of the conductive adhesive layer 110 is sandwiched between the first dielectric layer 115 and the passivation layer 105. The first dielectric layer 115 may be an organic layer. For example, the first dielectric layer 115 may include polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), epoxy resin, photosensitive material, other suitable polymer materials, or combinations thereof.

In some embodiments, the first RDL structure 117 is formed on the first dielectric layer 115 and is electrically coupled to the conductive adhesive layer 110. For example, the pillar portion 118 of the first RDL structure 117 is in direct contact with the exposed top surface 110a of the conductive adhesive layer 110. Therefore, the first RDL structure 117 is electrically connected to the conductive pad 103 through the conductive adhesive layer 110. By adding the conductive adhesive layer 110 between the conductive pad 103 and the pillar portion 118 of the first RDL structure 117, the adhesive contact area between the conductive pad 103 and the pillar portion 118 of the first RDL structure 117 can be expanded.

Furthermore, according to an embodiment, the adhesion between the conductive pad 103 and the conductive adhesive layer 110 is stronger than the adhesion between the conductive pad 103 and the first RDL structure 117 , thereby preventing conventional delamination between the conductive pad and the metal trace of the RDL structure.

For brevity, details of the configuration, materials, and manufacturing methods of the first dielectric layer 115 and the first redistribution layer (RDL) structure 117 in FIG. 3B are similar to those described above with reference to FIGS. 1D and 1E , and are not repeated here.

3C , in some embodiments, a mold layer 120 is formed to surround the semiconductor substrate 100, the passivation layer 105, the conductive adhesive layer 110, the first dielectric layer 115, and the first RDL structure 117. In some embodiments, a top surface 120a of the mold layer 120 is coplanar with a top surface 117a of the first RDL structure 117. A bottom surface 120b of the mold layer 120 is coplanar with the second surface 100b of the semiconductor substrate 100.

For brevity, details of the configuration, materials, and manufacturing method of the molding layer 120 in FIG. 3C are similar to those described above with reference to FIGS. 1F and 1G , and will not be repeated here.

Next, referring to FIG. 3D , in some embodiments, a second dielectric layer 125 is formed on the first RDL structure 117. The second dielectric layer 125 exposes a portion of the top surface 117a of the first RDL structure 117. The second RDL structure 127 is formed on the second dielectric layer 125 and rewires the path of the circuit from the conductive pad 103 to the circuit outside the semiconductor substrate 100. The second RDL structure 127 may be a single-layer structure or a multi-layer structure, and may include gold, silver, copper, nickel, tungsten, aluminum, and/or alloys thereof. In this exemplary embodiment, the second RDL structure 127 includes a pillar portion 128 (extending along the second direction D2) and a main portion 129 (extending along the first direction D1). The pillar portion 128 of the second RDL structure 127 is in direct contact with the first RDL structure 117. In addition, a third dielectric layer 135 is formed on the second RDL structure 127. The third dielectric layer 135 has an opening 136 to expose a portion of the top surface 127a of the second RDL structure 127 (ie, the top surface 129a of the main portion 129). The third dielectric layer 135 and the second dielectric layer 125 may be made of the same dielectric material.

For the sake of brevity, details of the configuration, materials, and manufacturing methods of the second dielectric layer 125 , the second RDL structure 127 , and the third dielectric layer 135 in FIG. 3D are similar to those described above with reference to FIG. 1H , and are not repeated here.

3E, in some embodiments, a plurality of bump structures 140 are formed on the exposed portion of the top surface 127a of the second RDL structure 127. Each bump structure 140 may include an under bump metallization (UBM) layer 141 and a solder portion 142. For the sake of brevity, the details of the construction, materials, and manufacturing methods of the bump structure 140 in FIG. 3E are similar to the above description with reference to FIG. 1I, and are not repeated here.

In this exemplary embodiment, as shown in FIG. 3E , a lateral distance D _R2 (in the first direction D1 ) between the bump structures 140 may be longer than a lateral distance D _R1 (in the first direction D1 ) between the traces of the first RDL structure 117 to implement a fan-out structure.

According to some of the above-mentioned embodiments, the semiconductor package structure and the method for forming the semiconductor package structure achieve multiple advantages. In some embodiments, the contact area between the conductive adhesive layer and the conductive pad is greater than the contact area between the RDL structure and the conductive adhesive layer. Therefore, by adding a conductive adhesive layer between the conductive pad and the RDL structure, the contact area between the conductive pad and the RDL structure can be expanded. According to an embodiment, the bonding between the conductive pad and the conductive adhesive layer is stronger than the bonding between the conductive pad and the RDL structure, thereby preventing delamination between the conductive pad and the RDL structure. Therefore, according to some embodiments, having a conductive adhesive layer between the conductive pad and the RDL can improve the reliability of the semiconductor package structure. In addition, the method for forming the semiconductor package structure of the embodiment is compatible with existing processes and does not include complex and expensive manufacturing processes. Therefore, it saves time in manufacturing the semiconductor package structure without increasing manufacturing costs.

It should be noted that the details of the structure and manufacture of the embodiments are provided for illustration, and the details of the embodiments are not intended to limit the present invention. It should be noted that not all embodiments of the present invention are shown. Modifications and changes can be made without departing from the spirit of the present disclosure to meet the requirements of practical applications. Therefore, there may be other embodiments of the present disclosure that are not specifically shown. In addition, in order to clearly illustrate the embodiments, the drawings are simplified. The dimensions and proportions in the drawings may not be proportional to the actual product. Therefore, the description and drawings are considered to be illustrative rather than restrictive.

Although the present invention has been described by way of example and preferred embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, the present invention is intended to cover various modifications and similar arrangements (which are obvious to those skilled in the art). Therefore, the scope of the appended claims should be interpreted in the broadest manner so as to cover all such modifications and similar arrangements.

Claims (30)

1. A semiconductor package structure, comprising: Semiconductor substrate; a conductive pad, the conductive pad being on the semiconductor substrate; a passivation layer on the semiconductor substrate and the conductive pad, wherein the passivation layer exposes a portion of a top surface of the conductive pad; a conductive adhesive layer on the conductive pad; a dielectric layer on the passivation layer and the conductive adhesive layer, wherein the dielectric layer exposes a portion of a top surface of the conductive adhesive layer; a redistribution layer (RDL) structure on the dielectric layer and electrically connected to the conductive pad through the conductive adhesive layer; and A bump structure is on the redistribution layer (RDL) structure. 2 . The semiconductor package structure according to claim 1 , wherein the exposed top surface of the conductive adhesive layer is in direct contact with the redistribution layer (RDL) structure. 3 . The semiconductor package structure according to claim 1 , wherein a contact area between the conductive adhesive layer and the conductive pad is greater than a contact area between the redistribution layer (RDL) structure and the conductive adhesive layer. 4 . The semiconductor package structure according to claim 1 , wherein the passivation layer has a first opening, the first opening exposing the portion of the top surface of the conductive pad, and the conductive adhesive layer is configured as a liner in the first opening. 5 . The semiconductor package structure according to claim 4 , wherein the dielectric layer has a second opening exposing the portion of the top surface of the conductive adhesive layer, and the redistribution layer (RDL) structure comprises a pillar portion in the second opening. The semiconductor package structure according to claim 5 , wherein the first opening is larger than the second opening. 7 . The semiconductor package structure according to claim 5 , wherein a bottom surface of the pillar portion of the redistribution layer (RDL) structure is in direct contact with the top surface of the conductive adhesive layer. 8 . The semiconductor package structure according to claim 1 , wherein a portion of the redistribution layer (RDL) structure directly contacting the conductive adhesive layer has a first symmetry line, the conductive adhesive layer has a second symmetry line, and the first symmetry line is aligned with the second symmetry line. 9 . The semiconductor package structure according to claim 1 , wherein the conductive adhesive layer comprises a wing portion extending on the passivation layer, and the wing portion of the conductive adhesive layer is disposed between the dielectric layer and the passivation layer. 10 . The semiconductor package structure according to claim 1 , wherein the conductive adhesive layer comprises two or more metal layers. 11. The semiconductor package structure according to claim 1, wherein the conductive adhesive layer comprises: a first adhesive film on the conductive pad; and a second adhesive film, the second adhesive film being on the first adhesive film, The first adhesive film and the second adhesive film include different conductive materials. 12 . The semiconductor package structure of claim 11 , wherein adhesion between the conductive pad and the first adhesive film is stronger than adhesion between the conductive pad and the redistribution layer (RDL) structure. 13 . The semiconductor package structure of claim 11 , wherein the second adhesive film and the redistribution layer (RDL) structure comprise a same material. 14 . The semiconductor package structure of claim 1 , wherein the dielectric layer formed on the passivation layer and the conductive adhesive layer has a flat top surface. 15. The semiconductor package structure according to claim 1, wherein the dielectric layer is a first dielectric layer, and the semiconductor package structure further comprises: a second dielectric layer, the second dielectric layer being above the redistribution layer RDL structure, The second dielectric layer exposes a portion of the top surface of the redistribution layer (RDL) structure. 16. The semiconductor package structure according to claim 15, wherein the redistribution layer (RDL) structure is a first redistribution layer (RDL) structure, and the semiconductor package structure further comprises: a second redistribution layer RDL structure, the second redistribution layer RDL structure being disposed on the second dielectric layer and electrically connected to the first redistribution layer RDL structure, Wherein, the bump structure is arranged above the second redistribution layer RDL structure; and The bump structure is electrically connected to the semiconductor substrate through the second redistribution layer (RDL) structure, the first redistribution layer (RDL) structure, the conductive adhesive layer and the conductive pad. 17. The semiconductor package structure according to claim 1, wherein the bump structure comprises: an under bump metallization (UBM) layer, the UBM layer being above the redistribution layer (RDL) structure; and a solder portion, the solder portion being over the UBM layer, The UBM layer is in direct contact with a top surface of the redistribution layer (RDL) structure, and the solder portion is electrically connected to the semiconductor substrate through the UBM layer, the redistribution layer (RDL) structure, the conductive adhesive layer and the conductive pad. 18. The semiconductor package structure according to claim 1, further comprising: A molding layer surrounds the semiconductor substrate, the passivation layer, the dielectric layer and the conductive adhesive layer. 19. A method for forming a semiconductor package structure, the method comprising the following steps: providing a semiconductor substrate; forming a conductive pad on the semiconductor substrate; forming a passivation layer on the semiconductor substrate and the conductive pad, wherein the passivation layer exposes a portion of a top surface of the conductive pad; forming a conductive adhesive layer on the conductive pad; forming a dielectric layer on the passivation layer and the conductive adhesive layer, wherein the dielectric layer exposes a portion of a top surface of the conductive adhesive layer; forming a redistribution layer (RDL) structure on the dielectric layer, and the redistribution layer (RDL) structure is electrically connected to the conductive pad through the conductive adhesive layer; and A bump structure is formed above the redistribution layer (RDL) structure. 20 . The method for forming a semiconductor package structure according to claim 19 , wherein the exposed top surface of the conductive adhesive layer is in direct contact with the redistribution layer (RDL) structure. 21. The method for forming a semiconductor package structure according to claim 19, wherein the step of forming the conductive adhesive layer comprises: forming a first adhesive film material on the passivation layer and the exposed portion of the top surface of the conductive pad; and forming a second adhesive film material on the first adhesive film material, wherein the first adhesive film material and the second adhesive film material include different conductive materials; and patterning the second adhesive film material and the first adhesive film material to form a second adhesive film and a first adhesive film, respectively, The second adhesive film and the first adhesive film together form the conductive adhesive layer. 22 . The method for forming a semiconductor package structure according to claim 21 , wherein the first adhesive film material and the second adhesive film material are formed by sputtering. 23 . The method for forming a semiconductor package structure according to claim 21 , wherein the dielectric layer formed on the passivation layer and the conductive adhesive layer has a flat top surface. 24 . The method for forming a semiconductor package structure according to claim 19 , wherein a contact area between the conductive adhesive layer and the conductive pad is greater than a contact area between the redistribution layer (RDL) structure and the conductive adhesive layer. 25 . The method for forming a semiconductor package structure according to claim 19 , wherein the formed passivation layer has a first opening exposing the portion of the top surface of the conductive pad, and the conductive adhesive layer is configured as a liner in the first opening. 26 . The method for forming a semiconductor package structure according to claim 25 , wherein the formed dielectric layer has a second opening, the second opening exposes the portion of the top surface of the conductive adhesive layer, and the first opening is larger than the second opening. 27 . The method for forming a semiconductor package structure according to claim 26 , wherein after forming the dielectric layer having the second opening, a center line of the second opening is aligned with a center line of the first opening. 28 . The method for forming a semiconductor package structure according to claim 21 , wherein after forming the dielectric layer, the wing portion of the conductive adhesive layer extending on the passivation layer is disposed between the dielectric layer and the passivation layer. 29. The method for forming a semiconductor package structure according to claim 21, wherein the method further comprises: after forming the redistribution layer (RDL) structure, A mold layer is formed around the semiconductor substrate, the passivation layer, the dielectric layer, and the conductive adhesive layer. 30. The method for forming a semiconductor package structure according to claim 21, wherein the dielectric layer is a first dielectric layer, and the method further comprises: before forming the bump structure, forming a second dielectric layer on the first dielectric layer and the redistribution layer RDL structure, The second dielectric layer exposes a portion of the top surface of the redistribution layer (RDL) structure, and Wherein, the bump structure is formed on an exposed portion of the top surface of the redistribution layer (RDL) structure.