CN118115038B - LED chip defect detection method, device, equipment and storage medium - Google Patents

Abstract

The invention provides a method, a device, equipment and a storage medium for detecting defects of an LED chip, wherein the method comprises the following steps: selecting a plurality of corresponding chip process detection models according to a plurality of equipment nodes respectively, and inputting chip process data of each equipment node in a target time period into the corresponding chip process detection models respectively to obtain corresponding process yield; calculating the process passing rate of the target LED chip produced in the target time period based on the weight data corresponding to each equipment node and the corresponding process yield; judging whether the product grade of the target LED chip is a preset defective grade or not based on the process passing rate; and carrying out chip electrical detection on the target LED chips with defective product grades to obtain chip defect detection results. The method uses the process data in different process steps before the electrical detection of the LED chip, predicts the shipment quality and grade of the product, only performs electrical measurement on the bad product, reduces the electrical measurement cost, and can reduce the secondary bad rate caused by the electrical measurement of the product.

Description

LED chip defect detection method, device, equipment and storage medium

Technical Field

The present invention relates to the field of defect detection, and in particular to a method, device, equipment and storage medium for detecting defects in an LED chip.

Background Art

LED (Light Emitting Diode) chip is an important semiconductor device, widely used in lighting, display and communication. In order to ensure the quality and stable performance of LED chips, electrical testing has become an indispensable part of the LED production process. However, electrical testing is the least efficient process in the LED manufacturing process, with the largest number of equipment sets and the largest occupied area. With the substantial growth in the demand for mini and micro displays, the electrode geometry is getting smaller and smaller, and it is becoming more and more difficult to accurately pierce the electrode, and the proportion of products that are damaged will become higher and higher.

Summary of the invention

The main purpose of the present invention is to solve the technical problem that the existing use of electrical detection to perform defect detection on LED chips leads to an increase in the number of damaged products.

A first aspect of the present invention provides a method for detecting defects in an LED chip. The method is applied to an LED chip production system. The LED chip production system includes a plurality of device nodes corresponding to a plurality of process stages of an LED chip during a process. The method includes:

Obtain chip process data of each device node in the LED chip production system in a target time period;

Selecting corresponding multiple chip process detection models according to the multiple device nodes, and inputting the chip process data into the corresponding chip process detection models, respectively, to obtain the process yield corresponding to the corresponding device node in the target time period;

Calculate the process pass rate of the target LED chips produced in the target time period based on the weight data corresponding to each device node and the corresponding process yield rate;

Determining a product grade of the target LED chips produced in the target time period based on the process pass rate, and judging whether the product grade is a preset defective grade;

If so, electrical chip testing is performed on the target LED chips produced in the target time period to obtain chip defect detection results.

Optionally, in a first implementation of the first aspect of the present invention, the chip process data includes chip process parameters and/or three-dimensional topography detection images;

The selecting corresponding multiple chip process detection models according to the multiple device nodes respectively, and inputting the chip process data into the corresponding chip process detection models respectively, to obtain the process yield corresponding to the device node in the target time period includes:

Selecting corresponding multiple chip process detection models according to the multiple device nodes respectively, and determining whether the process segment corresponding to the corresponding device node is an image detection process segment according to the device types of the multiple device nodes;

If so, obtain the three-dimensional shape detection image in the image detection process section, and pre-process the three-dimensional shape detection image and the chip process parameters and input them into the corresponding chip process detection model to obtain the process yield corresponding to the corresponding device node in the target time period;

If not, the chip process parameters are pre-processed and then respectively input into the corresponding chip process detection model to obtain the process yield of the corresponding device node in the target time period.

Optionally, in a second implementation of the first aspect of the present invention, the preprocessing of the chip process parameters and inputting them into corresponding chip process detection models to obtain the process yield corresponding to the corresponding device node in the target time period includes:

Preprocessing the chip process parameters and inputting them into the corresponding chip process detection model respectively, wherein the chip process detection model includes an input layer, a cross layer, a depth layer, a combination layer and an output layer;

Performing data preprocessing and data feature extraction on the chip process parameters through the input layer to obtain multiple data features;

Performing first feature correlation processing on multiple data features through a cross layer to obtain a first correlation feature, and performing second feature correlation processing on multiple data features through a depth layer to obtain a second correlation feature;

The first associated feature and the second associated feature are connected through the combination layer, and the connected feature vector is used to calculate the process yield of the corresponding device node in the target time period through an activation function.

Optionally, in a third implementation of the first aspect of the present invention, the performing data preprocessing and data feature extraction on the chip process parameters through the input layer to obtain the data features includes:

Extracting features of the chip process parameters through the input layer to obtain first feature data;

Generate an adjacency matrix according to the first feature data, and calculate a corresponding Laplace matrix based on the adjacency matrix;

Performing eigenvalue decomposition on the Laplace matrix to obtain a plurality of eigenvectors and corresponding eigenvalues, and screening the eigenvectors according to the eigenvalues to obtain corresponding eigensubspaces;

Second feature data is acquired based on the feature subspace, and the second feature data is iteratively processed according to a particle swarm algorithm to obtain data features.

Optionally, in a fourth implementation of the first aspect of the present invention, the acquiring of the three-dimensional shape detection image in the image detection process segment, and pre-processing the three-dimensional shape detection image and the chip process parameters and inputting them into a corresponding chip process detection model, to obtain the process yield corresponding to the corresponding device node in the target time period includes:

Acquire a three-dimensional shape detection image in the image detection process section, and pre-process the three-dimensional shape detection image and the chip process parameters and input them into a corresponding chip process detection model, wherein the chip process detection model includes an input layer, an attention mechanism layer, a feature fusion layer, a classification layer, and an output layer;

Performing data preprocessing and data feature extraction on the chip process parameters through the input layer to obtain data features, and performing image preprocessing and image feature extraction on the three-dimensional shape detection image to obtain image features;

Calculate the attention weight vectors of the data features and the image features respectively through the attention mechanism layer;

The data feature and the image feature are weightedly fused according to the weight vector by the feature fusion layer to obtain a fused feature vector;

The classification layer calculates the process yield of the corresponding device node in the target time period according to the fused feature vector, and outputs the process yield through the output layer.

Optionally, in a fifth implementation of the first aspect of the present invention, before obtaining the three-dimensional shape detection image in the image detection process segment and pre-processing the three-dimensional shape detection image and the chip process parameters and inputting them into the corresponding chip process detection model, it also includes:

Obtaining the resolution of the optical lens device corresponding to each image process section, and calculating the number of scanning layers corresponding to each image process section according to a preset super-depth-of-field synthesis imaging algorithm and the resolution;

Based on the number of scanning layers, the optical lens equipment of the corresponding image process section is controlled to perform three-dimensional shape detection on the target chip produced in the target time period to obtain depth images of different scanning layers of each image process section;

The depth images of the different scanning layers are stitched and merged to generate a three-dimensional shape detection image of each image process section.

Optionally, in a sixth implementation manner of the first aspect of the present invention, calculating the process yield corresponding to the corresponding device node in the target time period according to the fused feature vector through the classification layer, and outputting the process yield through the output layer includes:

The fused feature vector is linearly transformed and mapped to a high-dimensional feature space through the classification layer to obtain a linear transformation result;

Performing a nonlinear transformation on the linear transformation result through a preset activation function to obtain a nonlinear transformation result;

Calculate the probability of the corresponding device node in the process yield interval corresponding to the target time period according to the nonlinear transformation result through the fully connected layer in the classification layer;

The process yield interval with the highest probability is used as the process yield corresponding to the corresponding device node in the target time period, and the process yield is output through the output layer.

A second aspect of the present invention provides an LED chip defect detection device, which is applied to an LED chip production system, wherein the LED chip production system includes a plurality of device nodes corresponding to a plurality of process stages of an LED chip during a process; the LED chip defect detection device includes:

An acquisition module, used to acquire chip process data of each device node in the LED chip production system in a target time period;

A yield calculation module is used to select corresponding multiple chip process detection models according to the multiple device nodes, and input the chip process data into the corresponding chip process detection model to obtain the process yield of the corresponding device node in the target time period;

A pass rate calculation module, used to calculate the process pass rate of the target LED chips produced in the target time period based on the weight data corresponding to each device node and the corresponding process yield;

A judgment module, configured to determine the product grade of the target LED chips produced in the target time period based on the process pass rate, and to judge whether the product grade is a preset defective grade;

The electrical inspection module is used to perform chip electrical inspection on the target LED chips produced in the target time period to obtain chip defect inspection results if the product grade is a defective grade.

The third aspect of the present invention provides an LED chip defect detection device, comprising: a memory and at least one processor, wherein instructions are stored in the memory, and the memory and the at least one processor are interconnected through lines; the at least one processor calls the instructions in the memory so that the LED chip defect detection device performs the steps of the above-mentioned LED chip defect detection method.

A fourth aspect of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores instructions, which, when executed on a computer, enable the computer to execute the steps of the above-mentioned LED chip defect detection method.

The above-mentioned LED chip defect detection method, device, equipment and storage medium respectively select corresponding multiple chip process detection models according to multiple device nodes, and input the chip process data of each device node in the target time period into the corresponding chip process detection model to obtain the corresponding process yield; calculate the process pass rate of the target LED chip produced in the target time period based on the weight data corresponding to each device node and the corresponding process yield; judge whether the product grade of the target LED chip is a preset defective grade based on the process pass rate; perform chip electrical detection on the target LED chip of the defective grade to obtain the chip defect detection result. This method uses the process data at different process steps before the LED chip is electrically tested to predict the product's shipping quality and grade, and only performs electrical testing on defective products, thereby reducing the cost of electrical testing and reducing the secondary defect rate caused by product electrical testing.

Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of an embodiment of a method for detecting defects in an LED chip according to an embodiment of the present invention;

FIG2 is a schematic diagram of an embodiment of a device for detecting defects in an LED chip according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of an embodiment of an LED chip defect detection device according to an embodiment of the present invention.

DETAILED DESCRIPTION

In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

The terms "including" and "having" and any variations thereof mentioned in the embodiments of the present invention are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but may optionally include other steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices.

To facilitate understanding of this embodiment, a method for detecting defects in LED chips disclosed in an embodiment of the present invention is first described in detail. The method for detecting defects in LED chips is applied to an LED chip production system, and the LED chip production system includes multiple device nodes corresponding to multiple process stages of the LED chip during the process. As shown in FIG1 , the method for detecting defects in LED chips includes the following steps:

101. Obtain chip process data of each device node in the LED chip production system in a target time period;

In one embodiment of the present invention, the LED chip production system includes multiple equipment nodes, such as wafer processing equipment, deposition equipment, photolithography equipment, etching equipment, metallization equipment and packaging equipment, etc., wherein the wafer processing equipment includes a wafer cleaning machine, a cutting machine, a grinder, etc. These equipment are used to process the original wafer of the LED chip, and the process data provided may include wafer size, cutting quality, grinding uniformity, etc. Deposition equipment such as chemical vapor deposition (CVD) equipment, physical vapor deposition (PVD) equipment, etc. These equipment are used to deposit materials on the wafer, and the process data may involve deposition rate, film quality, interface characteristics, etc. The photolithography equipment is used to transfer the pattern on the photosensitive adhesive layer to the wafer. The process data may include exposure time, alignment accuracy, exposure dose, etc. The etching equipment is used to remove unnecessary materials on the wafer. The process data may include etching depth, etching rate, surface quality, etc. Metallization equipment such as vacuum evaporation machine, electroplating equipment, etc. These equipment are used to form metal electrodes or wires on the wafer. The process data may include film thickness, resistance value, metal bonding, etc. Packaging equipment such as packaging machines, welding equipment, etc. These equipment are used to package LED chips into final products. Process data may involve packaging quality, solder joint reliability, packaging speed, etc.

102. Select corresponding multiple chip process detection models according to multiple device nodes, and input chip process data into corresponding chip process detection models to obtain corresponding process yields of corresponding device nodes in target time periods;

In one embodiment of the present invention, the chip process data includes chip process parameters and/or three-dimensional morphology detection images; the selecting corresponding multiple chip process detection models according to the multiple device nodes, and inputting the chip process data into the corresponding chip process detection models, to obtain the process yield corresponding to the device node in the target time period includes: selecting corresponding multiple chip process detection models according to the multiple device nodes, and determining whether the process segment corresponding to the corresponding device node is an image detection process segment according to the device type of the multiple device nodes; if so, obtaining the three-dimensional morphology detection image in the image detection process segment, and pre-processing the three-dimensional morphology detection image and the chip process parameters and inputting them into the corresponding chip process detection model to obtain the process yield corresponding to the corresponding device node in the target time period; if not, pre-processing the chip process parameters and inputting them into the corresponding chip process detection models to obtain the process yield corresponding to the corresponding device node in the target time period.

Specifically, the chip process data also includes three-dimensional morphology detection images. Three-dimensional morphology detection images are images used to observe and analyze the surface morphology and structure of the chip. It provides detailed information about the geometric features and microstructure of the chip surface. Usually, the three-dimensional morphology detection image of the chip is obtained by using high-resolution surface scanning technology, such as atomic force microscopy (AFM), scanning electron microscope (SEM) or white light interferometer. In the production process of LED chips, three-dimensional morphology detection is usually applied to the process segments of the following equipment nodes, including wafer processing equipment, deposition equipment, etching equipment and metallization equipment. During wafer cutting and polishing, three-dimensional morphology detection can be used to evaluate the surface flatness and quality of the chip to ensure that the size and shape of the chip meet the requirements. Deposition equipment such as chemical vapor deposition (CVD) equipment and physical vapor deposition (PVD) equipment are used to deposit materials on the wafer to form structures at different levels. At this stage, three-dimensional morphology detection can help evaluate the thickness, uniformity and surface quality of the film. Engraving equipment is used to remove unnecessary materials on the wafer to form the desired pattern and structure. In the etching process, three-dimensional morphology detection can be used to detect etching depth, sidewall quality and structural morphology. Metallization equipment is used to form metal electrodes or wires on wafers. The thickness, flatness and connection quality of metal films can be evaluated through 3D topography detection. In addition, 3D topography detection can be performed directly at the last step of the process to obtain a 3D topography image. For process sections where 3D topography detection does not exist, yield prediction is performed directly based on chip process parameters. For process sections that require 3D topography detection, yield prediction is performed by combining chip process parameters and 3D topography detection images.

Furthermore, the preprocessing of the chip process parameters and inputting them into the corresponding chip process detection model to obtain the process yield corresponding to the corresponding device node in the target time period includes: preprocessing the chip process parameters and inputting them into the corresponding chip process detection model, wherein the chip process detection model includes an input layer, a cross layer, a depth layer, a combination layer and an output layer; performing data preprocessing and data feature extraction on the chip process parameters through the input layer to obtain multiple data features; performing first feature association processing on the multiple data features through the cross layer to obtain first association features, and performing second feature association processing on the multiple data features through the depth layer to obtain second association features; connecting the first association features and the second association features through the combination layer, and calculating the process yield corresponding to the corresponding device node in the target time period through the connected feature vector through an activation function.

Specifically, after preprocessing, the chip process parameters are respectively input into the corresponding chip process detection model. The model includes an input layer, a cross layer, a depth layer, a combination layer and an output layer. First, the input layer performs data preprocessing and feature extraction on the chip process parameters to obtain multiple data features. These features may include chip size, material properties, process parameters, etc. Next, the cross layer performs first feature association processing on multiple data features. It combines different features, such as through multiplication or addition operations, to obtain new feature representations. These new features capture the association information between the original features and have higher dimensional expression capabilities. These first association features provide linear relationships between different features. Then, the depth layer performs second feature association processing on multiple data features. Through multiple hidden layers, the model learns the nonlinear relationship between different features. Through optimization methods such as back propagation algorithm and gradient descent, the depth layer can automatically learn the complex relationship between these features and generate second association features. These features represent more abstract associations between the original features in high-dimensional space. Next, the combination layer connects the first association feature and the second association feature to form a new feature vector. This connection can be in series, parallel or skip connection. Through the connection, the information of the first associated feature and the second associated feature is integrated into a richer feature representation. This connected feature vector is passed to the output layer. Finally, the output layer uses the activation function to calculate the connected feature vector to obtain the process yield of the corresponding device node in the target time period. The activation function can be selected according to specific needs. Common ones include sigmoid function, ReLU function, etc. This process is to map the feature vector to a range between 0 and 1 to represent the process yield of the device node.

Furthermore, the chip process parameters are subjected to data preprocessing and data feature extraction through the input layer to obtain data features, including: extracting features of the chip process parameters through the input layer to obtain first feature data; generating an adjacency matrix according to the first feature data, and calculating a corresponding Laplace matrix based on the adjacency matrix; performing eigenvalue decomposition on the Laplace matrix to obtain multiple eigenvectors and corresponding eigenvalues, and screening the eigenvectors according to the size of the eigenvalues to obtain a corresponding feature subspace; obtaining second feature data based on the feature subspace, and iteratively processing the second feature data according to the particle swarm algorithm to obtain data features.

Specifically, for a given feature data set, we first need to construct an adjacency matrix to describe the degree of association between features. The adjacency matrix can be constructed using metrics such as similarity or correlation between features. Based on the adjacency matrix, the Laplace matrix can be calculated, which usually has different forms such as standard Laplace matrix and symmetric normalized Laplace matrix. These matrices can capture the internal structure and association information of the data. Perform eigenvalue decomposition on the Laplace matrix to obtain its eigenvalues and corresponding eigenvectors. The eigenvalues corresponding to the eigenvectors can provide important information about the data structure, where the eigenvectors corresponding to smaller eigenvalues usually contain noise or irrelevant information. According to the size of the eigenvalues, the first k corresponding eigenvectors are selected as the final feature subspace. Usually, eigenvectors with larger eigenvalues are selected because the feature information they correspond to is more important.

Furthermore, the three-dimensional shape detection image in the image detection process section is obtained, and the three-dimensional shape detection image and the chip process parameters are pre-processed and input into the corresponding chip process detection model to obtain the process yield corresponding to the corresponding device node in the target time period, which includes: obtaining the three-dimensional shape detection image in the image detection process section, and pre-processing the three-dimensional shape detection image and the chip process parameters and inputting into the corresponding chip process detection model, wherein the chip process detection model includes an input layer, an attention mechanism layer, a feature fusion layer, a classification layer and an output layer; through the input layer The chip process parameters are subjected to data preprocessing and data feature extraction to obtain data features, and the three-dimensional morphology detection images are subjected to image preprocessing and image feature extraction to obtain image features; the attention weight vectors of the data features and the image features are respectively calculated through the attention mechanism layer; the data features and the image features are weightedly fused according to the weight vector through the feature fusion layer to obtain a fused feature vector; the process yield corresponding to the corresponding device node in the target time period is calculated according to the fused feature vector through the classification layer, and the process yield is output through the output layer.

Specifically, in practical applications, because data such as chip process parameters are all numerical data, and three-dimensional shape detection images are image data, a neural network model that fuses multiple types of features can be used to process numerical data and image data. The neural network model that fuses multiple types of features can use a multi-input model, a deep fusion model, or an attention fusion model, wherein the multi-input model can use numerical data and image data as different input layers, and merge them into one model through a connection layer. This method can use common convolutional neural networks, such as ResNet, EfficientNet, etc., or visual Transformer to process image data, and use a fully connected layer to process numerical data. The deep fusion model can send numerical data and image data to their respective neural networks for feature extraction and classification prediction, and connect their outputs to the fully connected layer for comprehensive learning and classification prediction. This method can use multiple neural network models, such as a convolutional neural network and a fully connected neural network, to process different types of features. This embodiment mainly uses an attention fusion model, which uses an attention mechanism to weightedly fuse different types of features. This method can extract features from numerical data and image data separately.

Specifically, the input layer performs data preprocessing and data feature extraction on the numerical data to obtain data features, and performs image feature extraction on the image data such as the three-dimensional shape detection image to obtain image features, wherein for the numerical data, the numerical data is used as the neurons of the input layer, and feature extraction and transformation are performed through some fully connected layers to obtain a numerical feature vector with a dimension of d. The image feature extraction can use a visual Transformer (such as ViT) to process the image data and extract image features. Assuming that an image feature vector with a dimension of d is obtained, the attention mechanism is used in the attention mechanism layer to weightedly fuse the numerical features and image features. The self-attention mechanism can be used to calculate the importance weight of each feature, and the attention weight vector of the numerical features and image features is obtained. Then, the numerical feature vector and the image feature vector are weightedly fused according to the attention weight to obtain the final fused feature vector, and finally the fused feature vector is input into the fully connected layer for classification prediction. This layer can include multiple fully connected layers, activation functions, and loss functions for model training and optimization.

Furthermore, before obtaining the three-dimensional morphology detection image in the image detection process section and pre-processing the three-dimensional morphology detection image and the chip process parameters and inputting them into the corresponding chip process detection model, it also includes: obtaining the resolution of the optical lens equipment corresponding to each image process section, and calculating the number of scanning layers corresponding to each image process section according to a preset super-depth of field synthetic imaging algorithm and the resolution; based on the number of scanning layers, controlling the optical lens equipment of the corresponding image process section to perform three-dimensional morphology detection on the target chip produced in the target time period, and obtaining depth images of different scanning layers of each image process section; splicing and merging the depth images of different scanning layers to generate three-dimensional morphology detection images of each image process section.

Specifically, first of all, it is necessary to understand the resolution of the optical lens device used, that is, the image details and pixel density that can be captured. This is an important parameter for calculating the number of scanning layers. According to the preset super-depth synthetic imaging algorithm and the resolution of the optical lens device, the number of scanning layers required for each image process segment can be calculated. The super-depth synthetic imaging algorithm can expand the clear area of the image by multiple focusing or superposition of multiple images. According to the calculated number of scanning layers, the corresponding optical lens device is used to perform three-dimensional morphology detection on the target chip. By scanning different scanning layers, the depth information of each image process segment can be obtained. Finally, the depth images of different scanning layers are spliced and merged to generate the final three-dimensional morphology detection image. In this way, the complete three-dimensional morphology information of each image process segment can be obtained. Among them, for each image process segment, a three-dimensional morphology detection is first performed to obtain the depth images of different scanning layers. Ensure that each depth image is aligned with the same coordinate system and has the same size and image format. Since there may be slight position deviations between different scanning layers, image alignment operations are required. Specific image registration algorithms, such as feature matching, phase correlation, mutual information, etc., can be used to align each pair of adjacent depth images so that they have consistent features in the same area. The aligned depth images are fused to generate the final three-dimensional shape detection image. Common fusion methods include weighted averaging, image fusion algorithms (such as Poisson reconstruction), multi-view stereo matching, etc. During the fusion process, the weights of different depth images can be adjusted according to actual needs to control the contribution of different scanning layers. Finally, as needed, the fused image can be further post-processed, such as denoising, smoothing, edge enhancement, etc., to improve image quality and clarity and obtain a three-dimensional shape detection image.

Furthermore, the process yield corresponding to the corresponding device node in the target time period is calculated according to the fused feature vector through the classification layer, and the process yield is output through the output layer, including: linearly transforming the fused feature vector to a high-dimensional feature space through the classification layer to obtain a linear transformation result; nonlinearly transforming the linear transformation result through a preset activation function to obtain a nonlinear transformation result; calculating the probability of the process yield interval corresponding to the corresponding device node in the target time period according to the nonlinear transformation result through the fully connected layer in the classification layer; taking the process yield interval with the highest probability as the process yield corresponding to the corresponding device node in the target time period, and outputting the process yield through the output layer.

Specifically, the obtained fused feature vector is used as the input of the fully connected layer, and the fused feature vector is mapped to a higher-dimensional feature space through a linear transformation. This linear transformation is usually a fully connected layer, which contains multiple neurons (nodes), each of which is connected to each element of the fused feature vector. The result of the linear transformation is nonlinearly transformed, and a nonlinear relationship is introduced to increase the expressive power of the model. Common activation functions include ReLU, sigmoid, tanh, etc. The choice of activation function depends on the specific task and model design. The design of the output layer will also vary depending on the task. For example, for a binary classification task, a neuron can be used and a sigmoid activation function can be applied to output a probability value between 0 and 1; for a multi-classification task, multiple neurons can be used and a softmax activation function can be applied to output the probability distribution of each category. According to the results of the output layer, the process yield corresponding to the corresponding device node in the target time period is obtained.

103. Calculate the process pass rate of the target LED chips produced in the target time period based on the weight data corresponding to each device node and the corresponding process yield rate;

In one embodiment of the present invention, the weights of different device nodes can be determined based on the degree of their influence on the chip process. For example, for key nodes such as lithography equipment and etching equipment, their weights may be higher because they play a decisive role in the pattern and structural morphology of the chip; while the weights of nodes such as wafer processing equipment and deposition equipment may be slightly lower because they have a relatively small influence on the surface morphology and material properties of the chip. When calculating the process pass rate of the target LED chip produced in the target time period, the weight of each device node and the process yield can be combined for use. For example, for a process flow consisting of 5 device nodes, their weights are set to w1, w2, w3, w4, and w5 respectively, and the corresponding process yields are r1, r2, r3, r4, and r5, then the comprehensive process yield of the process flow can be calculated as:

Comprehensive process yield = w1×r1 + w2×r2 + w3×r3 + w4×r4 + w5×r5

Finally, based on the calculated comprehensive process yield, the process pass rate of the target LED chips produced in the target time period can be predicted. If the comprehensive process yield is high, the predicted process pass rate will also increase accordingly, otherwise it will decrease. In addition, in actual production, the process can be adjusted and optimized based on real-time monitoring data to further improve the process pass rate.

104. Determine the product grade of the target LED chip produced in the target time period based on the process pass rate, and determine whether the product grade is a preset defective grade;

In one embodiment of the present invention, in the production process of LED chips, the process pass rate is an important indicator for evaluating the quality of the chip. When determining the product grade of the target LED chip produced in the target time period, the process pass rate can be used to determine whether the quality of the chip meets expectations, and the chip can be divided into different grades. Generally speaking, the higher the process pass rate, the higher the quality of the chip. Therefore, in the case of a high process pass rate, the produced chips can often be classified as high-grade products. For example, a chip with a process pass rate of more than 90% may be classified as a grade A product, a chip with a process pass rate between 80% and 90% may be classified as a grade B product, and a chip with a process pass rate below 80% may be classified as a grade C product. In addition, while judging the product grade, it is also necessary to determine whether the chip is a defective product. Generally speaking, for a preset defective product grade, only chips with a process pass rate below a certain value (such as 20%) will be identified as defective products. If the process pass rate of the chip is higher than the threshold, it may be identified as a qualified product even if there are some defects or flaws. In actual production, the specific product grade and defective product grade classification standards can be formulated according to the actual situation of the enterprise and market demand. In order to ensure that the quality of chips produced meets customer requirements, companies need to strengthen management in process control, equipment maintenance, etc., continuously improve the process pass rate, and promptly adjust the grade classification standards to adapt to changes in market demand.

105. If yes, perform chip electrical testing on the target LED chips produced in the target time period to obtain chip defect detection results.

In one embodiment of the present invention, the products identified as defective products in the above steps are subjected to secondary inspection, that is, the electrical inspection requires the chip pins to be connected to the test instrument so as to conduct electrical testing on the chip. This step requires careful planning of the wiring scheme to ensure the correct transmission and collection of the test signal. In this process, electrode alignment is required. Electrode alignment refers to the use of metal needles or probes to make precise contact on the chip pins to ensure the reliability of the test signal transmission and the accuracy of the test results. In chip electrical testing, electrode alignment is a very important step, which is related to the accuracy of the test data and the credibility of the test results. Because the chip pin spacing is very small, sometimes only tens of microns or even smaller, and the number of pins is usually large, high-precision equipment and technology are required to achieve electrode alignment. Generally speaking, electrode alignment requires the use of special needles or probes, which have very small diameters and high-precision tips, and can easily and accurately locate and contact the chip pins. It should be noted that when performing electrode alignment, relevant safety specifications and operating procedures should be followed to avoid damaging the chip or test instrument, and the needles or probes should also be protected to avoid affecting the test results. In addition, before electrode alignment, relevant test instrument calibration and test procedure writing are required to ensure the accuracy and reliability of the test results.

In this embodiment, by selecting corresponding multiple chip process detection models according to multiple device nodes, and inputting the chip process data of each device node in the target time period into the corresponding chip process detection model, the corresponding process yield is obtained; the process pass rate of the target LED chip produced in the target time period is calculated based on the weight data corresponding to each device node and the corresponding process yield; based on the process pass rate, it is determined whether the product grade of the target LED chip is a preset defective grade; the target LED chip of the defective grade is subjected to chip electrical detection to obtain the chip defect detection result. This method uses the process data at different process steps before the LED chip is subjected to electrical detection to predict the product's shipping quality and grade, and only conducts electrical testing on defective products, thereby reducing the electrical testing cost and reducing the secondary defect rate caused by product electrical testing.

The above describes the LED chip defect detection method in the embodiment of the present invention. The following describes the LED chip defect detection device in the embodiment of the present invention. The LED chip defect detection device is applied to the LED chip production system. The LED chip production system includes multiple device nodes corresponding to multiple process stages of the LED chip during the process. Please refer to FIG. 2. An embodiment of the LED chip defect detection device in the embodiment of the present invention includes:

An acquisition module 201 is used to acquire chip process data of each device node in the LED chip production system in a target time period;

The yield calculation module 202 is used to select corresponding multiple chip process detection models according to the multiple device nodes, and input the chip process data into the corresponding chip process detection model to obtain the process yield of the corresponding device node in the target time period;

A pass rate calculation module 203, used to calculate the process pass rate of the target LED chips produced in the target time period based on the weight data corresponding to each device node and the corresponding process yield;

A judgment module 204 is used to determine the product grade of the target LED chips produced in the target time period based on the process pass rate, and to judge whether the product grade is a preset defective grade;

The electrical inspection module 205 is used to perform chip electrical inspection on the target LED chips produced in the target time period to obtain chip defect inspection results if the product grade is a defective grade.

In an embodiment of the present invention, the LED chip defect detection device runs the above-mentioned LED chip defect detection method, wherein the LED chip defect detection device selects corresponding multiple chip process detection models according to multiple device nodes, and inputs the chip process data of each device node in the target time period into the corresponding chip process detection model to obtain the corresponding process yield; calculates the process pass rate of the target LED chip produced in the target time period based on the weight data corresponding to each device node and the corresponding process yield; determines whether the product grade of the target LED chip is a preset defective grade based on the process pass rate; performs chip electrical detection on the target LED chip of the defective grade to obtain the chip defect detection result. This method uses the process data at different process steps before the LED chip is electrically tested to predict the product's shipping quality and grade, and only performs electrical testing on defective products, thereby reducing the electrical testing cost and reducing the secondary defect rate caused by product electrical testing.

FIG. 2 above describes in detail the LED chip defect detection device in the embodiment of the present invention from the perspective of modular functional entities, and the following describes in detail the LED chip defect detection device in the embodiment of the present invention from the perspective of hardware processing.

FIG3 is a schematic diagram of the structure of an LED chip defect detection device provided by an embodiment of the present invention. The LED chip defect detection device 300 may have relatively large differences due to different configurations or performances, and may include one or more processors (central processing units, CPU) 310 (for example, one or more processors) and a memory 320, and one or more storage media 330 (for example, one or more mass storage devices) storing application programs 333 or data 332. Among them, the memory 320 and the storage medium 330 may be temporary storage or permanent storage. The program stored in the storage medium 330 may include one or more modules (not shown in the figure), and each module may include a series of instruction operations in the LED chip defect detection device 300. Furthermore, the processor 310 may be configured to communicate with the storage medium 330, and execute a series of instruction operations in the storage medium 330 on the LED chip defect detection device 300 to implement the steps of the above-mentioned LED chip defect detection method.

The LED chip defect detection device 300 may further include one or more power supplies 340, one or more wired or wireless network interfaces 350, one or more input and output interfaces 360, and/or one or more operating systems 331, such as Windows Serve, Mac OS X, Unix, Linux, FreeBSD, etc. Those skilled in the art will appreciate that the structure of the LED chip defect detection device shown in FIG. 3 does not limit the LED chip defect detection device provided by the present invention, and may include more or less components than shown in the figure, or combine certain components, or arrange components differently.

The present invention also provides a computer-readable storage medium, which may be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium. Instructions are stored in the computer-readable storage medium. When the instructions are executed on a computer, the computer executes the steps of the LED chip defect detection method.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described system, device, or unit can refer to the corresponding process in the aforementioned method embodiment and will not be repeated here.

If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the whole or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (9)

1. The LED chip defect detection method is characterized by being applied to an LED chip production system, wherein the LED chip production system comprises a plurality of equipment nodes corresponding to a plurality of process sections of an LED chip in the process; the LED chip defect detection method comprises the following steps:

acquiring chip process data of each equipment node in the LED chip production system in a target time period;

Selecting a plurality of corresponding chip process detection models according to the plurality of equipment nodes, and respectively inputting the chip process data into the corresponding chip process detection models to obtain the process yield of the corresponding equipment nodes in the target time period; the chip process data comprise chip process parameters and/or three-dimensional morphology detection images; the step of respectively selecting a plurality of corresponding chip process detection models according to the plurality of equipment nodes, respectively inputting the chip process data into the corresponding chip process detection models, and obtaining the process yield of the equipment nodes corresponding to the target time period comprises the following steps: respectively selecting a plurality of corresponding chip process detection models according to the plurality of equipment nodes, and determining whether a process section corresponding to the corresponding equipment nodes is an image detection process section according to the equipment types of the plurality of equipment nodes; if yes, acquiring a three-dimensional morphology detection image in the image detection processing section, preprocessing the three-dimensional morphology detection image and the chip processing parameters, and inputting the preprocessed three-dimensional morphology detection image and the preprocessed chip processing parameters into a corresponding chip processing detection model to obtain the processing yield of the corresponding equipment node in the target time section; if not, the chip process parameters are preprocessed and then respectively input into corresponding chip process detection models, so that the process yield of the corresponding equipment nodes in the target time period is obtained;

Calculating the process passing rate of the target LED chip produced in the target time period based on the weight data corresponding to each equipment node and the corresponding process yield;

determining the product grade of the target LED chip produced in the target time period based on the process passing rate, and judging whether the product grade is a preset defective grade or not;

If yes, the chip electrical detection is carried out on the target LED chip produced in the target time period, and a chip defect detection result is obtained.

2. The method for detecting defects of an LED chip according to claim 1, wherein said preprocessing the chip process parameters and then inputting the preprocessed chip process parameters into corresponding chip process detection models, respectively, to obtain the process yield of the corresponding equipment node corresponding to the target time period comprises:

the chip process parameters are preprocessed and then respectively input into corresponding chip process detection models, wherein the chip process detection models comprise an input layer, a cross layer, a depth layer, a combination layer and an output layer;

Performing data preprocessing and data feature extraction on the chip process parameters through the input layer to obtain a plurality of data features;

performing first feature association processing on the plurality of data features through the cross layer to obtain first association features, and performing second feature association processing on the plurality of data features through the depth layer to obtain second association features;

and connecting the first association feature and the second association feature through the combination layer, and calculating the process yield of the corresponding equipment node in the target time period through an activation function by using the connected feature vector.

3. The method for detecting defects of an LED chip according to claim 2, wherein said performing data preprocessing and data feature extraction on said chip process parameters through said input layer, obtaining data features comprises:

performing feature extraction on the chip process parameters through the input layer to obtain first feature data;

Generating an adjacency matrix according to the first characteristic data, and calculating a corresponding Laplace matrix based on the adjacency matrix;

performing eigenvalue decomposition on the Laplace matrix to obtain a plurality of eigenvectors and corresponding eigenvalues, and screening the eigenvectors according to the eigenvalue sizes to obtain corresponding eigenvalue subspaces;

And acquiring second characteristic data based on the characteristic subspace, and carrying out iterative processing on the second characteristic data according to a particle swarm algorithm to obtain data characteristics.

4. The method of claim 2, wherein the obtaining a three-dimensional feature detection image in the image detection process segment, preprocessing the three-dimensional feature detection image and the chip process parameters, and inputting the preprocessed three-dimensional feature detection image and the preprocessed chip process parameters into a corresponding chip process detection model, and obtaining a process yield corresponding to the corresponding equipment node in the target time segment comprises:

acquiring a three-dimensional morphology detection image in the image detection processing section, preprocessing the three-dimensional morphology detection image and the chip processing parameters, and inputting the preprocessed three-dimensional morphology detection image and the preprocessed three-dimensional morphology detection image into a corresponding chip processing detection model, wherein the chip processing detection model comprises an input layer, an attention mechanism layer, a feature fusion layer, a classification layer and an output layer;

Performing data preprocessing and data feature extraction on the chip process parameters through the input layer to obtain data features, and performing image preprocessing and image feature extraction on the three-dimensional morphology detection image to obtain image features;

calculating attention weight vectors of the data features and the image features through the attention mechanism layer respectively;

the feature fusion layer carries out weighted fusion on the data features and the image features according to the weight vector to obtain a fusion feature vector;

And calculating the process yield of the corresponding equipment node in the target time period according to the fusion feature vector through the classification layer, and outputting the process yield through the output layer.

5. The method of claim 4, further comprising, before the step of obtaining the three-dimensional topography detection image in the image detection process section and preprocessing the three-dimensional topography detection image and the chip process parameters and inputting the preprocessed three-dimensional topography detection image and the chip process parameters into a corresponding chip process detection model:

The method comprises the steps of obtaining the resolution of optical lens equipment corresponding to each image processing section, and calculating the number of scanning layers corresponding to each image processing section according to a preset super-depth-of-field synthetic imaging algorithm and the resolution;

the optical lens equipment of the corresponding image processing section is controlled based on the scanning layer number to perform three-dimensional morphology detection on the target chip produced in the target time section, so that depth images of different scanning layers of each image processing section are obtained;

and combining the depth images of the different scanning layers to generate three-dimensional morphology detection images of each image processing section.

6. The method of claim 4, wherein the calculating, by the classification layer, a process yield of the corresponding device node in the target period according to the fusion feature vector, and outputting, by the output layer, the process yield comprises:

mapping the fusion feature vector to a high-dimensional feature space through the classification layer in a linear transformation way to obtain a linear transformation result;

Nonlinear transformation is carried out on the linear transformation result through a preset activation function, and a nonlinear transformation result is obtained;

Calculating the probability of the corresponding equipment node in the process yield interval corresponding to the target time period according to the nonlinear transformation result through a full-connection layer in the classification layer;

And taking the process yield interval with the highest probability as the process yield corresponding to the corresponding equipment node in the target time period, and outputting the process yield through the output layer.

7. The LED chip defect detection device is characterized by being applied to an LED chip production system, wherein the LED chip production system comprises a plurality of equipment nodes corresponding to a plurality of process sections of an LED chip in the process; the LED chip defect detection device comprises:

the acquisition module is used for acquiring chip process data of each equipment node in the LED chip production system in a target time period;

The yield calculation module is used for respectively selecting a plurality of corresponding chip process detection models according to the plurality of equipment nodes, and respectively inputting the chip process data into the corresponding chip process detection models to obtain the process yield of the corresponding equipment nodes in the target time period; the chip process data comprise chip process parameters and/or three-dimensional morphology detection images; the step of respectively selecting a plurality of corresponding chip process detection models according to the plurality of equipment nodes, respectively inputting the chip process data into the corresponding chip process detection models, and obtaining the process yield of the equipment nodes corresponding to the target time period comprises the following steps: respectively selecting a plurality of corresponding chip process detection models according to the plurality of equipment nodes, and determining whether a process section corresponding to the corresponding equipment nodes is an image detection process section according to the equipment types of the plurality of equipment nodes; if yes, acquiring a three-dimensional morphology detection image in the image detection processing section, preprocessing the three-dimensional morphology detection image and the chip processing parameters, and inputting the preprocessed three-dimensional morphology detection image and the preprocessed chip processing parameters into a corresponding chip processing detection model to obtain the processing yield of the corresponding equipment node in the target time section; if not, the chip process parameters are preprocessed and then respectively input into corresponding chip process detection models, so that the process yield of the corresponding equipment nodes in the target time period is obtained;

The passing rate calculation module is used for calculating the process passing rate of the target LED chip produced in the target time period based on the weight data corresponding to each equipment node and the corresponding process yield;

The judging module is used for determining the product grade of the target LED chip produced in the target time period based on the process passing rate and judging whether the product grade is a preset defective grade or not;

and the electric detection module is used for carrying out chip electric detection on the target LED chip produced in the target time period if the product grade is a defective grade, so as to obtain a chip defect detection result.

8. An LED chip defect detection apparatus, characterized in that the LED chip defect detection apparatus comprises: a memory and at least one processor, the memory having instructions stored therein;

The at least one processor invokes the instructions in the memory to cause the LED chip defect detection apparatus to perform the steps of the LED chip defect detection method according to any one of claims 1-6.

9. A computer readable storage medium having instructions stored thereon, which when executed by a processor, implement the steps of the LED chip defect detection method according to any of claims 1-6.