CN118103975A - Chip and electronic equipment - Google Patents

Abstract

The application provides a chip and electronic equipment, which can reduce time delay, power and cost and can be applied to the electronic equipment. The chip comprises: handle wafer, connect wafer, and memory wafer (memory die). Wherein the handle wafer and the storage wafer are disposed on the same side surface of the connection wafer. The connection wafer is coupled with the processing wafer and with the storage wafer for coupling the processing wafer with the storage wafer.

Description

Chips and electronic devices Technical Field

The present application relates to the field of microelectronics technology, and in particular to a chip and an electronic device.

Background technique

High bandwidth memory (HBM) has a high bandwidth and can be used in scenarios with high bandwidth requirements, such as graphics processors or network switching and forwarding equipment.

At present, the data of the memory can be read and written based on the control circuit. Specifically, as shown in Figures 1 and 2, the memory includes a memory chip 101 and a logic chip 102, the logic chip 102 and the processing chip (main die) 103 shown in Figure 2 are both arranged on the same side surface of the connector 104 (such as an interposer) shown in Figure 2, and the memory chip 101 is arranged on the side of the logic chip 102 away from the connector 104. A control circuit 1020 for controlling the memory chip 101 is arranged in the logic chip 102, and the control circuit 1020 in the logic chip 102 is coupled to the memory chip 101 and the processing chip 103 respectively, so as to realize the data reading and writing function.

However, in the above solution, when data is transmitted between the processing chip 103 and the storage chip 101, it needs to pass through the logic chip 102 and the connector 104. The long transmission path may cause high latency and power consumption in reading and writing data.

Summary of the invention

The embodiments of the present application provide a chip and an electronic device, which can reduce the number of connection levels between a storage chip and a processing chip, thereby reducing latency and lowering power consumption.

In order to achieve the above objectives, this application adopts the following technical solutions:

In a first aspect, a chip is provided. The chip includes: a processing chip, a connection chip and a storage chip. The processing chip and the storage chip are arranged on the connection chip. The connection chip includes a control circuit. The control circuit is coupled to the processing chip and to the storage chip, and is used to couple the processing chip to the storage chip. The control circuit is used to control the storage chip.

Based on the chip provided in the first aspect, by integrating a control circuit in a connecting chip, the processing chip and the storage chip can be coupled through a connecting chip, such as an interposer or a control circuit in an embedded bridge. In this way, the connecting chip can be reused to shorten the length of the data transmission path between the processing chip and the storage chip, thereby reducing latency and power consumption. There is no need to set up a separate logic chip (logic die), which can simplify the chip structure and reduce costs.

Optionally, the connection wafer may include a first region corresponding to the processing wafer, wherein a first terminal group is disposed in the first region, and the first terminal group is coupled to the processing wafer and to the control circuit.

Furthermore, there may be a plurality of first regions, each of which is provided with a first end group, each of which corresponds to a processing wafer, and the first end group in each first region is coupled to the corresponding processing wafer.

Thus, coupling the storage chip with multiple processing chips can realize the reading and writing of the storage chip by multiple processing chips. In addition, coupling the first end group in each first region with the corresponding processing chip can reduce the delay difference of different processing chips accessing the storage chip.

In a possible design solution, the connection wafer may be an interposer.

In another possible design, the connecting chip may be an embedded bridge, so that the structures of different process steps can be closely combined through the embedded bridge, thereby reducing the size of the chip, further reducing the delay and reducing power consumption.

Optionally, the chip of the first aspect may further include a substrate, and the substrate may include a first surface and a second surface opposite to the first surface. A first groove is provided on the first surface, the embedded bridge is provided in the first groove, the processing wafer and the storage wafer are provided on a side of the embedded bridge away from the second surface, and the processing wafer is coupled to the substrate.

In this way, the control circuit can be set inside, further shortening the data transmission distance between the processing chip and the storage chip, thereby further reducing the delay and reducing power consumption.

In a second aspect, an electronic device is provided, comprising a printed circuit board and the chip as described in the first aspect, wherein the chip is disposed on the printed circuit board and coupled to the printed circuit board.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of a memory in the prior art;

FIG2 is a schematic diagram of a chip in the prior art;

FIG3 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

FIG4 is a schematic diagram 1 of a chip provided in an embodiment of the present application;

FIG5 is a second schematic diagram of a chip provided in an embodiment of the present application;

FIG6 is a schematic diagram 1 of a memory provided in an embodiment of the present application;

FIG7 is a second schematic diagram of a memory provided in an embodiment of the present application;

FIG8 is a third schematic diagram of a chip provided in an embodiment of the present application;

FIG9 is a fourth schematic diagram of a chip provided in an embodiment of the present application;

FIG10 is a fifth schematic diagram of a chip provided in an embodiment of the present application;

FIG. 11 is a sixth schematic diagram of the chip provided in an embodiment of the present application.

Figure markings: 101-storage chip; 102-logic chip; 1020-control circuit; 103-processing chip; 104-connector; 20-printed circuit board; 30-chip; 301-connection chip; 3010-control circuit; 302-processing chip; 303-storage chip; 304-first end group; 305-first connection layer; 306-through hole; 307-second connection layer; 308-substrate.

Detailed ways

The technical terms involved in the embodiments of the present application are explained below.

1. High bandwidth memory (HBM) is a high-performance dynamic random access memory (DRAM) that can be used in application scenarios with high memory bandwidth requirements.

At present, HBM can be formed based on a three-dimensional (3D) stacking process. As shown in FIG1 , illustratively, in an HBM based on a 3D stacking process, a memory chip 101 is stacked (stacking) on a logic chip 102, and is coupled to a control circuit 1020 in the logic chip 102 based on through silicon vias (TSV) technology. Compared with a double data rate memory (DDR) 4 and a graphics double data rate memory (GDDR) 5, the HBM not only has a smaller volume and lower power, but also has a higher bandwidth. Taking an HBM including four memory chips 101 as an example, if each memory chip 101 has two 128-bit channels, the four memory chips 101 have a total of 8 128-bit channels.

The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features.

In addition, in the present application, directional terms such as "upper" and "lower" are defined relative to the orientation of the components in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they can change accordingly according to the changes in the orientation of the components in the drawings.

In this application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium. In addition, the term "coupling" can be a way of achieving electrical connection for signal transmission. "Coupling" can be a direct electrical connection or an indirect electrical connection through an intermediate medium.

The embodiment of the present application provides an electronic device. The electronic device may include electronic devices such as servers and supercomputers. It is understood that the electronic device may also include electronic devices for industrial control or electronic devices for data centers. The embodiment of the present application does not impose any special restrictions on the specific form of the above electronic devices.

As shown in FIG3 , the electronic device includes a printed circuit board (PCB) 20 and a chip 30 . The chip 30 is disposed on the PCB 20 and coupled to the PCB 20 .

The chip 30 is described in detail below in conjunction with FIG. 4 to FIG. 11 .

FIG4 is a chip 30 provided in an embodiment of the present application. As shown in FIG4 , the chip 30 includes: a connection chip 301 , a processing chip (main die) 302 , and a memory chip (memory die) 303 .

FIG5 is a schematic diagram of the cross-sectional structure along the A-A direction in FIG4. Taking the orientation of the structure shown in FIG5 as an example, the processing chip 302 and the storage chip 303 are arranged on the connection chip 301. Exemplarily, the processing chip 302 and the storage chip 303 can be located on the same side of the connection chip 301. For example, the processing chip 302 and the storage chip 303 are both arranged on the upper surface of the connection chip 301. When describing the positional relationship between the components in the chip 30 below, this orientation is used as a reference.

In addition, the connection chip 301 is coupled to the processing chip 302 and coupled to the memory chip 303 , thereby coupling the processing chip 302 and the memory chip 303 .

In the embodiment of the present application, the processing chip 302 is a chip with data processing functions, such as a central processing unit (CPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC) or a graphics processing unit (GPU), but the embodiment of the present application is not limited to this.

In the embodiment of the present application, the memory chip 303 is a chip for storing information. Exemplarily, the memory chip 303 may be a static random access memory (SRAM), or a ferroelectric random access memory (FeRAM), or a magnetic random access memory (MRAM). In the embodiment of the present application, the type of the memory chip 303 is not limited.

It should be noted that, in the embodiment of the present application, the storage chip 303 may be one or more. If there are multiple storage chips 303, the storage chips 303 may be stacked. Exemplarily, the stacked storage chips 303 may be coupled with the connection chip 301, such as being coupled with the connection chip 301 through silicon via technology. Exemplarily, a through hole 306 may be provided on both the storage chip 303 and the connection chip 301, and a metal is provided in the through hole 306 for interconnection. The storage chip 303 is coupled with the conductor in the through hole 306, and the connection chip 301 is coupled with the conductor in the through hole 306. The conductor in the through hole 306 of the storage chip 303 may be coupled with the connection chip 301 by means of a bump, or may be coupled with the connection chip 301 by means of hybrid bonding. It should be noted that the through hole 306 may be a through silicon via. In this way, the coupling between the storage chip 303 and the connection chip 301 can be achieved. It is understandable that in the embodiment of the present application, the storage chips 303 can also be arranged side by side on the upper surface of the connection chip 301.

In addition, in the embodiment of the present application, the connection chip 301 includes a control circuit 3010. The control circuit 3010 is coupled to the processing chip 302 and to the storage chip 303, thereby coupling the processing chip 302 to the storage chip 303. The control circuit 3010 is used to control the storage chip 303.

Exemplarily, the control circuit 3010 may include one or more of the following: a memory controller, a design for test (DFT) logic circuit, a physical layer circuit, an input/output (IO) port, a clock (CLK) circuit, and a power circuit. The specific implementation of the control circuit 3010 may refer to the existing implementation method, which will not be described here.

It should be noted that in the embodiment of the present application, other circuits may be provided in the connection chip 301, such as other circuits related to the business processed by the chip 30 in the device to which the chip 30 is applicable.

In this way, by integrating the control circuit 3010 in the connecting chip 301, the processing chip 302 and the storage chip 303 can be coupled through the connecting chip 301, such as the control circuit 3010 in the intermediate layer or the embedded bridge. In this way, the connecting chip 301 can be reused to shorten the length of the data transmission path between the processing chip 302 and the storage chip 303, thereby reducing the delay and power consumption. There is no need to set up a separate logic chip (logic die), which can simplify the structure of the chip 30 and reduce costs.

The chip 30 is described below with reference to its specific structure.

As shown in FIG5 , optionally, the connection wafer 301 includes a first region corresponding to the processing wafer 302 , and a first terminal group 304 is disposed in the first region. The first terminal group 304 is coupled to the processing wafer 302 and coupled to the control circuit 3010 .

Exemplarily, the first region may be located on the upper surface of the connection wafer 301, and the first region is located at the periphery of the side surface of the storage wafer 303. The side surface of the storage wafer 303 is the surface of the storage wafer 303, except the upper surface and the lower surface of the storage wafer 303. The first end group 304 may be a bump, such as a micro bump, a solder bump, or a solder ball, or a copper pillar. The specific implementation of the first end group 304 is not limited in the embodiment of the present application.

As shown in FIG6 , in some possible implementations, there may be one first region. Exemplarily, the first region may be located on the connection wafer 301 on the left side of the storage wafer 303 .

In this case, as shown in FIG. 5 , at least a portion of the projection of the handling wafer 302 on the connecting wafer 301 is located within the first region.

As shown in Fig. 7, in some other possible implementations, there may be multiple first regions, each of which is provided with a first end group 304. The following takes two first regions as an example for explanation.

As shown in FIG7 , there are two first regions. One first region may be located on the connection wafer 301 on the left side of the storage wafer 303. Another first region may be located on the connection wafer 301 on the right side of the storage wafer 303. In this case, in combination with FIG7 , as shown in FIG8 , each first region corresponds to a processing wafer 302 , and the first end group 304 in each first region is coupled to the corresponding processing wafer 302 .

Exemplarily, a first end group 304 is disposed in the first region on the left side of the storage chip 303, and another first end group 304 is disposed in the first region on the right side of the storage chip 303. The first end group 304 on the left side of the storage chip 303 is coupled to one processing chip 302, and the first end group 304 on the right side of the storage chip 303 is coupled to another processing chip 302.

Based on this, at least a portion of the projection of the processing wafer 302 corresponding to a first area on the connecting wafer 301 is located within the first area.

In this way, by coupling the storage chip 303 with multiple processing chips 302, the multiple processing chips 302 can realize the read and write functions of the storage chip 303. In addition, the first end group 304 in each first region is coupled with the corresponding processing chip 302, which can reduce the delay difference of different processing chips 302 accessing the storage chip 303.

It should be noted that, in the embodiment of the present application, the number of the first regions may also be three, four or more. When the number of the first regions is greater than or equal to three, the connection method between the processing wafer 302 and the connection wafer 301 may refer to the connection method when the number of the first regions is two, and will not be repeated here.

It can be understood that the storage chip 303 can also be set at other positions on the side of the storage chip 303, which is not limited in the embodiments of the present application.

The following takes a first area as an example to describe in detail the configuration of the processing chip 302 and the storage chip 303 in combination with the specific type of the connection chip 301 .

In a possible design, as shown in any one of FIG. 4, FIG. 5, FIG. 8 or FIG. 9, the connection wafer 301 may be an interposer. In this case, the silicon substrate of the connection wafer 301 includes wiring for interconnection, control circuit 3010 and other active devices. In this case, the interposer may be called an active interposer.

Based on this, the storage chip 303 is disposed on the connection chip 301. In other words, the projection of the storage chip 303 in the vertical direction is entirely located within the upper surface of the connection chip 301.

Optionally, as shown in FIG. 5 or FIG. 8 , the chip 30 may further include a first connection layer 305. The first connection layer 305 is arranged side by side with the connection wafer 301. Exemplarily, the connection wafer 301 is arranged on the upper surface of the substrate 308, and the first connection layer 305 is arranged on the upper surface of the substrate 308. In this case, a part of the processing wafer 302 is arranged on the connection wafer 301, and another part of the processing wafer 302 is arranged on the first connection layer 305, that is, a part of the projection of the processing wafer 302 in a direction perpendicular to the upper surface of the connection wafer 301 is located in the upper surface of the connection wafer 301, and another part is located in the upper surface of the first connection layer 305.

The first connection layer 305 may also be an intermediate layer.

Alternatively, as shown in Fig. 9, the projection of the processing wafer 302 on the connecting wafer 301 may be entirely located within the first region corresponding to the processing wafer 302. For example, in combination with a first region shown in Fig. 6, as shown in Fig. 9, the processing wafer 302 is entirely disposed on the upper surface of the connecting wafer 301, that is, the projection of the processing wafer 302 in the vertical direction is located on the upper surface of the connecting wafer 301.

In the embodiment of the present application, the interposer is a semiconductor structure with through holes and routings for interconnection. The through holes and routings of the interposer can be used to couple the pins of two different components. In other words, data can reach another component through the interposer.

In another possible design, as shown in FIG10 or FIG11 , the connection wafer 301 may be an embedded bridge. In this case, the silicon substrate of the connection wafer 301 includes wiring for interconnection, control circuit 3010 and other active devices.

It should be noted that in the embodiments of the present application, the above-mentioned embedded bridge can be an embedded multi-die interconnect bridge (EMIB) or a fan-out embedded bridge (fin out embedded bridge).

At this time, optionally, as shown in FIG. 10 , the chip 30 may further include a substrate 308, the substrate 308 including a first surface and a second surface opposite to the first surface. Assume that the upper surface of the substrate 308 is the first surface of the substrate 308, and the lower surface of the substrate 308 is the second surface. A first groove is provided on the first surface, that is, the first groove is provided on one side of the upper surface of the substrate 308. The connecting wafer 301, that is, the embedded bridge is provided in the first groove, and the processing wafer 302 and the storage wafer 303 are provided on one side of the first surface, that is, the processing wafer 302 and the storage wafer 303 are provided on one side of the upper surface of the substrate 308.

In this way, the transmission distance of data between the processing chip 302 and the storage chip 303 can be further shortened, thereby further reducing the delay and the power consumption. In addition, the processing chip 302 can be coupled to the substrate 308 .

10 , a portion of the storage wafer 303 is disposed on the upper surface of the connection wafer 301, and another portion of the storage wafer 303 is disposed on the upper surface of the substrate 308. In other words, a portion of the projection of the storage wafer 303 in the vertical direction is on the upper surface of the connection wafer 301, and another portion is on the upper surface of the substrate 308.

In addition, a portion of the processing wafer 302 is disposed on the upper surface of the connection wafer 301, and another portion of the processing wafer 302 is disposed on the first surface of the substrate 308, that is, the upper surface of the substrate 308. In other words, a portion of the projection of the processing wafer 302 in the vertical direction is on the upper surface of the connection wafer 301, and another portion is on the upper surface of the substrate 308.

Alternatively, as shown in FIG. 11 , the chip 30 may further include a second connection layer 307. The second connection layer 307 may be an interposer or a redistribution layer (RDL). A second groove is disposed on one surface, such as the upper surface, of the second connection layer 307. The connection wafer 301, i.e., the embedded bridge, may be disposed in the second groove on the second connection layer 307.

Exemplarily, as shown in FIG11 , a portion of the storage chip 303 is disposed on the upper surface of the connection chip 301, that is, the embedded bridge, and another portion of the storage chip 303 is disposed on the upper surface of the second connection layer 307. In other words, a portion of the projection of the storage chip 303 in the vertical direction is on the upper surface of the connection chip 301, and another portion is on the upper surface of the second connection layer 307.

Similarly, the first region may also be disposed on the upper surface of the connection wafer 301, a portion of the processing wafer 302 may be disposed on the upper surface of the connection wafer 301, and another portion of the processing wafer 302 may be disposed on the upper surface of the second connection layer 307. In other words, a portion of the projection of the processing wafer 302 in the vertical direction is disposed on the upper surface of the connection wafer 301, and another portion is disposed on the upper surface of the second connection layer 307.

In the embodiment of the present application, the second connection layer 307 may also be connected to the substrate 308. For example, the second connection layer 307 and the substrate 308 may be coupled by solder balls, etc., which is not limited in the embodiment of the present application.

In this way, the structures of different process steps can be closely combined through the embedded bridge, thereby reducing the volume of the chip 30, further reducing the delay and lowering the power consumption.

It can be understood that when there are multiple first regions, the implementation of coupling between the storage chip 303 and the processing chip 302 is similar to that when there is only one first region, and will not be repeated here.

It should be noted that the intermediate layer in the embodiment of the present application may also be called a transfer board, an inner plug-in board, etc.

In summary, in the embodiment of the present application, by setting the control circuit 3010 in the connection chip 301, the connection chip 301 can be reused, shortening the data transmission path between the storage chip 303 and the processing chip 302, thereby reducing latency and reducing power consumption.

The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims (7)

1. A chip, comprising: a handle wafer, a link wafer, and a storage wafer; wherein,

   The processing wafer and the storage wafer are arranged on the connecting wafer;

   The connection wafer comprises a control circuit; wherein the control circuit is used for controlling the storage wafer;

   The control circuit is coupled to the handle wafer and to the storage wafer for coupling the handle wafer to the storage wafer.
2. The chip of claim 1, wherein the connection wafer includes a first region corresponding to the handle wafer, the first region having a first end set disposed therein;

   the first end set is coupled with the processing wafer and coupled with the control circuit.
3. The chip of claim 2, wherein the first areas are plural, each first area is provided with the first end group, each first area corresponds to one of the processing wafers, and the first end group in each first area is coupled with the corresponding processing wafer.
4. A chip according to any one of claims 1-3, wherein the connection wafer is an interposer.
5. A chip according to any of claims 1-3, wherein the connection wafer is an embedded bridge.
6. The chip of claim 5, further comprising a substrate, the substrate comprising a first surface and a second surface opposite the first surface;

   The first surface is provided with a first groove, the embedded bridge is arranged in the first groove, the processing wafer and the storage wafer are arranged on one side of the embedded bridge, which is far away from the second surface, and the processing wafer is coupled with the substrate.
7. An electronic device comprising a printed circuit board, and the chip of any of claims 1-6 disposed on and coupled to the printed circuit board.