CN118103911A

CN118103911A - Address failure detection in a memory system

Info

Publication number: CN118103911A
Application number: CN202280068533.6A
Authority: CN
Inventors: H·V·特兰
Original assignee: Silicon Storage Technology Inc
Current assignee: Silicon Storage Technology Inc
Priority date: 2021-11-22
Filing date: 2022-02-01
Publication date: 2024-05-28
Also published as: KR20240060673A; JP2024539920A; TW202324435A; US20230162794A1; EP4413571A1; TWI852136B

Abstract

Various examples of memory systems including address failure detection systems are disclosed. The memory system includes a first memory array, a row decoder that decodes a row address into word lines, each word line coupled to a row of cells in the first array and a row of cells in the second array, and an address failure detection system including the second array. The second array contains digital bits and/or analog values for identifying address faults.

Description

Address failure detection in a memory system

Priority statement

The present application claims priority from U.S. provisional patent application 63/281,868 entitled "address failure detection in flash memory System (Address Fault Detection in a Flash Memory System)" filed on month 11 and 22 of 2021 and U.S. patent application 17/588,198 entitled "address failure detection in memory System (Address Fault Detection in a Memory System)" filed on month 1 and 28 of 2022.

Technical Field

Various mechanisms for performing address failure detection in a memory system are disclosed.

Background

Nonvolatile memory cells are well known in the art. A prior art nonvolatile split gate memory cell 10 is shown in fig. 1 and includes five terminals. The memory cell 10 includes a semiconductor substrate 12 of a first conductivity type, such as P-type. The substrate 12 has a surface on which a first region 14 (also referred to as a source line SL) of a second conductivity type, such as N-type, is formed. A second region 16 (also referred to as a drain line), also of N-type, is formed on this surface of the substrate 12. Between the first region 14 and the second region 16 is a channel region 18. The bit line BL 20 is connected to the second region 16. The word line WL 22 is positioned over and insulated from the first portion of the channel region 18. The word line 22 overlaps little or no second region 16. Floating gate FG 24 is over another portion of channel region 18. The floating gate 24 is insulated from the other portion and adjacent to the word line 22. The floating gate 24 is also adjacent to the first region 14. The floating gate 24 may overlap the first region 14 to provide coupling from the first region 14 into the floating gate 24. A coupling gate CG (also referred to as a control gate) 26 is located over and insulated from the floating gate 24. The erase gate EG28 is over the first region 14 and adjacent to and insulated from the floating gate 24 and the coupling gate 26. The top corners of the floating gate 24 may be directed toward the interior corners of the T-shaped erase gate 28 to enhance erase efficiency. The erase gate 28 is also insulated from the first region 14. Memory cell 10 is more particularly described in U.S. Pat. No. 7,868,375, the disclosure of which is incorporated herein by reference in its entirety.

One exemplary operation of the erase and program of the prior art nonvolatile memory cell 10 is as follows. Memory cell 10 is erased by Fowler-Nordheim tunneling mechanism (Fowler-Nordheim tunneling mechanism) by applying a high voltage on erase gate 28 with the other terminals equal to zero volts. Electrons tunnel from the floating gate 24 into the erase gate 28, causing the floating gate 24 to be positively charged, thereby turning on the cell 10 in the read state. The resulting erased state of the cell is referred to as the "1" state.

The memory cell 10 is programmed by a source side hot electron programming scheme by applying a high voltage on the coupling gate 26, a high voltage on the source line 14, a medium voltage on the erase gate 28, and a programming current on the bit line 20. A portion of the electrons flowing through the gap between the word line 22 and the floating gate 24 gain sufficient energy to be injected into the floating gate 24, causing the floating gate 24 to be negatively charged, thereby turning off the cell 10 in the read state. The resulting cell programmed state is referred to as the "0" state.

The memory cell 10 is read in the current sense mode as follows: a bias voltage is applied to bit line 20, a bias voltage is applied to word line 22, a bias voltage is applied to coupling gate 26, a bias voltage or zero voltage is applied to erase gate 28, and a ground potential (i.e., zero voltage) is applied to source line 14. For the erased state there is a cell current flowing from the bit line 20 to the source line 14, while for the programmed state there is an insignificant or zero cell current flowing from the bit line 20 to the source line 14. Alternatively, the memory cell 10 may be read in a reverse current sense mode in which the bit line 20 is grounded and a bias voltage is applied to the source line 24. In this mode, the current reverses direction, flowing from the source line 14 to the bit line 20.

Or the memory cell 10 may be read in the voltage sense mode as follows: a bias current (ground) is applied to bit line 20, a bias voltage is applied to word line 22, a bias voltage is applied to coupling gate 26, a bias voltage is applied to erase gate 28, and a bias voltage is applied to source line 14. For the erased state there is a cell output voltage on bit line 20 (significantly > 0V), while for the programmed state there is an output voltage on bit line 20 that is not significant or near zero. Or the memory cell 10 can be read in a reverse voltage sense mode in which the bit line 20 is biased at a bias voltage and a bias current (ground) is applied on the source line 14. In this mode, the memory cell 10 output voltage is on the source line 14 and not on the bit line 20.

In the prior art, various combinations of positive or zero voltages are applied to the word line 22, the coupling gate 26, and the floating gate 24 to perform read, program, and erase operations.

In response to a read, erase, or program command, logic circuitry 270 (not shown) causes various voltages to be supplied to various portions of both selected memory cells 10 and any unselected memory cells 10 in a timely and minimally disturbing manner.

For selected and unselected memory cells 10, the voltages and currents applied are as follows. As used below, the following abbreviations are used: a source line or first region 14 (SL), a bit line 20 (BL), a word line 22 (WL), and a coupling gate 26 (CG).

Table 1: operation of memory cell 10 for reading, erasing, and programming using positive voltages

	SL	SL-unselected
			Reading	0V	0V-FLT
Erasing	0V	0V
			Programming	4.5V-5V	0V-1V/FLT

In U.S. patent 9,361,995, issued at 6/7 of 2016, incorporated by reference, a negative voltage may be applied to word line 22 and/or coupling gate 26 during read, program, and/or erase operations. In this example, the voltages and currents applied to the selected and unselected memory cells 10 are as follows.

Table 2: operation of memory cell 10 using negative voltage for reading and/or programming

	SL	SL-unselected
			Reading	0V	0V-FLT
Erasing	0V	0V
			Programming	4.5V-5V	0V-1V/FLT

In another example mentioned above, when the memory cell 10 is not selected during read, erase, and program operations, a negative voltage may be applied to the word line 22, and a negative voltage may be applied to the coupling gate 26 during an erase operation, such that the following voltages are applied:

table 3: operation of memory cell 10 erased using negative voltage

	SL	SL-unselected
			Reading	0V	0-FLT
Erasing	0V	0V
			Programming	4.5V-5V	0V-1V/FLT

The CGINH signal is a inhibit signal that is applied to the coupling gate 26 of the unselected cell that shares the erase gate 28 with the selected cell.

Fig. 2 depicts another example of a prior art non-volatile split gate memory cell 210. As with memory cell 10, memory cell 210 includes a substrate 12, a first region (source line) 14, a second region 16, a channel region 18, a bit line 20, a word line 22, a floating gate 24, and an erase gate 28. Unlike memory cell 10, memory cell 210 does not include a coupling gate, but only four terminals: bit line 20, word line 22, erase gate 28, and source line 14. This significantly reduces the complexity of the circuitry (such as decoder circuitry) required to operate such an array of memory cells.

The erase operation (erase by erase gate) and read operation are similar to those of fig. 1, except that there is no control gate bias. The programming operation is also completed without a control gate bias, so the programming voltage on the source line is higher to compensate for the lack of a control gate bias.

Table 4 depicts typical voltage ranges that may be applied to four terminals for performing read, erase, and program operations:

Table 4: operation of memory cell 210

Fig. 3 depicts another example of a prior art non-volatile split gate memory cell 310. As with memory cell 10, memory cell 310 includes a substrate 12, a first region (source line) 14, a second region 16, a channel region 18, a bit line 20, and a floating gate 24, and an erase gate 28. Unlike memory cell 10, memory cell 310 does not include a coupling gate or an erase gate. In addition, word line 322 replaces word line 22 and has a different physical shape than word line 22 as shown.

One exemplary operation of the erase and program of the prior art nonvolatile memory cell 310 is as follows. Cell 310 is erased by the fowler-nordheim tunneling mechanism by applying a high voltage on word line 322 and the voltages on the bit line and source line are zero volts. Electrons tunnel from the floating gate 24 into the word line 322, causing the floating gate 24 to be positively charged, turning on the cell 310 under read conditions. The resulting erased state of the cell is referred to as the "1" state. The cell 310 is programmed by a source side hot electron programming scheme by applying a high voltage on the source line 14, a low voltage on the word line 322, and a programming current on the bit line 320. A portion of the electrons flowing through the gap between the word line 322 and the floating gate 24 gain sufficient energy to be injected into the floating gate 24, causing the floating gate 24 to be negatively charged, turning off the cell 310 under read conditions. The resulting cell programmed state is referred to as the "0" state.

Exemplary voltages that may be used for read, program, erase, and standby operations in memory cell 310 are shown in table 5 below:

Table 5: operation of memory cell 310

Various techniques for performing address failure detection in memory systems are also known in the art. Address failures can sometimes occur due to imperfections in the material or due to radiation (such as solar flares), which can cause a "1" bit to flip to a "0" bit within the address, and vice versa. The result of the address failure is that the decoder may receive the intended operating address, but due to the failure, the bits in the decoder will be altered and the decoder may activate the word line corresponding to a different address, which will result in the wrong row in the memory array being accessed. Another possible result is that the failure will cause the decoder to activate the word line corresponding to the intended address and, in addition, the word line corresponding to another address different from the intended address. If not detected or corrected, the address failure will result in an erroneous read or write/program operation.

Fig. 4 depicts a prior art memory system 400. The prior art memory system 400 includes a row decoder 410 and an array 420. The row decoder 410 receives an address X, which is here an address or a portion of an address corresponding to a selected row in the array 420. The row decoder 410 decodes the address X and selects a word line corresponding to the selected row. In this simplified example, four word lines are shown: WL0 (corresponding to address 0000), WL1 (corresponding to address 0001), WL2 (corresponding to address 0010), and WL3 (corresponding to address 0011). The selected word line will activate a row of memory cells within array 420. Thus, for example, if address 0010 is received, row decoder 410 will activate WL2 (corresponding to address 0010).

Fig. 5 depicts a prior art memory system 400 as shown in fig. 4. In this case, however, an address failure occurs. The row decoder 410 receives address 0010, but this time, instead of activating WL2 (corresponding to address 0010), the row decoder 410 activates WL3 (corresponding to address 0011) instead due to a failure in the row decoder 410. If the failure is not detected or corrected, an erroneous read or program operation may occur.

Fig. 6 depicts a prior art memory system 400 as shown in fig. 4 and 5. In this case, however, a different type of address failure from that in fig. 4 occurs. The row decoder 410 receives address 0010, but this time, instead of activating only WL2 (corresponding to address 0010), the row decoder 410 activates both WL2 and WL3 (corresponding to addresses 0010 and 0011, respectively) instead, as a result of a fault occurring in the row decoder 410. If the failure is not detected or corrected, an erroneous read or program operation may occur.

Fig. 7 depicts a prior art memory system 700. The memory system 700 includes a row decoder 410 and an array 420, as in the memory system of the previous figures. However, word lines such as WL0, WL1, WL2, and WL3 are also coupled to a ROM (read only memory) 710. The ROM 710 performs an authentication function. Each word line is coupled to a row of cells in ROM 710. When a particular word line is activated, the corresponding row of cells in ROM 710 is activated. By design, each word line corresponds to a row in ROM 710, and each row in ROM 710 stores different values in its cells. In this example, each row in ROM 710 stores the same value as the address corresponding to the word line bound to that row. Therefore, WL0 corresponds to address 0000, and the value stored in the row in ROM 710 attached to WL0 is also 0000.

In fig. 8, the memory system 700 is again depicted. The row decoder 410 receives address 0010, but due to a fault condition, word line WL3 (corresponding to address 0011) is selected instead of word line WL2 (corresponding to address 0010). This will result in the wrong row of memory cells being selected in array 420. Since the word line WL3 is activated, a row corresponding to the word line WL3 in the ROM 710 is also activated, and the ROM 710 outputs a value 0011 stored in the row. Comparator 450 compares the address received by row decoder 410 (i.e., 0010) with the output of ROM 710 (i.e., 0011) and determines that the values do not match. Comparator 450 may then output a value (such as a "0") that is understood to indicate that no match was found, indicating that an address failure has occurred.

Although prior art memory system 700 is capable of detecting an address failure in which the wrong word line is activated, prior art memory system 700 is not capable of detecting a failure in at least some cases in which multiple rows are selected instead of only one row. In fig. 9, the memory system 700 is again depicted. In this example, an address failure occurs in which the word line for the intended row (i.e., word line WL3 for address 0011) is activated, and the other word line (i.e., word line WL2 for address 0010) is activated. Both word lines WL2 and WL3 will be activated and the contents of both rows in ROM 710 will be output. Logically, ROM 710 is designed such that when two rows are activated, the output will be the OR of the two rows. Thus, the stored values 0010 and 0011 will have an output of 0011. Comparator 450 compares the address received by row decoder 410 (i.e., 0011) with the output of ROM 710 (i.e., 0011). In this case no fault will be detected. Thus, it will be appreciated that the memory system 700 is not always effective in identifying the type of address failure in which two rows are selected instead of a row.

There is a need for an improved address fault detection system that can identify three types of address faults in a memory system, namely a first case where the wrong word line is asserted, a second case where the correct word line is asserted but the second line is also erroneously asserted, and a third case where no word line is asserted.

Disclosure of Invention

Drawings

FIG. 1 is a cross-sectional view of a prior art nonvolatile memory cell to which the present invention is applicable.

FIG. 2 is a cross-sectional view of another prior art nonvolatile memory cell to which the present invention is applicable.

FIG. 3 is a cross-sectional view of another prior art nonvolatile memory cell to which the present invention is applicable.

Fig. 4 depicts a prior art memory system.

FIG. 5 depicts one type of address failure that may occur in the prior art memory system of FIG. 4.

FIG. 6 depicts another type of address failure that may occur in the prior art memory system of FIG. 4.

Fig. 7 depicts a prior art address failure detection system.

FIG. 8 depicts the prior art address failure detection system of FIG. 7 and one type of address failure.

FIG. 9 depicts the prior art address failure detection system of FIG. 7 and another type of address failure.

Fig. 10 is a layout diagram of a die including a non-volatile memory cell of the type shown in fig. 1-3 and including an improved address failure detection system.

FIG. 11 depicts an example of an address failure detection system.

Fig. 12 depicts a prior art encoding scheme for verification data of an address.

Fig. 13A depicts an example of an encoding scheme for verification data of an address.

Fig. 13B depicts another example of an encoding scheme for verification data of an address.

Fig. 14 depicts another example of a coding scheme for verification data of an address.

Fig. 15 depicts another example of an address failure detection system.

Fig. 16 depicts an example of an address failure detection circuit.

Fig. 17A and 17B depict another example of an address failure detection system.

Fig. 18 depicts another example of a coding scheme for verification data of an address.

Fig. 19 depicts another example of an address failure detection system.

Fig. 20 depicts another example of an address failure detection system.

Fig. 21 depicts another example of an address failure detection system.

Fig. 22 depicts another example of an address failure detection system.

Fig. 23 depicts a coding scheme for an address failure detection system.

Fig. 24A depicts a coding scheme for an address failure detection system.

Fig. 24B depicts a coding scheme for an address failure detection system.

Fig. 25A depicts an encoding scheme for an address failure detection system.

Fig. 25B depicts an encoding scheme for an address failure detection system.

Fig. 26 depicts an example of an address failure detection system.

Fig. 27 depicts another example of an address failure detection system.

Fig. 28 depicts another example of an address failure detection system.

Fig. 29 depicts another example of an address failure detection system.

Fig. 30 depicts another example of an address failure detection system.

Fig. 31 depicts another example of an address failure detection system.

FIG. 32 depicts an example of a sensing circuit for use in an example of an address failure detection system.

Fig. 33 depicts an example of a comparator used in the sensing circuit of fig. 32.

FIG. 34 depicts another example of a sensing circuit for use in an example of an address failure detection system.

FIG. 35 depicts another example of a sensing circuit for use in an example of an address failure detection system.

Fig. 36 depicts a layout of a flash memory cell for use in an example.

Fig. 37 depicts a layout of a flash memory cell configured as a ROM cell for use in an example.

FIG. 38 depicts an example of a row decoder for use with an example of an address failure detection system.

FIG. 39 depicts an example of an erase gate decoder for use with an example of an address failure detection system.

FIG. 40 depicts an example of a source line decoder for use with an example of an address failure detection system.

FIG. 41 depicts an example of a control gate decoder for use with an example of an address failure detection system.

FIG. 42 depicts an example of a high voltage level shifter for use with an example of an address failure detection system.

Detailed Description

FIG. 10 depicts an example of a memory system on a die. The die 1000 includes: memory arrays 1001, 1002, 1003, and 1004 for storing data, each memory array optionally utilizing memory cell 10 as shown in FIG. 1, memory cell 210 as shown in FIG. 2, memory cell 310 as shown in FIG. 3, or other known types of memory cells; a row decoder circuit 1005, a row decoder circuit 1006, a row decoder circuit 1007, and a row decoder circuit 1008 for accessing rows in the memory array 1001, the memory array 1002, the memory array 1003, and the memory array 1004 to read from or write to the rows, respectively; column decoder circuit 1009, column decoder circuit 1010, column decoder circuit 1011, and column decoder circuit 1012 for accessing columns in memory array 1001, memory array 1002, memory array 1003, and memory array 1004, respectively, to read from or write to those columns; a sense circuit 1013 for reading data from the memory arrays 1002 and 1004 and a sense circuit 1014 for reading data from the memory arrays 1001 and 1003; analog circuitry 1050; control logic 1051 for providing various control functions such as redundancy and built-in self-test; a high voltage circuit 1052 for providing positive and negative high voltage supplies for the memory system; charge pump circuit 1053 for providing increased voltages for erase and program operations of memory arrays 1001, 1002, 1003, and 1004; interface circuitry (ITFC) 1054 for providing interface pins to connect to other macros on the chip; high voltage decoder circuits 1018, 1019, 1020, and 1021 for use during read, erase, and program operations as needed. The die 1000 also includes address fault detection circuits 1022, 1023, 1024, and 1025, and array fault detection sensing circuits 1026, 1027, 1028, and 1029, discussed in more detail below with respect to certain embodiments.

FIG. 11 depicts an example of a memory system with improved address failure detection capability. Memory system 1100 includes a row decoder 1110, an array 1120, a high voltage decoder 1140, a column decoder 1150, and a sense amplifier 1160, each of which corresponds to components having a similar description as fig. 10. The high voltage decoder 1140 provides the high voltages required for erase and program operations in the array 1120.

Memory system 1100 also includes an address failure detection system 1125 that includes an address failure detection array 1130, sense amplifiers 1170, and comparators 1180. The address failure detection array 1130 includes a ROM array, a flash memory array, or other non-volatile memory array that stores encoded values for each possible address that may be received by the row decoder 1110 and/or the column decoder 1150.

To generate authentication data for each possible address, various encoding schemes are conceivable. A prior art coding scheme is shown in fig. 12. In this example, a four-bit address is shown, which is an address that may be received by row decoder 1110 and/or column decoder 1150. For simplicity, it may be assumed that the row portion of the address is four bits, ranging from 0000 to 1111. Each of these possible addresses is associated with a word line, here a range of word lines would be WL0 to WL15 (16 different row addresses and word lines). Each word line will activate a row in the address failure detection array 1130 and each row stores a value equal to the row address associated with that word line. Thus, address 0000 is associated with WL0, WL0 will then activate the row that stores value 0000 in address failure detection array 1130.

Referring again to FIG. 11, under the encoding scheme of FIG. 12, the row decoder 1110 receives an address X, which in turn will activate a word line that will access the row in array 1120 and the row in address failure detection array 1130. The sense amplifier 1170 will sense the value of each column of activated word lines in the address failure detection array 1130. The value in each column will be a logical "OR" of the values in the columns of each active row in the address failure detection array 1130, i.e., if multiple rows have been activated, then the value of the bit in multiple active rows for that column will be 1, if any of the bits in the columns in multiple rows are activated is 1. The value from each column will be input to a comparator 1180 that compares the received value with address X (or, in this example, the row address portion of address X). As previously described, the output of the comparator 1180 will identify a fault in the case where the wrong row is activated, because in that case the comparator will output a value indicating that the two input values are different. However, this solution is not effective in every case involving a failure in which two rows are activated due to the failure, as described below with respect to fig. 9.

The improved coding scheme is shown in fig. 13A to increase power savings. Those of ordinary skill in the art will appreciate that storing and detecting a "1" value in the address failure detection array 1130 consumes more energy than a "0" value. In this coding scheme, additional bits, here labeled "PB" (polarity bits), are stored. If PB is "0", the encoded bits are directly matched to the associated address. If PB is a "1", the encoded bits are an inverted version of the associated address. In this example, as long as more than half of the bits in the address are "1", the "1" value is used for PB, and these bits will be stored in the opposite direction. For example, for address "1111", a value "0000" is stored in address failure detection array 1130, and a "1" is stored in the PB bit of the value to indicate that each value is an inverted version of the corresponding address. By following this scheme, the memory system will consume less energy than would be the case with the prior art scheme of FIG. 12, as overall less "1 s" will be stored.

Fig. 13B shows another encoding scheme. It is similar to the coding scheme of fig. 13A but contains an additional column for multi-row detection (MRD) that is able to detect the case where multiple rows are activated erroneously, at the cost of additional power consumption compared to the coding scheme of fig. 13A. The MRD column contains a "1" in each row. The following contains a detailed description of multi-line detection.

Another modified coding scheme is shown in fig. 14. Here, each "0" in the address is encoded as "01" in the address failure detection array 1130, and each "1" in the address is encoded as "10" in the address failure detection array 1130. Thus, address "0000" is encoded as "01010101", and address "1111" is encoded as "10101010". Each bit Ax in the address is encoded as EAx and EBx. This means that the encoded value in the address fault detection circuit 1130 will contain twice the bits of the corresponding address. Since any two addresses always differ from each other by at least one bit, the sum of any two encoded values corresponding to the two addresses will include an "11" pattern in at least one bit pair (EAx and EBx). Thus, detecting an "11" pattern in the sense value of the address failure detection array 1130 would indicate that both addresses have been activated, which is a failure condition. This is one type of fault condition that the prior art solution of fig. 12 cannot detect at least at some time.

FIG. 15 depicts an example of a memory system with an improved address failure detection system for implementing the encoding scheme of FIG. 14. Memory system 1500 includes the same components as memory system 1100, except that address failure detection system 1525 follows a different design than address failure detection system 1125. Here, the address failure detection system 1525 includes an address failure detection array 1130 and an address failure detection circuit 1510. The address fault detection circuit 1510 receives an output from each column in the address fault detection array 1130 in which the word line has been activated, wherein the value in any given column in which the word line has been activated is logically ored to create the output for that column.

Fig. 16 also depicts an example of an address failure detection circuit 1510. In response to activation of a row containing bits EA [ x ] and EB [ x ] (where x=the number of address bits encoded in each row of address fault detection circuit 1210), each bit pair (EA [ x ] and EB [ x ]) is input into address fault detection circuit 1510. The address fault detection circuit 1510 includes a set of NAND gates 1601 and 1604, a NOR gate 1602 and an inverter 1603, configured as shown, for each pair of bits EA [ x ] and EB [ x ].

If the input is "01" or "10" (where the first bit is EA [ x ] and the second bit is EB [ x ]), then the output A [ x ] of the address fault detection circuit 1510 for a pair of bits EA [ x ] and EB [ x ] will be "0", otherwise "1". "1" indicates a fault condition (because based on the encoding scheme shown in FIG. 14, where EA [ x ] and EB [ x ] are always different bit values, no "11" or "00" mode should occur during normal operation) and would indicate that two rows, rather than one, have been activated, which is the only case that would result in EAx and EBx being "11", or that the received address has been altered, which is the only case that would result in EAx and EBx being "00", or no rows being selected. Thus, the address failure detection system 1525 can detect a failure condition in which two rows have been incorrectly activated or no row has been selected.

FIG. 17A depicts another example of a memory system with an improved address failure detection system. The memory system 1700 includes a row decoder 1110, an array 1120, and a column decoder 1150, as in the previously described examples. Memory system 1700 also includes an address failure detection system 1725 that includes an address failure detection array 1730, an address failure detection array 1731, and an address failure detection circuit 1710.

The column decoder 1150 is a set of multiplexers and may include a layer column multiplexer. Referring to fig. 17B, a portion of an example of a column decoder 1150 is shown. Each column in array 1120 is coupled to a bit line. Here, four bit lines are shown and labeled BL0 through BL3. A first level of multiplexers selects a pair of adjacent bit lines to activate. A portion of two such first layer multiplexers are shown: t0 and T1. The second level of multiplexers selects a bit line of a pair of adjacent bit lines. Here, each bit line has its own second layer multiplexer, which is partially shown and receives signals labeled V0 through V3. Thus, if BL0 is expected to be selected, T0 and V0 will be activated; if BL1 is expected to be selected, then T0 and V1 will be activated; if BL2 is expected to be selected, T1 and V2 will be activated; and if BL3 is expected to be selected, T1 and V3 will be activated.

Referring again to both fig. 17A and 17B, it can be appreciated that the column decoder 1150 is as prone to failure as the row decoder 1110. In this example, address X is input to a column decoder 1150. Here, the address X includes a row address portion and a column address portion. The column portion of address X contains bits indicating which multiplexers are to be activated (which in turn will assert the bit lines). Each activation signal (V0, V1, V2, V3 … …) for the second layer multiplexer of the column decoder 1150 is coupled to a row in the address failure detection array 1730, and each activation signal for the first layer multiplexer of the column decoder 1150 is coupled to a row (T0, T1 … …) in the address failure detection array 1731. When the bit lines are asserted, the rows in address failure detection array 1730 will be asserted and the rows in address failure detection array 1731 will be asserted, and values will be output by each of address failure detection array 1730 and address failure detection array 1731. Those values may be compared to the column portion of address X by address fault detection circuit 1710. If the values are different, then a fault has occurred and the wrong bit line has been asserted.

An example coding scheme used in the example of fig. 17A is shown in fig. 18. Here, two levels of multiplexers are used. The first layer includes a multiplexer controlled by values T [0] to T [3], which has column address bits AY [4] and AY [0]. The second layer includes a multiplexer controlled by values V [0] to V [7] having column address bits AY [2], AY [1] and AY [0]. It should be appreciated that additional levels are possible. The address fault detection arrays 1330 and 1331 contain encoded values for each multiplexer value, specifically AYA [2], AYB [2], AYA [1], AYB [1] for V [0] … … V [7], and AYA [4], AYB [4], AYA [3] and AYB [3] for T [0] … … T [3]. As shown in fig. 14, each "0" in the column component of the address is encoded as "01" and each "1" in the address is encoded as "10".

Referring again to fig. 17A, the encoding scheme of fig. 18 may be used. The address fault detection circuit 1710 follows the same design as the address fault detection circuit 1510 and if either an "11" or "00" pattern is detected in the bit pairs of the encoded values stored in the address fault detection array 1310, a "0" will be output (since no "11" or "00" pattern should occur during normal operation based on the encoding scheme shown in FIG. 18, with AYA [ x ] and AYB [ x ] always being different bit values). Thus, as a result of the operation of address failure detection system 1725, memory system 1700 is able to detect a failure in the column component of an address.

Fig. 19 and 20 show a variation of the example already described. It can be seen that the functional blocks of the examples can be arranged in different configurations.

Fig. 19 depicts a memory system 1900. Memory system 1900 is identical to memory system 1100 in FIG. 11, except that a high voltage decoder 1140 is coupled between array 1120 and address failure detection array 1130. The system is otherwise identical to the operation in fig. 11.

Fig. 20 depicts a memory system 2000. Memory system 2000 is identical to memory system 1100 in fig. 11, except that a row decoder 1110 is coupled between array 1120 and address failure detection array 1130. The system operates in the same manner as in the previous example.

Fig. 21 depicts a memory system 2100. Here, the row decoder 2103 operates in two arrays (an array 2101 and an array 2102). The array 2101 is coupled to a high voltage decoder 2104, a column decoder 2106 and a sense amplifier 2108. The array 2102 is coupled to a high voltage decoder 2105, a column decoder 2107, and a sense amplifier 2109. A single address failure detection system 2125 is used. The address fault detection system 2125 includes an address fault detection array 2110, a sense amplifier 2111, and a comparator 2112. The address fault detection array 2110 is coupled to the sense amplifier 2111 and the comparator 2112 and can operate as in the previously described examples.

FIG. 22 depicts another example of a memory system with an improved address failure detection system. The memory system 2200 includes a row decoder 2210, an array 2220, a high voltage decoder 2240, a column decoder 2250, and a sense amplifier 2260, each of which corresponds to components having similar descriptions as those of fig. 10, 11, 15, 17A, 19, 20, and 21. Memory system 2200 also includes an address failure detection system 2225 that includes an address failure detection array 2230, an analog multi-state sense amplifier 2270, and an analog comparator 2280. The address failure detection array 2230 includes a ROM array, a flash memory array, or other non-volatile memory array that stores encoded values for each possible address that may be received by the row decoder 2210 and/or the column decoder 2250.

Memory system 2200 utilizes the encoding scheme shown in fig. 23. The address fault detection array 2230 contains the encoded value for each possible address that is the same as the associated address. In this example, a four-bit address [ A3 ] is shown: a0], which is an address that can be received by the row decoder 2210 and/or the column decoder 2250. For simplicity, it may be assumed that the row portion of the address is four bits, ranging from 0000 to 1111. Each of these possible addresses is associated with a word line, here a range of word lines would be WL0 to WL15 (16 different row addresses and word lines). Each word line will activate a row in the address failure detection array 2230, and each row in the address failure detection array 2230 stores a value equal to the row address associated with that word line. Thus, address 0000 is associated with WL0, WL0 will then activate storing value 0000 at bit location [ EA3: EA0] and a row in the address failure detection array 2230.

In fig. 22, the multi-state sense amplifier 2270 is capable of sensing analog levels corresponding to more than 2 bit (or more) values in each column; for example, it may sense a 2-bit value in a column instead of a 1-bit value. For each activated row in address failure detection array 1130, the currents generated in each column representing the value of that column are added, i.e., if multiple rows have been activated, the values of the bits in the multiple activated rows of that column are added together. The multi-state sense amplifier 2270 optionally includes a multi-state digital sense amplifier, a multi-state analog sense amplifier, or both. In the example shown in fig. 23, row 6 (ROM code pattern (0110)) and row 7 (code pattern 0111) are unintentionally shorted together, resulting in an error. The multi-state sense amplifier 2270 indicates the output mode as (0,2,2,1), which is essentially the value of row 6 plus the value of row 7. The failure address may be determined by subtracting the input address bits from the output pattern, here: 0221-0110=0111.

Fig. 24A,24B, 25A, 25B illustrate additional encoding schemes that may be implemented in the address failure detection system 2225 of fig. 22.

FIG. 24A shows the input address A [4 ] for 5 bits: 0] is encoded in the ROM mode. Cells in the table that are blank should be understood to contain a "0". The codeword pattern is such that the number of "1" s on each codeword is less than half the number of bits in the codeword, as shown. For example, the code word ER [ 0] at all 32 lines: 9] there are three and only three "1" s in any word. Such as for codeword ER [0:9] the coding mode is such that for the first four coded bits ER [0 ]: 3] there is one and only one "1", for the last four encoded bits ER [4:7 there is one and only one "1", and for the latter two encoded bits ER [8:9] there is one and only one "1".

In another example shown in FIG. 24B, the encoding mode is such that each word is encoded with the first 8 bits ER [0:7 comprises one and only one "1" and one and only one "1" in the next 4 bits ER [8-11 ]. Cells in the table that are blank should be understood to contain a "0". Thus, each of the 32 rows contains exactly two "1".

More generally, for a code word as in fig. 24A or 24B, for K and/or L groups of bits in an N-bit code word, there is only one "1" in the K and/or L groups of bits, where K >2 and/or L >2. For example, for a 12-bit code word (n=12), there are 3 groups of 4 bits (k=4), where each 4-bit group contains one and only one "1". In another example, different combinations of K-bit and/or L-bit groups (e.g., 8-bit group (k=8) and 4-bit (l=4) groups) may be combined together.

Fig. 25A shows a coding scheme using digital ROM cells and analog (multi-state or multi-level) ROM cells, such as the memory cells in fig. 1 or fig. 2 or fig. 3. The code word in this example includes code words corresponding to four digit columns ER [0 ]: 3] and four simulated columns EAR [0: four digital bits ER [0-3] of 3] and four analog bits EAR [0 ]: 3] (analog ROM cells, e.g. multi-state or multi-level cells, meaning that each cell stores multiple levels). The multi-state sense amplifier 2270 is used in an analog column to detect whether the cell current is 0.5X Ir or 1.0X Ir. The first 4-bit ER [0 ]: 3] follow the same pattern as in fig. 24A. Cells in the table that are blank should be understood to contain a "0". The first four code words have EAR [0] equal to 0.5 XIr (ROM cell current), and the last four code words have EAR [0] equal to 1.0 XIr (ROM cell current). This characteristic is used to distinguish the first four codewords from the last four codewords. Columns EAR [1], EAR [2] and EAR [3] perform the same function for the next 8 row group.

Fig. 25B shows a coding scheme using only analog ROM cells. The code word in this example comprises 6 analog ROM cells. The multi-state sense amplifier 2270 is used to read all columns.

Fig. 26 depicts a memory system 2600. Memory system 2600 includes array 1120, address failure detection array 1130, and analog comparator 2610. In this example, the address failure detection array 1130 includes a single column of non-volatile memory or ROM cells that each store a "1" value. The output of each nonvolatile memory or ROM cell is coupled in parallel to a single bit line. When the word line is asserted, the corresponding cell in the row will output a "1", which generates a current Ir. Typical values for Ir are 20 μA. If more than one word line is asserted (which would occur if the failure resulted in the desired word line and the undesired word line being asserted), more than one cell in the address failure detection array 1130 would output a "1" with a total output current of n Ir, where n is the number of active word lines. The output is input to an analog comparator 2610. The reference current is also input to the analog comparator 2610. An exemplary reference current is 1.3Ir. If the input from the address fault detection array 1130 exceeds 1.3Ir, the output of the analog comparator 2610 will be a "1", which indicates that more than one word line is activated, indicating a fault condition. If the input from the address fault detection array 1130 is less than 1.3Ir, the output will be a "0", which indicates that one or zero word lines are activated, indicating a non-fault condition. (the zero word line condition may be a fault; this example will not detect this condition.) it will be appreciated that multiples other than 1.3 may be selected.

In some examples where address failure detection array 1130 includes flash memory cells, the "1" state in the cell is the erased state (cell current is Ir) and the "0" state in the cell is the programmed state (cell current is about 0 μA). In other examples where address failure detection array 1130 includes flash memory cells, a "1" in the cell is the erased state and a "0" state in the cell is the state where there is no bit line contact between the cell and the array columns.

Fig. 27 depicts a memory system 2700. Memory system 2700 is similar to memory system 2600 of fig. 26, except that it has two columns of cells in address failure detection array 1130. Memory system 2700 includes array 1120, address failure detection array 1130, and analog comparators 2710 and 2720. In this example, the address failure detection array 1130 includes two columns of non-volatile memory or ROM cells that each store a "1" value. The output of each non-volatile memory or ROM cell in each respective column is coupled in parallel to a single bit line. When the word line is asserted, the corresponding cells in the row will each output a "1", which corresponds to the current Ir. Typical values for Ir are 20 μA. If more than one word line is asserted (which is a type of fault condition), more than one cell pair in the address fault detection array 1130 will output a "1", with the total output current in each column being n Ir, where n is the number of active word lines. The outputs are input to analog comparators 2710 and 2720. Reference currents such as 0.5Ir and 1.1Ir are also input to analog comparators 2710 and 2720, respectively. If the input from the address fault detection array 1130 exceeds 1.1Ir, the comparator 2720 output will be a "1", which indicates that more than one word line is activated, indicating a fault condition. If the input from the address fault detection array 1130 exceeds 0.5Ir but is less than 1.1Ir, the comparator 2710 output will be a "1" and the comparator 2720 output will be a "0", indicating that exactly one word line is activated, indicating a non-fault condition. If the input from the address fault detection array 1130 is less than 0.5Ir, the comparator 2710 output will be a "0", which indicates that no word line is activated, indicating a fault condition. It will be appreciated that other multiples than 1.1 may be selected to determine whether a certain number of word lines (e.g., 3) are faulty.

Fig. 28 depicts a memory system 2800. Memory system 2800 includes array 1120, address failure detection array 1130, and analog comparator 2810. Memory system 2800 is identical to memory system 2600 in fig. 26, except that address failure detection array 1130 is controlled by its own control gate signal (CGAFD), erase gate signal (EGAFD), and source wire gate Signal (SLGAFD). As shown in fig. 26, array 1120 and address failure detection array 1130 share word lines. Thus, in this example, array 1120 and address failure detection array 1130 share word lines, but separate high voltage control lines are used so that address failure detection array 1130 can be erased or programmed independently of array 1120.

Fig. 29 depicts a memory system 2900. Memory system 2900 includes an array 1120 and an address failure detection array 1130. The address failure detection array 1130 includes one or more columns of non-volatile memory cells. Since the array 1120 and the address failure detection array 1130 share word lines and high voltage control lines (control, erase and source wire grid signals), cells in a row of a particular address failure detection array 1130 will be erased when cells in the same row are erased in the array 1120. Thus, after an erase operation, the controller or other device needs to program the appropriate values into each erased row in the address failure detection array 1130. Some columns in the address failure detection array 1130 contain coded verification bits for each possible address's row portion and/or column using the coding scheme of FIG. 12, FIG. 13A, FIG. 13B, FIG. 14, FIG. 18, FIG. 23, FIG. 24A, FIG. 24B, FIG. 25A, or FIG. 25B, or another coding scheme.

Fig. 30 depicts a memory system 3000. Memory system 3000 includes an array 1120 and an address failure detection array 1130. The address failure detection array 1130 includes one or more columns of non-volatile memory cells. Memory system 3000 is identical to memory system 2900, except that memory system 3000 includes circuits 3010 and 3020 that pull down one or more bit lines to ground during operation. This is used to pull the local source line more strongly down to ground, for example due to multiple cells, and at the same time turn on locally in ROM (address failure detection array 1130) mode. It should be appreciated that memory system 3000 may include one such circuit per column in address failure detection array 1130. Some columns in the address failure detection array 1130 contain coded verification bits for each possible address's row portion and/or column using the coding scheme of FIG. 12, FIG. 13A, FIG. 13B, FIG. 14, FIG. 18, FIG. 23, FIG. 24A, FIG. 24B, FIG. 25A, or FIG. 25B, or another coding scheme.

Fig. 31 depicts a memory system 3100. Memory system 3100 includes array 1120, address failure detection array 1130, and analog comparator 3130. The address failure detection array 1130 includes one or more columns of non-volatile memory cells. Memory system 3100 is identical to memory system 3000 except that memory system 3100 includes a polarity column 3110 and a multi-row sense column 3120. Polarity column 3110 contains a single bit per row to perform the function of the PB bit in FIG. 13A or FIG. 13B. The multi-row detection column 3120 contains a single cell for each row, with each single cell in the multi-row detection column 3120 storing a "1". This column implements the functionality as previously described with respect to fig. 26. Other columns in the address failure detection array 1130 contain coded verification bits for each possible address's row portion and/or column using the coding scheme of FIG. 12, FIG. 13A, FIG. 13B, FIG. 14, FIG. 18, FIG. 23, FIG. 24A, FIG. 24B, FIG. 25A, or FIG. 25B, or another coding scheme.

In all examples described herein, when a failure is indicated, the memory system may take appropriate steps. For example, the memory system may ignore the results of any read operations affected by the failure and may repeat the read operations. The memory system may also repeat any write operations affected by the failure. In the case where array 1120 comprises flash memory cells, the memory system may first erase the relevant portion of the array before repeating the write (program) operation.

Fig. 32 depicts an example of a sensing circuit. The sense circuit 3200 includes bias transistors 3202 and 3204, current source (reference current) transistors 3201 and 3203, and a comparator 3205. Bias transistor 3202 is connected to the bit lines (columns) in address failure detection array 1130. Bias transistor 3203 is connected to the dummy bit line to balance capacitance or to a reference current generator.

By selecting appropriate transistors for current source transistors 3201 and 3203, different configurations can be selected. In one configuration, the output of comparator 3205 will indicate whether a word line is asserted. For example, a current source (reference current) transistor 3201 may be selected or set to generate a current equal to 0.5 IR, where IR is the current drawn by a single cell when the word line is asserted. In this configuration, an output "0" from comparator 3205 indicates that no word line is asserted, and an output "1" indicates that one word line is asserted.

In another configuration, the output of comparator 3205 will indicate whether more than one word line is asserted. Current source transistors 3201 and 3203 are selected or set to generate a current equal to 1.1 IR, where IR is the current drawn by a single cell when the word line is asserted. In this configuration, an output "0" from comparator 3205 indicates that one word line or less is asserted, which indicates that more than one word line is asserted.

Fig. 33 depicts additional details of the sensing circuit 3200. Bias switches 3301 and 3302 are also depicted.

FIG. 34 depicts another example of a sensing circuit. The sense circuit 3400 includes bias transistors 3402 and 3404 and current mirror transistors 3401 and 3403. Transistors 3403 and 3404 constitute an output comparison stage 3410. The bias transistor 3402 is connected to a bit line (column) in the address failure detection array 1130. The bias transistor 3404 is connected to ground or other common potential. The mirror transistor 3403 mirrors the cell current (Ir) through the mirror transistor 3401 from the bit line in the address fault detection array 1130 to compare with the reference current Iref from the bias transistor 3404. The bias transistor 3404 is changed (e.g., trimmable in size) to achieve different current comparison (% > Ir). The output (Out) will indicate whether a "1" or "0" is output on that bit line of the address fault detection array 1130. Specifically, if cell current Ir > Iref (indicating a relatively high memory cell current, indicating that "0" is stored in the cell), then Out will be "1", and if cell current Ir < Iref (indicating a relatively low memory cell current, indicating that "1" is stored in the cell), then Out will be "0". There may be multiple blocks of the output compare stage 3410 to achieve different current ratios simultaneously, where multiple outputs indicate different current sense ratios. Further, the transistor 3403 (e.g., trimmable size) can be changed to achieve different mirror ratios from the transistor 3401 into the transistor 3403.

FIG. 35 depicts another example of a sensing circuit. Sense circuit 3500 includes bias transistors 3504 and 3502, control transistors 3501 and 3503, and an inverter formed by transistors 3505 and 3506. Bias transistor 3504 is connected to a bit line (column) in address failure detection array 1130. Bias transistor 3506 is connected to ground. The output at AFD _ OUT will indicate whether a "1" or "0" is output on that bit line of the address fault detection array 1130. Once sensing is complete, control transistor 3503 is used to turn off the current in transistors 3502 and 3504 (the output of the inverter switches from "0" to "1", which means that the gate of transistor 3503 is off). Bias transistor 3502 is used to establish a reference current that will be compared to the cell current (Ir) coupled to transistor 3504.

Fig. 36 depicts a layout of nonvolatile memory cells 3600 that may be used in address failure detection array 1130. Memory cell 3600 follows the architecture of memory cell 10 in fig. 1.

Fig. 37 depicts a layout of ROM cells 3700 that may be used in address failure detection array 1130. ROM memory cell 3700 follows the architecture of memory cell 10 in FIG. 1, but is modified to operate as a ROM cell, e.g., CG and EG gates may be removed from cell 3600.

Fig. 38 depicts a row decoder 3800 for 8 word lines in a sector within a memory array, such as memory arrays 1001, 1002, 1003, and 1004. The row decoder 3800 may be used for the row decoder 1110 in the above example. The row decoder 3800 includes a NAND gate 3801 that receives pre-decoded address signals (shown here as lines XPA, XPB, XPC and XPD) that select sectors within the memory array. When XPA, XPB, XPC and XPD are both "high", the output of NAND gate 3801 will be "low" and that particular sector will be selected.

The row decoder 3800 further includes an inverter 3802, a decoder circuit 3810 for generating a word line WL0, a decoder circuit 3820 for generating a WL7, and additional decoder circuits (not shown) for generating word lines WL1, WL2, WL3, WL4, WL5, and WL 6.

Decoder circuit 3810 includes PMOS transistors 3811, 3812, and 3814 and NMOS transistors 3813 and 3815 configured as shown. Decoder circuit 3810 receives the output of nand gate 3801, the output of inverter 3802, and pre-decoded address signal XPZB0 from the previous decoding level. When the particular sector is selected and XPZB is "low", then WL0 will be asserted. When XPZB0 is "high", then WL0 will not be asserted.

Similarly, decoder circuit 3820 includes PMOS transistors 3821, 3822, and 3824 and NMOS transistors 3823 and 3825, configured as shown. Decoder circuit 3820 receives the output of NAND gate 3801, the output of inverter 3802, and pre-decoded address signal XPZB. When the particular sector is selected and XPZB is "low", then WL7 will be asserted. When XPZB7 is "high", then WL7 will not be asserted.

It should be appreciated that the decoder circuits (not shown) of WL1, WL2 and WL3, WL4, WL5 and WL6 will follow the same design as decoder circuits 3810 and 3820, except that they will receive inputs XPZB, XPZB2, XPZB3, XPZB4, XPZB5 and XPZB6 instead of XPZB0 or XPZB, respectively.

In the case where the sector is selected and WL0 is desired to be asserted, the output of nand gate 3801 will be "low" and the output of the inverter will be "high". PMOS transistor 3811 will be turned on and the node between PMOS transistor 3812 and NMOS transistor 3813 will receive the value XPZB0, which will be "low" when word line WL0 will be asserted. This will turn on PMOS transistor 3814, which pulls WL0 "high" to ZVDD, which indicates an asserted state. In this case XPZB is "high", meaning WL7 is not asserted, which will pull the node between PMOS transistor 3822 and NMOS transistor 3823 to the value of XPZB7 (which is "high"), which will turn on NMOS transistor 3825 and make WL "low", which indicates a non-asserted state. In this way, when the sector is selected, one of the word lines WL0 … WL7 can be selected.

Fig. 39 shows an erase gate decoder 3900 as part of the high voltage decoders 1018-1021. The erase gate decoder 3900 includes an NMOS transistor 3901 and PMOS transistors 3902 and 3903, configured as shown. PMOS transistor 3903 is a current limiter with EGHV _bias as the current mirror BIAS level. When the erase gate signal (EG) is to be asserted, en_hv_n is to be set low (e.g., 0V or 1.2V or 2.5V), which turns on PMOS transistor 3902 and turns off NMOS transistor 3901, which results in Erase Gate (EG) being high (i.e., = VEGSUP, e.g., 11.5V). When the erase gate signal (EG) will not be asserted, en_hv_n will be set high, which will turn off PMOS transistor 3902 and turn on NMOS transistor 3901, which will result in the Erase Gate (EG) being LOW (i.e., = VEGSUP _low level, e.g., 0V or 1.2V or 2.5V).

Fig. 40 shows a source line decoder 4000 as part of high voltage decoders 1018-1021. The source line decoder 4000 includes NMOS transistors 4001, 4002, 4003, and 4004, configured as shown. The NMOS transistor 4001 pulls the Source Line (SL) low during a read operation in response to activating a high slrd_en signal. The NMOS transistor 4002 pulls the Source Line (SL) low during a programming operation in response to activating the slp_en signal. The NMOS transistor 4003 performs a monitoring function through output VSLMON, i.e., it provides the voltage on SL to be detected on output VSLMON. The NMOS transistor 4004 provides a voltage to the Source Line (SL) in response to an active high en_hv signal.

Fig. 41 depicts a control gate decoder 4100 as part of the high voltage decoders 1018-1021. The control gate decoder 4100 includes an NMOS transistor 4101 and a PMOS transistor 4102. The NMOS transistor 4101 will pull down the control gate signal (CG) in response to the activation high signal en_hv_n. PMOS transistor 4102 will pull up the control gate signal (CG) in response to activating the low signal en_hv_n.

Fig. 42 depicts a latch voltage shifter 4200 as part of the high voltage decoders 1018-1021. In the illustrated configuration, latch voltage shifter 4200 includes a low voltage latch inverter 4209, NMOS transistors 4203, 4204, 4207, and 4208, and PMOS transistors 4201, 4202, 4205, and 4206. Latch voltage shifter 4200 receives signal en_sec as input and outputs en_hv and en_hv_n, en_hv and en_hv_n having a voltage swing greater than the swing of en_sec.

Claims

1. A memory system, the memory system comprising:

a memory array comprising a first set of memory cells arranged in rows and columns;

A row decoder for receiving as input an N-bit row address, the row decoder coupled to a plurality of word lines, wherein each word line is coupled to a row of cells in the first set of memory cells, wherein N is an integer; and

An address failure detection array comprising a second set of memory cells arranged in rows and columns, wherein each sub-line of the plurality of word lines is coupled to a row of cells in the second set of memory cells, the row of cells including an encoded word comprising one or more of:

one or more K groups of bits; and

One or more L-bit groups;

wherein each of the K and L groups of bits contains only one "1" bit, K and L are integers, K N and L N.

2. The memory system of claim 1, wherein K is ≡2.

3. The memory system of claim 1, wherein L is ≡2.

4. The memory system of claim 1, further comprising:

and a comparator for identifying an address fault based on the N-bit row address and an output of the address fault detection array.

5. The memory system of claim 4, wherein the comparator indicates a failure if no row is selected.

6. The memory system of claim 4, wherein the comparator indicates a failure if two or more rows of the memory array are selected.

7. The memory system of claim 4, wherein the comparator comprises a digital bit comparator and an analog comparator.

8. The memory system of claim 1, wherein each cell in the first set of memory cells is a split gate flash memory cell.

9. The memory system of claim 1, wherein each cell in the second set of memory cells is a split gate flash memory cell.

10. The memory system of claim 1, wherein each cell in the second set of memory cells is a read only memory cell.

11. The memory system of claim 1, wherein each cell in the first set of memory cells is an analog memory cell.

12. The memory system of claim 1, further comprising:

a multi-state sense amplifier for sensing the memory array.

13. A memory system, the memory system comprising:

An address failure detection array comprising a second set of memory cells arranged in rows and columns, wherein each sub-line of the plurality of word lines is coupled to a row of cells in the second set of memory cells, the row of cells comprising an encoded word comprising a pair of encoded bits for each of the N bits in the N-bit row address, wherein each pair of encoded bits comprises a different value of encoded bit.

14. The memory system of claim 13, further comprising a comparator that indicates a fault if no row is selected.

15. The memory system of claim 13, further comprising a comparator that indicates a failure if two or more rows are selected.

16. The memory system of claim 13, wherein each cell in the first set of memory cells is a split gate flash memory cell.

17. The memory system of claim 13, wherein each cell in the second set of memory cells is a split gate flash memory cell.

18. The memory system of claim 13, wherein each cell in the second set of memory cells is a read only memory cell.

19. The memory system of claim 13, wherein each cell in the first set of memory cells is an analog memory cell.

20. A memory system, the memory system comprising:

An address failure detection array comprising analog comparators and a second set of memory cells arranged in rows and columns, wherein each sub-line of the plurality of word lines is coupled to a row of cells in the second set of memory cells, the row of cells contains an encoded word, and each encoded word comprises one or more analog values.

21. The memory system of claim 20, wherein each encoded word further comprises one or more digital bits.

22. The memory system of claim 20, wherein the analog comparator indicates a fault if no row is selected.

23. The memory system of claim 20, wherein the analog comparator indicates a failure if two or more rows of the memory array are selected.

24. The memory system of claim 20, wherein each cell in the first set of memory cells is a split gate flash memory cell.

25. The memory system of claim 20, wherein each cell in the second set of memory cells is a split gate flash memory cell.

26. The memory system of claim 20, wherein each cell in the second set of memory cells is a read only memory cell.

27. The memory system of claim 20, wherein each cell in the first set of memory cells is an analog memory cell.

28. A memory system, the memory system comprising:

A memory array comprising first memory cells arranged in rows and columns, wherein the first memory cells are multi-state memory cells;

a row decoder for receiving as input an N-bit row address, the row decoder coupled to a plurality of word lines, wherein each word line is coupled to a row of the first memory cells, wherein N is an integer; and

An address failure detection array comprising second memory cells arranged in rows and columns, wherein each sub-line of the plurality of word lines is coupled to a row of the second memory cells.

29. The memory system of claim 28, wherein the first memory cell is an analog memory cell.

30. The memory system of claim 28, wherein the address failure detection array includes an encoded word comprising one or more of:

one or more K groups of bits; and

One or more L-bit groups;

31. The memory system of claim 30, wherein K is ≡2.

32. The memory system of claim 30, wherein L is ≡2.

33. The memory system of claim 28, wherein each first memory cell is a split gate flash memory cell.

34. The memory system of claim 28, wherein each second memory cell is a split gate flash memory cell.

35. The memory system of claim 28, wherein each second memory cell is a read only memory cell.

36. The memory system of claim 28, further comprising:

a multi-state sense amplifier for sensing the memory array.