CN118102701A - Semiconductor structure and forming method thereof - Google Patents

Abstract

The embodiment of the disclosure provides a semiconductor structure and a forming method thereof, wherein the forming method of the semiconductor structure comprises the following steps: providing a substrate and a laminated structure which is arranged on the substrate at intervals, wherein the laminated structure comprises first semiconductor layers which are arranged at intervals along a first direction, each first semiconductor layer comprises a channel region and sacrificial regions which are arranged at two sides of the channel region, and the two sacrificial regions of the first semiconductor layer are arranged along a second direction; removing the first semiconductor layer of the sacrificial region to form a groove; and forming a second semiconductor layer filling the groove, wherein the second semiconductor layer is doped with doping ions, and the second semiconductor layer is contacted with the rest of the first semiconductor layer. At least to facilitate improving the performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present disclosure relate to the field of semiconductors, and more particularly, to a semiconductor structure and a method for forming the same.

Background

A dynamic random access memory (dynamic random access memory, dram), a semiconductor memory that randomly writes and reads data at high speed, is widely used in data storage devices or apparatuses.

Dynamic random access memory includes a plurality of repeating memory cells, each memory cell typically including a capacitor and a transistor having a gate connected to a Word Line (WL), a drain connected to a bit line, and a source connected to the capacitor. The voltage signal on the word line can control the transistor to turn on or off, thereby reading the data information stored in the capacitor through the bit line or writing the data information into the capacitor through the bit line for storage.

However, as the integration density of the dynamic random access memory is increased, there is a higher requirement for a transistor in the dynamic random access memory array structure, and the transistor may affect the performance of the semiconductor structure.

Disclosure of Invention

Embodiments of the present disclosure provide a semiconductor structure and a method of forming the same, which are at least beneficial to improving performance of the semiconductor structure.

According to some embodiments of the present disclosure, an aspect of an embodiment of the present disclosure provides a method for forming a semiconductor structure, including: providing a substrate and a laminated structure which is arranged on the substrate at intervals, wherein the laminated structure comprises first semiconductor layers which are arranged at intervals along a first direction, each first semiconductor layer comprises a channel region and sacrificial regions which are arranged at two sides of the channel region, and the two sacrificial regions of the first semiconductor layer are arranged along a second direction; removing the first semiconductor layer of the sacrificial region to form a groove; and forming a second semiconductor layer filling the groove, wherein the second semiconductor layer is doped with doping ions, and the second semiconductor layer is contacted with the rest of the first semiconductor layer.

According to further embodiments of the present disclosure, forming the second semiconductor layer filling the recess includes: the second semiconductor layer is formed on the side surface of the first semiconductor layer of the channel region in the second direction by adopting a selective epitaxial process, and in-situ doping of the doping ions is performed in the process step of forming the second semiconductor layer.

According to further embodiments of the present disclosure, the first semiconductor layer of the channel region is doped with first doping ions, and the second semiconductor layer is doped with first doping ions, the concentration of the first doping ions in the second semiconductor layer being greater than the concentration of the first doping ions in the first semiconductor layer; or the first semiconductor layer of the channel region is doped with first doping ions, and the second semiconductor layer is doped with second doping ions.

According to other embodiments of the present disclosure, the process gas forming the second semiconductor layer includes a silicon source gas, a germanium source gas, and a boron source gas; or the process gas for forming the second semiconductor layer includes a silicon source gas and a phosphorus source gas.

According to other embodiments of the present disclosure, the first direction is a direction perpendicular to the substrate surface, and the second direction is a direction parallel to the substrate surface.

According to other embodiments of the present disclosure, after forming the second semiconductor layer, further includes: and forming a word line structure extending along a third direction and arranged at intervals, wherein the word line structure surrounds the first semiconductor layer of the channel region arranged along the third direction.

According to other embodiments of the present disclosure, the third direction is the same as the first direction, the stacked structure includes first semiconductor layers and dielectric layers alternately arranged along the first direction, and the method further includes: forming sacrificial layers which are arranged at intervals and extend along the third direction, wherein the sacrificial layers cover the side surfaces of the first semiconductor layers of the channel regions, and the sacrificial layers are positioned between the first semiconductor layers of the adjacent channel regions which are arranged along the third direction; forming a support layer between adjacent laminated structures, wherein the support layer covers the side surface of the sacrificial layer and the side surface of the first semiconductor layer of the sacrificial region; forming the word line structure includes: removing the dielectric layer between the sacrificial layer and the first semiconductor layer of the channel region in the laminated structure to form a first gap, wherein the first gap exposes the side surface of the first semiconductor layer of the channel region extending along the second direction; the word line structure is formed within the first void.

According to other embodiments of the present disclosure, providing the stacked structure including the first semiconductor layer includes: providing the substrate; forming an initial laminated structure which is arranged at intervals on the substrate, wherein the initial laminated structure comprises initial first semiconductor layers and dielectric layers which are alternately arranged along the first direction, grooves are formed between the initial laminated structures, and the grooves expose the side surfaces of the initial first semiconductor layers; and doping the initial first semiconductor layer through the grooves to form the first semiconductor layer arranged along the first direction.

According to other embodiments of the present disclosure, forming a sacrificial layer arranged at intervals and extending in the third direction includes: filling an initial sacrificial layer in the groove; patterning the initial sacrificial layer to form a layer along the sacrificial layer.

According to other embodiments of the present disclosure, before removing the first semiconductor layer of the sacrificial region to form a recess, further comprising: removing the dielectric layer between the first semiconductor layers of the sacrificial region in the laminated structure to form a second gap, wherein the second gap exposes the side surface of the first semiconductor layer of the sacrificial region extending along the second direction; and forming an isolation layer in the second gap.

According to other embodiments of the present disclosure, the third direction is the same as the arrangement direction of the stacked structure, and the method further includes: forming sacrificial layers which are arranged at intervals and extend along the third direction, wherein the sacrificial layers encircle the side face of the first semiconductor layer of the channel region; forming a support layer between sacrificial layers surrounding the first semiconductor layers of different layers; forming the word line structure includes: removing the sacrificial layer to form a third gap exposing a side surface of the first semiconductor layer of the channel region extending in the second direction; the word line structure is formed within the third void.

According to other embodiments of the present disclosure, before forming the sacrificial layer, providing the stacked structure including the first semiconductor layer includes providing the substrate; forming an initial laminated structure which is arranged at intervals on the substrate, wherein the initial laminated structure comprises initial first semiconductor layers and dielectric layers which are alternately arranged along the first direction, grooves are formed between the initial laminated structures, and the grooves expose the side surfaces of the initial first semiconductor layers; doping the initial first semiconductor layer through the grooves to form first semiconductor layers arranged along the first direction; and removing the dielectric layer between the first semiconductor layers of the channel region to form the sacrificial layer.

According to further embodiments of the present disclosure, before removing the dielectric layer between the first semiconductor layers of the channel region, the method further comprises: removing the dielectric layer between the first semiconductor layers of the sacrificial region in the laminated structure to form a fourth gap, wherein the fourth gap exposes the side surface of the first semiconductor layer of the sacrificial region extending along the second direction; and forming an isolation layer in the fourth gap.

According to some embodiments of the present disclosure, another aspect of embodiments of the present disclosure further provides a semiconductor structure, including: a substrate; the semiconductor device comprises a substrate, a stacking structure arranged on the substrate at intervals, and a plurality of semiconductor layers, wherein the stacking structure comprises semiconductor layers arranged at intervals along a first direction, each semiconductor layer comprises a first semiconductor layer and second semiconductor layers arranged on two sides of the first semiconductor layer, two second semiconductor layers in the semiconductor layers are arranged along a second direction, and doped ions are doped in the second semiconductor layers; the support layers extend along the third direction and are distributed at intervals, and the support layers are located between the adjacent stacking structures; and the isolation layer is positioned between the second semiconductor layers.

According to other embodiments of the present disclosure, further comprising: and the word line structures extend along a third direction and are arranged at intervals, and the word line structures encircle the first semiconductor layers arranged along the third direction.

According to further embodiments of the present disclosure, the first semiconductor layer is doped with first doping ions, and the second semiconductor layer is doped with first doping ions, the concentration of the first doping ions in the second semiconductor layer being greater than the concentration of the first doping ions in the first semiconductor layer; or the first semiconductor layer is doped with first doping ions, and the second semiconductor layer is doped with second doping ions.

According to other embodiments of the present disclosure, the third direction is the same as the first direction; the support layer is positioned between adjacent word line structures along the arrangement direction of the stacked structures, and the support layer is positioned between the second semiconductor layers; the isolation layer is located between the second semiconductor layers along the first direction.

According to other embodiments of the present disclosure, the third direction is the same as the arrangement direction of the stacked structure; along the first direction, the support layer is positioned between adjacent word line structures, and the isolation layer is positioned between the second semiconductors; the isolation layers are also located between the stacked structures along the arrangement direction of the stacked structures.

The technical scheme provided by the embodiment of the disclosure has at least the following advantages:

In the method for forming a semiconductor structure provided in the embodiments of the present disclosure, a substrate and a stacked structure disposed on the substrate at intervals are provided first, the stacked structure includes a first semiconductor layer disposed along a first direction at intervals, the first semiconductor layer includes a channel region and sacrificial regions disposed at two sides of the channel region, two sacrificial regions of the first semiconductor layer are disposed along a second direction, then, the first semiconductor layer of the sacrificial regions is removed to form a groove, a second semiconductor layer filling the groove is formed, doped with doped ions in the second semiconductor layer, and the second semiconductor layer is in contact with the remaining first semiconductor layer. The second semiconductor layer is a source-drain region, and the first semiconductor layer is a channel. Therefore, the second semiconductor layer doped with ions is directly formed in the groove, the formed semiconductor layer can be prevented from being doped to form the second semiconductor layer, and the manufacturing difficulty of the source drain region is reduced. In the laminated structure, a plurality of semiconductor layers are laminated and placed, a thicker dielectric film is arranged between the upper semiconductor layer and the lower semiconductor layer, if a traditional source-drain region forming mode is adopted, a completely formed active region is formed first, then doping treatment is carried out on the semiconductor layer positioned in the source-drain region in the active region to form a second semiconductor layer of the source-drain region, and due to the influence of the dielectric film, the injected doping ions are difficult to dope into each semiconductor layer, so that the performance of the whole semiconductor structure is poor. Therefore, the embodiment of the disclosure is further beneficial to improving the performance of the semiconductor structure by directly forming the doped second semiconductor layer in the groove.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

Fig. 1 to 10 are schematic views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the disclosure;

Fig. 11 to 16 are schematic views illustrating steps of another method for forming a semiconductor structure according to an embodiment of the disclosure;

Fig. 17 is a schematic structural diagram of a semiconductor structure according to an embodiment of the disclosure;

fig. 18 is a schematic structural diagram of another semiconductor structure according to an embodiment of the present disclosure.

Detailed Description

As known from the background art, the current semiconductor structure manufacturing process has certain problems, which result in poor performance of the semiconductor structure manufactured by the process.

The embodiment of the disclosure provides a semiconductor structure and a forming method thereof, in the forming method of the semiconductor structure, a substrate and a laminated structure which is arranged on the substrate at intervals are provided, the laminated structure comprises first semiconductor layers which are arranged at intervals along a first direction, the first semiconductor layers comprise a channel region and sacrificial regions at two sides of the channel region, two sacrificial regions of the first semiconductor layers are arranged along a second direction, then the first semiconductor layers in the sacrificial regions are removed to form grooves, then second semiconductor layers doped with doping ions are filled in the grooves, and the second semiconductor layers are in contact with the rest of the first semiconductor layers. Therefore, the manufacturing difficulty of the source and drain regions can be reduced, and the performance of the semiconductor structure can be improved.

Embodiments of the present disclosure will be described in detail below with reference to the attached drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the present disclosure. The technical solutions claimed in the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments.

Fig. 1 to 16 are schematic structural views of steps of a method for forming a semiconductor structure according to an embodiment of the present disclosure.

For word line structures formed in semiconductor structures, the word line structures may extend in a direction perpendicular to the substrate surface in some embodiments. In other embodiments, the word line structure may also extend in a direction parallel to the substrate surface. The following description will be made taking an example in which a word line structure extends in a direction perpendicular to a substrate surface.

Referring to fig. 1, a substrate 100 and a stacked structure 200 disposed on the substrate 100 at intervals are provided, the stacked structure 200 includes a first semiconductor layer 210 disposed at intervals along a first direction X, the first semiconductor layer 210 includes a channel region 211 and sacrificial regions 212 disposed at both sides of the channel region 211, and two sacrificial regions 212 of the first semiconductor layer 210 are disposed along a second direction Y.

In some embodiments, the substrate 100 may be a silicon substrate, which may include one or more of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon. In other embodiments, the material of the substrate 100 may also include silicon carbide, an organic material, or a multi-compound. The multi-component compounds may include, but are not limited to, perovskite, gallium arsenide, cadmium telluride, copper indium selenium, and the like. Illustratively, the substrate 100 in the presently disclosed embodiments is a single crystal silicon substrate 100.

In some embodiments, the first direction X is a direction perpendicular to the surface of the substrate 100, and the second direction Y is a direction parallel to the surface of the substrate 100. That is, the first semiconductor layers 210 are spaced apart in a direction perpendicular to the surface of the substrate 100, and the two sacrificial regions 212 of the first semiconductor layers 210 are arranged in a direction parallel to the surface of the substrate 100. Sacrificial region 212 is subsequently used to form a source drain region in a transistor.

Specifically, in some embodiments, the steps of forming the substrate 100 and forming the stacked structure 200 may include: providing a substrate 100, forming an initial laminated structure arranged at intervals on the substrate 100, wherein the initial laminated structure comprises initial first semiconductor layers and dielectric layers 220 which are alternately arranged along a first direction, a groove 300 is arranged between the initial laminated structures, and the groove 300 exposes the side surface of the initial first semiconductor layers; the initial first semiconductor layer is subjected to a doping process through the trench 300 to form the first semiconductor layer 210 arranged in the first direction. An undoped initial first semiconductor layer is formed as an active region, and then ion doping is carried out on the initial first semiconductor layer. The doping of the initial first semiconductor layer by the trench 300 is advantageous in reducing the difficulty in forming the first semiconductor layer 210 of the channel region 211.

In some embodiments, the process of Doping the initial first semiconductor layer may include a Plasma Doping Process (PLAD) or a Plasma immersion ion implantation Process (PIII).

The material of the initial first semiconductor layer may include silicon, a metal oxide semiconductor, for example, zinc tin oxide (ZnxSnyO, commonly referred to as "ZTO"), indium zinc oxide (InxZnyO, commonly referred to as "IZO"), zinc oxide (ZnxO), indium gallium zinc oxide (InxGayZnzO, commonly referred to as "IGZO"), indium gallium silicon oxide (InxGaySizO, commonly referred to as "IGSO"), and indium tungsten oxide (InxWyO, commonly referred to as "IWO"), and the material of the dielectric layer 220 may include silicon oxide. The initial first semiconductor layer is the active region in the undoped transistor. Dielectric layers 220 are located between each adjacent first semiconductor layer 210, and function as dielectric films to isolate the adjacent first semiconductor layers 210.

The ions doped in the first semiconductor layer 210 are the ions to be doped in the channel region 211. In some embodiments, the channel region 211 of the first semiconductor layer 210 is doped N-type, and the ions doped in the first semiconductor layer 210 may include ions of group v elements such As phosphorus (P) ions, bismuth (Bi) ions, antimony (Sb) ions, or arsenic (As) ions. In other embodiments, the channel region 211 In the first semiconductor layer 210 is P-doped, and the doped ions In the first semiconductor layer 210 may further include ions of group iii elements such as boron (B) ions, aluminum (Al) ions, gallium (Ga) ions, or indium (In) ions.

Additionally, in some embodiments, the step of forming an initial laminate structure may include: firstly, forming a whole laminated layer structure on the surface of a substrate 100, wherein the formed whole laminated layer structure covers the whole surface of the substrate 100; and removing the whole laminated layer structure in the region of the groove 300 through an etching process to form an initial laminated layer structure which is arranged on the substrate 100 at intervals. In other embodiments, the initial stacked structures may be formed in a spaced apart arrangement directly on the surface of the substrate 100.

Referring to fig. 2 to 3, in some embodiments, a sacrificial layer 310 arranged at intervals and extending in a third direction may be formed, the sacrificial layer 310 covering sides of the first semiconductor layer 210 of the channel region 211, and the sacrificial layer 310 being located between the first semiconductor layers 210 of adjacent channel regions 211 arranged in the third direction. The third direction is the same as the first direction X, that is, the third direction is a direction perpendicular to the surface of the substrate 100, and the sacrificial layer 310 extends in a direction perpendicular to the surface of the substrate 100. The sacrificial layer 310 is used for forming a word line structure in a subsequent step, and the position of the sacrificial layer 310 is a part of the position of the word line structure formed in the subsequent step.

Specifically, in some embodiments, the step of forming the sacrificial layer 310 may include: referring to fig. 2, an initial sacrificial layer 3101 is filled in the trench 300; referring to fig. 3, the initial sacrificial layer 3101 is patterned to form a sacrificial layer 310. The material of the sacrificial layer 310 may include silicon oxide, and in a subsequent step, the location of the sacrificial layer 310 will be used to form a word line structure. The process of patterning the initial sacrificial layer 3101 may include an etching process.

In other embodiments, the step of forming the sacrificial layer 310 may be to form the sacrificial layer 310 extending along the third direction directly on the side surface of the first semiconductor layer 210 of the channel region 211.

Referring to fig. 4, in some embodiments, a support layer 320 may be formed after forming the sacrificial layer 310, the support layer 320 being located between adjacent stacked structures 200, the support layer 320 covering sides of the sacrificial layer 310 and sides of the first semiconductor layer 210 of the sacrificial region 212. That is, the sacrificial layer 310 fills the trench 300 together with the supporting layer 320 (refer to fig. 3).

In some embodiments, the material of the support layer 320 may include silicon nitride. The support layer 320 can enable the stability of the semiconductor structure to be improved and the semiconductor structure to have higher mechanical strength. In addition, the material of the sacrificial layer 310 may include silicon oxide, the material of the sacrificial layer 310 is different from that of the supporting layer 320, and when the grooves for forming the word line structures are formed by subsequent etching, the sacrificial layer 310 can be selectively etched and removed, so that the supporting layer 320 is not removed, and the supporting layer 320 located in the central area of the trench 300 can play a role in isolating the adjacent word line structures.

Referring to fig. 5 to 6, in some embodiments, referring to fig. 5, the dielectric layer 220 between the first semiconductor layers 210 of the sacrificial region 212 in the stacked structure 200 (referring to fig. 4) may be removed to form a second void 230, the second void 230 exposing a side of the first semiconductor layer 210 of the sacrificial region 212 extending in the second direction Y. Referring to fig. 6, an isolation layer 240 is formed in the second void 230.

The process step of removing the dielectric layer 220 between the first semiconductor layers 210 of the sacrificial regions 212 in the stacked structure 200 may include an etching process. The etching process is a lateral etching process, which is particularly applied to the steps of the method for forming the semiconductor structure. The lateral etching is specifically, from the dielectric layer 220 to start etching inward at both sides in the second direction Y, and the etching direction is always toward the channel region 211. The dielectric layer 220 etched by the lateral etching process is the dielectric layer 220 between the first semiconductor layers 210 of the sacrificial region 212 in the first direction X, that is, the length of the first semiconductor layers 210 of the sacrificial region 212 in the second direction Y is defined by the second gap 230 formed by the lateral etching process, so as to control the length of the source drain regions of the subsequently formed transistors, and the first semiconductor layers 210 remaining after the lateral etching process is completed are the channels of the transistors. Thus, the length of the source and drain regions in the transistor formed later can be controlled by controlling the etching parameters of the etching process. For example, when the etching time of the lateral etching is longer, the length of the second void 230 formed at this time is longer, and the length of the source drain region in the finally formed transistor is longer; when the etching time of the lateral etching is shorter, the length of the second void 230 formed at this time is shorter, and the length of the source drain region in the finally formed transistor is shorter.

In some embodiments, the material of the isolation layer 240 formed within the second voids 230 may include silicon nitride. The isolation layer 240 is in contact with the remaining dielectric layer 230. The material of the sacrificial layer 310 is different from that of the isolation layer 240, so that the sacrificial layer 310 is selectively removed, the isolation layer 240 is not etched, and the isolation layer 240 protects the subsequently formed second semiconductor layer, so that the word line structure is not formed around the source drain region, i.e., the formed word line structure is only in contact with the channel region 211.

Referring to fig. 7, the first semiconductor layer 210 of the sacrificial region 212 is removed to form a recess 250. The recess 250 is used to form the source and drain regions of the transistor in a subsequent semiconductor structure formation process. It is understood that the width of the groove 250 along the extending direction of the first semiconductor layer 210 may be flush with the width of the isolation layer 240 along the extending direction of the first semiconductor layer 210, and the groove 250 may be opposite to the isolation layer 240 along the first direction X. In other embodiments, the width of the groove 250 along the extending direction of the first semiconductor layer 210 may be greater than or less than the width of the isolation layer 240 along the extending direction of the first semiconductor layer 210.

Referring to fig. 8, a second semiconductor layer 260 filling the recess 250 is formed, the second semiconductor layer 260 is doped with doping ions, and the second semiconductor layer 260 is in contact with the remaining first semiconductor layer 210. The second semiconductor layer 260 is used as a source/drain in the transistor, and the first semiconductor layer 210 is a channel in the transistor, and the source/drain is located at two sides of the channel and contacts the channel.

In some embodiments, the process steps of forming the second semiconductor layer 260 filling the recess 250 may include: a second semiconductor layer 260 is formed on the side of the first semiconductor layer 210 of the channel region 211 in the second direction using a selective epitaxial process, and in-situ doping of dopant ions is performed in the process step of forming the second semiconductor layer 260.

In forming the second semiconductor layer 260, doping ions are also doped into the second semiconductor layer 260 by in-situ doping at the same time as the second semiconductor layer 260 is grown gradually epitaxially from the side of the channel region 211 in the second direction of the first semiconductor layer 210. The second semiconductor layer 260 is not required to be subjected to ion implantation after the second semiconductor layer 260 is formed, so that the defect that doping ions cannot be doped into all transistors due to the influence of a dielectric layer by an ion implantation method is overcome, the doping ions can be uniformly distributed in each transistor in a semiconductor structure by forming the second semiconductor layer 260 through an in-situ doping and epitaxial deposition method, the manufacturing difficulty of the semiconductor structure is reduced, and the performance of the semiconductor structure can be improved.

In some embodiments, the material of the second semiconductor layer 260 may include silicon phosphide, silicon germanium, and the like. When the N-type doping is performed, the doping ions in the second semiconductor layer 260 may include ions of a v group element such As phosphorus (P) ions, bismuth (Bi) ions, antimony (Sb) ions, or arsenic (As) ions. When P-type doping is performed, the doping ions In the second semiconductor layer 260 may include ions of group iii elements such as boron (B) ions, aluminum (Al) ions, gallium (Ga) ions, or indium (In) ions.

In some embodiments, the first semiconductor layer 210 of the channel region 211 is doped with first doping ions, and the second semiconductor layer 260 is doped with first doping ions, and the concentration of the first doping ions in the second semiconductor layer 260 is greater than the concentration of the first doping ions in the first semiconductor layer 210. That is, the ions doped in the first semiconductor layer 210 may be the same as the ions doped in the second semiconductor layer 260, but the concentration of the ions doped in the second semiconductor layer 260 is greater than the concentration of the ions doped in the first semiconductor layer 210, in which case the transistor is a junction-free transistor. For example, when the transistor is an N-type transistor, the first doping ions in the first semiconductor layer 210 and the second semiconductor layer 260 may include ions of group v elements such As phosphorus (P) ions, bismuth (Bi) ions, antimony (Sb) ions, or arsenic (As) ions. When the transistor is a P-type transistor, the first doping ions In the first semiconductor layer 210 and the second semiconductor layer 260 may include ions of group iii elements such as boron (B) ions, aluminum (Al) ions, gallium (Ga) ions, or indium (In) ions.

In other embodiments, the first semiconductor layer 210 of the channel region 211 is doped with first doping ions, and the second semiconductor layer 260 is doped with second doping ions. That is, the ions doped in the first semiconductor layer 210 are different from the ions doped in the second semiconductor layer 260, and the transistor is a junction transistor. For example, when the first doping ions doped in the first semiconductor layer 210 are N-type doping ions, the second doping ions doped in the second semiconductor layer 260 may be P-type doping ions. When the first doping ions in the first semiconductor layer 210 are P-type doping ions, the second doping ions doped in the second semiconductor layer 260 may be N-type doping ions. The concentration of the first dopant ions in the second semiconductor layer 260 may be increased in a direction away from the first semiconductor layer 210, thereby suppressing a hot electron effect.

In some embodiments, the doping concentration of the doping ions within the second semiconductor layer 260 may increase in a direction away from the first semiconductor layer 210. That is, in the second semiconductor layer 260, the concentration of the dopant ions in the region close to the first semiconductor layer 210 is smaller than that in the region far from the first semiconductor layer 210. Thus, the contact resistance can be reduced, and the performance of the semiconductor structure can be further improved.

In some embodiments, when the second semiconductor layer 260 is P-doped, the process gas forming the second semiconductor layer 260 may include a silicon source gas, a germanium source gas, and a boron source gas. Or when the second semiconductor layer 260 is N-doped, the process gas forming the second semiconductor layer 260 includes a silicon source gas and a phosphorus source gas.

Referring to fig. 9 to 10, after forming the second semiconductor layer 260, in some embodiments, it may further include: the word line structures 330 extending in the third direction and arranged at intervals are formed, and the word line structures 330 surround the first semiconductor layer 210 of the channel regions 211 arranged in the third direction. The word line structure 330 is in sufficient contact with the channel of each transistor in the semiconductor structure, i.e., the word line structure 330 is in sufficient contact with each first semiconductor layer 210 stacked in the semiconductor structure.

Specifically, in some embodiments, the process steps of forming the word line structure 330 may include: referring to fig. 9, the dielectric layer 220 between the sacrificial layer 310 and the first semiconductor layer 210 of the channel region 211 in the stacked structure 200 is first removed to form a first void 340, and the first void 340 exposes a side surface of the first semiconductor layer 210 of the channel region 211 extending along the second direction. As can be seen from the above, the material of the sacrificial layer 310 located at the side of the first semiconductor layer 210 and extending in the first direction and the material of the dielectric layer 220 located between the stacked first semiconductor structures 210 may be silicon oxide. The process of removing the sacrificial layer 310 and the dielectric layer 220 between the first semiconductor layers 210 of the channel region 211 in the stacked structure 200 may be an etching process, where the first space 340 is formed, that is, where the word line structure 330 needs to be formed.

In addition, the material etched by the etching process is silicon oxide. As can be seen from the above, the interlayer material facing the second semiconductor layer 260 is the isolation layer 240, the isolation layer 240 is made of silicon nitride, the interlayer material facing the second semiconductor layer 260 is the dielectric layer 220 before the isolation layer 240 is formed, and the dielectric layer 220 is made of silicon oxide. Replacing the dielectric layer 220 opposite to the second semiconductor layer 260 with the isolation layer 240 ensures that the etching range is more precise when the one-step etching process is performed, and the formed word line structure 330 can maximize the contact range between the first semiconductor layer 210 and the word line structure 330 while only contacting the first semiconductor layer 210 serving as a channel. The performance of the semiconductor structure can be further improved, and the manufacturing difficulty of the semiconductor structure can be further reduced because the etching process does not need to control the etching range.

Referring to fig. 10, a word line structure 330 is formed within the first void 340. The word line structure 330 may include a lateral word line dielectric layer covering the first semiconductor layer 210 extending in the second direction and a word line conductive layer covering a surface of the word line dielectric layer and filling the first void 340.

Another embodiment of the present application further provides a method for forming a semiconductor structure, which is substantially the same as the method for forming a semiconductor structure provided in the foregoing embodiment, and is mainly different in that a word line structure formed by the method for forming a semiconductor structure provided in the other embodiment of the present application extends in a direction parallel to a surface of a substrate, and an extending direction of the word line structure is the same as an arrangement direction of a stacked structure.

The method for forming a semiconductor structure according to another embodiment of the present application will be described in detail with reference to the accompanying drawings, and the same or corresponding parts as those of the foregoing embodiments will be referred to for details of the foregoing embodiments, which will not be repeated.

First, a substrate and a stacked structure disposed on a surface of the substrate at intervals are provided, and the substrate and the stacked structure are the same as those described in the above embodiments, and are not described herein again.

In some embodiments, the step of forming the substrate to form a laminate structure may include: providing a substrate; forming initial laminated structures which are arranged at intervals on a substrate, wherein the initial laminated structures comprise initial first semiconductor layers and dielectric layers which are alternately arranged along a first direction, grooves are formed between the initial laminated structures, and the grooves expose the side surfaces of the initial first semiconductor layers; the initial first semiconductor layer is doped through the trench to form a first semiconductor layer arranged along a first direction.

Wherein the material of the initial first semiconductor layer may comprise silicon and the material of the dielectric layer may comprise silicon oxide. The ions doped in the first semiconductor layer are the ions to be doped in the channel region. The doped ions in the first semiconductor layer may be N-type doped ions or P-type doped ions.

Since the extending direction of the word line structure is the same as the arrangement direction of the stacked structure, and the word line structure needs to be located around the first semiconductor layer and contact with the first semiconductor layer, the sacrificial layer formed later needs to be located between the stacked first semiconductor layers at the channel region. Therefore, the dielectric layer opposite to the semiconductor layer of the source/drain region needs to be replaced by an isolation layer, and then a sacrificial layer is formed.

In some embodiments, removing the dielectric layer between the first semiconductor layers of the sacrificial region in the stacked structure to form a fourth void exposing a side of the first semiconductor layer of the sacrificial region extending in the second direction; and forming an isolation layer in the fourth gap.

The process step of removing the dielectric layer between the first semiconductor layers of the sacrificial region in the stacked structure may include an etching process, and the length of the source/drain region in the transistor formed later may be controlled by controlling the etching parameters of the etching process. The material of the dielectric layer may include silicon oxide, and the material of the isolation layer may include silicon nitride, so that when the word line structure is subsequently formed, the formed word line structure is only in contact with the first semiconductor layer of the channel region.

In some embodiments, the dielectric layer between the first semiconductor layers of the channel region may be removed to form the sacrificial layer. In a subsequent step, the sacrificial layer and the support layer are both located between the stacked different first semiconductor layers.

The process of removing the dielectric layer between the first semiconductor layers of the channel region may be an etching process.

Referring to fig. 11, fig. 11 is a schematic cross-sectional view of a step in a method for forming a semiconductor structure according to an embodiment of the present disclosure, wherein a cross-sectional view of the schematic cross-sectional view is an arrangement direction of a stacked structure 500, and fig. 11 is a cross-section at a first semiconductor layer 510 of a channel region 511, and the cross-section is perpendicular to a surface of a substrate 400. In some embodiments, the sacrificial layer 610 is formed to be spaced apart and extend in the third direction, the sacrificial layer 610 surrounding the side of the first semiconductor layer 510 of the channel region 511. The third direction is the arrangement direction of the stacked structure 500. The extension direction of the sacrificial layer 610 is parallel to the surface of the substrate 400.

Referring to fig. 12, fig. 12 is a schematic cross-sectional view illustrating a step in a method for forming a semiconductor structure according to an embodiment of the disclosure. The support layer 620 is formed, and the support layer 620 is located between the sacrificial layers 610 surrounding the different first semiconductor layers 510. In some embodiments, the material of support layer 620 may include silicon nitride.

Referring to fig. 13 to 14, fig. 14 is a schematic structural diagram of a step in a method for forming a semiconductor structure according to an embodiment of the disclosure, and fig. 13 is a schematic sectional view along AA1 of fig. 4. The process steps for forming the word line structures 630 may include: the sacrificial layer 610 is removed to form a third void 650, and the third void 650 exposes a side surface of the first semiconductor layer 510 of the channel region 511 extending in the second direction Y. The process of removing the sacrificial layer 610 may be an etching process.

Referring to fig. 15 to 16, fig. 16 is a schematic structural diagram of a step in a method for forming a semiconductor structure according to an embodiment of the disclosure, and fig. 15 is a schematic sectional structural diagram of fig. 16 along BB 1. The word line structure 630 is formed within the third void 650 (refer to fig. 14). The word line structure 630 formed at this time extends in the arrangement direction of the stacked structure 500, and the word line structure 630 is in contact with the first semiconductor layer 510 of the channel region 511.

The embodiment of the disclosure provides a method for forming a semiconductor structure, firstly providing a substrate 100 and a stacked structure 200 arranged at intervals on the substrate 100, wherein the stacked structure 200 includes a first semiconductor layer 210 arranged at intervals along a first direction X, the first semiconductor layer 210 includes a channel region 211 and sacrificial regions 212 on two sides of the channel region 211, the two sacrificial regions 212 of the first semiconductor layer 210 are arranged along a second direction Y, then removing the first semiconductor layer 210 in the sacrificial regions 212 to form a groove, then filling a second semiconductor layer doped with doped ions in the groove, and the second semiconductor layer is in contact with the rest of the first semiconductor layer 210. Thus, the manufacturing difficulty of the semiconductor structure can be reduced, and the performance of the semiconductor structure can be improved.

Accordingly, another embodiment of the present disclosure further provides a semiconductor structure manufactured by the method for forming a semiconductor structure, and the semiconductor structure provided in another embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

Fig. 17 to 18 are schematic structural diagrams of a semiconductor structure according to an embodiment of the present disclosure.

Referring to fig. 17 to 18, the semiconductor structure includes: a substrate 100; the stacked structure is arranged on the substrate 100 at intervals and comprises semiconductor layers arranged at intervals along a first direction, the semiconductor layers comprise a first semiconductor layer 210 and second semiconductor layers arranged at two sides of the first semiconductor layer 210, two second semiconductor layers in the semiconductor layers are arranged along a second direction, and doping ions are doped in the second semiconductor layers; the support layers extend along the third direction and are distributed at intervals, and the support layers are positioned between the adjacent stacking structures; and the isolation layer is positioned between the second semiconductor layers.

In some embodiments, the substrate 100 may be a silicon substrate, which may include one or more of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon. In other embodiments, the material of the substrate 100 may also include silicon carbide, an organic material, or a multi-compound. The multi-component compounds may include, but are not limited to, perovskite, gallium arsenide, cadmium telluride, copper indium selenium, and the like. Illustratively, the substrate 100 in the presently disclosed embodiments is a single crystal silicon substrate 100.

In some embodiments, the first semiconductor layer 210 is doped with first doping ions, and the second semiconductor layer is doped with first doping ions, wherein the concentration of the first doping ions in the second semiconductor layer is greater than the concentration of the first doping ions in the first semiconductor layer 210; that is, the ions doped in the first semiconductor layer 210 may be the same as the ions doped in the second semiconductor layer, but the concentration of the ions doped in the second semiconductor layer is greater than the concentration of the ions doped in the first semiconductor layer 210. At this time, the transistor is a junction-free transistor. For example, when the transistor is an N-type transistor, the first doping ions in the first semiconductor layer 210 and the second semiconductor layer may include ions of a group v element such As phosphorus (P) ions, bismuth (Bi) ions, antimony (Sb) ions, or arsenic (As) ions. When the transistor is a P-type transistor, the first doping ions In the first semiconductor layer 210 and the second semiconductor layer may include ions of group iii elements such as boron (B) ions, aluminum (Al) ions, gallium (Ga) ions, or indium (In) ions.

Or in other embodiments, the first semiconductor layer 210 is doped with first dopant ions and the second semiconductor layer is doped with second dopant ions. That is, the doped ions in the first semiconductor layer 210 are different from the doped ions in the second semiconductor layer, and the transistor is a junction transistor. For example, when the first doping ions doped in the first semiconductor layer 210 are N-type doping ions, the second doping ions doped in the second semiconductor layer may be P-type doping ions. When the first doped ions in the first semiconductor layer 210 are P-type doped ions, the second doped ions doped in the second semiconductor layer may be N-type doped ions.

In some embodiments, the word line structures extend along the third direction and are spaced apart, and the word line structures surround the first semiconductor layer 210 arranged along the third direction. The third direction may have a different direction, and the third direction may be the same as the first direction X, and may also be the same as the arrangement direction of the stacked structure.

Referring to fig. 17, in some embodiments, the third direction is the same as the first direction X. That is, the third direction is perpendicular to the surface of the substrate 100, and the word line structure 330 is perpendicular to the surface of the substrate 100. At this time, the support layer 320 is located between the adjacent word line structures 330 in the arrangement direction along the stacked structure, and the support layer 320 is located between the second semiconductor layers 260. In the first direction X, the isolation layer 240 is located between the second semiconductor layers 260.

Referring to fig. 18, in some embodiments, the third direction is the same as the arrangement direction of the stacked structure. That is, the third direction is parallel to the surface of the substrate 100, and the word line structure 630 is parallel to the surface of the substrate 100. At this time, the support layer 620 is located between adjacent word line structures 630 and the isolation layer 540 is located between the second semiconductor layers 560 in the first direction. The isolation layer 540 is also located between the stacked structures in the arrangement direction along the stacked structures.

Wherein the material of the isolation layer 540 may comprise silicon nitride. The material of the support layer 620 may include silicon nitride.

The embodiment of the disclosure provides a semiconductor structure, which has a substrate 100 and a stacked structure disposed on the substrate 100 at intervals, wherein the stacked structure includes semiconductor layers disposed along a first direction X at intervals, the semiconductor layers include a first semiconductor layer 210 and second semiconductor layers, the second semiconductor layers are disposed on two sides of the first semiconductor layer 210, two second semiconductor layers in the semiconductor layers are disposed along a second direction Y, and doped ions are disposed in the second semiconductor layers. The semiconductor structure is also provided with supporting layers which extend along the third direction and are arranged at intervals, the supporting layers are positioned between the adjacent stacked structures, and the isolating layers are positioned between the second semiconductor layers. Therefore, the doping conditions of doping ions in different semiconductor layers are uniform, each semiconductor layer has doping ions, and the performance of the semiconductor structure can be improved.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure. Variations and modifications may be made by one skilled in the art without departing from the spirit and scope of the disclosure, and the scope of the disclosure should therefore be assessed only by that of the appended claims.

Claims (18)

1. A method of forming a semiconductor structure, comprising:

Providing a substrate and a laminated structure which is arranged on the substrate at intervals, wherein the laminated structure comprises first semiconductor layers which are arranged along a first direction at intervals, the first semiconductor layers comprise a channel region and sacrificial regions which are arranged at two sides of the channel region,

The two sacrificial regions of the first semiconductor layer are arranged along a second direction;

removing the first semiconductor layer of the sacrificial region to form a groove;

And forming a second semiconductor layer filling the groove, wherein the second semiconductor layer is doped with doping ions, and the second semiconductor layer is contacted with the rest of the first semiconductor layer.

2. The method of forming a semiconductor structure of claim 1, wherein forming the second semiconductor layer filling the recess comprises: the second semiconductor layer is formed on the side surface of the first semiconductor layer of the channel region in the second direction by adopting a selective epitaxial process, and in-situ doping of the doping ions is performed in the process step of forming the second semiconductor layer.

3. The method of claim 2, wherein the first semiconductor layer of the channel region is doped with first dopant ions and the second semiconductor layer is doped with first dopant ions, the concentration of the first dopant ions in the second semiconductor layer being greater than the concentration of the first dopant ions in the first semiconductor layer; or alternatively

The first semiconductor layer of the channel region is doped with first doping ions and the second semiconductor layer is doped with second doping ions.

4. The method of claim 2, wherein the process gas for forming the second semiconductor layer comprises a silicon source gas, a germanium source gas, and a boron source gas; or the process gas for forming the second semiconductor layer includes a silicon source gas and a phosphorus source gas.

5. The method of claim 1, wherein the first direction is a direction perpendicular to the substrate surface and the second direction is a direction parallel to the substrate surface.

6. The method of forming a semiconductor structure of claim 1, further comprising, after forming the second semiconductor layer:

and forming a word line structure extending along a third direction and arranged at intervals, wherein the word line structure surrounds the first semiconductor layer of the channel region arranged along the third direction.

7. The method of forming a semiconductor structure of claim 6, wherein the third direction is the same as the first direction, the stacked structure including first semiconductor layers and dielectric layers alternately arranged along the first direction, the method further comprising:

Forming sacrificial layers which are arranged at intervals and extend along the third direction, wherein the sacrificial layers cover the side surfaces of the first semiconductor layers of the channel regions, and the sacrificial layers are positioned between the first semiconductor layers of the adjacent channel regions which are arranged along the third direction;

Forming a support layer between adjacent laminated structures, wherein the support layer covers the side surface of the sacrificial layer and the side surface of the first semiconductor layer of the sacrificial region;

Forming the word line structure includes: removing the dielectric layer between the sacrificial layer and the first semiconductor layer of the channel region in the laminated structure to form a first gap, wherein the first gap exposes the side surface of the first semiconductor layer of the channel region extending along the second direction;

The word line structure is formed within the first void.

8. The method of forming a semiconductor structure of claim 7, wherein providing the stacked structure including the first semiconductor layer comprises:

Providing the substrate;

Forming an initial laminated structure which is arranged at intervals on the substrate, wherein the initial laminated structure comprises initial first semiconductor layers and dielectric layers which are alternately arranged along the first direction, grooves are formed between the initial laminated structures, and the grooves expose the side surfaces of the initial first semiconductor layers;

and doping the initial first semiconductor layer through the grooves to form the first semiconductor layer arranged along the first direction.

9. The method of forming a semiconductor structure of claim 8, wherein forming a sacrificial layer spaced apart and extending along the third direction comprises:

Filling an initial sacrificial layer in the groove;

patterning the initial sacrificial layer to form a layer along the sacrificial layer.

10. The method of forming a semiconductor structure of claim 7, wherein prior to removing the first semiconductor layer of the sacrificial region to form a recess, further comprising:

removing the dielectric layer between the first semiconductor layers of the sacrificial region in the laminated structure to form a second gap, wherein the second gap exposes the side surface of the first semiconductor layer of the sacrificial region extending along the second direction;

And forming an isolation layer in the second gap.

11. The method of forming a semiconductor structure according to claim 6, wherein the third direction is the same as an arrangement direction of the stacked structure, the method further comprising:

Forming sacrificial layers which are arranged at intervals and extend along the third direction, wherein the sacrificial layers encircle the side face of the first semiconductor layer of the channel region;

Forming a support layer between sacrificial layers surrounding the first semiconductor layers of different layers;

Forming the word line structure includes: removing the sacrificial layer to form a third gap exposing a side surface of the first semiconductor layer of the channel region extending in the second direction;

The word line structure is formed within the third void.

12. The method of claim 11, wherein providing the stacked structure including the first semiconductor layer prior to forming the sacrificial layer comprises:

Providing the substrate;

Forming an initial laminated structure which is arranged at intervals on the substrate, wherein the initial laminated structure comprises initial first semiconductor layers and dielectric layers which are alternately arranged along the first direction, grooves are formed between the initial laminated structures, and the grooves expose the side surfaces of the initial first semiconductor layers;

Doping the initial first semiconductor layer through the grooves to form first semiconductor layers arranged along the first direction;

And removing the dielectric layer between the first semiconductor layers of the channel region to form the sacrificial layer.

13. The method of claim 12, wherein prior to removing the dielectric layer between the first semiconductor layers of the channel region, the method further comprises:

Removing the dielectric layer between the first semiconductor layers of the sacrificial region in the laminated structure to form a fourth gap, wherein the fourth gap exposes the side surface of the first semiconductor layer of the sacrificial region extending along the second direction;

And forming an isolation layer in the fourth gap.

14. A semiconductor structure, comprising:

a substrate;

The semiconductor device comprises a substrate, a stacking structure arranged on the substrate at intervals, and a plurality of semiconductor layers, wherein the stacking structure comprises semiconductor layers arranged at intervals along a first direction, each semiconductor layer comprises a first semiconductor layer and second semiconductor layers arranged on two sides of the first semiconductor layer, two second semiconductor layers in the semiconductor layers are arranged along a second direction, and doped ions are doped in the second semiconductor layers;

the support layers extend along the third direction and are distributed at intervals, and the support layers are located between the adjacent stacking structures;

and the isolation layer is positioned between the second semiconductor layers.

15. The semiconductor structure of claim 14, further comprising:

and the word line structures extend along a third direction and are arranged at intervals, and the word line structures encircle the first semiconductor layers arranged along the third direction.

16. The semiconductor structure of claim 14, wherein the first semiconductor layer is doped with first dopant ions and the second semiconductor layer is doped with first dopant ions, the concentration of first dopant ions in the second semiconductor layer being greater than the concentration of first dopant ions in the first semiconductor layer;

Or the first semiconductor layer is doped with first doping ions, and the second semiconductor layer is doped with second doping ions.

17. The semiconductor structure of claim 15, wherein the third direction is the same as the first direction; the support layer is positioned between adjacent word line structures along the arrangement direction of the stacked structures, and the support layer is positioned between the second semiconductor layers; the isolation layer is located between the second semiconductor layers along the first direction.

18. The semiconductor structure of claim 15, wherein the third direction is the same as an arrangement direction of the stacked structure; along the first direction, the support layer is positioned between adjacent word line structures, and the isolation layer is positioned between the second semiconductors; the isolation layers are also located between the stacked structures along the arrangement direction of the stacked structures.