CN118100878B

CN118100878B - Clock switching circuit integrating switching detection logic, chip and switching detection method

Info

Publication number: CN118100878B
Application number: CN202410487397.5A
Authority: CN
Inventors: 何再生; 赵伟兵; 肖刚军; 许登科
Original assignee: Zhuhai Amicro Semiconductor Co Ltd
Current assignee: Zhuhai Amicro Semiconductor Co Ltd
Priority date: 2024-04-23
Filing date: 2024-04-23
Publication date: 2024-07-05
Anticipated expiration: 2044-04-23
Also published as: CN118100878A

Abstract

The application discloses a clock switching circuit integrating switching detection logic, a chip and a switching detection method. When the output end of the second or gate outputs the first level under the condition that the selection signal is turned from the second level to the first level, the output end of the D flip-flop in the first switching detection logic circuit is set to the first level, and the switching from the second clock signal to the first clock signal is determined; when the selection signal is turned from the first level to the second level and the output end of the second or gate outputs the first level, the output end of the D flip-flop in the second switching detection logic circuit is set to the first level, and the switching from the first clock signal to the second clock signal is determined.

Description

Clock switching circuit integrating switching detection logic, chip and switching detection method

Technical Field

The present application relates to the field of clock sampling circuits, and in particular, to a clock switching circuit, a chip and a switching detection method for integrating switching detection logic.

Background

In system-on-chip design, as the system becomes larger and larger, the application scenarios that need to be faced also become complex. Some circuits in a system-on-chip will sometimes operate at higher frequencies (over 1 GHz) and at lower frequencies (below 1MHz, e.g., 32 KHz), which requires that the clock source of the circuit must be able to switch between high and low frequencies.

The clock switching circuit adopted in the integrated circuit design completes the switching of input clock signals, but due to the difference of the frequency of the input clocks and the non-synchronization of selection control signals, burrs of the clock signals or the time interval between adjacent jump edges are easily caused to be smaller than or equal to the half period of the currently switched clock in the process of switching into higher frequency clock signals, if the frequency of the currently switched clock exceeds 1GHz or even higher, the problem of unstable signal establishment time of a logic device can be caused, false triggering events are easily caused, the circuit works abnormally, and errors occur, so that the reliability of a system is influenced.

In order to solve the above problems, the high-frequency clock seamless switching circuit disclosed in chinese patent 2016103738577 does not adopt the design concept of clock seamless switching by sampling the rising edge and falling edge of the clock, but only adopts the manner of triggering the jump and the latch processing of the gate logic circuit by the clock single edge and gate logic circuit, when the clock source is switched, the signal output by the two input or gate is pulled down to enter the clock stop time (clock seamless switching period), after the clock stop time, the clock signal to be switched is output, and in the process of switching into the higher-frequency clock signal, the clock signal has burrs or the time interval between the adjacent jump edges is less than or equal to the half period of the clock switched currently, so that the high-frequency clock seamless switching circuit disclosed in chinese patent 2016103738577 is not affected by frequent jump of the signal edge whether it is high-frequency cut low-frequency or low-frequency cut high-frequency.

However, the high-frequency clock seamless switching circuit disclosed in chinese patent 2016103738577 does not detect whether the clock signal is switched. If a software system is used to control the high-frequency clock seamless switching circuit to perform clock switching, the original working clock (the clock to be switched) is generally turned off to save power consumption, if the frequency of the clock to be switched is low, the original working clock (the clock with relatively high frequency) is already turned off before the actual switching is completed, so that the system where the original working clock is located cannot operate because of no clock, which means that the high-frequency clock seamless switching circuit turns off the original working clock (the clock with relatively high frequency) before reaching the end of the clock stopping time, resulting in a phenomenon that the clock system is suspended, and therefore, a need exists for detecting the situation of clock signal switching.

Disclosure of Invention

The application discloses a clock switching circuit integrating switching detection logic, a chip and a switching detection method, and the specific technical scheme is as follows:

A clock switching circuit integrating the switching detection logic, the clock switching circuit including a first clock domain circuit and a second clock domain circuit; the output end of the first clock domain circuit and the output end of the first D trigger cascade circuit are respectively connected with the input end of the first switching detection logic circuit; the output end of the first switching detection logic circuit is used for indicating the target switching clock signal to be switched from the second clock signal to the first clock signal; the output end of the second clock domain circuit and the output end of the second D trigger cascade circuit are respectively connected with the input end of the second switching detection logic circuit; the output end of the second switching detection logic circuit is used for indicating the switching of the target switching clock signal from the first clock signal to the second clock signal; the output end of the first switching detection logic circuit and the output end of the second switching detection logic circuit are respectively connected with two input ends of the second OR gate, and the output end of the second OR gate is used for indicating that the clock signal switching is completed.

Specifically, the first clock domain circuit and the second clock domain circuit each comprise an AND gate and at least four D flip-flops connected in cascade; the output end of the AND gate in the first clock domain circuit is connected with the input end of the first stage D trigger in the first clock domain circuit; the AND gate in the first clock domain circuit is used for inputting a selection signal and a signal output by the inverting output end of the D flip-flop of the last stage in the second clock domain circuit respectively; the output end of the AND gate in the second clock domain circuit is connected with the input end of the first-stage D trigger in the second clock domain circuit; the AND gate in the second clock domain circuit is used for inverting the selection signal input respectively and outputting the signal output by the inverting output end of the D flip-flop of the last stage in the first clock domain circuit; The clock end of each D trigger in the first clock domain circuit is used for inputting a first clock signal; the clock end of each D trigger in the second clock domain circuit is used for inputting a second clock signal; the clock switching circuit further comprises a first D trigger cascade circuit, a second D trigger cascade circuit, a first switching detection logic circuit, a second switching detection logic circuit and a second OR gate; the first switching detection logic circuit and the second switching detection logic circuit comprise a D trigger and a multi-input combination logic circuit; the clock end of the D trigger in the first switching detection logic circuit is used for inputting a first clock signal; the clock end of the D trigger in the second switching detection logic circuit is used for inputting a second clock signal; The first D trigger cascade circuit and the second D trigger cascade circuit comprise at least three D triggers which are connected in cascade; the input end of the first-stage D trigger in the first D trigger cascade circuit is used for inputting a selection signal, and the input end of the first-stage D trigger in the second D trigger cascade circuit is used for inputting an inversion signal of the selection signal; the positive output end of the penultimate D trigger in the first clock domain circuit, the positive output end of the penultimate D trigger in the first D trigger cascade circuit and the negative output end of the penultimate D trigger in the first D trigger cascade circuit are respectively connected with the input end of the multi-input combination logic circuit in the first switching detection logic circuit; The output end of the multi-input combination logic circuit in the first switching detection logic circuit is connected with the input end of the D trigger in the first switching detection logic circuit; the non-inverting output end of the D trigger in the first switching detection logic circuit is an output end used for indicating that the target switching clock signal is switched from the second clock signal to the first clock signal in the first switching detection logic circuit; the positive output end of the last-second-stage D trigger in the second clock domain circuit, the positive output end of the last-first-stage D trigger in the second D trigger cascade circuit and the negative output end of the last-second-stage D trigger in the second D trigger cascade circuit are respectively connected with the input end of the multi-input combination logic circuit in the second switching detection logic circuit; The output end of the multi-input combination logic circuit in the second switching detection logic circuit is connected with the input end of the D trigger in the second switching detection logic circuit; the positive phase output end of the D trigger in the second switching detection logic circuit is an output end used for indicating that the target switching clock signal is switched from the first clock signal to the second clock signal in the second switching detection logic circuit; the positive phase output end of the D trigger in the first switching detection logic circuit and the positive phase output end of the D trigger in the second switching detection logic circuit are respectively connected with two input ends of a second OR gate, and the output end of the second OR gate is a port used for indicating that clock signal switching is completed in the clock switching circuit.

In summary, according to the application, the first D flip-flop cascade circuit, the second D flip-flop cascade circuit, the first switch detection logic circuit, the second switch detection logic circuit, and the second or gate are the first clock domain circuit and the second clock domain circuit to add the switch detection logic, so that the clock signal of the switch output can be used after the switch is completed when the first clock signal is completely switched to the second clock signal output or the second clock signal is completely switched to the first clock signal output, and the clock switch completion indication signal is provided; whether the clock signal with relatively high frequency is switched to the clock signal with relatively low frequency or the clock signal with relatively low frequency is switched to the clock signal with relatively high frequency, the phenomenon that the clock system is not successfully switched or is dead due to the fact that the clock is switched off in advance in the switching process is solved.

A switching detection method based on the clock switching circuit, the switching detection method comprising:

Performing AND operation on the selection signal and a signal output by an inverting output end of a first stage D trigger of the second clock domain circuit, and inputting a result of the AND operation into the first stage D trigger of the first clock domain circuit; then continuously sampling at least three clock cycles in the first clock domain circuit by using the first clock signal, so that the second last stage D trigger of the first clock domain circuit outputs an input signal from the first stage D trigger of the first clock domain circuit;

inverting the selection signal to obtain an inverted signal of the selection signal, performing AND operation on the inverted signal and a signal output by an inverted output end of a first-stage D trigger of a first clock domain circuit, inputting a result of AND operation into the first-stage D trigger of a second clock domain circuit, and continuously sampling at least three clock cycles in the second clock domain circuit by using the second clock signal to enable the second-stage D trigger of the second clock domain circuit to output an input signal from the first-stage D trigger of the second clock domain circuit;

the signal output by the positive phase output end of the second last stage D trigger of the first clock domain circuit and the first clock signal are sent to a first gating unit for gating, and a first gating clock signal is obtained; the signal output by the positive phase output end of the last second stage D trigger of the second clock domain circuit and the second clock signal are sent to a second gating unit for gating, and a second gating clock signal is obtained;

then, performing OR operation on the first gating clock signal and the second gating clock signal to obtain a target switching clock signal;

The switching detection method further comprises the following steps:

The selection signal is sent to the input end of a first stage D trigger of a first D trigger cascade circuit, and at least two clock cycles of output are continuously sampled by a first clock signal in the first D trigger cascade circuit; the method comprises the steps of sending a signal output by an inverted output end of a last second-stage D trigger of a first D trigger cascade circuit and a signal output by a normal phase output end of a last first-stage D trigger of the first D trigger cascade circuit to a two-input NAND gate in a first switching detection logic circuit for NAND operation to obtain a first one-to-one detection signal;

Inverting the selection signal to obtain an inverting signal of the selection signal, sending the inverting signal to the input end of a first stage D trigger of a second D trigger cascade circuit, and continuously sampling at least two clock cycles by using a second clock signal in the second D trigger cascade circuit for outputting; the signal output by the inverting output end of the last second stage D trigger of the second D trigger cascade circuit and the signal output by the non-inverting output end of the last first stage D trigger of the second D trigger cascade circuit are sent to a two-input NAND gate in a second switching detection logic circuit to be subjected to NAND operation, so that a second first detection signal is obtained;

in the first clock domain circuit, a first clock signal is used for continuously sampling at least three clock cycles, and the inverse signal of the signal output by the positive phase output end of the D flip-flop of the reciprocal first stage of the first clock domain circuit and the signal output by the positive phase output end of the D flip-flop of the reciprocal second stage of the first clock domain circuit are sent to a first preset two-input AND gate in a first switching detection logic circuit for performing AND operation to obtain a first two-detection signal; the first two detection signals and the signal output by the non-inverting output end of the D trigger in the first switching detection logic circuit are sent to two input OR gates in the first switching detection logic circuit to perform OR operation, so that a first three detection signal is obtained; then, the first one-to-one detection signal and the first third detection signal are sent to a second preset two-input AND gate in the first switching detection logic circuit to perform AND operation, so that a first fourth detection signal is obtained; the first four detection signals are sent to the input end of a D trigger in the first switching detection logic circuit, and the first clock signals are used for sampling one clock period to latch the first four detection signals;

Continuously sampling at least three clock cycles in a second clock domain circuit by using a second clock signal, and transmitting a signal inverse to a signal output by a positive phase output end of a first-to-last stage D trigger of the second clock domain circuit and a signal output by a positive phase output end of a second-to-last stage D trigger of the second clock domain circuit to a first preset two-input AND gate in a second switching detection logic circuit for performing AND operation to obtain a second detection signal; the second detection signal and the signal output by the positive phase output end of the D trigger in the second switching detection logic circuit are sent to a two-input OR gate in the second switching detection logic circuit for OR operation, so that a second third detection signal is obtained; then, the second detection signal and the second third detection signal are sent to a second preset two-input AND gate in a second switching detection logic circuit to perform AND operation, so that a second fourth detection signal is obtained; sending a second fourth detection signal to the input end of the D trigger in the second switching detection logic circuit, and sampling one clock cycle by using a second clock signal to latch the second fourth detection signal;

And then the signal output by the positive phase output end of the D trigger in the first switching detection logic circuit and the signal output by the positive phase output end of the D trigger in the second switching detection logic circuit are sent to a second OR gate for OR operation, so as to obtain a switching indication signal for indicating the completion of clock signal switching.

When the output end of the D flip-flop in the first switching detection logic circuit is set to be at the first level when the output end of the second OR gate outputs the first level under the condition that the selection signal is turned over from the second level to the first level, determining that the target switching clock signal output by the output end of the first OR gate is switched from the second clock signal to the first clock signal, and then closing the second clock signal;

When the selection signal is turned from the first level to the second level and the output end of the second or gate outputs the first level, the output end of the D trigger in the second switching detection logic circuit is set to the first level, the target switching clock signal output by the output end of the first or gate is determined to be switched from the first clock signal to the second clock signal, and then the first clock signal is closed;

Wherein the second level is lower than the first level, and the frequency of the second clock signal is different from the frequency of the first clock signal.

In summary, by executing the switching detection method, after determining the start point of the clock stop time when the first clock signal is switched to the second clock signal, the first D flip-flop cascade circuit determines the end point of the clock stop time through the second switching detection logic circuit; or the second D flip-flop cascade circuit may determine, through the first switching detection logic circuit, an end point of the clock stop time after determining that the start point of the clock stop time is entered in a process of switching the second clock signal to the first clock signal.

Therefore, according to the turnover condition of the selection signal, on the basis that the first D trigger cascade circuit or the second D trigger cascade circuit continuously samples at least two clock cycles for transmission, the multi-input combination logic circuit in each switching detection logic circuit is utilized to detect the clock switching condition within enough clock stopping time, so that the reliability of switching detection is improved. Therefore, when the first clock signal is completely switched to the second clock signal output or the second clock signal is completely switched to the first clock signal output, the clock switching completion indication signal is provided, and the clock signal of the switching output can be ensured to be used after the switching is completed; whether the clock signal with relatively high frequency is switched to the clock signal with relatively low frequency or the clock signal with relatively low frequency is switched to the clock signal with relatively high frequency, the phenomenon that the clock is not successfully switched or the clock system is suspended in the switching process because the clock is turned off in advance is prevented, the problem that the clock switching detection is influenced due to unstable signal establishment time of a logic device is solved, the accuracy and stability of triggering detection in the clock switching process are improved, the clock signal is ensured to be used after the switching is finished based on the finally output switching indication signal, and the original working clock signal can be turned off for low power consumption.

Drawings

Fig. 1 is a schematic diagram of a clock switching circuit with integrated switching detection logic according to an embodiment of the present application.

Detailed Description

The following describes the technical solution in the embodiment of the present invention in detail with reference to the drawings in the embodiment of the present invention.

As an embodiment, the present embodiment discloses a clock switching circuit integrating switching detection logic, the clock switching circuit including a first clock domain circuit, a second clock domain circuit, a first gating unit (which may be constituted by a latch), a second gating unit (which may be constituted by a latch), and a first or gate; in this embodiment, the first clock domain circuit and the second clock domain circuit each use one clock signal, which can be recorded as two clock domain circuits, and the two clock domain circuits can be regarded as two clock domain circuits with symmetrical structures in the application; the first clock domain circuit and the second clock domain circuit comprise an AND gate and at least four D flip-flops connected in cascade; of course, 5 cascaded D flip-flops, 6 cascaded D flip-flops, and even more stages of D flip-flops may be used in each clock domain circuit, and the clock stopping time generated in the clock switching process may also need to be adaptively changed.

The output end of the AND gate in the first clock domain circuit is connected with the input end of the first-stage D trigger in the first clock domain circuit, the AND gate in the first clock domain circuit is used for inputting a selection signal and a signal output by the inverted output end of the inverted first-stage D trigger in the second clock domain circuit respectively, the output end of the AND gate in the second clock domain circuit is connected with the input end of the first-stage D trigger in the second clock domain circuit, and the AND gate in the second clock domain circuit is used for inverting the selection signal input respectively and outputting a signal output by the inverted output end of the inverted first-stage D trigger in the first clock domain circuit; it can be understood that one input end of the and gate in the first clock domain circuit is connected to a selection signal, the other input end of the and gate in the first clock domain circuit is connected to the inverted output end of the penultimate stage D flip-flop in the second clock domain circuit, and one input end of the and gate in the second clock domain circuit inputs the selection signal through an inverter, and one input end of the and gate in the second clock domain circuit is connected to the inverted signal of the selection signal; the other input end of the AND gate in the first clock domain circuit is connected with the inverted output end of the inverted first stage D trigger in the second clock domain circuit, meanwhile, the other input end of the AND gate in the second clock domain circuit is connected with the inverted output end of the inverted first stage D trigger in the first clock domain circuit, the signal interaction relation between the first clock domain circuit and the second clock domain circuit is established, not only the selection signal is shared, but also the time sequence signal transmission condition of the other clock domain circuit is determined based on the time sequence signal transmission condition of the inverted first stage D trigger of one clock domain circuit (namely, the signal sampling condition according to the adopted clock signal) so that the output signal of the inverted output end of the inverted first stage D trigger of one clock domain circuit (driven by the current working clock) is a key signal for pushing the other clock domain circuit (not driven by the current working clock) to carry out sampling and beating so as to determine the progress of clock switching or determine the starting point of entering the clock stop time.

Schematically, referring to fig. 1, it can be seen that the sampling and beating of the 4-stage D flip-flops are respectively set in the first clock domain circuit and the second clock domain circuit, so as to form clock stop time in the subsequent process of switching clock signals; the 4-stage D flip-flops in the first clock domain circuit are DF11, DF12, DF13 and DF14 in sequence; in the first clock domain circuit, two input ends of the AND gate A1 are respectively connected with a selection signal select and an inverting output end QN of a fourth-stage trigger DF24 of the second clock domain circuit; the output end of the AND gate A1 is connected with the input end of a first-stage D trigger DF11, the normal phase output end Q of the first-stage D trigger DF11 is connected with the input end of a second-stage D trigger DF12, the normal phase output end of the second-stage D trigger DF12 is connected with the input end of a third-stage D trigger DF13, and the normal phase output end of the third-stage D trigger DF13 is connected with the input end of a fourth-stage D trigger DF14 and one input end of the first gating unit.

Referring to fig. 1, the 4-stage D flip-flops in the second clock domain circuit are DF21, DF22, DF23 and DF24 in this order; in the second clock domain circuit, two input ends of the AND gate A2 are respectively connected with a selection signal select and an inverting output end QN of a fourth-stage trigger DF14 of the first clock domain circuit; the output end of the AND gate A1 is connected with the input end of a first-stage D trigger DF21 through an inverter N1, the positive phase output end Q of the first-stage D trigger DF21 is connected with the input end of a second-stage D trigger DF22, the positive phase output end Q of the second-stage D trigger DF22 is connected with the input end of a third-stage D trigger DF23, and the positive phase output end Q of the third-stage D trigger DF23 is connected with the input end of a fourth-stage D trigger DF24 and one input end of a second gate control unit.

The non-inverting output end of the penultimate D trigger in the first clock domain circuit is connected with one input end of the first gating unit; the clock end of each D trigger (corresponding to each stage of D trigger) in the first clock domain circuit and the other input end of the first gating unit are used for inputting a first clock signal, so that the clock domain adopted by the first clock domain circuit is derived from a first clock source, and the first clock source generates the first clock signal; as shown in fig. 1, the first clock signal CLK1 is connected to the clock terminals of the D flip-flops DF11, DF12, DF13 and DF14 and the other input of the first gate unit, respectively.

Therefore, in this embodiment, the signal output by the positive output end of the last-second stage D flip-flop in the first clock domain circuit is used as the gate enable signal of the first gate unit, so that the first gate unit is used to latch the first clock signal according to the gate enable signal, and when the gate enable signal generates a corresponding level flip or is set to a specific logic level value, the first gate unit outputs the first clock signal as the selected clock signal, that is, the supporting clock switching circuit is currently switched from the second clock signal to the first clock signal for outputting.

The non-inverting output end of the penultimate D trigger in the second clock domain circuit is connected with one input end of the second gate control unit; the clock end of each D trigger (corresponding to each level of D trigger) in the second clock domain circuit and the other input end of the second gating unit are both used for inputting a second clock signal, so that the clock domain adopted by the second clock domain circuit is derived from a second clock source, and the second clock source generates the second clock signal; referring to fig. 1, the second clock signal CLK2 is connected to the clock terminals of the D flip-flops DF21, DF22, DF23 and DF24 and the other input of the second gating cell, respectively.

Therefore, in this embodiment, the signal output by the positive output end of the second last stage D flip-flop in the second clock domain circuit is used as the gate enable signal of the second gate unit, and then the second gate unit is used to latch the second clock signal according to the gate enable signal, and when the gate enable signal generates a corresponding level flip or is set to a specific logic level value, the second gate unit outputs the second clock signal as the selected clock signal, that is, supports that the clock switching circuit is currently switched from the first clock signal to the second clock signal.

As can be seen from fig. 1, the output end of the first gate unit and the output end of the second gate unit are respectively connected to two input ends of the first OR gate, the output end of the first OR gate is a port for outputting a target switching clock signal in the clock switching circuit, and referring to fig. 1, the output end of the first gate unit and the output end of the second gate unit are respectively connected to two inputs OR gate 1, wherein the first gate unit outputs a clock signal clk1_gate to represent the first clock signal CLK1, the second gate unit outputs a clock signal clk2_gate to represent the second clock signal CLK2, the two inputs OR gate OR1 outputs the selected target switching clock signal out_clk, and the target switching clock signal out_clk is the second clock signal CLK2 OR the first clock signal CLK1 selected based on the selection signal select.

The output end of the first or gate does not output any clock signal in a period of time in a clock switching process, but keeps a logic level 0, and the first clock signal input to the first gating unit or the second clock signal input to the second gating unit is latched in the period of time, so that the period of time is recorded as clock stop time, and the clock switching process is a process of switching the clock signal regarded as the occurrence level of the selection signal to the current working clock signal into the target switching clock signal, for example, when the current working clock signal is the first clock signal, the target switching clock signal is the second clock signal; when the currently operating clock signal is the second clock signal, the target switching clock signal is the first clock signal.

In the specific clock switching process, based on a selection signal, when the output end of the first gating unit keeps outputting logic level 0 and the output end of the second gating unit outputs a second clock signal, the output end of the first OR gate outputs the second clock signal, namely the second clock signal is currently used as the target switching clock signal; on the other hand, based on the selection signal, when the output terminal of the second gating unit keeps outputting the logic level 0 and the output terminal of the first gating unit outputs the first clock signal, the output terminal of the first or gate outputs the first clock signal, that is, the clock switching circuit selects the first clock signal as the target switching clock signal.

The clock switching circuit selects the output control gating unit of the last-second-stage D trigger in each clock domain circuit to output the clock signal to be switched, so that the clock stopping time formed in the switching process is not too short, the current working clock is stably switched to the target switching clock signal as far as possible, the number of the D triggers connected in cascade in each clock domain circuit is preferably 4, the clock stopping time is not too long, the clock stopping time is limited in a reasonable range, and the switching stability of different clock signals is improved.

In addition, the clock switching circuit disclosed in this embodiment does not adopt the design concept of clock rising edge sampling to perform clock seamless switching, but only adopts the mode of clock single edge and gate logic circuit to trigger jump and gate control unit latch processing, when the clock source is switched, the signal output by the first or gate is pulled down to enter clock stop time, after the clock stop time, the target switching clock signal to be switched is output, and in the process of switching into a higher frequency clock signal, burrs of the clock signal are not caused or the time interval between adjacent jump edges is smaller than or equal to the half period of the clock switched at present, so that the influence of frequent jump of the signal edge is avoided, no matter whether the clock source is switched at a high frequency or a low frequency, the switched clock is ensured to be free from burrs, and the clock switching circuit is safe and reliable.

The above-described embodiments represent only one exemplary implementation of a clock switching circuit, and the description thereof is not to be construed as limiting the scope of the application. It should be noted that several equivalent modifications or improvements made by those skilled in the art without departing from the spirit of the present application fall within the scope of the present disclosure. For example, the signal output by the positive output end of the last stage D flip-flop in the first clock domain circuit and the signal output by the positive output end of the last stage D flip-flop in the second clock domain circuit are both used as gating enabling signals, and in some embodiments, the signal output by the positive output end of the last stage D flip-flop in the clock domain circuit may also be used as a gating enabling signal, which is different in that the time of clock stopping is affected; of course, this clock stop time may also be lengthened or shortened by increasing or decreasing the number of subsequent register stages.

Based on the above embodiments, the present application makes the following modifications in order to detect the case where the clock signal is completely switched:

the clock switching circuit further comprises a first D trigger cascade circuit, a second D trigger cascade circuit, a first switching detection logic circuit, a second switching detection logic circuit and a second OR gate; the output end of the first clock domain circuit and the output end of the first D trigger cascade circuit are respectively connected with the input end of the first switching detection logic circuit; the output end of the first switching detection logic circuit is used for indicating the target switching clock signal to be switched from the second clock signal to the first clock signal; the output end of the second clock domain circuit and the output end of the second D trigger cascade circuit are respectively connected with the input end of the second switching detection logic circuit; the output end of the second switching detection logic circuit is used for indicating the switching of the target switching clock signal from the first clock signal to the second clock signal; the output end of the first switching detection logic circuit and the output end of the second switching detection logic circuit are respectively connected with two input ends of the second OR gate, and the output end of the second OR gate is used for indicating that the clock signal switching is completed.

Referring to fig. 1, the output of the first D flip-flop cascade circuit is connected to the input of the first switch detection logic circuit, the input of the first switch detection logic circuit is connected to the output of the first clock domain circuit to receive the gate enable signal output by the first clock domain circuit and the output of the last stage D flip-flop, the output of the second D flip-flop cascade circuit is connected to the input of the second switch detection logic circuit, the input of the second switch detection logic circuit is connected to the output of the second clock domain circuit to receive the gate enable signal output by the second clock domain circuit and the output of the last stage D flip-flop, and the output of the first switch detection logic circuit and the output of the second switch detection logic circuit are respectively connected to two input ends of the second or gate.

The first switching detection logic circuit and the second switching detection logic circuit comprise a D trigger and a multi-input combination logic circuit; the clock end of each D trigger in the first clock domain circuit, the clock end of the D trigger in the first switching detection logic circuit and the other input end of the first gating unit are all used for inputting a first clock signal, so that the D trigger in the first switching detection logic circuit, the first clock domain circuit and the first gating unit are all in the same clock domain; the non-inverting output end of the penultimate D trigger in the second clock domain circuit is connected with one input end of the second gate control unit; the clock end of each D trigger in the second clock domain circuit, the clock end of the D trigger in the second switching detection logic circuit and the other input end of the second gating unit are all used for inputting a second clock signal, so that the D trigger in the second switching detection logic circuit, the second clock domain circuit and the second gating unit are all in the same clock domain. The input end of the first stage D trigger in the first D trigger cascade circuit is used for inputting a selection signal, and the input end of the first stage D trigger in the second D trigger cascade circuit is used for inputting an inversion signal of the selection signal so as to determine whether to switch from the first clock signal to the second clock signal to output and be detected or switch from the second clock signal to the first clock signal to output and be detected.

Optionally, the frequency of the first clock signal is different from the frequency of the second clock signal, e.g. the frequency of the first clock signal is higher than the frequency of the second clock signal; in the actual clock switching or clock selection application, when the selection signal is turned to logic level 1, the current working clock signal is switched from the second clock signal to the first clock signal; when the selection signal is inverted to logic level 0, the current working clock signal required to be output/selected is switched from the first clock signal to the second clock signal.

The first D trigger cascade circuit and the second D trigger cascade circuit comprise at least three D triggers which are connected in cascade; preferably, when the first clock domain circuit and the second clock domain circuit each comprise four cascaded D flip-flops, the first D flip-flop cascade circuit and the second D flip-flop cascade circuit each comprise three cascaded D flip-flops; as shown in fig. 1, the 3-stage D flip-flops in the first D flip-flop cascade circuit are DF31, DF32, and DF33 in this order; in the first D flip-flop cascade circuit, an input end of the first stage flip-flop DF31 is connected with a select signal select, a positive phase output end Q of the first stage flip-flop DF31 is connected with an input end of the second stage flip-flop DF32, a positive phase output end Q of the second stage flip-flop DF32 is connected with an input end of the third stage D flip-flop DF33, and the positive phase output end Q of the third stage D flip-flop DF33 and an inverted phase output end QN of the second stage D flip-flop DF32 are selected as outputs of the first D flip-flop cascade circuit. The 3-stage D flip-flops in the second D flip-flop cascade circuit are DF41, DF42 and DF43 in sequence; in the second D flip-flop cascade circuit, the inverting signal of the selection signal select is received by the inverter N2 at the input terminal of the second stage flip-flop DF41, and the inverting signal of the selection signal select is input to the second stage flip-flop DF 41. In the second D flip-flop cascade circuit, the normal phase output terminal Q of the first stage flip-flop DF41 is connected to the input terminal of the second stage flip-flop DF42, the normal phase output terminal Q of the second stage flip-flop DF42 is connected to the input terminal of the third stage D flip-flop DF43, and the normal phase output terminal Q of the third stage D flip-flop DF43 and the reverse phase output terminal QN of the second stage D flip-flop DF42 are selected as the outputs of the second D flip-flop cascade circuit.

The positive output end of the last second stage D trigger in the first clock domain circuit, the positive output end of the last first stage D trigger in the first D trigger cascade circuit and the negative output end of the second stage D trigger in the first D trigger cascade circuit are respectively connected with the input end of the multi-input combination logic circuit in the first switching detection logic circuit, so that the signal output by the positive output end of the last second stage D trigger in the first clock domain circuit and the signal output by the positive output end of the last first stage D trigger in the first clock domain circuit can be respectively regarded as two gating enabling signals sent to the first D trigger cascade circuit by the first clock domain circuit, and the two gating enabling signals input to the first D trigger cascade circuit by the external clock domain can be expanded. If necessary, in order to connect out the latch loop, the positive phase output end of the D flip-flop in the first switch detection logic circuit is connected to the input end of the multi-input combinational logic circuit in the first switch detection logic circuit, the output end of the multi-input combinational logic circuit in the first switch detection logic circuit is connected to the input end of the D flip-flop in the first switch detection logic circuit, optionally, a plurality of two-input and gate circuits can be arranged in the multi-input combinational logic circuit to be respectively connected to the corresponding output ends, and if necessary, in order to detect the input and output of the logic level 1, an inverter or a nand gate can be introduced to form a safe combinational logic circuit without competition caused by the change of the input. The positive output end of the D flip-flop in the first switch detection logic circuit is an output end of the first switch detection logic circuit for indicating that the target switch clock signal is switched from the second clock signal to the first clock signal, as shown in fig. 1, the positive output end Q of the D flip-flop DF34 in the first switch detection logic circuit is used for outputting the signal sel1_sig_clk1, which belongs to an indication signal that the target switch clock signal is switched from the second clock signal to the first clock signal, but it is not yet determined whether the switch is safely completed, and it still needs to be performed OR operation with the output of the D flip-flop DF44 in the second switch detection logic circuit through the second OR gate 2, and when the logic level 1 is obtained by flipping, it can be determined that the target switch clock signal has been completely switched from the second clock signal to the first clock signal, and at the same time, there is no switching phenomenon that the target switch clock signal is switched from the first clock signal to the second clock signal.

It should be noted that, the positive phase output end of the penultimate stage D flip-flop in the first clock domain circuit and the positive phase output end of the penultimate stage D flip-flop in the first clock domain circuit both belong to the output end of the first clock domain circuit, and the positive phase output end of the penultimate stage D flip-flop in the first D flip-flop cascade circuit and the negative phase output end of the penultimate stage D flip-flop in the first D flip-flop cascade circuit both belong to the output end of the first D flip-flop cascade circuit; the input end of the multi-input combination logic circuit in the first switching detection logic circuit belongs to the input end of the first switching detection logic circuit; the output terminal in the first switching detection logic circuit belongs to the non-inverting output terminal of the D flip-flop in the first switching detection logic circuit.

The positive output end of the penultimate D trigger in the second clock domain circuit, the positive output end of the penultimate D trigger in the second D trigger cascade circuit and the negative output end of the penultimate D trigger in the second D trigger cascade circuit are respectively connected with the input end of the multi-input combination logic circuit in the second switching detection logic circuit, so that the signal output by the positive output end of the penultimate D trigger in the second clock domain circuit and the signal output by the positive output end of the penultimate D trigger in the second clock domain circuit can be respectively regarded as two gating enabling signals sent to the second D trigger cascade circuit by the second clock domain circuit, and the two gating enabling signals of the second D trigger cascade circuit can be expanded for the external clock domain to be input. If necessary, in order to connect out the latch loop, the positive phase output end of the D flip-flop in the second switch detection logic circuit is connected to the input end of the multi-input combinational logic circuit in the second switch detection logic circuit, the output end of the multi-input combinational logic circuit in the second switch detection logic circuit is connected to the input end of the D flip-flop in the second switch detection logic circuit, optionally, a plurality of two-input and gate circuits can be arranged in the multi-input combinational logic circuit in the second switch detection logic circuit to respectively access to the corresponding output ends, and if necessary, in order to detect the input and output of the logic level 1, an inverter or a nand gate can be introduced to form a safe combinational logic circuit without competition caused by the change of the input. The positive output end of the D flip-flop in the second switch detection logic circuit is an output end of the second switch detection logic circuit for indicating that the target switch clock signal is switched from the first clock signal to the second clock signal, as shown in fig. 1, the positive output end Q of the D flip-flop DF44 in the second switch detection logic circuit is used for outputting the signal sel2_sig_clk2, which belongs to an indication signal that the target switch clock signal is switched from the first clock signal to the second clock signal, but whether the switch is safely completed is not finally determined, and the target switch clock signal can be completely switched from the first clock signal to the second clock signal only when the output of the D flip-flop DF34 in the first switch detection logic circuit is turned over to obtain the logic level 1 through the second OR gate 2.

It should be noted that, the positive phase output end of the penultimate stage D flip-flop in the second clock domain circuit and the positive phase output end of the penultimate stage D flip-flop in the second clock domain circuit both belong to the output end of the second clock domain circuit, and the positive phase output end of the penultimate stage D flip-flop in the second D flip-flop cascade circuit and the negative phase output end of the penultimate stage D flip-flop in the second D flip-flop cascade circuit both belong to the output end of the second D flip-flop cascade circuit; the input end of the multi-input combination logic circuit in the second switching detection logic circuit belongs to the input end of the second switching detection logic circuit; the output end in the second switching detection logic circuit belongs to the non-inverting output end of the D flip-flop in the second switching detection logic circuit.

In the first clock domain circuit, a signal output by a positive output end of a second last stage D flip-flop in the first clock domain circuit can be regarded as a gate enabling signal of the first gate unit, then a jump condition (can be understood as a level inversion condition) between signals output by the positive output end of the second last stage D flip-flop and the positive output end of the second last stage D flip-flop can be combined, an end point of clock stop time (time when an output end of the first or gate outputs a low level, namely, a time period when the output end of the first or gate does not output the first or second clock signal) existing in a switching process is detected under the condition that the selection signal selects the second clock signal, and a start point of clock stop time existing in the switching process is detected under the condition that the selection signal selects the second clock signal; similarly, for the second clock domain circuit receiving the inverted selection signal from the first clock domain circuit, the signal output by the positive output end of the second-last stage D flip-flop in the second clock domain circuit may be regarded as the gate enable signal of the second gate unit, and then the clock stop time (the time when the output end of the first or gate outputs the low level, i.e. the time period when the output end of the first or gate does not output the first or second clock signal) existing in the switching process may be detected under the condition that the selection signal selects the first clock signal by combining with the jump condition (which may be understood as the level inversion condition) between the signals output by the positive output end of the first-last stage D flip-flop; and then output by the second OR gate.

The positive phase output end of the D trigger in the first switching detection logic circuit and the positive phase output end of the D trigger in the second switching detection logic circuit are respectively connected with two input ends of a second OR gate, and the output end of the second OR gate is a port used for indicating that clock signal switching is completed in the clock switching circuit. As shown in fig. 1, the non-inverting output terminal of the D flip-flop DF34 in the first switching detection logic circuit outputs sel1_sig_clk1, the non-inverting output terminal of the D flip-flop DF44 in the second switching detection logic circuit outputs sel2_sig_clk2, or the signals sel1_sig_clk1 and sel2_sig_clk2 are or-ed, the output signal selsig can indicate that the target switching clock signal is flipped from logic level 0 to logic level 1 and from logic level 1 to logic level 0 at the select signal select, indicating whether the clock switching process is completed, thereby determining when the target switching clock signal can be used based on the signal selsig, and determining when the original operating clock can be turned off based on the signal selsig for low power consumption consideration.

On the basis that the first clock domain circuit is provided with at least four cascaded D flip-flops and the second clock domain circuit is provided with at least four cascaded D flip-flops, the first cascaded D flip-flops designed in the embodiment are correspondingly provided with three cascaded D flip-flops and are both connected to the multi-input combination logic circuit in the first switching detection logic circuit, and the second cascaded D flip-flops are correspondingly provided with at least three cascaded D flip-flops and are both connected to the multi-input combination logic circuit in the second switching detection logic circuit; preferably, the sum of the number of cascade connected D flip-flops and the value 1 set by the first D flip-flop cascade circuit is equal to the number of cascade connected D flip-flops set by the first clock domain circuit, and the sum of the number of cascade connected D flip-flops and the value 1 set by the second D flip-flop cascade circuit is equal to the number of cascade connected D flip-flops set by the second clock domain circuit, so that the need of clock synchronization between the first clock domain circuit and the first switch detection logic circuit is considered in one clock domain and the need of clock synchronization between the second clock domain circuit and the second switch detection logic circuit is considered in the other clock domain.

The positive phase output end of the penultimate D flip-flop in the first clock domain circuit and the negative phase output end of the penultimate D flip-flop in the first D flip-flop cascade circuit can synchronously output, and the positive phase output end of the penultimate D flip-flop in the first clock domain circuit and the positive phase output end of the penultimate D flip-flop in the first D flip-flop cascade circuit can synchronously output. Based on this, the clock switching situation can be detected by a multi-input combinational logic circuit in the first switching detection logic circuit within a sufficiently long and controllable clock stop time; moreover, the clock switching circuit can use the output signal of the positive output end of the last-last stage D flip-flop in the first clock domain circuit as the enable signal of the first gating unit to output the latched first clock signal, the output signal of the positive output end of the last-last stage D flip-flop of the second clock domain circuit (driven to work by the current working clock) is a key signal for pushing the second clock domain circuit (not driven to work by the current working clock) to sample and beat, and the second D flip-flop cascade circuit can determine the start point of entering the clock stop time during the process of switching the second clock signal into the first clock signal or before the second clock signal is switched into the first clock signal.

Similarly, the positive phase output end of the penultimate D flip-flop in the second clock domain circuit and the negative phase output end of the penultimate D flip-flop in the second D flip-flop cascade circuit can synchronously output, and the positive phase output end of the penultimate D flip-flop in the second clock domain circuit and the positive phase output end of the penultimate D flip-flop in the second D flip-flop cascade circuit can synchronously output; based on this, the clock switching condition is detected by the multiple-input combinational logic circuit in the second switching detection logic circuit within a sufficiently long and controllable clock stop time; and, the clock switching circuit uses the output signal of the positive output end of the last-last stage D flip-flop in the second clock domain circuit as the enabling signal of the second gating unit to output the latched second clock signal, the output signal of the positive output end of the last-last stage D flip-flop of the first clock domain circuit (driven by the current working clock) is a key signal for pushing the second clock domain circuit (not driven by the current working clock) to perform sampling and beating, and the first D flip-flop cascade circuit can determine the starting point of entering the clock stop time when the first clock signal is switched into the second clock signal.

Further, after the first D trigger cascade circuit determines the start point of the clock stop time when the first clock signal is switched to the second clock signal, the second switching detection logic circuit determines the end point of the clock stop time; the second D flip-flop cascade circuit may determine an end point of the clock stop time through the first switching detection logic circuit after determining a start point of the clock stop time before the second clock signal is switched to the first clock signal or before the second clock signal is switched to the first clock signal.

Therefore, the multi-input combination logic circuit in the first switching detection logic circuit can stably judge the whole sampling condition of the D trigger of the first clock domain circuit by combining the output of the two-stage D trigger of the first D trigger cascade circuit while receiving the output signal of the positive output end of the first-last-stage D trigger and the output signal of the positive output end of the second-last-stage D trigger in the first clock domain circuit, and then beat and transmit the judgment information of the first switching detection logic circuit to one input end of the second OR gate through the D trigger in the first switching detection logic circuit; the multi-input combination logic circuit in the second switching detection logic circuit can stably judge the whole sampling condition of the D trigger of the second clock domain circuit by combining the output of the two-stage inverse D trigger of the cascade circuit of the first D trigger while receiving the output signal of the positive output end of the first-stage inverse D trigger of the second clock domain circuit, and then beat and transmit the judgment information of the second switching detection logic circuit to the other input end of the second OR gate through the D trigger in the second switching detection logic circuit; reducing the risk of contention and preventing the detection result of complete switching of the first clock signal or the second clock signal from being made in advance before the end of the clock stop time is reached; the problem that the clock switching detection is affected due to unstable signal establishment time of the logic device is solved, so that the accuracy and stability of triggering detection in the clock switching process are improved, and the clock signal is ensured to be used after switching is completed.

In summary, according to the application, the first D flip-flop cascade circuit, the second D flip-flop cascade circuit, the first switch detection logic circuit, the second switch detection logic circuit, and the second or gate are the first clock domain circuit and the second clock domain circuit to add the switch detection logic, so that the clock signal of the switch output can be used after the switch is completed when the first clock signal is completely switched to the second clock signal output or the second clock signal is completely switched to the first clock signal output, and the clock switch completion indication signal is provided; whether the clock signal with relatively high frequency is switched to the clock signal with relatively low frequency or the clock signal with relatively low frequency is switched to the clock signal with relatively high frequency, the phenomenon of clock system hanging up caused by early clock switching off in the switching process is solved.

As an embodiment, the first switch detection logic circuit or the second switch detection logic circuit is internal, the multiple-input combinational logic circuit includes a first preset two-input and gate, a second preset two-input and gate, a two-input nand gate, and a two-input or gate, the positive output end of the D flip-flop is connected to one input end of the two-input or gate, the other input end of the two-input or gate is connected to the output end of the first preset two-input and gate, the output end of the two-input or gate and the output end of the two-input nand gate are respectively connected to the two input ends of the second preset two-input and gate, and the output end of the second preset two-input and gate is connected to the input end of the D flip-flop to form a latch loop; the first preset two-input AND gate and the second preset two-input AND gate are both gate logic circuits for executing and operating, and one input end of the first preset two-input AND gate allows the external inverter to do the inverting operation and then do the inverting operation.

In the first switch detection logic circuit or the second switch detection logic circuit, when the input end of the first preset two-input and gate, the input end of the second preset two-input and gate, the input end of the two-input nand gate and the input end of the two-input or gate form each input end of the multi-input combination logic circuit, the detection results of each input signal are output through each and gate, the or gate, the inverter and the combination logic thereof in sequence, and are latched through the D flip-flop, for example, the flip-flop condition between the signals output by the positive phase output ends of the two-stage D flip-flops in one clock domain circuit is detected through the signal condition of each input end of the multi-input combination logic circuit at the same time, then the flip-flop condition is latched, and the result that the clock signal is switched is reliably indicated through the second or output through the second or gate disclosed in the previous embodiment, so that the influence of too short time interval or burrs between adjacent jump edges is reduced.

Therefore, after the input end of the multi-input combinational logic circuit in the first switching detection logic circuit is determined by the selection signal select, after sampling in at least three clock cycles, each input end of the first preset two-input AND gate only changes in 1 input at the same time, each input end of the two-input NAND gate only changes in 1 input at the same time, and the two-input NAND gate is latched by the D flip-flop and then output in one clock cycle, so that the occurrence of competition is reduced, and the detection reliability is improved.

Specifically, in the above embodiment, two input ends of the two-input nand gate in the first switch detection logic circuit are respectively connected to a non-inverting output end of a penultimate stage D flip-flop in the first D flip-flop cascade circuit and an inverting output end of a penultimate stage D flip-flop in the first D flip-flop cascade circuit; as shown in fig. 1, two input ends of the two-input nand gate a33 are respectively connected to the non-inverting output end Q of the D flip-flop DF33 and the inverting output end QN of the D flip-flop DF 32. The two-input nand gate a33 is configured to nand the signal q2_clk1 output from the non-inverting output terminal of the D flip-flop DF33 and the signal q1_clk1 output from the inverting output terminal of the D flip-flop DF32, and output a nand result to the second preset two-input and gate a32. The two-input nand gate a33 can detect the level inversion of the signal q2_clk1 with respect to the signal q1_clk1, and provide a structural basis for sampling synchronously with the first clock domain circuit and a synchronous change signal basis for detecting clock switching.

The first preset two-input AND gate is provided with a forward input end and a reverse input end, the forward input end of the first preset two-input AND gate in the first switching detection logic circuit is connected with the positive output end of the penultimate D trigger in the first clock domain circuit, and the reverse input end of the first preset two-input AND gate in the first switching detection logic circuit is connected with the positive output end of the penultimate D trigger in the first clock domain circuit so as to enable signals to be input reversely; in fig. 1, the upper input end of the first preset two-input and gate a31 is a forward input end for directly inputting the signal sel [2], and the lower input end of the first preset two-input and gate a31 is a reverse input end for reversely inputting the input signal sel [3], so that the first preset two-input and gate a31 is equivalent to a combined logic circuit of an inverter and an and gate; Wherein, the signal sel [2] represents the signal output by the non-inverting output end of the last-second stage D flip-flop in the first clock domain circuit under the condition that the first clock domain circuit only comprises four D flip-flops which are connected in cascade; the signal sel [3] represents a signal output from the non-inverting output terminal of the D flip-flop of the penultimate stage in the first clock domain circuit in the case where the first clock domain circuit includes only four D flip-flops connected in cascade. The first preset two-input AND gate A31 is used for performing AND operation on the inverted signals of the signal sel [2] and the signal sel [3], and can detect the level inversion condition of the signal sel [2] relative to the signal sel [3], and introduces a signal source and a switched change condition of the signal source to be synchronized for the first D trigger cascade circuit and the first switching detection logic circuit; The result of the AND operation is output to the two-input OR gate OR3, and the AND operation can be performed OR operated with the real-time output signal of the D trigger DF34, when the signal fed back to the two-input OR gate OR3 in real time by the D trigger DF34 is the logic level 1, the output of the first preset two-input AND gate A31 does not influence the output of the two-input OR gate OR3, namely the level inversion condition of the signal sel [2] relative to the signal sel [3] does not influence the output of the two-input OR gate OR 3; when the signal fed back to the two-input OR gate OR3 in real time by the D flip-flop DF34 is logic level 0, the output of the first preset two-input and gate a31 affects the output of the two-input OR gate OR3, that is, the level inversion condition of the signal sel [2] relative to the signal sel [3] can affect the output of the two-input OR gate OR3, so as to transmit the level inversion condition through the two-input OR gate OR3, thereby affecting the switching detection result; the two-input OR gate OR3 outputs the result of OR operation to the second preset two-input AND gate A32; then, the second preset two-input AND gate A32 performs AND operation according to the NAND result output by the two-input NAND gate A33 and the OR operation result output by the two-input OR gate OR3, obtains a preliminary detection result for switching the first clock signal, and then outputs the preliminary detection result in a latched mode by the D trigger DF34, so that synchronous sampling and synchronous detection signal change of the D trigger output of the first clock domain circuit and the D trigger in the first D trigger cascade circuit are completed, the conditions of burrs and the like generated by jump edges are reduced, and the starting point OR the ending point of the clock stop time is further determined; Then, the D flip-flop DF34 latches the output and the second OR gate OR2 to make a final judgment, and an indication signal indicating that the switching of the clock signal is completed is obtained.

Two input ends of a two-input NAND gate in the second switching detection logic circuit are respectively connected with a non-inverting output end of a first-last-stage D trigger in the second D trigger cascade circuit and an inverting output end of a second-stage D trigger in the second D trigger cascade circuit; as shown in fig. 1, two input ends of the two-input nand gate a43 are respectively connected to the non-inverting output end Q of the D flip-flop DF43 and the inverting output end QN of the D flip-flop DF 42. The two-input nand gate a43 is configured to nand the signal q2_clk2 output from the non-inverting output terminal of the D flip-flop DF43 and the signal q1_clk2 output from the inverting output terminal of the D flip-flop DF42, and output a nand result to the second preset two-input and gate a42. The two-input nand gate a43 can detect the level inversion of the signal q2_clk2 with respect to the signal q1_clk2, and provide a structural basis for sampling synchronously with the second clock domain circuit and a synchronous change signal basis for detecting clock switching.

The second preset two-input AND gate is provided with a forward input end and a reverse input end, the forward input end of the second preset two-input AND gate in the second switching detection logic circuit is connected with the forward output end of the penultimate D trigger in the second clock domain circuit, the reverse input end of the second preset two-input AND gate in the second switching detection logic circuit is connected with the forward output end of the penultimate D trigger in the second clock domain circuit so as to enable signals to be reversely input, the upper input end of the second preset two-input AND gate A41 is a forward input end for directly inputting a signal se2, the lower input end of the second preset two-input AND gate A41 is a reverse input end for reversely inputting the input signal se 23, the second preset two-input and gate a41 is equivalent to a combinational logic circuit of an inverter and an and gate; Wherein, the signal se2[2] represents the signal output by the non-inverting output end of the last-second stage D flip-flop in the second clock domain circuit under the condition that the second clock domain circuit only comprises four D flip-flops which are connected in cascade; the signal se2[3] represents a signal output from the non-inverting output terminal of the D flip-flop of the penultimate stage in the second clock domain circuit in the case where the second clock domain circuit includes only four D flip-flops connected in cascade. In the second switch detection logic circuit, the first preset two-input and gate A41 is used for performing AND operation on the signal se2[2] and the inverted signal se2[3], so that the level inversion condition of the signal se2[2] relative to the signal se2[3] can be detected, and a signal source and a switch change condition thereof which need to be synchronized are introduced for the second D trigger cascade circuit and the second switch detection logic circuit; The result of the AND operation is output to the two-input OR gate OR4, and the AND operation can be performed OR operated with the real-time output signal of the D trigger DF44, when the signal fed back to the two-input OR gate OR4 in real time by the D trigger DF44 is the logic level 1, the output of the first preset two-input AND gate A41 does not influence the output of the two-input OR gate OR4, namely the level inversion condition of the signal se2[2] relative to the signal se2[3] does not influence the output of the two-input OR gate OR 4; when the output of the D flip-flop DF44 is fed back in real time to the signal of the two-input OR gate OR4 as the logic level 0, the output of the first preset two-input and gate a41 affects the output of the two-input OR gate OR4, that is, the level inversion condition of the signal se2[2] relative to the signal se2[3] can affect the output of the two-input OR gate OR4, so as to transmit the level inversion condition through the two-input OR gate OR4, thereby affecting the switching detection result; The two-input OR gate OR4 outputs the result of OR operation to the second preset two-input AND gate A42; then, the second preset two-input and gate a42 performs an and operation according to the nand result output by the two-input and gate a43 and the OR operation result output by the two-input OR gate OR4, to obtain a preliminary detection result for the second clock signal switching, and then latches the output by the D flip-flop DF44, so as to complete synchronous sampling and synchronous detection signal change of the D flip-flop output of the second clock domain circuit and the D flip-flop in the second D flip-flop cascade circuit, reduce the burrs generated by the jump edge, and further determine the start point OR the end point of the clock stop time; The D flip-flop DF44 then latches the output and the second OR gate OR2 for final judgment, obtaining an indication signal that the clock signal switching is completed.

In summary, in the stage of level inversion of the selection signal, the first preset two-input and gate detects the jump condition between the output signals of the positive output ends of the last two-stage D flip-flops, so as to determine the time when the clock signal starts to switch and the time when the switching is completely finished.

The chip comprises the clock switching circuit disclosed in any embodiment, forms a clock switching chip architecture integrating switching detection logic, and can complete and detect clock switching, and can ensure that the switched clock has no burrs no matter whether the clock is switched to low frequency or high frequency. Compared with the prior art, the clock switching completion indication signal is added to the chip, so that the clock can be used after switching is completed, and the phenomenon that the clock is not successfully switched or is suspended when the clock source of the chip is switched because the clock is turned off is solved.

The application discloses a switching detection method of a clock switching circuit based on the embodiment, which can be executed by a controller inside and outside the clock switching circuit; the switching detection method comprises the following steps:

And the selection signal is subjected to AND operation with the signal output by the inverted output end of the D flip-flop of the penultimate stage of the second clock domain circuit, wherein the AND operation is carried out by the AND gate A1 in FIG. 1; inputting the result of AND operation into a first stage D trigger of the first clock domain circuit; then, at least three clock cycles are continuously sampled by the first clock signal in the first clock domain circuit, so that the second last stage D trigger of the first clock domain circuit outputs the input signal from the first stage D trigger of the first clock domain circuit, namely, the input signal is beaten by three clock cycles of the first clock signal CLK1 shown in FIG. 1, and the D trigger DF13 outputs the signal output by the AND gate A1 to the first switching detection logic circuit and the first gating unit; then, the clock signal CLK1 shown in fig. 1 is clocked for one clock cycle, and the D flip-flop DF14 outputs the signal output by the and gate A1 and transmits the signal to the and gate A2 in the second clock domain circuit; the fourth stage D flip-flop DF14 outputs the signal output by the and gate A1 and transmits it to the and gate A2 and the first switching detection logic circuit in the second clock domain circuit, respectively.

Inverting the selection signal to obtain an inverted signal of the selection signal and performing an and operation on the inverted signal and a signal output by an inverted output end of a first-to-last stage D flip-flop of the first clock domain circuit, where the and operation is performed by an and gate A2 shown in fig. 1; inputting the result of AND operation into the first stage D trigger of the second clock domain circuit, then continuously sampling at least three clock cycles in the second clock domain circuit by using the second clock signal, so that the penultimate stage D trigger of the second clock domain circuit outputs the input signal from the first stage D trigger of the second clock domain circuit, namely, the input signal is beaten by three clock cycles of the second clock signal CLK2 shown in FIG. 1, and the third stage D trigger DF23 outputs the signal output by the AND gate A2 to the second switching detection logic circuit and the second gate control unit; then, the second clock signal CLK2 shown in fig. 1 is clocked by one clock cycle, that is, the signal output from the and gate A2 is input to the first stage D flip-flop DF21 and clocked by 4 clock cycles, and the signal output from the and gate A1 is output by the fourth stage D flip-flop DF24 and is transmitted to the and gate A1 in the first clock domain circuit and the second switching detection logic circuit, respectively.

The method comprises the steps that a signal output by a positive output end of a next-to-last stage D trigger of a first clock domain circuit and a first clock signal are sent to a first gating unit to be gated, a first gating clock signal is obtained, the first gating unit is used for latching the first clock signal according to the signal output by the positive output end of the next-to-last stage D trigger of the first clock domain circuit, wherein the signal output by the positive output end of the next-to-last stage D trigger of the first clock domain circuit is used as a gating enabling signal of the first gating unit, and when the gating enabling signal of the first gating unit generates corresponding level inversion or is set to be a specific logic level value, the first gating unit outputs the first clock signal as the first gating clock signal, and the clock switching circuit is supported to be switched from a second clock signal to the first clock signal;

The signal output by the positive phase output end of the last second stage D trigger of the second clock domain circuit and the second clock signal are sent to a second gating unit for gating, and a second gating clock signal is obtained; the second gating unit is used for latching a second clock signal according to a signal output by a positive phase output end of a second-last-stage D trigger of the second clock domain circuit, wherein the signal output by the positive phase output end of the second-last-stage D trigger of the second clock domain circuit is used as a gating enabling signal of the second gating unit, and when the gating enabling signal of the second gating unit generates corresponding level inversion or is set to a specific logic level value, the second gating unit outputs the second clock signal as a second gating clock signal to support the clock switching circuit to be switched from the first clock signal to the second clock signal at present;

Then the first gating clock signal and the second gating clock signal are processed or operated to obtain a target switching clock signal, when the selection signal is turned from the logic level 0 to the logic level 1 in the actual clock switching or clock selection application, the current working clock signal required to be output/selected is switched from the second clock signal to the first clock signal, namely the target switching clock signal is the first clock signal; when the selection signal is turned from the logic level 1 to the logic level 0, the current working clock signal required to be output/selected is switched from the first clock signal to the second clock signal, namely, the target switching clock signal is changed into the second clock signal.

The circuit working principle corresponding to the switching detection method is described in stages by combining with fig. 1 as follows:

When the selection signal select is at logic level 1 (corresponding to the first level), the relevant clock source is started to output a first clock signal to the first clock domain circuit, which can be understood as opening the first clock domain; specifically, the select signal select is anded with the output signal from the inverting output of the fourth D flip-flop DF24 of the second clock domain circuit, and then sampled continuously for 4 clock cycles with the first clock signal CLK1 to be transferred among the 4D flip-flops in the first clock domain circuit in turn.

When the selection signal select is at logic level 0 (corresponding to the second level), the relevant clock source is started to output a second clock signal to the second clock domain circuit, which can be understood as turning on the second clock domain; the select signal select is inverted by an inverter and anded with the output signal from the inverted output of the fourth D flip-flop DF14 of the first clock domain circuit, and then sampled continuously for 4 clock cycles with the second clock signal CLK2 for transmission among the 4D flip-flops in the second clock domain circuit in turn.

Then, the signal output by the non-inverting output terminal of the third D flip-flop DF13 of the first clock domain circuit and the first clock signal CLK1 are sent to the first gating unit for gating, so as to obtain a clock signal clk1_gate, namely a latched first clock signal CLK1; and sending the signal output by the non-inverting output end of the third D flip-flop DF23 of the second clock domain circuit and the second clock signal CLK2 to the second gating unit for gating, so as to obtain the clock signal clk2_gate, namely the latched second clock signal CLK2.

Then, the first OR gate OR1 performs OR operation on the clock signal clk1_gate and the clock signal clk2_gate, so as to obtain a target switching clock signal out_clk.

Illustratively, based on the processing manner of the clock signal in each switching stage, there are:

when the selection signal select is logic level 0 (corresponding to the second level), the second clock signal CLK2 is started to be output first, and the second clock domain circuit is driven to work preferentially; then, when the select signal select is inverted from the logic level 0 to the logic level 1, the select signal select becomes the logic level 0 through an inverter (not gate N1), and performs an and operation with the signal output by the third D flip-flop DF13 of the first clock domain circuit, then the second clock signal CLK2 samples for 3 clock cycles, the third D flip-flop DF23 of the second clock domain circuit outputs the logic level 0, and then enters the second gate unit, and at this time, the signal clk2_gate output by the second gate unit is the logic level 0 based on the logic level 0 output by the third D flip-flop DF 23; after passing through the fourth D flip-flop DF24 of the second clock domain circuit, i.e. after passing through one clock cycle of the second clock signal CLK2, the inverting output terminal of the fourth D flip-flop DF24 outputs a logic level 1, which is sent back to the and gate A1 in the first clock domain circuit and is anded with the selection signal select by the and gate A1, then the third D flip-flop DF13 of the first clock domain circuit outputs a logic level 1 after sampling for 3 clock cycles by the first clock signal CLK1, and then enters the first gating unit, at this time, the third D flip-flop DF13 outputs a logic level 1, and the clk1_gate signal output by the first gating unit is the latched first clock signal CLK1, and at this time, clk1_gate and clk2_gate are obtained after being ored by the first OR gate OR1, i.e. the first clock signal CLK1 is currently selected out onto the out_clk signal line. It should be noted that, during the process of switching the signal out_clk from the second clock signal CLK2 to the first clock signal CLK1, the output terminal of the first OR gate OR1 is at a low level for a period of time, i.e. the logic level 0 is maintained, and the period of time during which the logic level 0 is maintained is referred to as a clock stop time, and the first D flip-flop cascade circuit, the second D flip-flop cascade circuit, the first switch detection logic circuit, the second switch detection logic circuit and the second OR gate in the clock switching circuit form a complete switch detection logic, so as to detect the start point and the end point of the clock stop time, and in fact, during the clock stop time, the first gate unit latches the first clock signal CLK1 and the second gate unit latches the second clock signal CLK2, and the clock stop time is also the clock seamless switching period.

The method steps executed simultaneously with the handover detection method disclosed in the foregoing embodiment include that the handover detection method further includes:

The selection signal is sent to the input end of a first stage D trigger of a first D trigger cascade circuit, and at least two clock cycles of output are continuously sampled by a first clock signal in the first D trigger cascade circuit; and sending a signal output by the inverted output end of the last second stage D trigger of the first D trigger cascade circuit and a signal output by the normal phase output end of the last first stage D trigger of the first D trigger cascade circuit to a two-input NAND gate in the first switching detection logic circuit for NAND operation, so as to obtain a first one-to-one detection signal.

Schematically, as can be seen from fig. 1, when the externally provided select signal select is input to the D flip-flop DF31, if the select signal select is at the second level and the reset level of the positive output terminal Q of each stage of the D flip-flop in the first D flip-flop cascade circuit is at the first level, the positive output terminal Q of the first stage of the D flip-flop DF31 in the first D flip-flop cascade circuit outputs the second level when the first clock signal CLK1 is used for sampling the first clock period during the continuous sampling of at least two clock periods; sampling the second clock period by using the first clock signal CLK1, and outputting a first level by the inverting output end QN of the second stage D flip-flop DF32, wherein the non-inverting output end of the third stage D flip-flop DF33 keeps the first level by default, and the reset level of the non-inverting output end Q of each stage D flip-flop in the second stage D flip-flop cascade circuit is equal to the second level; then, the first level output by the inverting output terminal QN of the second stage D flip-flop DF32 and the first level output by the non-inverting output terminal of the third stage D flip-flop DF33 are input into the two-input nand gate a33 to perform a nand operation, so that the two-input nand gate a33 can detect the level inversion condition of the signal q2_clk1 relative to the signal q1_clk1; when the first level represents logic level 1 and the second level represents logic level 0, the output of the two-input nand gate a33 obtains the second level, that is, the first one-to-one detection signal is the second level, which is different from the second level output by the inverting output terminal QN of the second stage D flip-flop DF32 and the first level output by the non-inverting output terminal of the third stage D flip-flop DF33 before sampling the first clock period and sampling, the nand result obtained by the two-input nand gate a33 is input, so that zero clearing of the output terminal sel1_sig_clk1 of the D flip-flop in the first switching detection logic circuit is started, and the start point of the clock stop time can be determined in the process of switching the first clock signal to the second clock signal or before switching the first clock signal to the second clock signal, so as to determine the start point of the clock stop time.

If the selection signal select is a first level and the reset level of the positive phase output terminal of each stage of D flip-flop in the first D flip-flop cascade circuit is a second level, then in the process of continuously sampling at least two clock cycles with the first clock signal CLK1, the positive phase output terminal Q of the first stage of D flip-flop DF31 in the first D flip-flop cascade circuit outputs the first level when sampling the first clock cycle with the first clock signal CLK 1; sampling the second clock period by using the first clock signal CLK1, and outputting a second level by the inverting output end QN of the second stage D flip-flop DF32, wherein the non-inverting output end of the third stage D flip-flop DF33 keeps the second level by default, and the reset level of the non-inverting output end of each stage D flip-flop in the second stage D flip-flop cascade circuit is equal to the first level; then, the second level output by the inverting output terminal QN of the second stage D flip-flop DF32 and the second level output by the non-inverting output terminal of the third stage D flip-flop DF33 are input into the two-input nand gate a33 to perform a nand operation, so that the two-input nand gate a33 can detect the level inversion condition of the signal q2_clk1 relative to the signal q1_clk1; when the first level represents a logic level 1 and the second level represents a logic level 0, the output of the two-input nand gate a33 obtains the first level, that is, the first detection signal is the first level, which is equivalent to the first level output by the inverting output terminal QN of the second stage D flip-flop DF32 and the second level output by the non-inverting output terminal Q of the third stage D flip-flop DF33 before sampling the first clock cycle and sampling, and the nand result obtained by the two-input nand gate a33 is input, the signal output by the non-inverting output terminal of the last stage D flip-flop in the first clock domain circuit and the signal output by the non-inverting output terminal of the last stage D flip-flop in the first clock domain circuit are further judged in the first switching detection logic circuit, so as to determine the signal of the output terminal sel1_sig_clk1 of the D flip-flop in the first switching detection logic circuit. Therefore, a basis for synchronously sampling the first D trigger cascade circuit and the first clock domain circuit and synchronously detecting signal change is provided for detecting clock switching operation, and further, whether the second clock signal is switched to the first clock signal (the target switching clock signal selected under the condition that the current selection signal is set to the first level) is detected later or not is facilitated.

As shown in fig. 1, no matter which clock cycle is used for sampling, the output signal of the non-inverting output terminal of D flip-flop DF31 is denoted by q0_clk1, the output signal of the non-inverting output terminal of D flip-flop DF32 is denoted by q1_clk1, and the output signal of the non-inverting output terminal of D flip-flop DF33 is denoted by q2_clk1. The last-last stage D flip-flop of the first D flip-flop cascade circuit is a D flip-flop DF32, the last-last stage D flip-flop of the first D flip-flop cascade circuit is a D flip-flop DF33, and a signal q2_clk1 output from a non-inverting output terminal Q of the D flip-flop DF33 and a signal output from an inverting output terminal QN of the D flip-flop DF32 (i.e., an inverting signal of the signal q1_clk1) are input to the two-input nand gate a33.

Inverting the selection signal to obtain an inverting signal of the selection signal, sending the inverting signal to the input end of a first stage D trigger of a second D trigger cascade circuit, and continuously sampling at least two clock cycles by using a second clock signal in the second D trigger cascade circuit for outputting; and sending the signal output by the inverting output end of the last second stage D trigger of the second D trigger cascade circuit and the signal output by the non-inverting output end of the last first stage D trigger of the second D trigger cascade circuit to a two-input NAND gate in a second switching detection logic circuit for NAND operation, so as to obtain a second first detection signal.

Schematically, as can be seen from fig. 1, when the externally provided selection signal is inverted to the selection signal select through the inverter N2 and then input to the D flip-flop DF41, if the selection signal select is at the first level and the reset level of the positive phase output terminal of each stage of the D flip-flop DF in the second D flip-flop cascade circuit is at the first level, during the process of continuously sampling at least two clock cycles with the second clock signal CLK2, the positive phase output terminal of the first stage of the D flip-flop DF41 in the second D flip-flop cascade circuit outputs the second level when sampling the first clock cycle with the second clock signal CLK2, and the negative phase output terminal QN of the second stage of the D flip-flop DF42 outputs the first level when sampling the second clock cycle with the second clock signal CLK2, and at this time, the positive phase output terminal of the third stage of the D flip-flop DF43 keeps the first level by default, wherein the reset level of the positive phase output terminal of each stage of the D flip-flop DF in the first D flip-flop cascade circuit is at the second level; then, the first level output by the inverting output terminal QN of the second stage D flip-flop DF42 and the first level output by the non-inverting output terminal of the third stage D flip-flop DF43 are input into the two-input nand gate a43 for performing a nand operation, so that the two-input nand gate a43 can detect the level inversion condition of the signal q2_clk2 relative to the signal q1_clk2; when the first level represents logic level 1 and the second level represents logic level 0, the output of the two-input nand gate a43 obtains the second level, that is, the second first detection signal is the second level, which is different from the second level output by the inverting output terminal QN of the second stage D flip-flop DF42 and the first level output by the non-inverting output terminal of the third stage D flip-flop DF43 before sampling the first clock period and sampling, the nand result obtained by the two-input nand gate a33 is input, so that the start of clearing the output terminal sel2_sig_clk2 of the D flip-flop in the second switching detection logic circuit is realized, and in order to detect whether the second clock signal is switched to the first clock signal (the target switching clock signal selected in the case that the current selection signal is set to the first level) to exclude interference, the start of the clock stop time can be determined in the process of switching the second clock signal to the first clock signal or before switching the second clock signal to the first clock signal, so that the start of the second D flip-flop cascade circuit can determine the start of the clock signal to enter the clock stop time.

If the selection signal select is at the second level and the reset level of the positive phase output end of each stage of D flip-flops in the second D flip-flop cascade circuit is at the second level, the positive phase output end of the first stage of D flip-flop DF41 in the second D flip-flop cascade circuit outputs the first level when the second clock signal CLK2 is used for sampling the first clock period in the process of continuously sampling at least two clock periods with the second clock signal CLK 2; sampling the second clock signal CLK2 to output the second level at the inverting output terminal QN of the second stage D flip-flop DF42 during the second clock period, where the non-inverting output terminal of the third stage D flip-flop DF43 keeps the second level by default, and the reset level of the non-inverting output terminal of each stage D flip-flop in the first D flip-flop cascade circuit is the first level; then, the second level output by the inverting output terminal QN of the second stage D flip-flop DF42 and the second level output by the non-inverting output terminal Q of the third stage D flip-flop DF43 are input into the two-input nand gate a43 for performing a nand operation, and the two-input nand gate a43 can detect the level inversion condition of the signal q2_clk2 relative to the signal q1_clk2; when the first level represents logic level 1 and the second level represents logic level 0, the output of the two-input nand gate a43 obtains the first level, that is, the second first detection signal is the first level, which is equivalent to sampling the first clock period and the first level output by the inverting output terminal QN of the second stage D flip-flop DF42 before sampling, and the second level output by the non-inverting output terminal of the third stage D flip-flop DF43 inputs the nand result obtained by the two-input nand gate a43, and then the signal output by the non-inverting output terminal of the last stage D flip-flop in the second clock domain circuit and the signal output by the non-inverting output terminal of the last stage D flip-flop in the first clock domain circuit are further judged in the second switching detection logic circuit, so as to determine the signal sel2_sig_ clk2 of the output terminal of the D flip-flop in the second switching detection logic circuit. Therefore, a basis for synchronously sampling the second D trigger cascade circuit and the second clock domain circuit and synchronously detecting signal change is provided for detecting clock switching operation, and further, whether the first clock signal is switched to the second clock signal (the target switching clock signal selected under the condition that the current selection signal is set to the second level) is detected later or not is facilitated.

As shown in fig. 1, no matter which clock cycle is used for sampling, the output signal at the non-inverting output of D flip-flop DF41 is denoted by q0_clk2, the output signal at the non-inverting output of D flip-flop DF42 is denoted by q1_clk2, and the output signal at the non-inverting output of D flip-flop DF43 is denoted by q2_clk2. The last-last stage D flip-flop of the second D flip-flop cascade circuit is a D flip-flop DF42, the last-last stage D flip-flop of the second D flip-flop cascade circuit is a D flip-flop DF43, and a signal q2_clk2 output from a non-inverting output terminal of the D flip-flop DF43 and a signal output from an inverting output terminal QN of the D flip-flop DF42 (i.e., an inverting signal of the signal q1_clk2) are input to the two-input nand gate a43.

In the first clock domain circuit, at least three clock cycles are continuously sampled by using a first clock signal, and the inverse signal of the signal output by the positive output end of the reciprocal first stage D trigger of the first clock domain circuit and the signal output by the positive output end of the reciprocal second stage D trigger of the first clock domain circuit are sent to a first preset two-input AND gate in the first switching detection logic circuit to perform AND operation, so as to obtain a first two-detection signal, wherein the inverse signal of the signal output by the positive output end of the reciprocal first stage D trigger of the first clock domain circuit is the inverse input end set by the input second preset two-input AND gate, and can be understood as that the signal output by the positive output end of the reciprocal first stage D trigger of the first clock domain circuit performs inverse operation before being input into the second preset two-input AND gate, or the signal output by the positive output end of the reciprocal first stage D trigger of the first clock domain circuit is input into the second preset two-input AND gate to perform inverse operation. As shown in fig. 1, a signal output by a positive output end of a first-last stage D flip-flop of the first clock domain circuit is denoted by sel [3], a signal output by a positive output end of a second-last stage D flip-flop of the first clock domain circuit is denoted by sel [2], a first preset two-input and gate a31 is used for performing an and operation on the signal sel [2] and the inverted signal sel [3], a level inversion condition of the signal sel [3] relative to the signal sel [2] can be detected, if the first two-detection signal is a logic level 0, the signal sel [3] does not have level inversion relative to the signal sel [2], and otherwise, the level inversion occurs; and then introducing a signal source needing to be synchronized and a switched change condition of the signal source for the first D trigger cascade circuit and the first switching detection logic circuit.

The first two detection signals and the signal output by the non-inverting output end of the D trigger in the first switching detection logic circuit are sent to two input OR gates in the first switching detection logic circuit to perform OR operation, so that a first three detection signal is obtained; then, the first one-to-one detection signal and the first third detection signal are sent to a second preset two-input AND gate in the first switching detection logic circuit to perform AND operation, so that a first fourth detection signal is obtained; the first four detection signals are sent to the input end of a D trigger in the first switching detection logic circuit, and the first clock signals are used for sampling one clock period to latch the first four detection signals; as can be seen from fig. 1, the first two-detection signal (the result of the and operation of the first preset two-input and gate a 31) and the signal output from the positive output end of the D flip-flop DF34 are given to the two-input OR gate OR3, so that the first two-detection signal can be used OR operated with the real-time output signal of the D flip-flop DF34, and when the signal output from the D flip-flop DF34 is fed back to the two-input OR gate OR3 in real time to be the logic level 1, the output of the first preset two-input and gate a31 (the first two-detection signal) does not affect the output of the two-input OR gate OR3, i.e. the level inversion condition of the signal sel [3] relative to the signal sel [2] does not change the first third detection signal; When the output of the D flip-flop DF34 is fed back to the two-input OR gate OR3 in real time and the signal is at logic level 0, the output of the first preset two-input and gate a31 affects the output of the two-input OR gate OR3, that is, sel [3] can change the first three detection signals relative to the level inversion condition of the signal sel [2], so as to transmit the level inversion condition through the two-input OR gate OR3, and further can be used for detecting the switching change result; then, the two-input OR gate OR3 outputs the first detection signal to the second preset two-input and gate a32; then, the second preset two-input and gate a32 performs an and operation according to the first one-to-one detection signal output by the two-input nand gate a33 and the first three detection signal output by the two-input OR gate OR3, to obtain a preliminary detection result of the first clock signal switching, and then outputs the preliminary detection result in a latch manner to the D flip-flop DF34, and after the output of the D flip-flop DF34 is turned from the logic level 0 to the logic level 1, it is determined that the target switching clock signal has been switched to the first clock signal CLK1, that is, the first OR gate OR1 can output the first clock signal CLK1, and meanwhile, the output of the D flip-flop DF44 may have been turned from the logic level 1 to the logic level 0; The synchronous sampling and synchronous detection signal change of the D trigger output of the first clock domain circuit and the D trigger in the first D trigger cascade circuit are completed, the end point of the clock stop time can be determined, whether the signal output by the positive phase output end of the last-last D trigger in the first clock domain circuit is overturned relative to the signal output by the positive phase output end of the last-last D trigger in the first clock domain circuit is detected through the signal condition of each input end of the multi-input combination logic circuit at the same moment, and then the overturned condition is latched; and then the D trigger DF34 latches and outputs to the second OR gate OR2 to carry out final judgment, so as to obtain an indication signal of the completion of clock signal switching, which is equivalent to the situation that the D trigger DF34 grabs one beat and then judges by the second OR gate OR2 after the multi-input combinational logic circuit, the situation that burrs and the like generated by jump edges can be reduced when the switching situation of the first clock signal is detected, the competition risk can not occur, and the detection process is safe and reliable.

Continuously sampling at least three clock cycles in a second clock domain circuit by using a second clock signal, and transmitting a signal inverse to a signal output by a positive phase output end of a first-to-last stage D trigger of the second clock domain circuit and a signal output by a positive phase output end of a second-to-last stage D trigger of the second clock domain circuit to a first preset two-input AND gate in a second switching detection logic circuit for performing AND operation to obtain a second detection signal; the inverse signal of the signal output by the positive output end of the first-last-stage D flip-flop of the second clock domain circuit is input to the inverse input end of the second preset two-input and gate setting, which can be understood as that the signal output by the positive output end of the first-last-stage D flip-flop of the second clock domain circuit performs the inverse operation before being input to the second preset two-input and gate, or that the signal output by the positive output end of the first-last-stage D flip-flop of the second clock domain circuit performs the inverse operation before being input to the second preset two-input and gate. As shown in fig. 1, a signal output by a positive output end of a first-last stage D flip-flop of the second clock domain circuit is denoted by se2[3], a signal output by a positive output end of a second-last stage D flip-flop of the second clock domain circuit is denoted by se2[2], a first preset two-input and gate a41 is used for performing an and operation on the signal se2[2] and the inverted signal se2[3], a level inversion condition of the signal se2[3] relative to the signal se2[2] can be detected, if the second detection signal is a logic level 0, the signal se2[3] does not have level inversion relative to the signal se2[2], otherwise, if the second detection signal is a logic level 1, the level inversion occurs; and then introducing a signal source needing to be synchronized and a switched change condition of the signal source for the second D trigger cascade circuit and the second switching detection logic circuit.

The second detection signal and the signal output by the positive phase output end of the D trigger in the second switching detection logic circuit are sent to a two-input OR gate in the second switching detection logic circuit for OR operation, so that a second third detection signal is obtained; then, the second detection signal and the second third detection signal are sent to a second preset two-input AND gate in a second switching detection logic circuit to perform AND operation, so that a second fourth detection signal is obtained; sending a second fourth detection signal to the input end of the D trigger in the second switching detection logic circuit, and sampling one clock cycle by using a second clock signal to latch the second fourth detection signal; Referring to fig. 1, it can be seen that, when the second detection signal (the result of the and operation of the first preset two-input and gate a 41) and the signal output from the positive output end of the D flip-flop DF44 are given to the two-input OR gate OR4, the second detection signal can be OR operated with the real-time output signal of the D flip-flop DF44, and when the signal output from the D flip-flop DF44 is fed back to the two-input OR gate OR4 in real time is the logic level 1, the output of the first preset two-input and gate a41 (the second detection signal) does not affect the output of the two-input OR gate OR4, i.e. the level inversion condition of the signal se2[3] relative to the signal se2[2] does not change the second three detection signal; When the output of the D flip-flop DF44 is fed back in real time to the signal of the two-input OR gate OR4 as the logic level 0, the output of the first preset two-input and gate a41 affects the output of the two-input OR gate OR4, that is, the level inversion condition of the signal se2[3] relative to the signal se2[2] can change the second and third detection signals, so as to transmit the level inversion condition through the two-input OR gate OR4, and further can be used for detecting the switching change result; then, the two-input OR gate OR4 outputs the second third detection signal to the second preset two-input and gate a42; Then, the second preset two-input and gate a42 performs an and operation according to the second first detection signal output by the two-input nand gate a43 and the first fourth detection signal output by the two-input OR gate OR4, to obtain a preliminary detection result of the second clock signal switching, and then latches the output by the D flip-flop DF44, when the output of the D flip-flop DF44 is turned from the logic level 0 to the logic level 1, it is determined that the target switching clock signal has been switched to the second clock signal CLK2, that is, the first OR gate OR1 can output the second clock signal CLK2, and meanwhile, the output of the D flip-flop DF34 may have been turned from the logic level 1 to the logic level 0; The synchronous sampling and synchronous detection signal change of the D trigger output of the first clock domain circuit and the D trigger in the first D trigger cascade circuit are completed, the end point of the clock stop time can be determined, whether the signal output by the positive phase output end of the last-last D trigger in the first clock domain circuit is overturned relative to the signal output by the positive phase output end of the last-last D trigger in the first clock domain circuit is detected through the signal condition of each input end of the multi-input combination logic circuit at the same moment, and then the overturned condition is latched; and then the D trigger DF44 latches and outputs to the second OR gate OR2 to carry out final judgment, so that an indication signal of the completion of the switching of the second clock signal can be obtained, which is equivalent to the situation that after the multi-input combination logic circuit is subjected to one beat of D trigger DF44 and then judged by the second OR gate OR2, burrs and the like generated by jump edges are reduced, the competition risk is avoided, and the detection process is safe and reliable.

Then, the signal output by the positive phase output end of the D trigger in the first switching detection logic circuit and the signal output by the positive phase output end of the D trigger in the second switching detection logic circuit are sent to a second OR gate for OR operation, so as to obtain a switching indication signal for indicating the completion of clock signal switching; as shown in fig. 1, the positive phase output terminal of the D flip-flop DF34 in the first switching detection logic circuit outputs sel1_sig_clk1, the positive phase output terminal of the D flip-flop DF44 in the second switching detection logic circuit outputs sel2_sig_clk2, the second OR gate OR2 performs OR operation on the signals sel1_sig_clk1 and sel2_sig_clk2, and the output signal sel_sig is used as a switching indication signal to indicate that the clock signal switching is completed.

Preferably, the second level is lower than the first level, e.g. the first level is logic level 1 and the second level is logic level 0; furthermore, the frequency of the second clock signal is different from the frequency of the first clock signal, e.g. the frequency of the second clock signal is lower than the frequency of the first clock signal.

Based on the switching detection method mentioned in the foregoing embodiment, in the case where the selection signal is inverted from the second level to the first level, each time the output terminal of the second or gate outputs the first level, when the output terminal of the D flip-flop in the first switching detection logic circuit is set to the first level, it is determined that the target switching clock signal output by the output terminal of the first or gate has been switched from the second clock signal to the first clock signal, and then the second clock signal is turned off; in order to ensure that the target switching clock signal is safely and stably completely switched from the second clock signal to the first clock signal, the second clock signal is closed when the output end of the second OR gate outputs the first level, a temporary no-clock use scene is not caused, and the phenomenon that the clock is not successfully switched or a clock system is suspended due to the fact that the clock is switched off in advance in the switching process is prevented; when the selection signal is at the second level, the output end of the D flip-flop in the first switch detection logic circuit is set at the second level, and the target switch clock signal output by the output end of the first or gate is the second clock signal, that is, when the selection signal is turned from the second level to the first level, the second clock signal is the working clock signal before the target switch clock signal is switched from the second clock signal to the first clock signal.

As can be seen from fig. 1, when the selection signal select is turned from logic level 0 to logic level 1, it indicates that the target switching clock signal starts to switch from the second clock signal CLK2 to the first clock signal CLK1, and when sel1_sig_clk1 output by the D flip-flop DF34 changes from logic level 0 to logic level 1, it indicates that the switching has been completed, the clock out_clk output by the clock switching circuit is the first clock signal CLK1, at this time, the positive phase output end of the D flip-flop DF44 in the second switching detection logic circuit outputs sel2_sig_clk2 to logic level 0, the second OR gate OR2 takes the signals sel1_sig_clk1 and sel2_sigclk2 as OR operation, the obtained switching indication signal selsig is logic level 1, that is, in the case that the selection signal select is turned from logic level 0 to logic level 1, the switching indication signal selsig is logic level 1, it indicates that the target switching clock signal has completely switched from the second clock signal CLK2 to logic level 1, that the first clock signal CLK2 is completely switched off, that the first OR gate signal CLK2 is completely switched off, and the first OR signal CLK2 is completely switched off, which can be ensured. The second clock signal CLK2 is the original working clock signal, and the first clock signal CLK1 is the target switching clock signal.

Under the condition that the selection signal is turned over from a first level to a second level, when the output end of the second OR gate outputs the first level, the output end of the D trigger in the second switching detection logic circuit is set to the first level, and it is determined that the target switching clock signal output by the output end of the first OR gate is switched from the first clock signal to the second clock signal, and then the first clock signal is closed; in order to ensure that the target switching clock signal is safely and stably completely switched from the first clock signal to the second clock signal, the first clock signal is closed when the output end of the second OR gate outputs a first level, a temporary no-clock use scene is not caused, and the phenomenon that the clock is not successfully switched or a clock system is suspended due to the fact that the clock is switched off in advance in the switching process is prevented; when the selection signal is at a first level, the output end of the D flip-flop in the second switch detection logic circuit is set at a second level, and the target switch clock signal output by the output end of the first or gate is a first clock signal, that is, when the selection signal is turned from the first level to the second level, the first clock signal is a working clock signal before the target switch clock signal is switched from the first clock signal to the second clock signal.

As can be seen from fig. 1, when the selection signal select is inverted from logic level 1 to logic level 0, which indicates that the target switching clock signal starts to switch from the first clock signal CLK1 to the second clock signal CLK2, when the D flip-flop DF44 outputs sel2_sig_clk2, which is the second clock signal CLK2, from logic level 0 to logic level 1, which indicates that the switching has been completed, the non-inverting output terminal of the D flip-flop DF34 in the first switching detection logic circuit outputs sel1_sig_clk1 to logic level 0, the second OR gate OR2 performs OR operation on the signals sel1_sig_clk1 and sel2_sig_clk2, the obtained switching indication signal sel_sig is a logic level 1, that is, in the case that the selection signal select is flipped from the logic level 1 to the logic level 0, the switching indication signal sel_sig is flipped to the logic level 1, which indicates that the target switching clock signal has been completely switched from the first clock signal CLK1 to the second clock signal CLK2, that is, the first clock signal CLK1 has been completely switched from the second clock signal CLK2 across the clock stop time, and determines that the second clock signal output by the first OR gate OR1 is safe and reliable, and at the same time, the first clock signal CLK1 can be turned off, thereby saving power consumption. The second clock signal CLK2 is a target switching clock signal, and the first clock signal CLK1 is an original operating clock signal.

Therefore, according to the turnover condition of the selection signal, on the basis that the first D trigger cascade circuit or the second D trigger cascade circuit continuously samples at least two clock cycles for transmission, the multi-input combination logic circuit in each switching detection logic circuit is utilized to detect the clock switching condition within enough clock stopping time, so that the reliability of switching detection is improved. Therefore, when the first clock signal is completely switched to the second clock signal output or the second clock signal is completely switched to the first clock signal output, the clock switching completion indication signal is provided, and the clock signal of the switching output can be ensured to be used after the switching is completed; whether the clock signal with relatively high frequency is switched to the clock signal with relatively low frequency or the clock signal with relatively low frequency is switched to the clock signal with relatively high frequency, the phenomenon that the clock is not successfully switched or the clock system is suspended in the switching process because the clock is turned off in advance is prevented, the problem that the clock switching detection is influenced due to unstable signal establishment time of a logic device is solved, the accuracy and stability of triggering detection in the clock switching process are improved, and the fact that the clock signal is used after the switching is finished is ensured based on the finally output switching indication signal is determined, and the time when the original working clock signal can be turned off is determined for low power consumption.

Based on the foregoing embodiment, when the first clock signal is turned off, the selection signal is turned to the second level (logic level 0 is used), and the output end of the first or gate outputs the second clock signal, it indicates that the current target switching clock signal has been completely switched to the second clock signal, the output end of the D flip-flop in the second switching detection logic circuit outputs the first level (logic level 1 is used), the second clock signal drives the D flip-flops in each stage in the second clock domain circuit and the D flip-flop in the second switching detection logic circuit to operate respectively, when the selection signal is turned from the second level to the first level, the first clock signal is enabled but the second clock signal is not influenced temporarily, the output end of the D flip-flop in the second switching detection logic circuit is cleared by the second D flip-flop cascade circuit to make the second or gate output the second level (logic level 0 is used), the stage of switching the target switching clock signal from the second clock signal to the first clock signal is started, namely the stage of switching the target switching clock signal from the second clock signal to the first clock signal can be started, the stage of switching the target switching clock signal can be started in the clock stop time, the stage of switching the target switching clock signal can be regarded as reaching the starting point of the clock stop time, the switching process is detected in real time by the output end of the D trigger in the first switching detection logic circuit and the output end of the D trigger in the second switching detection logic circuit together, after the first clock signal is output by the output end of the first OR gate and the output end of the D trigger in the first switching detection logic circuit is at the first level, the switching indication signal output by the output end of the second OR gate is at the first level, the stage of switching the signal output by the output end of the second OR gate can be regarded as reaching the end of the clock stop time can be regarded as starting to turn over, the second clock signal is completely switched to the first clock signal, the second clock signal is turned off.

As can be seen from the schematic diagram of fig. 1, after the select signal is turned from the second level to the first level, the second clock signal CLK2 is used to continuously sample, the second clock signal CLK2 is used to sample the second level (the level of q0_clk2) at the positive output end of the first stage D flip-flop DF41 in the second D flip-flop cascade circuit during the first clock period, the second clock signal CLK2 is used to sample the first level at the negative output end QN of the second stage D flip-flop DF42 during the second clock period, and at this time, the positive output end of the third stage D flip-flop DF43 keeps the first level (the level of q2_clk2) by default; then, a first level output by an inverting output end of the second stage D trigger DF42 and a first level output by a non-inverting output end of the third stage D trigger DF43 are input into the two-input NAND gate A43 to perform NAND operation, the output of the two-input NAND gate A43 obtains a second level, the zero clearing of an output end sel2_sig_clk2 of the D trigger in the second switching detection logic circuit is realized, and the starting point of the clock stop time can be determined in the process of switching the second clock signal into the first clock signal; interference is also eliminated for detecting whether or not to switch from the second clock signal to the first clock signal (the target switching clock signal selected in the case where the current selection signal is set to the first level).

When the selection signal is turned over from the first level to the second level, the second clock signal is started, but the working of the first clock signal is not influenced, the positive output end of the D flip-flop in the first switching detection logic circuit is cleared to enable the second OR gate to output the second level (using logic level 0), the stage of switching the target switching clock signal from the first clock signal to the second clock signal is started, namely the stage of switching the target switching clock signal from the first clock signal to the second clock signal can be started, the stage of switching the target switching clock signal can be started in the clock stop time, the stage of switching the target switching clock signal can be regarded as reaching the starting point of the clock stop time, the switching process is detected in real time by the output end of the D trigger in the first switching detection logic circuit and the output end of the D trigger in the second switching detection logic circuit together, after the second clock signal is output by the output end of the first OR gate and the positive phase output end of the D trigger in the second switching detection logic circuit is at the first level, the signal output by the output end of the second OR gate starts to turn over, the switching indication signal output by the output end of the second OR gate is at the first level, the first clock signal is determined to be completely switched into the second clock signal, and then the first clock signal is closed.

As can be seen schematically from fig. 1, after the selection signal select is turned from the first level to the second level, the output terminal of the D flip-flop DF31 in the first D flip-flop cascade circuit outputs the second level by continuously sampling the first clock signal CLK1 and sampling the first clock signal CLK1 for the first clock period; when the first clock signal CLK1 is used for sampling the second clock period, the inverted output end of the second stage D flip-flop DF32 outputs the first level, at this time, i.e., the first clock signal CLK1 is used for sampling the second clock period, the non-inverting output end of the third stage D flip-flop DF33 keeps the first level by default, the first level output by the inverted output end of the second stage D flip-flop DF32 and the first level output by the non-inverting output end of the third stage D flip-flop DF33 are input into the two-input nand gate a33 for performing nand operation, the two-input nand gate a33 outputs the second level, and then the output end sel1_sig_clk1 of the D flip-flop in the first switching detection logic circuit is cleared, so that the starting point of the clock stop time can be determined in/before the process of switching the first clock signal into the second clock signal; interference is also eliminated for detecting whether or not to switch from the first clock signal to the second clock signal (the target switching clock signal selected in the case where the current selection signal is set to the first level).

It should be noted that, in the stage of switching the target switching clock signal from the second clock signal to the first clock signal, there is a state in which both the first clock signal and the second clock signal are locked, that is, in the clock stop time; the output end of the first or gate does not output the first clock signal or the second clock signal in the locked state (in the clock stop time), so that the output end of the first or gate keeps outputting the second level, and the output end of the D flip-flop in the first switching detection logic circuit and the output end of the D flip-flop in the second switching detection logic circuit both keep outputting the second level, and after the clock stop time, the output end of the D flip-flop in the first switching detection logic circuit is the first level.

When the second clock signal is turned off, the signal output by the output end of the D trigger in the second switching detection logic circuit is of a second level; when the first clock signal is turned off, the signal output by the output end of the D flip-flop in the first switch detection logic circuit is at the second level.

Alternatively, the cascaded flip-flops in the first clock domain circuit, the second clock domain circuit, the first D flip-flop cascade circuit and the second D flip-flop cascade circuit are all equivalent to constitute a counter, and as known to those skilled in the relevant art, the count bit width/maximum count value of the counter is determined by the number of the cascaded flip-flops.

As an embodiment, when the initial level of the selection signal is the second level and the reset level of the positive output terminals of all the D flip-flops having the clock terminals input the second clock signal is the first level, the second clock signal is preferentially started to preferentially drive the second clock domain circuit to work, and if the flip-flops in cascade connection in the second clock domain circuit and the second D flip-flop cascade circuit are regarded as counters, the count values of the counters are equal to the maximum count value in the reset state/initial state; after the selection signal is turned from the second level to the first level, the first clock signal CLK1 is started to be output, but the second clock signal is not influenced temporarily, if the second clock signal is used for sampling, the second clock domain circuit and the second D trigger cascade circuit start to count down from the maximum count value, and at the moment, the D trigger connected in series in the second clock domain circuit and the second D trigger cascade circuit is regarded as a counter capable of counting.

In this embodiment, the maximum count value of the second clock domain circuit is a binary value composed of reset levels of the positive output terminals of all the D flip-flops in the second clock domain circuit, the actions corresponding to the logic level 1 of the positive output terminal of the D flip-flop DF21, the logic level 1 of the positive output terminal of the D flip-flop DF22, the logic level 1 of the positive output terminal of the D flip-flop DF23, and the logic level 1 of the positive output terminal of the D flip-flop DF24 in fig. 1 are triggered from the input terminal of the D flip-flop DF21, and the 4' b1111 (high order left, low order right) composed of the logic level 1 of the positive output terminal of the D flip-flop DF24 is recorded as the maximum count value of the second clock domain circuit, the actions of the second clock domain circuit and the second D flip-flop cascade circuit are triggered from the input terminal of the logic level 0 of the maximum count value of the second clock domain circuit, and the first clock cycle is sampled during the second clock signal CLK2 sampling for a plurality of clock cycles, and the 4' b1111 becomes 4' b1110, wherein se2[3] =1, se 2] =1; sampling the second clock cycle, the aforementioned 4'b1110 becomes 4' b1100, where se2[3] =1, se2[2] =1; sampling for the third clock cycle, the aforementioned 4'b1100 becomes 4' b1000, where se2[3] =1, se2[2] =0. Where b is the representation of bits, one bit representing the output of one D flip-flop.

Similarly, the maximum count value of the second D flip-flop cascade circuit is a binary value composed of reset levels of the non-inverting output terminals of all flip-flops in the second D flip-flop cascade circuit, the binary values correspond to 3' b111 (high left and low right) composed of logic level 1 of the non-inverting output terminal of the D flip-flop DF41, logic level 1 of the non-inverting output terminal of the D flip-flop DF42 and logic level 1 of the non-inverting output terminal of the D flip-flop DF43 in fig. 1, the operation of the second clock domain circuit and the second D flip-flop cascade circuit starting to count down from the maximum count value thereof is that the input terminal of the D flip-flop DF21 starts to trigger by inputting logic level 0, the first clock cycle is sampled during the second clock signal CLK2 sampling for a plurality of clock cycles, the aforementioned 3' b111 becomes 3' b110, wherein q2_clk2=1, q1_clk2=1; sampling the second clock cycle, the aforementioned 3'b110 becomes 3' b100, wherein q2_clk2=1 and q1_clk2=0; sampling for the third clock cycle, the aforementioned 3'b100 becomes 3' b000, where q2_clk2=0 and q1_clk2=0.

In some embodiments, after the selection signal is turned from the second level to the first level, the second clock signal is used to sample, and then the first clock signal is used to sample, that is, the second clock domain circuit is driven to operate for a corresponding clock period, and then the first clock domain circuit is driven to operate.

On the other hand, when the initial level of the selection signal is the second level and the reset levels of the positive phase output terminals of all the D flip-flops of the clock terminal input the first clock signal are the second level, it can be understood that the initial level of all the D flip-flops of the clock terminal input the first clock signal is the second level, and the second clock signal is preferentially started to preferentially drive the second clock domain circuit to operate, when the initial level of the selection signal is the second level, the reset levels of the positive phase output terminals of all the D flip-flops of the clock terminal input the first clock signal are the second level, and the reset levels of all the D flip-flops of the clock terminal input the second clock signal are the first level; and if the serially connected flip-flops in the first clock domain circuit and the first D flip-flop cascade circuit are regarded as counters, the count values of the counters are equal to the minimum count value in a reset state/initial state. After the selection signal is turned from the second level to the first level, the first clock signal is started to be output, but the operation of the second clock signal is not influenced temporarily, if the first clock signal is used for sampling, the first clock domain circuit and the first D trigger cascade circuit are both used for increasing and counting from the minimum count value, wherein the second clock signal may be prior to the first clock signal for sampling, and the D triggers connected in series in the first clock domain circuit and the first D trigger cascade circuit are regarded as counters capable of being used for counting.

In this embodiment, the minimum count value of the first clock domain circuit is a binary value composed of reset levels of the positive output terminals of all the D flip-flops in the first clock domain circuit, the actions corresponding to the logic level 0 of the positive output terminal of the D flip-flop DF11, the logic level 0 of the positive output terminal of the D flip-flop DF12, the logic level 0 of the positive output terminal of the D flip-flop DF13, and the logic level 0 of the positive output terminal of the D flip-flop DF14 in fig. 1 are the first clock cycle, and the 4' b0000 (high bit left and low bit right) is recorded as the minimum count value of the first clock domain circuit, the actions of the first clock domain circuit and the first D flip-flop cascade circuit starting to count up from the minimum count value thereof are the input logic level 1 of the D flip-flop DF11, the first clock cycle is sampled during the first clock signal CLK1 sampling for a plurality of clock cycles, the aforementioned 4' b0000 becomes 4' b0001, wherein se1[3] =0, se1[2] =0; sampling the second clock cycle, the aforementioned 4'b0001 becomes 4' b0011, where se1[3] =0, se1[2] =0; sampling for the third clock cycle, the aforementioned 4'b0011 becomes 4' b0111, where se1[3] =0, se1[2] =1.

The minimum count value of the first D flip-flop cascade circuit is a binary value composed of reset levels of the non-inverting output terminals of all the D flip-flops in the first D flip-flop cascade circuit, corresponds to 3' b000 (high left and low right) composed of logic level 0 of the non-inverting output terminal of the D flip-flop DF31, logic level 0 of the non-inverting output terminal of the D flip-flop DF32, and logic level 0 of the non-inverting output terminal of the D flip-flop DF33 in fig. 1, and is recorded as the minimum count value of the first D flip-flop cascade circuit, the actions of the first clock domain circuit and the first D flip-flop cascade circuit that the up-counting starts from the minimum count value thereof are that the input of the logic level 1 of the D flip-flop DF31 starts to trigger, the first clock cycle is sampled during the first clock signal CLK1 samples a plurality of clock cycles, the aforementioned 3' b000 becomes 3' b001, wherein q2_clk1=0, q1=0; sampling the second clock cycle, the aforementioned 3'b001 becomes 3' b011, where q2_clk1=0 and q1_clk1=1; sampling the third clock cycle, the aforementioned 3'b111 becomes 3' b011, where q2_clk1=1 and q1_clk1=1.

As an embodiment, as can be seen from fig. 1, when the selection signal is inverted from logic level 0 to logic level 1, the binary value formed by the signal output by the positive output terminal of the first stage D flip-flop of the second D flip-flop cascade circuit and the signal output by the positive output terminal of the second stage D flip-flop of the second D flip-flop cascade circuit changes from binary 11 to binary 10, and when the binary value corresponding to the signal represented by the signal q2_clk2 and the signal q1_clk2 in fig. 1 changes from binary 11, it is determined that the selection signal set to logic level 1 is inverted and is input to the first stage D flip-flop of the second D flip-flop cascade circuit, and then changes to binary 10 after two clock cycles of the second clock signal CLK2, at this time, the signal output by the two input nand gate a43 in the second switch detection logic circuit is inverted from logic level 1 to logic level 0, so that the signal output by the positive output terminal of the D flip-flop in the second switch detection logic circuit is inverted from logic level 1 to logic level 10, and the second switch detection logic 2 is realized.

It should be noted that, before the second clock cycle of the second clock signal CLK2 is clocked, the binary value formed by the signal q2_clk2 and the signal q1_clk2 is kept at binary 11, the signal se2[3] output by the positive output terminal of the last second stage D flip-flop of the second clock domain circuit and the signal se2[2] output by the positive output terminal of the last second stage D flip-flop of the second clock domain circuit are also kept at binary 11, the output sel1_sig_clk1 is logic level 1, that is, the signal at the output terminal of the D flip-flop in the second switch detection logic circuit is logic level 1, the reset level at the positive output terminal of the D flip-flop DF44 of the second switch detection logic circuit is also logic level 1, and the output signal sel2_sig_clk2 of the second switch detection logic circuit is logic level 1. In the second clock period of the second clock signal CLK2, a binary value formed by a signal output by the positive output terminal of the last stage D flip-flop of the second D flip-flop cascade circuit and a signal output by the positive output terminal of the last stage D flip-flop of the second D flip-flop cascade circuit changes from binary 11 to binary 10, and a signal output by the two-input nand gate a43 in the second switch detection logic circuit is flipped from logic level 1 to logic level 0, so that a signal output by the positive output terminal of the D flip-flop in the second switch detection logic circuit is flipped from logic level 1 to logic level 0.

When the binary value of the signal output from the positive output terminal of the last stage D flip-flop of the second D flip-flop cascade circuit and the signal output from the positive output terminal of the last stage D flip-flop of the second D flip-flop cascade circuit is changed from binary 10 to binary 00, corresponding to fig. 1, the signal output from the binary input nand gate a43 in the second switch detection logic circuit is inverted from logic level 0 to logic level 1 in the first stage D flip-flop of the second D flip-flop cascade circuit after passing through three clock cycles of the second clock signal CLK2, that is, the binary 10 of the signal q2_clk2 and the signal q1_clk2 is changed to binary 00 in the third clock cycle of the second clock signal CLK2, the output of the D flip-flop in the second switch detection logic circuit is determined by the first preset two-input and gate and the second preset two-input and gate in the second switch detection logic circuit, as shown in fig. 1, when the output of the D flip-flop DF44 in the second switch detection logic circuit outputs the logic level 1, the output is determined by the first preset two-input and gate a41, the second preset two-input and gate a42 and the two-input OR gate OR4 in the second switch detection logic circuit, wherein the two inputs of the first preset two-input and gate a41 are respectively derived from the signal output by the positive output terminal of the reciprocal first stage D flip-flop of the second clock domain circuit and the signal output by the positive output terminal of the reciprocal second stage D flip-flop of the second clock domain circuit.

Based on the selection signal, when the logic level 0 is inverted to the logic level 1, the positive phase output end of the D flip-flop in the second switching detection logic circuit keeps outputting the logic level 0 in the process that the binary value formed by the signal output by the positive phase output end of the D flip-flop in the last stage of the second clock domain circuit and the signal output by the positive phase output end of the D flip-flop in the last stage of the second clock domain circuit changes from the binary 10 to the binary 00; as shown in fig. 1, the binary value formed by the signal output by the positive output terminal of the last stage D flip-flop of the second clock domain circuit and the signal output by the positive output terminal of the last stage D flip-flop of the second clock domain circuit corresponds to the binary value formed by se2[3] and se2[2] in fig. 1, and after the selection signal set to the logic level 1 is inverted and input to the first stage D flip-flop DF21 of the second clock domain circuit through the and gate A2, the binary value remains to be binary 11 until reaching the second clock cycle of the second clock signal CLK2, and changes to binary 10 after three clock cycles of the second clock signal CLK 2; then in the third clock cycle of the second clock signal CLK2, the first preset two-input and gate a41 outputs a logic level 0, at this time, since the positive output terminal of the D flip-flop in the second switching detection logic circuit is the logic level 0 output in the second clock cycle, the two-input OR gate OR4 outputs the logic level 0, and simultaneously, the signal q2_clk2 output by the positive output terminal of the third stage D flip-flop DF43 of the second D flip-flop cascade circuit and the signal q1_clk2 output by the positive output terminal of the second stage D flip-flop DF42 are binary 00, and the signal output by the two-input nand gate a43 outputs the logic level 1; then, the second preset two-input AND gate A42 outputs a logic level 0, so that the non-inverting output terminal of the D flip-flop DF44 in the second switching detection logic circuit still outputs the logic level 0. Then, as can be seen from fig. 1, after the selection signal set to the logic level 1 is inverted and is input to the first stage D flip-flop DF21 of the second clock domain circuit through the and gate A2, the binary values formed by se2[3] and se2[2] change to binary 00 after four clock cycles of the second clock signal CLK2, the first preset two-input and gate a41 outputs the logic level 0, at this time, the non-inverting output terminal of the D flip-flop DF44 still outputs the logic level 0, then the two-input OR gate OR4 outputs the logic level 0, and then the and operation of the second preset two-input and gate a42 outputs the logic level 0, so that the non-inverting output terminal of the D flip-flop DF44 in the second switch detection logic circuit still outputs the logic level 0. Thus, the non-inverting output of the D flip-flop in the second switch detect logic circuit remains at output logic level 0 during the transition of the binary values of se2[3] and se2[2] from binary 10 to binary 00.

It should be noted that, after the binary value formed by the signal output by the positive output end of the last stage D flip-flop of the second D flip-flop cascade circuit and the signal output by the positive output end of the last stage D flip-flop of the second D flip-flop cascade circuit changes to binary 10, the binary value formed by the signal output by the positive output end of the last stage D flip-flop of the second clock domain circuit and the signal output by the positive output end of the last stage D flip-flop of the second clock domain circuit changes to binary 10 after at least one clock cycle of the second clock signal.

On the basis of the above embodiment, as can be seen from fig. 1, in the case that the selection signal is inverted from logic level 0 to logic level 1, when the binary value of the signal outputted by the non-inverting output terminal of the first-stage D flip-flop of the first D flip-flop cascade circuit and the signal outputted by the non-inverting output terminal of the second-stage D flip-flop of the first D flip-flop cascade circuit changes from binary 00 to binary 01, it is determined that, in the case that the binary value of the signal denoted as signal q2_clk1 and signal q1_clk1 in fig. 1 changes from binary 00 to binary 01: after the selection signal set to logic level 1 is input to the first stage D flip-flop of the first D flip-flop cascade circuit has passed two clock cycles of the first clock signal CLK1 and changed to binary 01, At this time, the signal output by the two-input nand gate a33 in the first switching detection logic circuit is inverted from the logic level 0 to the logic level 1, and the signal output by the two-input nand gate a33 maintains the logic level 1 until the first D flip-flop cascade circuit counts to the maximum count value after the first inversion from the logic level 0 to the logic level 1. Specifically, when the binary value of the signal output from the positive output terminal of the last stage D flip-flop of the first D flip-flop cascade circuit and the signal output from the positive output terminal of the last stage D flip-flop of the first D flip-flop cascade circuit is changed from binary 01 to binary 11, corresponding to fig. 1, the selection signal set to logic level 1 is input to the first stage D flip-flop of the first D flip-flop cascade circuit, and is changed to binary 11 after three clock cycles of the first clock signal CLK1, that is, binary 01 composed of the signal q2_clk1 and the signal q1_clk1 is changed to binary 11 after one clock cycle of the first clock signal CLK1, The signal output by the two-input nand gate a33 in the first switch detection logic circuit is a logic level 1, and in the third clock cycle, the output of the D flip-flop in the first switch detection logic circuit is determined by the first preset two-input and gate and the second preset two-input and gate in the first switch detection logic circuit, as shown in fig. 1, when the output of the D flip-flop DF34 in the first switch detection logic circuit outputs a logic level 1 at the two-input nand gate a33 in the first switch detection logic circuit, the first preset two-input and gate a31, the second preset two-input and gate a32 and the two-input OR gate OR3 in the first switch detection logic circuit are determined together, The two inputs of the first preset two-input and gate a31 are derived from a signal output by the positive output terminal of the last-to-last stage D flip-flop of the first clock domain circuit and a signal output by the positive output terminal of the last-to-last stage D flip-flop of the first clock domain circuit, respectively. Then, at the fourth clock cycle of the first clock signal CLK1, the signal q2_clk1 output from the non-inverting output terminal of the third stage D flip-flop DF33 of the first D flip-flop cascade circuit and the signal q1_clk1 output from the non-inverting output terminal of the second stage D flip-flop DF32 are binary 11, and the signal output from the two-input nand gate a33 in the first switch detection logic circuit is logic level 1.

It should be noted that, before the second clock cycle of the first clock signal CLK1, the binary value formed by the signal q2_clk1 and the signal q1_clk1 remains at a binary 00, the signal se1[3] output by the positive output terminal of the last stage D flip-flop of the first clock domain circuit and the signal se1[2] output by the positive output terminal of the last stage D flip-flop of the first clock domain circuit also remain at a binary 00, and the first switch detection logic circuit is input, and since the reset level of the positive output terminal of the D flip-flop in the first switch detection logic circuit is a logic level 0, the signal sel1 sig_clk1 output by the positive output terminal of the D flip-flop in the first switch detection logic circuit is a logic level 0 before the binary value formed by the signal q2_clk1 and the signal q1_clk1 changes from a binary 00 to a binary 01.

It should be noted that, after the binary value formed by the signal output by the positive output end of the last stage D flip-flop of the first D flip-flop cascade circuit and the signal output by the positive output end of the last stage D flip-flop of the first D flip-flop cascade circuit changes to binary 01, the binary value formed by the signal output by the positive output end of the last stage D flip-flop of the first clock domain circuit and the signal output by the positive output end of the last stage D flip-flop of the first clock domain circuit changes to binary 01 after at least one clock cycle of the first clock signal.

When the selection signal is changed from a logic level 0 to a logic level 1, a binary value formed by a signal output by a positive output end of a first-stage D flip-flop of the first clock domain circuit and a signal output by a positive output end of a second-stage D flip-flop of the first clock domain circuit is changed from a binary 00 to a binary 01, an output signal of the positive output end of the D flip-flop in the first switching detection logic circuit is changed from a logic level 0 to a logic level 1, a binary value corresponding to the elements of se1[3] and se1[2] in fig. 1 is changed from a binary 00 to a binary 01, a logic level 1 is input to an input end of the D flip-flop in the first switching detection logic circuit, and the input end of the D flip-flop is latched by the D flip-flop in the first switching detection logic circuit for one clock cycle, so that the positive output end of the D flip-flop in the first switching detection logic circuit is changed from the logic level 0 to the logic level 1, a switching indication signal output by the output end of the second or gate is the logic level 1, and the second clock signal is completely switched to the first clock signal is determined.

As can be seen from fig. 1, in the process of changing the binary value formed by se1[3] and se1[2] from binary 00 to binary 01, the binary value formed by the signal se1[3] and the signal se1[2] is inverted by the selection signal set to the logic level 1 and is kept at the binary 00 before reaching the third clock cycle of the first clock signal CLK1 after the selection signal is input to the first stage D flip-flop DF11 of the first clock domain circuit through the and gate A1, so that the first preset two-input and gate a31 keeps outputting the logic level 0, while the binary value formed by the signal q2_clk1 and the signal q1_clk1 is changed from binary 00 to binary 01 before reaching the third clock cycle of the first clock signal CLK1, so that the signal output by the two-input nand gate a33 keeps the logic level 1, and the reset level of the positive phase output end of the D flip-flop DF34 in the first switch detection logic circuit is kept at the logic level 0, so that the output of the second preset two-input gate 3 keeps outputting the logic level 0 before reaching the third clock cycle of the first clock signal CLK1, and the output of the positive phase gate 34 is kept at the logic level 0.

When reaching the third clock cycle of the first clock signal CLK1, the binary value of the signal q2_clk1 and the signal q1_clk1 changes to binary 11, the binary value of the signal q1 [3] and the signal se1[2] changes to binary 01, when reaching the third clock cycle of the first clock signal CLK1, the first preset two-input and gate a31 outputs a logic level 1, the two-input nand gate a33 outputs a logic level 1, and at this time, since the positive phase output terminal of the D flip-flop in the first switch detection logic circuit is a logic level 0 (generated during the second clock cycle of the first clock signal CLK 1), the two-input OR gate OR3 outputs a logic level 1, and at the same time, the signal q2_clk1 output by the positive phase output terminal of the third stage D flip-flop DF33 of the first D flip-flop cascade circuit and the signal q1_clk1 output by the positive phase output terminal of the second stage D flip-flop DF32 are binary 11, and the signal output by the two-input nand gate a33 outputs a logic level 1; then, the second preset two-input and gate a32 outputs a logic level 1, so that the non-inverting output terminal of the D flip-flop DF34 in the first switching detection logic circuit is turned from a logic level 0 to a logic level 1, and the second OR gate OR2 outputs a logic level 1, so as to determine that the second clock signal CLK2 is completely switched to the first clock signal CLK1.

Further, after the selection signal set to the logic level 1 is input to the first stage D flip-flop DF11 of the first clock domain circuit through the and gate A1, the selection signal changes to the binary 11 after four clock cycles of the first clock signal CLK1, the first preset two-input and gate a31 outputs the logic level 0 in the fourth clock cycle of the first clock signal CLK1, at this time, the signal q2_clk1 and the signal q1_clk1 still form the binary 11, the signal output from the two-input nand gate a33 outputs the logic level 1, the non-inverting output terminal of the D flip-flop DF34 outputs the logic level 1, the two-input OR gate OR3 outputs the logic level 1, and then outputs the logic level 1 after the and operation of the second preset two-input and gate a32, so that the non-inverting output terminal of the D flip-flop DF34 in the first switch detection logic circuit still outputs the logic level 1.

As another embodiment, when the initial level of the selection signal is the first level and the reset levels of the positive output terminals of all the D flip-flops having the clock terminals input with the first clock signal are the first level, the first clock signal is preferentially started to preferentially drive the first clock domain circuit to work, and if the flip-flops in the cascade connection of the first clock domain circuit and the first D flip-flop cascade circuit are regarded as counters, the count values of the counters are equal to the maximum count value in the reset state/initial state; after the selection signal is turned from the first level to the second level, the second clock signal is started to be output, the work of the first clock signal is not influenced temporarily, if the first clock signal is used for sampling, the first clock domain circuit and the first D trigger cascade circuit start to count down from the maximum count value, and at the moment, the D trigger connected in series in the first clock domain circuit and the first D trigger cascade circuit is regarded as a counter capable of counting.

In this embodiment, the maximum count value of the first clock domain circuit is a binary value composed of reset levels of the positive output terminals of all the D flip-flops in the first clock domain circuit, the actions corresponding to the logic level 1 of the positive output terminal of the D flip-flop DF11, the logic level 1 of the positive output terminal of the D flip-flop DF12, the logic level 1 of the positive output terminal of the D flip-flop DF13, and the logic level 1 of the positive output terminal of the D flip-flop DF14 in fig. 1 are the first clock cycle, and the 4' b1111 (high bit on the left and low bit on the right) is recorded as the maximum count value of the first clock domain circuit, the actions of the first clock domain circuit and the first D flip-flop cascade circuit starting to count down from the maximum count value thereof are the input logic level 0 of the input terminal of the D flip-flop DF11, and during the first clock signal CLK1 sampling for a plurality of clock cycles, the aforementioned 4' b1111 becomes 4' b1110, wherein se1[3] =1, se1[2] =1; sampling the second clock cycle, the aforementioned 4'b1110 becomes 4' b1100, where se1[3] =1, se1[2] =1; sampling for the third clock cycle, the aforementioned 4'b1100 becomes 4' b1000, where se1[3] =1, se1[2] =0. Where b is the representation of bits, one bit representing the output of one D flip-flop.

Similarly, the maximum count value of the first D flip-flop cascade circuit is a binary value composed of reset levels of the non-inverting output terminals of all flip-flops in the first D flip-flop cascade circuit, the logic level 1 of the non-inverting output terminal of the D flip-flop DF31 in fig. 1, the logic level 1 of the non-inverting output terminal of the D flip-flop DF32, and the 3' b111 (high left and low right) composed of the logic level 1 of the non-inverting output terminal of the D flip-flop DF33 are correspondingly counted as the maximum count value of the first D flip-flop cascade circuit, the actions of the first clock domain circuit and the first D flip-flop cascade circuit from the maximum count value start to count down are that the input logic level 0 of the D flip-flop DF31 starts to trigger, the first clock cycle is sampled during the first clock signal CLK1 sampling for a plurality of clock cycles, the aforementioned 3' b111 becomes 3' b110, wherein q2_clk1=1 and q1_clk1=1; sampling the second clock cycle, the aforementioned 3'b110 becomes 3' b100, wherein q2_clk1=1 and q1_clk1=0; sampling for the third clock cycle, the aforementioned 3'b100 becomes 3' b000, where q2_clk1=0 and q1_clk1=0.

In some embodiments, after the selection signal is turned from the first level to the second level, the first clock signal is used for sampling, and then the second clock signal is used for sampling, that is, the first clock domain circuit is driven to operate for a corresponding clock period, and then the second clock domain circuit is driven to operate.

When the initial level of the selection signal is the first level and the reset levels of the positive phase output terminals of all the D flip-flops of the clock terminal input the second clock signal are the second level, it can be understood that the initial levels of the outputs of all the D flip-flops of the clock terminal input the second clock signal are the second level, and the first clock signal is preferentially started to preferentially drive the first clock domain circuit to work, at this time, when the initial level of the selection signal is the first level, the reset levels of the positive phase output terminals of all the D flip-flops of the clock terminal input the second clock signal are the second level, and the reset levels of all the D flip-flops of the clock terminal input the first clock signal are the first level; and if the serially connected flip-flops in the second clock domain circuit and the second D flip-flop cascade circuit are regarded as counters, the count values of the counters are equal to the minimum count value in a reset state/initial state. After the selection signal is turned from the first level to the second level, the second clock signal is started to be output, but the work of the first clock signal is not influenced temporarily, if the second clock signal is used for sampling, the second clock domain circuit and the second D trigger cascade circuit are both used for increasing and counting from the minimum count value, wherein the first clock signal may be already sampled prior to the second clock signal, and the D trigger connected in cascade in the second clock domain circuit and the second D trigger cascade circuit is regarded as a counter capable of being counted.

In this embodiment, the minimum count value of the second clock domain circuit is a binary value composed of reset levels of the positive output terminals of all the D flip-flops in the second clock domain circuit, the actions corresponding to the logic level 0 of the positive output terminal of the D flip-flop DF21, the logic level 0 of the positive output terminal of the D flip-flop DF22, the logic level 0 of the positive output terminal of the D flip-flop DF23, and the logic level 0 of the positive output terminal of the D flip-flop DF24 in fig. 1 are the logic level 1 input to the input terminal of the D flip-flop DF21, and the first clock cycle is sampled during the second clock signal CLK2 sampling for a plurality of clock cycles, and the aforementioned 4'b0000 becomes 4' b0001 (high bit left, low bit right) denoted as the minimum count value of the second clock domain circuit, the actions of the second clock domain circuit and the second D flip-flop cascade circuit are the logic level 1 input to start triggering from the minimum count value thereof, and the first clock cycle is sampled during the second clock signal CLK2 sampling for a plurality of clock cycles, wherein, se2[3] =0, se 2] =0; sampling the second clock cycle, the aforementioned 4'b0001 becomes 4' b0011, where se2[3] =0, se2[2] =0; sampling for the third clock cycle, the aforementioned 4'b0011 becomes 4' b0111, where se2[3] =0, se2[2] =1.

The minimum count value of the second D flip-flop cascade circuit is a binary value composed of reset levels of the non-inverting output terminals of all the D flip-flops in the second D flip-flop cascade circuit, and corresponds to 3' b000 (high left and low right) composed of logic level 0 of the non-inverting output terminal of the D flip-flop DF41, logic level 0 of the non-inverting output terminal of the D flip-flop DF42, and logic level 0 of the non-inverting output terminal of the D flip-flop DF43 in fig. 1, and the actions of the second clock domain circuit and the second D flip-flop cascade circuit for counting up from the minimum count value thereof are that the input terminal of the D flip-flop DF41 starts to trigger, and during the process of sampling the second clock signal CLK2 for a plurality of clock cycles, the first clock cycle is sampled, the aforementioned 3' b000 becomes 3' b001, wherein q2_clk2=0, q1_clk2=0; sampling the second clock cycle, the aforementioned 3'b001 becomes 3' b011, where q2_clk2=0 and q1_clk2=1; sampling the third clock cycle, the aforementioned 3'b011 becomes 3' b111, where q2_clk2=1 and q1_clk2=1.

As an embodiment, as can be seen from fig. 1, when the selection signal is inverted from logic level 1 to logic level 0, the binary value formed by the signal output by the positive output terminal of the last stage D flip-flop of the first D flip-flop cascade circuit and the signal output by the positive output terminal of the last stage D flip-flop of the first D flip-flop cascade circuit changes from binary 11 to binary 10, and when the binary value corresponding to the binary value represented as signal q2_clk1 and signal q1_clk1 in fig. 1 changes from binary 11 to binary 10, it is determined that after the selection signal set to logic level 0 is input to the first stage D flip-flop of the first D flip-flop cascade circuit, the signal output by the binary input nand gate a33 in the first switch detection logic circuit is inverted from logic level 1 to logic level 0 after two clock cycles of the first clock signal CLK1, furthermore, the signal output by the normal phase output end of the D trigger in the first switching detection logic circuit is turned from the logic level 1 to the logic level 0, so as to realize zero clearing of the output signal sel1_sig_clk1 of the first switching detection logic circuit, the binary value formed by the signal Q2_clk1 and the signal Q1_clk1 keeps binary 11 before the second clock period of the first clock signal CLK1 is beaten, the signal se1[3] output by the normal phase output end of the last second stage D trigger in the first clock domain circuit and the signal se1[2] output by the normal phase output end of the last second stage D trigger in the second clock domain circuit also keep binary 11, the output signal sel1_sig_clk1 of the first switching detection logic circuit is logic level 1, namely the signal output by the output end of the D trigger in the first switching detection logic circuit is logic level 1, let the output signal sel1_sig_clk1 of the first switching detection logic circuit be logic level 1 as well.

Then, when the binary value of the signal output from the positive output terminal of the last stage D flip-flop of the first D flip-flop cascade circuit and the signal output from the positive output terminal of the last stage D flip-flop of the first D flip-flop cascade circuit is changed from binary 10 to binary 00, corresponding to fig. 1, the signal output from the binary input nand gate a33 in the first switch detection logic circuit is inverted from logic level 0 to logic level 1 after three clock cycles of the first clock signal CLK1, that is, the binary 10 of the signal q2_clk1 and the signal q1_clk1 after one clock cycle of the first clock signal CLK1 (the third clock cycle of the first clock signal CLK1 is reached), and in the third clock cycle, the output of the D flip-flop in the first switch detection logic circuit is determined by the first preset two-input and gate and the second preset two-input and gate in the first switch detection logic circuit, as shown in fig. 1, when the output of the D flip-flop DF34 in the first switch detection logic circuit outputs the logic level 1 at the two-input nand gate a33 in the first switch detection logic circuit, the first preset two-input and gate a31, the second preset two-input and gate a32 and the two-input OR gate OR3 in the first switch detection logic circuit are determined together, wherein the two inputs of the first preset two-input and gate a31 are respectively derived from the signal output by the positive output end of the first-stage D flip-flop of the first clock domain circuit and the signal output by the positive output end of the second-stage D flip-flop of the first clock domain circuit.

Based on the above, in the case that the selection signal is inverted from the logic level 1 to the logic level 0, the positive phase output end of the D flip-flop in the first switching detection logic circuit keeps outputting the logic level 0 or keeps inputting the logic level 0 in the process that the binary value composed of the signal output by the positive phase output end of the D flip-flop in the last first clock domain circuit and the signal output by the positive phase output end of the D flip-flop in the second last clock domain circuit changes from the binary 10 to the binary 00; as shown in fig. 1, the binary value formed by the signal output from the positive output terminal of the last stage D flip-flop of the first clock domain circuit and the signal output from the positive output terminal of the last stage D flip-flop of the first clock domain circuit corresponds to the binary value formed by se1[3] and se1[2] in fig. 1, and after the selection signal set to the logic level 0 is input to the first stage D flip-flop DF11 of the first clock domain circuit through the and gate A1, the selection signal remains as binary 11 until reaching the second clock cycle of the first clock signal CLK1, and changes to binary 10 after three clock cycles of the first clock signal CLK 1; then in the third clock cycle of the first clock signal CLK1, the first preset two-input and gate a31 outputs a logic level 0, at this time, since the positive output terminal of the D flip-flop in the first switch detection logic circuit is the logic level 0 cleared in the second clock cycle, the two-input OR gate OR3 outputs the logic level 0, and at the same time, the signal q2_clk1 output by the positive output terminal of the third stage D flip-flop DF33 of the first D flip-flop cascade circuit and the signal q1_clk1 output by the positive output terminal of the first stage D flip-flop DF32 are binary 00, the signal output by the two-input nand gate a33 outputs the logic level 1, and then the second preset two-input and gate a32 outputs the logic level 0, so that the positive output terminal of the D flip-flop DF34 in the first switch detection logic circuit still outputs the logic level 0.

As can be seen from fig. 1, after the selection signal set to the logic level 0 is input to the first stage D flip-flop DF11 of the first clock domain circuit through the and gate A1, the binary values formed by se1[3] and se1[2] are changed to be binary 00 after passing through four clock cycles of the first clock signal CLK1, the first preset two-input and gate a31 outputs the logic level 0, at this time, the non-inverting output terminal of the D flip-flop DF34 still outputs the logic level 0 (output in the third clock cycle of the first clock signal CLK 1), then the two-input OR gate OR3 outputs the logic level 0, and then the and operation of the second preset two-input and gate a32 outputs the logic level 0, so that the non-inverting output terminal of the D flip-flop DF34 in the first switch detection logic circuit still outputs the logic level 0. Thus, the non-inverting output of the D flip-flop in the first switch detect logic circuit remains at output logic level 0 during the transition of the binary values of se1[3] and se1[2] from binary 10 to binary 00.

It should be noted that, after the binary value formed by the signal output by the positive output end of the last stage D flip-flop of the first D flip-flop cascade circuit and the signal output by the positive output end of the last stage D flip-flop of the first D flip-flop cascade circuit changes to binary 10, the binary value formed by the signal output by the positive output end of the last stage D flip-flop of the first clock domain circuit and the signal output by the positive output end of the last stage D flip-flop of the first clock domain circuit changes to binary 10 after at least one clock cycle of the first clock signal.

On the basis of the above-described embodiments, as can be seen from fig. 1, in the case where the selection signal is inverted from logic level 1 to logic level 0, when the binary value composed of the signal output from the non-inverting output terminal of the first-to-last stage D flip-flop of the second D flip-flop cascade circuit and the signal output from the non-inverting output terminal of the second-to-last stage D flip-flop of the second D flip-flop cascade circuit changes from binary 00 to binary 01, the signal output from the second input nand gate a43 in the second switch detection logic circuit is inverted from logic level 0 to logic level 1 corresponding to the case where the binary value represented as the signal q2_clk2 and the signal q1_clk2 in fig. 1 changes from binary 00 to binary 01, and the signal output from the second input nand gate a43 remains at logic level 1 until the second D flip-flop cascade circuit counts up to the maximum count value after being inverted from logic level 0 to logic level 1 for the first time. Specifically, when the binary value formed by the signal output by the positive output terminal of the last stage D flip-flop of the second D flip-flop cascade circuit and the signal output by the positive output terminal of the last stage D flip-flop of the second D flip-flop cascade circuit changes from binary 01 to binary 11, corresponding to fig. 1, when the selection signal set to logic level 0 is inverted through the inverter N2 and input to the first stage D flip-flop of the second D flip-flop cascade circuit, the binary value changes to binary 11 after three clock cycles of the second clock signal CLK2, that is, binary 01 formed by the signal q2_clk2 and the signal q1_clk2 changes to binary 11 after one clock cycle of the second clock signal CLK2, and the binary input nand gate a43 in the second switch detection logic circuit outputs logic level 1. Then, at the fourth clock period of the second clock signal CLK2, the signal q2_clk2 output from the non-inverting output terminal of the third stage D flip-flop DF43 of the second D flip-flop cascade circuit and the signal q1_clk2 output from the non-inverting output terminal of the second stage D flip-flop DF42 are binary 11, and the signal output from the two-input nand gate a43 in the second switch detection logic circuit is logic level 1.

It should be noted that, before the second clock period of the second clock signal CLK2, the binary value formed by the signal q2_clk2 and the signal q1_clk2 remains at a binary 00, the signal se2[3] output by the positive output terminal of the last stage D flip-flop of the second clock domain circuit and the signal se2[2] output by the positive output terminal of the last stage D flip-flop of the second clock domain circuit also remain at a binary 00, and are input to the second switch detection logic circuit, since the reset level of the positive output terminal of the D flip-flop in the second switch detection logic circuit is at a logic level 0, the signal sel2_sig_clk2 output by the positive output terminal of the D flip-flop in the second switch detection logic circuit remains at a logic level 0, that is, before the binary value formed by the signal q2_clk2 and the signal q1_clk2 changes from a binary 00 to a binary 01.

It should be noted that, after the binary value formed by the signal output by the positive output end of the last stage D flip-flop of the second D flip-flop cascade circuit and the signal output by the positive output end of the last stage D flip-flop of the second D flip-flop cascade circuit changes to binary 01, the binary value formed by the signal output by the positive output end of the last stage D flip-flop of the second clock domain circuit and the signal output by the positive output end of the last stage D flip-flop of the second clock domain circuit changes to binary 01 after at least one clock cycle of the second clock signal.

When the selection signal is changed from a logic level 1 to a logic level 0, a binary value formed by a signal output by a positive output end of a last-last stage D flip-flop of the second clock domain circuit and a signal output by a positive output end of a last-last stage D flip-flop of the second clock domain circuit is changed from a binary 00 to a binary 01, an output signal of the positive output end of the D flip-flop in the second switching detection logic circuit is changed from a logic level 0 to a logic level 1, and when the binary value corresponding to the fact that the binary value formed by se2[3] and se2[2] in fig. 1 is changed from the binary 00 to the binary 01, the input end of the D flip-flop in the second switching detection logic circuit is input with the logic level 1, and is latched for one clock cycle through the D flip-flop in the second switching detection logic circuit, so that a switching instruction signal output by the output end of the second OR gate is the logic level 1, and the first clock signal is completely switched to the second clock signal is determined.

Specifically, as can be seen from fig. 1, in the process of changing se2[3] and se2[2] from binary 00 to binary 01, the binary values of the signals se2[3] and se2[2] are inverted by the selection signal set to logic level 0 and are kept at binary 00 before reaching the third clock cycle of the second clock signal CLK2 after the selection signal is input to the first stage D flip-flop DF21 of the second clock domain circuit through the and gate A2, so that the first preset two-input and gate a41 keeps outputting logic level 0, while the binary values of the signals q2_clk2 and q1_clk2 are changed to binary 01 through binary 00 before reaching the third clock cycle of the second clock signal CLK2, so that the signal output from the two-input nand gate a43 keeps logic level 1, and the reset level of the positive phase output DF of the D flip-flop 44 in the second switch detection logic circuit is kept at logic level 0, so that the output of the positive phase OR4 keeps outputting logic level 0 before reaching the third clock cycle of the second clock signal CLK2 and the output of the second stage D flip-flop DF4 keeps outputting logic level 0.

When reaching the third clock cycle of the second clock signal CLK2, the binary value of the signal q2_clk2 and the signal q1_clk2 changes to binary 11, the binary value of the signal q2 [3] and the signal se2[2] changes to binary 01, when reaching the third clock cycle of the second clock signal CLK2, the first preset two-input and gate a41 outputs a logic level 1, the two-input and gate a43 outputs a logic level 1, at this time, since the positive phase output terminal of the D flip-flop in the second switching detection logic circuit is a logic level 0 (generated during the second clock cycle of the second clock signal CLK 2), the two-input OR gate OR4 outputs a logic level 1, and at the same time, the signal q2_clk2 output by the positive phase output terminal of the third stage D flip-flop DF43 of the second D flip-flop cascade circuit and the signal q1_clk2 output by the positive phase output terminal of the second stage D flip-flop DF42 are binary 11, and the signal output by the two-input and gate a43 outputs a logic level 1; then, the second preset two-input and gate a42 outputs a logic level 1, so that the non-inverting output terminal of the D flip-flop DF44 in the second switching detection logic circuit is turned from a logic level 0 to a logic level 1, and the second OR gate OR2 outputs a logic level 1, so as to determine that the first clock signal CLK1 is completely switched to the second clock signal CLK2.

The above embodiments are merely for fully disclosing the present application, but not limiting the present application, and should be considered as the scope of the present disclosure based on the substitution of equivalent technical features of the inventive subject matter without creative work.

Claims

1. A clock switching circuit integrating the switching detection logic, the clock switching circuit including a first clock domain circuit and a second clock domain circuit; the clock switching circuit is characterized by further comprising a first D trigger cascade circuit, a second D trigger cascade circuit, a first switching detection logic circuit, a second switching detection logic circuit and a second OR gate;

The output end of the first clock domain circuit and the output end of the first D trigger cascade circuit are respectively connected with the input end of the first switching detection logic circuit; the output end of the first switching detection logic circuit is used for indicating the target switching clock signal to be switched from the second clock signal to the first clock signal;

The output end of the second clock domain circuit and the output end of the second D trigger cascade circuit are respectively connected with the input end of the second switching detection logic circuit; the output end of the second switching detection logic circuit is used for indicating the switching of the target switching clock signal from the first clock signal to the second clock signal;

the output end of the first switching detection logic circuit and the output end of the second switching detection logic circuit are respectively connected with two input ends of a second OR gate, and the output end of the second OR gate is used for indicating that clock signal switching is completed;

the first switching detection logic circuit and the second switching detection logic circuit comprise a D trigger and a multi-input combination logic circuit;

the first clock domain circuit and the second clock domain circuit comprise an AND gate and at least four D flip-flops connected in cascade;

the clock end of the D trigger in the first switching detection logic circuit is used for inputting a first clock signal; the clock end of the D trigger in the second switching detection logic circuit is used for inputting a second clock signal;

The input end of the first-stage D trigger in the first D trigger cascade circuit is used for inputting a selection signal, and the input end of the first-stage D trigger in the second D trigger cascade circuit is used for inputting an inversion signal of the selection signal;

The positive output end of the penultimate D trigger in the first clock domain circuit, the positive output end of the penultimate D trigger in the first D trigger cascade circuit and the negative output end of the penultimate D trigger in the first D trigger cascade circuit are respectively connected with the input end of the multi-input combination logic circuit in the first switching detection logic circuit; the output end of the multi-input combination logic circuit in the first switching detection logic circuit is connected with the input end of the D trigger in the first switching detection logic circuit; the non-inverting output end of the D trigger in the first switching detection logic circuit is an output end used for indicating that the target switching clock signal is switched from the second clock signal to the first clock signal in the first switching detection logic circuit;

the positive output end of the last-second-stage D trigger in the second clock domain circuit, the positive output end of the last-first-stage D trigger in the second D trigger cascade circuit and the negative output end of the last-second-stage D trigger in the second D trigger cascade circuit are respectively connected with the input end of the multi-input combination logic circuit in the second switching detection logic circuit; the output end of the multi-input combination logic circuit in the second switching detection logic circuit is connected with the input end of the D trigger in the second switching detection logic circuit; the positive phase output end of the D trigger in the second switching detection logic circuit is an output end used for indicating that the target switching clock signal is switched from the first clock signal to the second clock signal in the second switching detection logic circuit;

the positive phase output end of the D trigger in the first switching detection logic circuit and the positive phase output end of the D trigger in the second switching detection logic circuit are respectively connected with two input ends of a second OR gate, and the output end of the second OR gate is a port used for indicating that clock signal switching is completed in the clock switching circuit;

The multi-input combination logic circuit comprises a first preset two-input AND gate, a second preset two-input AND gate, a two-input NAND gate and a two-input OR gate, wherein the positive phase output end of the D trigger is connected with one input end of the two-input OR gate, the other input end of the two-input OR gate is connected with the output end of the first preset two-input AND gate, the output end of the two-input OR gate and the output end of the two-input NAND gate are respectively connected with the two input ends of the second preset two-input AND gate, and the output end of the second preset two-input AND gate is connected with the input end of the D trigger to form a latch loop;

Two input ends of a two-input NAND gate in the first switching detection logic circuit are respectively connected with a non-inverting output end of a penultimate stage D trigger in the first D trigger cascade circuit and an inverting output end of a penultimate stage D trigger in the first D trigger cascade circuit; two input ends of a two-input NAND gate in the second switching detection logic circuit are respectively connected with a non-inverting output end of a penultimate stage D trigger in the second D trigger cascade circuit and an inverting output end of a penultimate stage D trigger in the second D trigger cascade circuit;

The first preset two-input AND gate is provided with a forward input end and a reverse input end; the positive input end of a first preset two-input AND gate in the first switching detection logic circuit is connected with the positive output end of a penultimate stage D trigger in the first clock domain circuit, and the negative input end of the first preset two-input AND gate in the first switching detection logic circuit is connected with the positive output end of the penultimate stage D trigger in the first clock domain circuit; the second preset two-input AND gate is provided with a forward input end and a reverse input end; the positive input end of a second preset two-input AND gate in the second switching detection logic circuit is connected with the positive output end of the penultimate D trigger in the second clock domain circuit, the reverse input end of the second preset two-input AND gate in the second switching detection logic circuit is connected with the positive output end of the penultimate D trigger in the second clock domain circuit, and after the level of the selection signal is turned over, the jump condition between the positive output signals of the positive output ends of the last two-stage D trigger is detected through the first preset two-input AND gate, so that the starting point or the ending point of the clock stop time is determined.

2. A chip comprising the clock switching circuit of claim 1.

3. A switching detection method based on the clock switching circuit of claim 1, characterized in that the switching detection method comprises:

When the output end of the second or gate outputs the first level under the condition that the selection signal is turned from the second level to the first level, the output end of the D flip-flop in the first switching detection logic circuit is set to the first level, and it is determined that the target switching clock signal output by the output end of the first or gate is switched from the second clock signal to the first clock signal;

When the selection signal is turned from the first level to the second level and the output end of the second or gate outputs the first level, the output end of the D flip-flop in the second switching detection logic circuit is set to the first level, and it is determined that the target switching clock signal output by the output end of the first or gate is switched from the first clock signal to the second clock signal;

4. The switching detection method according to claim 3, wherein when the first clock signal is turned off, the selection signal is turned to a second level, and the output end of the first or gate outputs the second clock signal, the positive phase output end of the D flip-flop in the second switching detection logic circuit outputs the first level, the second clock signal drives each stage of the D flip-flop in the second clock domain circuit and the D flip-flop in the second switching detection logic circuit to operate respectively, when the selection signal is turned from the second level to the first level, the first clock signal is enabled, the positive phase output end of the D flip-flop in the second switching detection logic circuit is cleared through the second D flip-flop cascade circuit, the phase of switching the target switching clock signal from the second clock signal to the first clock signal starts, after the output end of the first or gate outputs the first clock signal and the positive phase output end of the D flip-flop in the first switching detection logic circuit is the first level, the switching instruction signal output by the output end of the second or gate is the first level, and the second clock signal is determined to be completely switched to the second clock signal, and the second clock signal is turned off;

or when the second clock signal is turned off, the selection signal is turned to a first level, and the output end of the first or gate outputs the first clock signal, the positive phase output end of the D flip-flop in the first switching detection logic circuit outputs the first level, the first clock signal respectively drives all stages of the D flip-flops in the first clock domain circuit and the D flip-flop in the first switching detection logic circuit to work, when the selection signal is turned from the first level to the second level, the second clock signal is started, the positive phase output end of the D flip-flop in the first switching detection logic circuit is cleared through the first D flip-flop cascade circuit, the stage of switching the target switching clock signal from the first clock signal to the second clock signal is started, after the output end of the first or gate outputs the second clock signal and the positive phase output end of the D flip-flop in the second switching detection logic circuit is the first level, the switching indication signal output by the output end of the second or gate is the first level, the first clock signal is determined to be completely switched to the second clock signal, and the first clock signal is closed;

The target switching clock signal is switched from the second clock signal to the first clock signal or the target switching clock signal is switched from the first clock signal to the second clock signal, a locked state exists between the first clock signal and the second clock signal, and the output end of the first or gate does not output the first clock signal or the second clock signal in the locked state;

wherein the first level is a logic level 1 and the second level is a logic level 0.

5. The switching detection method according to claim 4, wherein, in the case where the initial level of the selection signal is the second level and the reset levels of all the D flip-flops whose clock terminals input the second clock signal are the first level, after the selection signal is inverted from the second level to the first level, if the second clock signal is used for sampling, the second clock domain circuit and the second D flip-flop cascade circuit each count down from their maximum count values, wherein the maximum count value of the second clock domain circuit is a binary value composed of the reset levels of the positive phase outputs of all the D flip-flops inside thereof, and the maximum count value of the second D flip-flop cascade circuit is a binary value composed of the reset levels of the positive phase outputs of all the D flip-flops inside thereof;

When the initial level of the selection signal is the second level and the reset levels of the non-inverting output terminals of all the D flip-flops of which the clock terminals are input with the first clock signal are the second level, after the selection signal is turned over from the second level to the first level, if the first clock signal is used for sampling, the first clock domain circuit and the first D flip-flop cascade circuit are both counted up from the minimum count value, wherein the minimum count value of the first clock domain circuit is a binary value formed by the reset levels of the non-inverting output terminals of all the D flip-flops in the first clock domain circuit, and the minimum count value of the first D flip-flop cascade circuit is a binary value formed by the reset levels of the non-inverting output terminals of all the D flip-flops in the first clock domain circuit.

6. The switching detection method according to claim 5, wherein when a binary value formed by a signal output from a positive output terminal of a next-to-last stage D flip-flop of the second D flip-flop cascade circuit and a signal output from a positive output terminal of a next-to-last stage D flip-flop of the second D flip-flop cascade circuit changes from binary 11 to binary 10, a signal output from a two-input nand gate in the second switching detection logic circuit is flipped from logic level 1 to logic level 0, so that a signal output from a positive output terminal of a D flip-flop in the second switching detection logic circuit is flipped from logic level 1 to logic level 0; after a binary value formed by a signal output by a positive phase output end of a first-last-stage D trigger of the second D trigger cascade circuit and a signal output by a positive phase output end of a second-last-stage D trigger of the second D trigger cascade circuit is changed from binary 10 to binary 00, a signal output by a two-input NAND gate in the second switching detection logic circuit is turned from logic level 0 to logic level 1;

And in the process that the binary value formed by the signal output by the positive phase output end of the last stage D trigger of the second clock domain circuit and the signal output by the positive phase output end of the last stage D trigger of the second clock domain circuit changes from binary 10 to binary 00, the positive phase output end of the D trigger in the second switching detection logic circuit keeps outputting logic level 0.

7. The switching detection method according to claim 6, wherein in the case where the selection signal is inverted from a logic level 0 to a logic level 1, when a binary value composed of a signal output from a non-inverting output terminal of a last-to-last stage D flip-flop of the first D flip-flop cascade circuit and a signal output from a non-inverting output terminal of a last-to-last stage D flip-flop of the first D flip-flop cascade circuit is changed from a binary 00 to a binary 01, a signal output from a two-input nand gate in the first switching detection logic circuit is inverted from the logic level 0 to the logic level 1.

8. The switching detection method according to claim 7, wherein when the binary value of the signal outputted from the positive output terminal of the last stage D flip-flop of the first clock domain circuit and the signal outputted from the positive output terminal of the last stage D flip-flop of the first clock domain circuit is changed from binary 00 to binary 01 in the case where the selection signal is flipped from logic level 0 to logic level 1, the output signal of the positive output terminal of the D flip-flop in the first switching detection logic circuit is flipped from logic level 0 to logic level 1, the switching instruction signal outputted from the output terminal of the second or gate is made to logic level 1, and it is determined that the second clock signal is completely switched to the first clock signal.

9. The switching detection method according to claim 4, wherein, in the case where the initial level of the selection signal is the first level and the reset levels of the positive phase outputs of all the D flip-flops whose clock terminals input the first clock signal are the first level, after the selection signal is inverted from the first level to the second level, if the first clock signal is used for sampling, the first clock domain circuit and the first D flip-flop cascade circuit each count down from their maximum count values, wherein the maximum count value of the first clock domain circuit is a binary value composed of the reset levels of the positive phase outputs of all the flip-flops therein, and the maximum count value of the first D flip-flop cascade circuit is a binary value composed of the reset levels of the positive phase outputs of all the flip-flops therein;

When the initial level of the selection signal is a first level and the reset levels of the normal phase output ends of all the D flip-flops with the clock ends inputting a second clock signal are a second level, after the selection signal is turned over from the first level to the second level, if the selection signal is sampled by the second clock signal, the second clock domain circuit and the second D flip-flop cascade circuit are both counted up from the minimum count value of the second clock domain circuit, wherein the minimum count value of the second clock domain circuit is a binary value formed by the reset levels of the normal phase output ends of all the flip-flops in the second clock domain circuit, and the minimum count value of the second D flip-flop cascade circuit is a binary value formed by the reset levels of the normal phase output ends of all the flip-flops in the second clock domain circuit;

After the selection signal is turned from the first level to the second level, the selection signal is sampled by using the first clock signal and then sampled by using the second clock signal.

10. The switching detection method according to claim 9, wherein in the case that the selection signal is inverted from a logic level 1 to a logic level 0, when a binary value composed of a signal output from a positive output terminal of a last-to-last stage D flip-flop of the first D flip-flop cascade circuit and a signal output from a positive output terminal of a last-to-last stage D flip-flop of the first D flip-flop cascade circuit changes from a binary 11 to a binary 10, a signal output from a two-input nand gate in the first switching detection logic circuit is inverted from a logic level 1 to a logic level 0, so that a signal output from a positive output terminal of a D flip-flop in the first switching detection logic circuit is inverted from a logic level 1 to a logic level 0; when a binary value formed by a signal output by a positive phase output end of a first-last-stage D trigger of the first D trigger cascade circuit and a signal output by a positive phase output end of a second-last-stage D trigger of the first D trigger cascade circuit is changed from binary 10 to binary 00, a signal output by a two-input NAND gate in the first switching detection logic circuit is turned from logic level 0 to logic level 1, and the output of the D trigger in the first switching detection logic circuit is determined by a first preset two-input AND gate and a second preset two-input AND gate in the first switching detection logic circuit;

When the selection signal is turned from logic level 1 to logic level 0, the positive phase output end of the D flip-flop in the first switching detection logic circuit keeps outputting logic level 0 in the process that a binary value formed by a signal output by the positive phase output end of the D flip-flop in the last stage of the first clock domain circuit and a signal output by the positive phase output end of the D flip-flop in the last stage of the first clock domain circuit changes from binary 10 to binary 00.

11. The switching detection method according to claim 10, wherein when the binary value of the signal output from the non-inverting output terminal of the last stage D flip-flop of the second D flip-flop cascade circuit and the signal output from the non-inverting output terminal of the last stage D flip-flop of the second D flip-flop cascade circuit is changed from binary 00 to binary 01 in the case that the selection signal is flipped from logic level 1 to logic level 0, the signal output from the two-input nand gate of the second switching detection logic circuit is flipped from logic level 0 to logic level 1; then, when the binary value formed by the signal output by the non-inverting output end of the last stage D flip-flop of the second D flip-flop cascade circuit and the signal output by the non-inverting output end of the last stage D flip-flop of the second D flip-flop cascade circuit changes from binary 01 to binary 11, the signal output by the two-input nand gate in the second switch detection logic circuit is kept at logic level 1.

12. The switching detection method according to claim 11, wherein when the binary value of the signal output from the positive output terminal of the last stage D flip-flop of the second clock domain circuit and the signal output from the positive output terminal of the last stage D flip-flop of the second clock domain circuit is changed from binary 00 to binary 01 in the case that the selection signal is flipped from logic level 1 to logic level 0, the input terminal of the D flip-flop in the second switching detection logic circuit inputs logic level 1, latches the D flip-flop in the second switching detection logic circuit for one clock cycle and outputs the switching instruction signal output from the output terminal of the second or gate to logic level 1, and determines that the first clock signal is completely switched to the second clock signal.