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CN118099102A - Chip package and packaging method thereof - Google Patents

Chip package and packaging method thereof Download PDF

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Publication number
CN118099102A
CN118099102A CN202410192656.1A CN202410192656A CN118099102A CN 118099102 A CN118099102 A CN 118099102A CN 202410192656 A CN202410192656 A CN 202410192656A CN 118099102 A CN118099102 A CN 118099102A
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CN
China
Prior art keywords
chip
bottom plate
metal
groove
plastic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202410192656.1A
Other languages
Chinese (zh)
Inventor
李天海
宋关强
李俞虹
王红昌
赵为
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sky Chip Interconnection Technology Co Ltd
Original Assignee
Sky Chip Interconnection Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sky Chip Interconnection Technology Co Ltd filed Critical Sky Chip Interconnection Technology Co Ltd
Priority to CN202410192656.1A priority Critical patent/CN118099102A/en
Publication of CN118099102A publication Critical patent/CN118099102A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The application discloses a chip package and a packaging method thereof, wherein the chip package comprises: the chip is arranged on one side of the metal bottom plate; the first plastic layer at least wraps one side of the metal bottom plate, on which the chip is mounted; the connecting piece penetrates through the first plastic sealing layer and is connected with the chip so as to lead out signals of the chip. By the mode, when the chip package is applied to a high-power product, the high-voltage and high-current can be born to a certain extent, and the application range of the chip package is further improved.

Description

Chip package and packaging method thereof
Technical Field
The application is applied to the technical field of chip packaging, in particular to a chip packaging body and a packaging method thereof.
Background
The chip package is used for preparing a shell for mounting the semiconductor integrated circuit chip, and plays roles of placing, fixing, sealing, protecting the chip and enhancing the electrothermal performance.
At present, the chip package has certain limitation when dealing with high-power products, and is difficult to bear high voltage and high current.
Disclosure of Invention
The application provides a chip package and a packaging method thereof, which are used for solving the problem that the chip package is difficult to bear high voltage and high current.
In order to solve the above technical problems, the present application provides a chip package, including: the chip is arranged on one side of the metal bottom plate; the first plastic layer at least wraps one side of the metal bottom plate, on which the chip is mounted; the connecting piece penetrates through the first plastic sealing layer and is connected with the chip so as to lead out signals of the chip.
Wherein, the metal bottom plate installs the one side of chip and is formed with the mounting groove, and the bottom welding of mounting groove fixes the chip.
The first plastic sealing layer is provided with a plurality of first blind holes at one side far away from the chip, a first connecting piece is arranged in the first blind holes, one end of the first connecting piece is connected with the chip, and one end far away from the chip extends to one side, far away from the metal bottom plate, of the first plastic sealing layer along the first blind holes so as to lead out signals of the chip; the laminating is provided with the second connecting piece on the lateral wall of chip package body, and metal bottom plate is connected to the one end of second connecting piece, and keeps away from metal bottom plate's one end along the lateral wall and extends to one side that the metal bottom plate was kept away from to first plastic envelope.
Wherein, the chip package further includes: a metal substrate and a second plastic sealing layer; a through groove is formed on the metal substrate, and a chip and a metal bottom plate which are mutually attached are arranged in the through groove; the second plastic layer wraps the two opposite sides of the metal substrate and fills the through groove.
The connecting pieces comprise a third connecting piece, a fourth connecting piece and a fifth connecting piece; a second blind hole is formed in one side, close to the chip, of the second plastic layer, the second blind hole exposes the chip, a third blind hole is formed in one side, close to the metal bottom plate, of the second plastic layer, and the third blind hole exposes the metal bottom plate; one end of the third connecting piece is connected with the chip, and one end far away from the chip extends to one side, close to the chip, of the second plastic layer along the second blind hole; one end of the fourth connecting piece is connected with the metal bottom plate, and one end far away from the chip extends to one side of the second plastic layer far away from the chip along the third blind hole; the fifth connecting piece is attached to the side wall of the metal substrate, and two opposite ends of the fifth connecting piece extend to two opposite sides of the second plastic layer respectively.
In order to solve the above technical problems, the present application provides a method for packaging a chip package, where the method for packaging a chip package is used for preparing any one of the above chip packages, and the method includes: acquiring a metal bottom plate with preset thickness, and mounting a chip on one side of the metal bottom plate; at least plastic packaging is carried out on one side of the metal bottom plate, on which the chip is mounted, so as to form a chip mounting piece; and preparing a connecting piece for leading out chip signals on the chip mounting piece to obtain the chip packaging body.
Wherein, obtain the metal bottom plate of predetermineeing thickness, install the step of one side at metal bottom plate with the chip includes: obtaining a metal bottom plate with preset thickness, and etching one side of the metal bottom plate to form a plurality of mounting grooves and form a first preset groove between every two adjacent mounting grooves; each chip is welded and fixed at the bottom of the corresponding mounting groove correspondingly; at least one side of the metal base plate, on which the chip is mounted, is subjected to plastic packaging, and the step of forming the chip mounting part further comprises the following steps: carrying out plastic packaging on one side of the metal base plate, on which the chip is mounted, until the mounting groove and the first preset groove are filled, so as to form a first plastic packaging layer for packaging the chip; and drilling the metal bottom plate and the first plastic sealing layer based on the position of the first preset groove so as to penetrate through the first preset groove to obtain a plurality of chip mounting pieces.
Wherein, based on the position of the first groove of predetermineeing to metal bottom plate and first plastic envelope bore a hole to run through the first groove of predetermineeing, obtain a plurality of chip mountings's step still includes: drilling one side of the first plastic sealing layer far away from the metal bottom plate to form a first blind hole of the exposed chip; the step of preparing a connector for extracting chip signals on the chip mounting part to obtain a chip package comprises the following steps: electroplating and etching the first blind holes and the first preset grooves of the chip mounting pieces in sequence to form first connecting pieces for connecting the chips in the first blind holes and second connecting pieces for connecting the metal bottom plates on the side walls of the first preset grooves; and cutting the metal bottom plate and the first plastic sealing layer based on the position of the first preset groove to obtain the chip packaging body.
Wherein, the step of preparing a connector for leading out chip signals on the chip mounting member to obtain a chip package comprises: obtaining a metal substrate, and preparing at least one through groove on the metal substrate; installing each chip installation piece in each corresponding through groove; carrying out double-sided plastic packaging on the metal substrate until each through groove is filled, and forming a second plastic packaging layer wrapping the two opposite sides of the metal substrate; and leading out the electric signal of the chip on the second plastic sealing layer to obtain the chip packaging body.
Wherein, the step of leading out the electric signal of the chip on the second plastic sealing layer to obtain the chip package body comprises the following steps: drilling holes on two opposite sides of the second plastic sealing layer respectively to form a second blind hole of the exposed chip and a third blind hole of the exposed metal bottom plate; drilling through holes on the metal substrate to form second preset grooves between every two adjacent chip mounting pieces; electroplating and etching are sequentially carried out on two opposite sides of the second plastic sealing layer, so that a third connecting piece for connecting a chip is formed in the second blind hole, a fourth connecting piece for connecting a metal bottom plate is formed in the third blind hole, and a fifth connecting piece for connecting a metal substrate is formed in a second preset groove; and cutting the metal substrate based on the second preset groove to obtain the chip package.
In order to solve the technical problems, the chip package body of the application mounts the chip on the metal bottom plate, so that when the chip package body is applied to a high-power product, the metal bottom plate can be utilized to bear high voltage and high current to a certain extent, the chip is connected with the metal bottom plate, and the heat dissipation effect of the chip can be improved by utilizing the metal bottom plate.
Drawings
Fig. 1 is a schematic flow chart of a first embodiment of a packaging method of a chip package according to the present application;
fig. 2 is a schematic flow chart of a second embodiment of a packaging method of a chip package according to the present application;
FIG. 3 is a schematic diagram of an embodiment of the preparation process of the example of FIG. 2;
Fig. 4 is a schematic flow chart of a third embodiment of a packaging method of a chip package according to the present application;
FIG. 5 is a schematic diagram of an embodiment of the preparation process of the example of FIG. 4;
FIG. 6 is a schematic diagram of a first embodiment of a chip package according to the present application;
fig. 7 is a schematic structural diagram of a first embodiment of a chip package according to the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to fall within the scope of the present application.
It should be noted that, if directional indications (such as up, down, left, right, front, and rear … …) are included in the embodiments of the present application, the directional indications are merely used to explain the relative positional relationship, movement conditions, etc. between the components in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are correspondingly changed.
In addition, if there is a description of "first", "second", etc. in the embodiments of the present application, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present application.
Referring to fig. 1, fig. 1 is a flowchart illustrating a first embodiment of a packaging method of a chip package according to the present application. The packaging method of the chip package body of the embodiment is used for packaging to obtain the chip package body of any subsequent embodiment.
Step S11: and obtaining a metal bottom plate with a preset thickness, and mounting the chip on one side of the metal bottom plate.
The metal base plate may include, but is not limited to, a base plate made of a metal material such as a copper base plate, a silver base plate, an aluminum base plate, a nickel base plate, or an alloy base plate. The predetermined thickness may be above 1 millimeter including, but not limited to, 1 millimeter, 1.1 millimeter, 1.2 millimeter, 1.5 millimeter, 1.6 millimeter, 2.0 millimeter, 2.5 millimeter, 2.6 millimeter, 3.0 millimeter, 4.0 millimeter, 5.0 millimeter, etc.
The chip is arranged on one side of the metal bottom plate, the metal bottom plate is arranged at the bottom of the chip, so that the chip package body can bear high voltage and high current to a certain extent when being applied to a high-power product, and the chip is connected with the metal bottom plate, and the heat dissipation effect of the chip can be improved by utilizing the metal bottom plate.
Step S12: and at least plastic packaging is carried out on one side of the metal base plate, on which the chip is mounted, so as to form the chip mounting piece.
The material of the plastic package may include, but is not limited to, one or more of epoxy resin, polyester resin (PET), polyimide-based, polycarbonate (PC), bismaleimide triazine (Bismaleimide Triazine, BT), ceramic-based, etc. insulating materials.
In a specific application scenario, the side of the metal base plate on which the chip is mounted can be individually subjected to plastic packaging so as to fix the chip and the metal base plate. In a specific application scenario, the metal bottom plate can be subjected to double-sided plastic packaging so as to match with corresponding plastic packaging requirements.
And after plastic packaging, obtaining the chip mounting piece.
Step S13: and preparing a connecting piece for leading out chip signals on the chip mounting piece to obtain the chip packaging body.
Connectors for extracting chip signals can be prepared on the chip mounting part based on the plastic package condition. In a specific application scenario, when the plastic layer is molded on the side of the metal substrate on which the chip is mounted, a connecting piece for connecting the chip can be prepared on the side plastic layer so as to lead out the chip signal, and the chip package is obtained.
In a specific application scenario, when the metal bottom plate is molded on both sides of the molding layer, a connecting piece for connecting the chip or the metal bottom plate can be respectively prepared on two opposite sides of the molding layer so as to lead out a chip signal, and thus the chip package body is obtained. And is not particularly limited herein.
Through the steps, the packaging method of the chip packaging body of the embodiment is to obtain the metal bottom plate with the preset thickness, and install the chip on one side of the metal bottom plate; at least plastic packaging is carried out on one side of the metal bottom plate, on which the chip is mounted, so as to form a chip mounting piece; the connecting piece for leading out the chip signals is prepared on the chip mounting piece to obtain the chip packaging body, so that the metal bottom plate is arranged at the bottom of the chip, when the chip packaging body is applied to a high-power product, high voltage and high current can be born to a certain extent, the application range of the chip packaging body is further improved, the chip is connected with the metal bottom plate, the metal bottom plate can be used as a heat dissipation channel of the chip, the heat dissipation effect of the chip is further improved, and the service life of the chip packaging body is prolonged.
Referring to fig. 2-3, fig. 2 is a flow chart of a second embodiment of a packaging method of a chip package according to the present application. Fig. 3 is a schematic structural diagram of an embodiment of the preparation flow of the example of fig. 2.
Step S21: a metal bottom plate with a preset thickness is obtained, one side of the metal bottom plate is etched to form a plurality of mounting grooves, and a first preset groove is formed between every two adjacent mounting grooves.
Referring to fig. 3a, a metal base plate 110 of a predetermined thickness is obtained, and one side of the metal base plate 110 is etched to form a plurality of mounting grooves 112 and a first predetermined groove 111 is formed between each adjacent two of the mounting grooves 112. The first preset groove 111 is provided based on the position where the subsequent board is cut, and the first preset groove 111 may be provided at a part or the whole of the cutting position between each adjacent two of the mounting grooves 112.
The metal base 110 may include, but is not limited to, a base made of metal such as a copper base, a silver base, an aluminum base, a nickel base, or an alloy base. The predetermined thickness may be above 1 millimeter including, but not limited to, 1 millimeter, 1.1 millimeter, 1.2 millimeter, 1.5 millimeter, 1.6 millimeter, 2.0 millimeter, 2.5 millimeter, 2.6 millimeter, 3.0 millimeter, 4.0 millimeter, 5.0 millimeter, etc. The metal bottom plate 110 within the thickness range can enable the chip package to bear high voltage and high current to a certain extent, so that the application range of the chip package is improved.
A specific method of etching the mounting groove 112 and the first preset groove 111 may be obtained by the steps of covering the dry film, performing exposure development based on the positions of the mounting groove 112 and the first preset groove 111, and removing the remaining dry film.
In other embodiments, the mounting groove 112 and the first preset groove 111 may be prepared by laser or mechanical depth control, which is not limited herein.
The chip packages of the embodiment can be prepared on a large-sized metal base plate 110 in batches, and finally separated by cutting to obtain independent multiple chip packages, and the position of the first preset groove 111 is the subsequent cutting position.
The mounting groove 112 is used for mounting the fixed chip 120 and generating a height difference on the surface of the metal base plate 110, so that solder paste or conductive adhesive can be prevented from overflowing to the surface of the metal base plate 110 by utilizing the height difference in the subsequent process of mounting the chip 120.
Step S22: and respectively and correspondingly welding and fixing each chip at the bottom of the corresponding mounting groove.
Referring to fig. 3b, each chip 120 is soldered to the bottom of the corresponding mounting groove 112. The chip 120 may be mounted by soldering or fixing with conductive adhesive, so as to fixedly connect the chip 120 and the metal base plate 110.
The present embodiment is described taking an example in which the chip 120 is fixed to the bottom of the mounting groove 112 by soldering with the solder paste 121. Since the mounting grooves 112 for mounting the chips 120 are correspondingly formed in the metal bottom plate 110 in this embodiment, the solder paste 121 is accommodated in the mounting grooves 112, the occurrence of glue overflow during the fixing of the chips 120 is reduced, the occurrence of the situation that the solder paste 121 affects other structures is reduced, and the structural stability of the chip package is improved.
Step S23: and plastic packaging is carried out on one side of the metal base plate, on which the chip is mounted, until the mounting groove and the first preset groove are filled, so that a first plastic sealing layer for wrapping the chip is formed.
Referring to fig. 3c, the side of the metal base plate 110 on which the chip 120 is mounted is encapsulated until the mounting groove 112 and the first preset groove 111 are filled, so as to form a first molding layer 130 that encapsulates the chip 120.
The first molding layer 130 may include, but is not limited to, one or more of epoxy resin, polyester resin (PET), polyimide-based, polycarbonate (PC), bismaleimide triazine (Bismaleimide Triazine, BT), ceramic-based, etc. insulating materials.
In this embodiment, the package description of the chip package is performed by taking a single-sided plastic package as an example, and in other embodiments, the chip package may be prepared by double-sided plastic package.
Step S24: drilling one side of the first plastic sealing layer far away from the metal bottom plate to form a first blind hole of the exposed chip; and drilling the metal bottom plate and the first plastic sealing layer based on the position of the first preset groove so as to penetrate through the first preset groove to obtain a plurality of chip mounting pieces.
Referring to fig. 3d, a side of the first molding layer 130 away from the metal base plate 110 is drilled to form a first blind hole 131 of the bare chip. And the metal base plate 110 and the first plastic layer 130 are drilled based on the position of the first preset groove 111 to penetrate the first preset groove 111. The drilling may be laser drilling or mechanical drilling.
In a specific application scenario, when the whole cutting position is provided with the first preset groove 111, the drilling of the step can realize the cutting function, so as to obtain a plurality of chip mounters 140. In other application scenarios, when the first preset groove 111 is provided in a part of the cutting position, the plurality of chip mountings 140 of this step are not separated from each other, and only the first preset groove 111 penetrating the board is provided. The present embodiment will be described taking the case where the first preset groove 111 is partially provided at the cutting position as an example.
Step S25: and sequentially electroplating and etching the first blind holes and the first preset grooves of each chip mounting piece to form first connecting pieces for connecting chips in the first blind holes and second connecting pieces for connecting the metal bottom plates on the side walls of the first preset grooves, and cutting the metal bottom plates and the first plastic sealing layers based on the positions of the first preset grooves so as to obtain chip packaging bodies.
Referring to fig. 3e, the first blind holes 131 and the first pre-grooves 111 of each chip mounting member 140 are sequentially etched by electroplating to form first connecting members 132 for connecting the chips 120 in the first blind holes 131 and second connecting members 133 for connecting the metal bottom plate 110 on the sidewalls of the first pre-grooves 111.
Specifically, the entire plate is first electroplated, such that the electroplated layer fills the first blind holes 131 and extends onto a side surface of the molding layer 130 away from the metal base plate 110, and such that the electroplated layer extends along the sidewalls of the first preset groove 111 onto the metal base plate 110 and a side surface of the molding layer 130 away from the metal base plate 110, respectively. After the plating is completed, the plating layer is etched based on the connection requirements to form the first connection member 132 and the second connection member 133. One end of the first connecting piece 132 is connected with the chip 120, and the other end extends to one side surface of the plastic layer 130 away from the metal base plate 110; one end of the second connection member 133 is connected to the metal base plate 110, and the other end extends to a side surface of the plastic layer 130 adjacent to the metal base plate 110. That is, the chip 120, the metal bottom plate 110 and the second connecting piece 133 are sequentially connected, and the G/S electrode of the chip 120 can be led out by using the second connecting piece 133 arranged on the side wall of the chip mounting piece 140 in a side wall half-hole mode, so that a smaller occupied area is realized, and the packaging size of the product can be reduced to a certain extent. And the second connecting piece 133 arranged on the side wall of the chip mounting piece 140 can further increase the welding surface, so that the welding reliability is effectively improved, and the product yield is improved.
Finally, the metal base plate 110 and the first molding layer 130 are cut based on the position of the first preset groove 111, thereby separating the chip mounts 140 to obtain a chip package.
Through the steps, the metal bottom plate is arranged at the bottom of the chip, so that the chip package can bear high voltage and high current to a certain extent when being applied to high-power products, the application range of the chip package is further improved, the chip is connected with the metal bottom plate, the metal bottom plate can be used as a heat dissipation channel of the chip, the heat dissipation effect of the chip is further improved, and the service life of the chip package is prolonged. In addition, the G/S electrode of the chip can be led out in a side wall half-hole mode by using the second connecting piece arranged on the side wall of the chip mounting piece, so that smaller occupied area is realized, and the packaging size of the product can be reduced to a certain extent. And the second connecting piece arranged on the side wall of the chip mounting piece can further increase the welding surface, so that the welding reliability is effectively improved, and the product yield is improved. And when the chip is fixed, the solder paste is contained through the mounting groove, so that the occurrence of glue overflow during chip fixation can be reduced, the occurrence of the condition that the solder paste affects other structures is reduced, and the structural stability of the chip packaging body is improved.
Referring to fig. 4-5, fig. 4 is a flowchart illustrating a third embodiment of a packaging method of a chip package according to the present application. Fig. 5 is a schematic structural diagram of an embodiment of the preparation flow of the example of fig. 4.
Step S31: a metal bottom plate with a preset thickness is obtained, one side of the metal bottom plate is etched to form a plurality of mounting grooves, and a first preset groove is formed between every two adjacent mounting grooves.
Step S32: and respectively and correspondingly welding and fixing each chip at the bottom of the corresponding mounting groove.
Step S33: and plastic packaging is carried out on one side of the metal base plate, on which the chip is mounted, until the mounting groove and the first preset groove are filled, so that a first plastic sealing layer for wrapping the chip is formed.
The steps S31-S33 in this step are the same as the steps S21-S23 in the previous embodiment, refer to the above and 3a-3c in FIG. 3, and are not described here again.
Step S34: and drilling the metal bottom plate and the first plastic sealing layer based on the position of the first preset groove so as to penetrate through the first preset groove to obtain a plurality of chip mounting pieces.
Referring to fig. 5a, a mounting groove 212 and a first preset groove 211 are formed on one side of the metal base plate 210, the chip 220 is soldered at the bottom of the mounting groove 212, and the first plastic layer 230 plastic seals one side of the metal base plate 210 with the chip 220 to fill the mounting groove 212 and the first preset groove 211 and encapsulate the chip 220.
Referring to fig. 5b, the metal base plate 210 and the first molding layer 230 are drilled based on the positions of the first preset grooves 211 to penetrate the first preset grooves 211 to obtain a plurality of chip mountings 240. The drilling of the present embodiment is cutting, and a plurality of independent chip mountings 240 are obtained based on the first preset groove 211.
Step S35: obtaining a metal substrate, and preparing at least one through groove on the metal substrate; and installing each chip installation piece in each corresponding through groove.
Referring to fig. 5c, a metal substrate 250 is obtained, and at least one through groove 251 is formed on the metal substrate 250; each chip mount 240 is mounted in a corresponding one of the through grooves 251. The preparation of the through groove 251 may be performed by mechanical drilling, laser drilling, etching, or the like.
In a specific application scenario, a temporary carrier may be attached to one side of the metal substrate 250, and the chip mounting member 240 may be mounted in each corresponding through slot 251 until the chip mounting member 240 contacts the temporary carrier, so as to implement mounting of the chip mounting member 240 in each corresponding through slot 251.
Step S36: and carrying out double-sided plastic packaging on the metal substrate until each through groove is filled, so as to form a second plastic packaging layer wrapping the two opposite sides of the metal substrate.
Referring to fig. 5d, the metal substrate 250 is double-sided molded until the through grooves 251 are filled, so as to form second molding layers 260 wrapping opposite sides of the metal substrate 250.
In a specific application scenario, after the chip mounting member 240 is mounted in each corresponding through groove 251 through the temporary carrier, the side, away from the temporary carrier, of the metal substrate 250 may be first subjected to plastic packaging to fix the chip mounting member 240, then the side, exposed to the metal substrate 250, of the temporary carrier is removed, and then the side, exposed to the metal substrate 250, is subjected to plastic packaging, so that the plastic packaging of the two opposite sides of the metal substrate 250 is realized.
The material of the second plastic layer 260 includes, but is not limited to, one or more of epoxy resin, polyester resin (PET), polyimide, polycarbonate (PC), bismaleimide triazine (Bismaleimide Triazine, BT), ceramic matrix, etc. insulating materials.
Step S37: and leading out the electric signal of the chip on the second plastic sealing layer to obtain the chip packaging body.
Referring to fig. 5e, the opposite sides of the second molding layer 260 are drilled to form a second blind hole 261 of the bare chip 220 and a third blind hole 262 of the bare metal base plate 210; the metal substrate 250 is drilled with a through hole to form a second pre-groove 263 between each adjacent chip mount 240. The second pre-groove 263 may be partially or entirely provided at a cutting position between each adjacent chip mounting member 240, which is not limited herein. Drilling can be performed by laser drilling, etching or the like. The second preset groove 263 can reduce the difficulty of subsequent cutting and improve the cutting efficiency.
Referring to fig. 5f, the opposite sides of the second molding layer 260 are sequentially subjected to a plating etching process to form a third connecting member 271 for connecting the chip 220 in the second blind hole 261, a fourth connecting member 272 for connecting the metal base plate 210 in the third blind hole 262, and a fifth connecting member 273 for connecting the metal base plate 250 in the second pre-groove 263.
Specifically, the entire plate is first electroplated, so that the electroplated layer fills the second blind holes 261 and the third blind holes 262 and correspondingly extends onto the surface of the second molding layer 260, and the electroplated layer extends onto the surfaces of the opposite sides of the second molding layer 260 along the sidewalls of the second preset groove 263. After the plating is completed, the plating layer is etched based on the connection requirements, forming third connection member 271, fourth connection member 272, and fifth connection member 273. One end of the third connecting piece 271 is connected with the chip 220, and the other end extends to one side surface of the second plastic layer 260 away from the metal base plate 210; one end of the fourth connection member 272 is connected to the metal base plate 210, and the other end extends to a side surface of the second molding layer 260 adjacent to the metal base plate 210. The fifth connecting member 273 is disposed on the sidewall of the second preset groove 263, and has one end extending to a side surface of the second plastic layer 260 near the metal base plate 210, and the other end extending to a side surface of the second plastic layer 260 far from the metal base plate 210, and is connected to the third connecting member 271. The above-mentioned connection member arrangement can utilize the fifth connection member 273 disposed on the sidewall of the second preset groove 263 to lead out the G/S electrode of the chip 220 in a sidewall half-hole manner, thereby realizing a smaller occupied area and reducing the packaging size of the product to a certain extent. And the fifth connecting part 273 can also increase the welding surface, so that the welding reliability is effectively improved, and the product yield is improved.
In a specific application scenario, a rigid plastic package material may be laminated on one side of the metal substrate 250, so as to improve structural rigidity of the integral board, and enhance structural stability of the chip package. And (5) pressing the rigid plastic packaging material and then carrying out surface metallization.
Finally, the metal substrate 250 is cut based on the second preset groove 263, so as to obtain a plurality of independent chip packages.
Through the steps, the metal bottom plate is arranged at the bottom of the chip, so that the chip package can bear high voltage and high current to a certain extent when being applied to high-power products, the application range of the chip package is further improved, the chip is connected with the metal bottom plate, the metal bottom plate can be used as a heat dissipation channel of the chip, the heat dissipation effect of the chip is further improved, and the service life of the chip package is prolonged. In addition, the G/S electrode of the chip can be led out in a side wall half-hole mode by using the fifth connecting piece arranged on the side wall of the chip mounting piece, so that smaller occupied area is realized, and the packaging size of the product can be reduced to a certain extent. And the fifth connecting piece arranged on the side wall of the chip mounting piece can further increase the welding surface, so that the welding reliability is effectively improved, and the product yield is improved. And when the chip is fixed, the solder paste is contained through the mounting groove, so that the occurrence of glue overflow during chip fixation can be reduced, the occurrence of the condition that the solder paste affects other structures is reduced, and the structural stability of the chip packaging body is improved.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a first embodiment of a chip package according to the present application. The chip package of this embodiment may be prepared by the packaging method of the chip package of any of the above embodiments.
The chip package 300 of the present embodiment includes a metal base plate 310, a chip 320, a first molding layer 330 and a connecting member 360, wherein the chip 320 is mounted on one side of the metal base plate 310.
The first molding layer 330 wraps at least one side of the metal base plate 310 on which the chip 320 is mounted, so as to fix the chip 320. The connector 360 is connected to the chip 320 through the first molding layer 330 to draw out signals from the chip 320.
The metal base 310 may include, but is not limited to, a base made of metal such as a copper base, a silver base, an aluminum base, a nickel base, or an alloy base. The predetermined thickness may be above 1 millimeter including, but not limited to, 1 millimeter, 1.1 millimeter, 1.2 millimeter, 1.5 millimeter, 1.6 millimeter, 2.0 millimeter, 2.5 millimeter, 2.6 millimeter, 3.0 millimeter, 4.0 millimeter, 5.0 millimeter, etc.
Through the above structure, when the chip 320 is mounted on the metal base plate 310 in the present embodiment and the chip package 300 is applied to a high-power product, the metal base plate 310 can be utilized to bear high voltage and high current to a certain extent, and the chip 320 is connected with the metal base plate 310, so that the heat dissipation effect of the chip 320 can be improved by utilizing the metal base plate 310.
In some embodiments, a mounting groove 331 is formed on a side of the metal base plate 310 on which the chip 320 is mounted, the chip 320 is welded and fixed to the bottom of the mounting groove 331, and the chip 320 is welded and fixed to the bottom of the mounting groove 331, so that the phenomenon of glue overflow of the chip 320 can be prevented by using a height difference of the mounting groove 331.
In some embodiments, a plurality of first blind holes 321 are formed on a side of the first plastic layer 330 away from the chip 320, a first connecting member 340 is disposed in the first blind holes 321, one end of the first connecting member 340 is connected to the chip 320, and one end of the first connecting member 340 away from the chip 320 extends to a side of the first plastic layer 330 away from the metal base plate 310 along the first blind holes 321 so as to lead out signals of the chip 320; the second connecting piece 350 is attached to the side wall of the chip package 300, one end of the second connecting piece 350 is connected to the metal bottom plate 310, and one end far away from the metal bottom plate 310 extends to one side, far away from the metal bottom plate 310, of the first plastic layer 330 along the side wall.
The chip package 300 of the present embodiment is applicable to the packaging method of the chip package of the first embodiment or the second embodiment described above.
Through the structure, the packaging method of the chip packaging body is characterized in that the metal bottom plate is arranged at the bottom of the chip, so that the chip packaging body can bear high voltage and high current to a certain extent when being applied to high-power products, the application range of the chip packaging body is further improved, the chip is connected with the metal bottom plate, the metal bottom plate can be used as a heat dissipation channel of the chip, the heat dissipation effect of the chip is further improved, and the service life of the chip packaging body is prolonged. In addition, the G/S electrode of the chip can be led out in a side wall half-hole mode by using the second connecting piece arranged on the side wall of the chip mounting piece, so that smaller occupied area is realized, and the packaging size of the product can be reduced to a certain extent. And the second connecting piece arranged on the side wall of the chip mounting piece can further increase the welding surface, so that the welding reliability is effectively improved, and the product yield is improved. And when the chip is fixed, the solder paste is contained through the mounting groove, so that the occurrence of glue overflow during chip fixation can be reduced, the occurrence of the condition that the solder paste affects other structures is reduced, and the structural stability of the chip packaging body is improved.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a first embodiment of a chip package according to the present application. The chip package of the present embodiment may be manufactured by the packaging method of the chip package of the first embodiment or the third embodiment described above.
The chip package 400 of the present embodiment includes a metal base plate 410, a chip 420, a first molding layer 430 and a connector (not labeled in the drawing), and the chip 420 is mounted on one side of the metal base plate 410.
The first molding layer 430 wraps at least one side of the metal base plate 410 on which the chip 420 is mounted, so as to fix the chip 420. The connection member is connected to the chip 420 through the first molding layer 430 to draw out signals of the chip 420.
The metal bottom plate 410 may include, but is not limited to, a bottom plate made of metal such as a copper bottom plate, a silver bottom plate, an aluminum bottom plate, a nickel bottom plate, or an alloy bottom plate. The predetermined thickness may be above 1 millimeter including, but not limited to, 1 millimeter, 1.1 millimeter, 1.2 millimeter, 1.5 millimeter, 1.6 millimeter, 2.0 millimeter, 2.5 millimeter, 2.6 millimeter, 3.0 millimeter, 4.0 millimeter, 5.0 millimeter, etc.
With the above structure, when the chip 420 is mounted on the metal base plate 410 in the present embodiment, the metal base plate 410 can be used to bear high voltage and high current to a certain extent when the chip package 400 is applied to a high-power product, and the chip 420 is connected with the metal base plate 410, so that the heat dissipation effect of the chip 420 can be improved by using the metal base plate 410.
In some embodiments, a mounting groove 431 is formed on one side of the metal base plate 410 on which the chip 420 is mounted, the chip 420 is welded and fixed to the bottom of the mounting groove 431, and the chip 420 is welded and fixed to the bottom of the mounting groove 431, so that the phenomenon of glue overflow of the chip 420 can be prevented by using the height difference of the mounting groove 431.
In some embodiments, the chip package 400 further includes: a metal substrate 450 and a second molding layer 470; a through groove 453 is formed in the metal substrate 450, and the chip 420 and the metal base plate 410 which are mutually adhered are mounted in the through groove 453; the second molding layer 470 wraps the opposite sides of the metal substrate 450 and fills the through groove 453.
In some embodiments, the connectors include a third connector 461, a fourth connector 462, and a fifth connector 463.
A second blind hole 451 is formed on one side of the second plastic layer 470 near the chip 420, the second blind hole 451 exposes the chip 420, a third blind hole 452 is formed on one side of the second plastic layer 470 near the metal bottom plate 410, and the third blind hole 452 exposes the metal bottom plate 410.
One end of the third connecting member 461 is connected with the chip 420, and one end far away from the chip 420 extends to one side of the second plastic layer 470 near the chip 420 along the second blind hole 451; one end of the fourth connecting member 462 is connected to the metal base plate 410, and the end far away from the chip 420 extends along the third blind hole 452 to a side of the second molding layer 470 far away from the chip 420.
The fifth connecting member 463 is adhered to the side wall of the metal substrate 450, and two opposite ends of the fifth connecting member 463 extend to two opposite sides of the second molding layer 470 respectively.
Through the structure, the packaging method of the chip packaging body is characterized in that the metal bottom plate is arranged at the bottom of the chip, so that the chip packaging body can bear high voltage and high current to a certain extent when being applied to high-power products, the application range of the chip packaging body is further improved, the chip is connected with the metal bottom plate, the metal bottom plate can be used as a heat dissipation channel of the chip, the heat dissipation effect of the chip is further improved, and the service life of the chip packaging body is prolonged. In addition, the G/S electrode of the chip can be led out in a side wall half-hole mode by using the fifth connecting piece arranged on the side wall of the chip mounting piece, so that smaller occupied area is realized, and the packaging size of the product can be reduced to a certain extent. And the fifth connecting piece arranged on the side wall of the chip mounting piece can further increase the welding surface, so that the welding reliability is effectively improved, and the product yield is improved. And when the chip is fixed, the solder paste is contained through the mounting groove, so that the occurrence of glue overflow during chip fixation can be reduced, the occurrence of the condition that the solder paste affects other structures is reduced, and the structural stability of the chip packaging body is improved.
The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the application, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present application or directly or indirectly applied to other related technical fields are included in the scope of the present application.

Claims (10)

1. A chip package, the chip package comprising:
A metal base plate;
a chip mounted on one side of the metal base plate;
the first plastic layer at least wraps one side of the metal base plate, on which the chip is mounted;
And the connecting piece penetrates through the first plastic sealing layer and is connected with the chip so as to lead out signals of the chip.
2. The chip package according to claim 1, wherein a mounting groove is formed in a side of the metal base plate on which the chip is mounted, and a bottom of the mounting groove is solder-fixed to the chip.
3. The chip package according to claim 1 or 2, wherein a plurality of first blind holes are formed in a side of the first plastic layer away from the chip, a first connecting piece is arranged in the first blind holes, one end of the first connecting piece is connected with the chip, and one end of the first connecting piece away from the chip extends to a side of the first plastic layer away from the metal bottom plate along the first blind holes so as to lead out signals of the chip;
the laminating is provided with the second connecting piece on the lateral wall of chip package body, the one end of second connecting piece is connected metal bottom plate, and keep away from metal bottom plate's one end is followed the lateral wall extends to first plastic envelope is kept away from one side of metal bottom plate.
4. The chip package according to claim 1 or 2, characterized in that the chip package further comprises: a metal substrate and a second plastic sealing layer;
A through groove is formed on the metal substrate, and the chip and the metal bottom plate which are mutually attached are installed in the through groove;
and the second plastic sealing layer wraps the two opposite sides of the metal substrate and fills the through groove.
5. The chip package of claim 4, wherein the connectors comprise a third connector, a fourth connector, and a fifth connector;
a second blind hole is formed in one side, close to the chip, of the second plastic layer, the second blind hole exposes the chip, a third blind hole is formed in one side, close to the metal bottom plate, of the second plastic layer, and the third blind hole exposes the metal bottom plate;
One end of the third connecting piece is connected with the chip, and one end far away from the chip extends to one side, close to the chip, of the second plastic sealing layer along the second blind hole; one end of the fourth connecting piece is connected with the metal bottom plate, and one end far away from the chip extends to one side of the second plastic sealing layer far away from the chip along the third blind hole;
the fifth connecting piece is attached to the side wall of the metal substrate, and two opposite ends of the fifth connecting piece extend to two opposite sides of the second plastic sealing layer respectively.
6. A packaging method of a chip package, wherein the packaging method of the chip package is used for preparing the chip package according to any one of claims 1 to 5, and the packaging method comprises the steps of:
Acquiring a metal bottom plate with preset thickness, and mounting a chip on one side of the metal bottom plate;
At least plastic packaging is carried out on one side of the metal bottom plate, on which the chip is mounted, so as to form a chip mounting piece;
And preparing a connecting piece for leading out the chip signal on the chip mounting piece to obtain a chip package.
7. The method of claim 6, wherein the step of obtaining a metal base plate of a predetermined thickness and mounting the chip on one side of the metal base plate comprises:
A metal bottom plate with preset thickness is obtained, one side of the metal bottom plate is etched to form a plurality of mounting grooves, and a first preset groove is formed between every two adjacent mounting grooves;
Fixing the chips at the bottoms of the corresponding mounting grooves in a corresponding welding mode respectively;
The step of forming the chip mounting part by at least plastic packaging the side of the metal bottom plate on which the chip is mounted further comprises the following steps:
Carrying out plastic packaging on one side of the metal bottom plate, on which the chip is mounted, until the mounting groove and the first preset groove are filled, so as to form a first plastic packaging layer for packaging the chip;
And drilling holes on the metal bottom plate and the first plastic sealing layer based on the position of the first preset groove so as to penetrate through the first preset groove to obtain a plurality of chip mounting pieces.
8. The method of claim 7, wherein the step of drilling the metal base plate and the first molding layer based on the position of the first preset groove to penetrate the first preset groove to obtain the plurality of chip mountings further comprises:
Drilling one side, far away from the metal bottom plate, of the first plastic sealing layer to form a first blind hole exposing the chip;
the step of preparing a connector for leading out the chip signal on the chip mounting part to obtain a chip package body comprises the following steps:
electroplating and etching the first blind holes of the chip mounting pieces and the first preset groove in sequence to form a first connecting piece connected with the chip in the first blind holes and a second connecting piece connected with the metal bottom plate on the side wall of the first preset groove;
And cutting the metal bottom plate and the first plastic sealing layer based on the position of the first preset groove to obtain the chip packaging body.
9. The method of packaging a chip package according to claim 7, wherein the step of preparing a connection member on the chip mount member that leads out the chip signal to obtain the chip package comprises:
obtaining a metal substrate, and preparing at least one through groove on the metal substrate;
mounting each chip mounting piece in each corresponding through groove;
carrying out double-sided plastic packaging on the metal substrate until each through groove is filled, and forming a second plastic packaging layer wrapping the two opposite sides of the metal substrate;
and leading out the electric signal of the chip on the second plastic sealing layer to obtain the chip packaging body.
10. The method of packaging a chip package according to claim 9, wherein the step of extracting the electrical signal of the chip on the second molding layer to obtain the chip package comprises:
Drilling holes on two opposite sides of the second plastic sealing layer respectively to form a second blind hole exposing the chip and a third blind hole exposing the metal bottom plate;
drilling through holes on the metal substrate to form second preset grooves between every two adjacent chip mounting pieces;
electroplating and etching are sequentially carried out on two opposite sides of the second plastic sealing layer, so that a third connecting piece connected with the chip is formed in the second blind hole, a fourth connecting piece connected with the metal bottom plate is formed in the third blind hole, and a fifth connecting piece connected with the metal substrate is formed in the second preset groove;
And cutting the metal substrate based on the second preset groove to obtain the chip package.
CN202410192656.1A 2024-02-21 2024-02-21 Chip package and packaging method thereof Pending CN118099102A (en)

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Application Number Priority Date Filing Date Title
CN202410192656.1A CN118099102A (en) 2024-02-21 2024-02-21 Chip package and packaging method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118315347A (en) * 2024-06-13 2024-07-09 荣耀终端有限公司 Chip packaging structure, electronic device and manufacturing method of chip packaging structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118315347A (en) * 2024-06-13 2024-07-09 荣耀终端有限公司 Chip packaging structure, electronic device and manufacturing method of chip packaging structure

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