CN118075066A

CN118075066A - Error code detection method and related equipment

Info

Publication number: CN118075066A
Application number: CN202211483137.8A
Authority: CN
Inventors: 李苏
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-11-24
Filing date: 2022-11-24
Publication date: 2024-05-24
Also published as: WO2024109014A1

Abstract

The embodiment of the application discloses an error code detection method and related equipment, which are used for reducing the probability of error judgment and reducing the error code rate. The method of the embodiment of the application comprises the following steps: and acquiring a signal set comprising initial EOB error code signals, carrying out reverse error code transmission by taking the initial EOB error code signals as starting points, determining initial SOB error code signals from the signal set, and taking the signals between the initial SOB error code signals and the signals from the initial SOB error code signals to the initial EOB error code signals in the signal set as signals to be detected. And respectively calculating the accumulated error from each signal to be detected to the initial EOB error signal, wherein the accumulated error is determined according to the error from each signal to be detected to any two adjacent signals in the initial EOB signal. And determining whether the target SOB error signal exists or not from the signal to be detected according to the accumulated error.

Description

Error code detection method and related equipment

Technical Field

The present application relates to the field of communications, and in particular, to an error code detection method and related device.

Background

In a high-speed wired serial communication system, as the data rate increases, the signal spectrum is wider and wider, but the bandwidth of a channel is limited, so that a signal received by a receiver is influenced by intersymbol interference (inert-symbol interference, ISI) in addition to noise, and is not beneficial to signal decision and demodulation. How to eliminate the intersymbol interference becomes an urgent problem to be solved.

The burst error signal also leaves a start of burst (SOB) error signal and an end of burst (EOB) error signal based on the use of a decision feedback equalizer (decision feedback equalizer, DFE) +precoding. In the conventional method, in the case of determining the EOB error signal, the SOB error signal is determined according to a decision error of a single symbol.

In the method, the SOB error code signal is determined by taking the decision error of a single symbol as the basis, and the probability of error judgment is high due to the fact that the basis is thin.

Disclosure of Invention

The embodiment of the application provides an error code detection method and related equipment. In the error code detection method, the initial EOB error code signals are subjected to reverse error code transmission, after the initial SOB error code signals are determined, the accumulated error from each signal to be detected to the initial EOB error code signals is calculated respectively, and the signal with the accumulated error meeting the condition is determined as the target SOB error code signal from the signals to be detected. The accumulated error of each signal to be detected is determined according to the error of any two adjacent signals in the initial EOB signal of the signal to be detected, that is, the technical scheme of the application is based on the sequence accumulated error, the determined SOB error code signal enriches the determination basis, reduces the error judgment probability and reduces the error rate.

An embodiment of the present application provides a method for detecting an error code, including:

And acquiring a signal set, wherein the signal set comprises an initial EOB error signal, and the initial SOB error signal can be determined according to the initial EOB error signal. And taking the initial EOB error code signal as a starting point, and carrying out reverse error code transmission to determine an initial SOB error code signal from the signal set, wherein the initial SOB error code signal is a possible SOB error code signal. The signal set comprises a signal to be detected, wherein the signal to be detected comprises an initial SOB error code signal and a signal from the initial SOB error code signal to the initial EOB error code signal. That is, from the initial SOB error signal to the signal before the initial EOB error signal, the signals are all to be measured. And respectively calculating the accumulated error from each signal to be detected to the initial EOB error code signal, wherein the accumulated error is determined according to the error from each signal to be detected to any two adjacent signals in the initial EOB error code signal. For example, the 7 signals with serial numbers of 1 to 7, the 7 signal is an initial EOB error signal, after the transmission of the reverse error, the 2 signal is determined to be an initial SOB error signal, and then the 2 signal to the 6 signal are signals to be tested. The accumulated error from the No. 2 signal to the initial EOB error signal (No. 7 signal) is the sum of the errors of any two adjacent signals from the No. 2 signal to the No. 7 signal; the accumulated error of the No. 3 signal to the No. 7 signal is the sum of the errors of any two adjacent signals from the No. 3 signal to the No. 7 signal. After the accumulated error of each signal to be detected is obtained, determining whether a target SOB error signal exists in the signal to be detected according to the accumulated error of each signal to be detected, wherein the target SOB error signal is a real SOB error signal.

From the above technical solutions, the embodiment of the present application has the following advantages:

and carrying out reverse error code transmission on the initial EOB error code signals, and after the initial SOB error code signals are determined, respectively calculating the accumulated error from each signal to be detected to the initial EOB error code signals, and determining the signal with the accumulated error meeting the condition from the signals to be detected as the target SOB error code signal. The accumulated error of each signal to be detected is determined according to the error of any two adjacent signals in the initial EOB signal of the signal to be detected, that is, the technical scheme of the application is based on the sequence accumulated error, and the determined SOB error code signal enriches the determination basis, reduces the probability of error judgment and can reduce the error rate. Meanwhile, the method can also detect the error codes of various channels, is not limited to 1+D channels, has good effects on other channels, and improves generalization of the technical scheme of the application.

In a possible implementation manner of the first aspect, if there is a target signal to be measured with a minimum accumulated error and less than the accumulated error threshold value in the signal to be measured, the target signal to be measured may be determined to be a target SOB error signal. The accumulated error threshold is the error corresponding to the initial EOB error signal.

In the embodiment of the application, the target SOB error code signal is determined from the signal to be detected by comparing the accumulated error of the signal to be detected with the error threshold value, thereby providing an implementation basis for the technical scheme of the application and further improving the practicability and the realizability of the scheme.

In a possible implementation manner of the first aspect, the accumulated error includes a reverse compensation error and a decision error. Error code transmission can occur in the signal set, and error code signals can be compensated in the process of reverse error code transmission by taking the initial EOB error code signals as starting points so as to compensate errors. That is, the reverse compensation error is used to compensate the error signal. In addition, the decision error indicates the error before and after the signal decision.

In the embodiment of the application, the accumulated errors comprise reverse compensation errors and decision errors, so that errors generated in the signal processing process can be compensated and corrected, the calculation result of the accumulated errors is more accurate, and the accuracy of error code detection is further improved.

In a possible implementation manner of the first aspect, the specific process of determining the initial SOB error signal from the signal set includes: and (3) carrying out reverse error code transmission by taking the initial EOB error code signal as a starting point, and when an abnormal level value occurs, considering the next signal of the signal corresponding to the abnormal level value as the initial SOB error code signal. The abnormal level value is a level value (or a level value greater or less than a level extremum) which does not occur during normal signal transmission. Illustratively, taking a 4-level pulse amplitude modulation (pulse amplitude modulation, pam-4) as an example, there are 4 possible level values per symbol, e.g., { -3, -1, 3}, then the level extremum is ± 3. In this case, a level value greater than +3 or less than-3 is an abnormal level value. The reverse error code transmission is carried out on the PAM-4 signal, specifically, the cyclic operation of +2, -2 or-2 and +2 is carried out on the original decision result level by taking a certain signal as a starting point. Assuming that the signal No. 5 is an initial EOB error signal, the signal No. 5 is used as a starting point to perform reverse error transmission, and an abnormal level value-5 appears when the signal No. 1 is transmitted, so that the next signal of the signal No. 1 (i.e. the signal No. 2) can be determined to be the initial SOB error signal.

In the embodiment of the application, the initial SOB error code signal is determined by the abnormal level value in the reverse error code transmission process, so that the rule of signal transmission is met, technical support is provided for realizing the technical scheme of the application, and the feasibility of the scheme is further improved.

In a possible implementation manner of the first aspect, the first equalization result and the second equalization result may also be obtained. The first equalization result is obtained by equalizing a plurality of continuous signals in the signal set based on a first equalization mode, and the second equalization result is obtained by equalizing the plurality of continuous signals based on a second equalization mode, wherein the plurality of continuous signals comprise target signals. If the first equalization result is different from the second equalization result, then the target signal may be determined to be an initial EOB error signal.

In the embodiment of the application, the possible error code signals are determined as the initial EOB error code signals from the signal set by combining the equalization results of different equalization modes on the continuous multiple signals, so that the EOB error code signals can be screened as much as possible. Meanwhile, the continuous multiple signals are balanced, and compared with a mode of judging only a single signal, the balanced result is more accurate.

In a possible implementation manner of the first aspect, the continuous plurality of signals includes a target signal and a previous signal of the target signal; or the target signal and the latter signal of the target signal.

In the embodiment of the application, a plurality of continuous signals which are balanced by using different equalization modes are possible, the realization mode and the application scene of the technical scheme of the application are enriched, different requirements can be met, and the flexibility of the technical scheme is improved.

In a possible implementation manner of the first aspect, the initial EOB error signal may also be determined by other manners. The decision result and decision error of the target signal in the signal set can be obtained. If the decision result is the extremum corresponding to the signal set and the absolute value of the decision error is greater than the error threshold, then the target signal may be determined to be the initial EOB error signal.

In the embodiment of the application, whether the signal is the initial EOB error code signal can be determined by the judgment result and the judgment error of the single signal, the process is simple, and the implementation is easy. In addition, the initial EOB error code signals are determined in a plurality of modes, so that the implementation modes of the technical scheme of the application are further enriched, and the flexibility of the technical scheme is improved.

In a possible implementation manner of the first aspect, a decision error of the target signal in the signal set and the first decision result may be acquired. If the decision error is greater than or equal to the first threshold, confirming that the target signal is an initial EOB error signal; if the decision error is less than or equal to the second threshold, confirming that the target signal is not the initial EOB error signal; if the decision error is greater than the second threshold and less than the first threshold, a second stage decision is made to confirm whether the target signal is the initial error signal. And determining a second judgment result of the target signal according to the input signal corresponding to the next signal of the target signal and the equalization result. And acquiring a third judgment result and a fourth judgment result of a signal before the target signal, wherein the third judgment result and the first judgment result are based on the same judgment mode, and the second judgment result and the fourth judgment result are based on the same judgment mode. Under the condition that the judgment error is larger than the second threshold value and smaller than the first threshold value, if the first judgment result is the same as the second judgment result and the third judgment result is different from the fourth judgment result, confirming that the target signal is an initial EOB error signal; otherwise, the target signal is confirmed to be a non-initial EOB error signal.

In a possible implementation manner of the first aspect, if the target SOB error signal exists in the signal to be measured, the initial EOB error signal may be determined to be the correct EOB error signal, and the target SOB error signal and the initial SOB error signal may be corrected.

In the embodiment of the application, besides the error code detection, the finally determined error code signal can be corrected, so that the accuracy of signal transmission is ensured.

In a possible implementation manner of the first aspect, if the accumulated error corresponding to any one of the signals to be measured is not less than the accumulated error threshold, that is, the error corresponding to the initial EOB error signal is the smallest error value, it may be determined that the target SOB error signal does not exist in the signals to be measured. Based on this, it is explained that the initial EOB error signal is a false decision, and the initial EOB error signal is actually a non-error signal.

In the embodiment of the application, the signal which is misjudged as the EOB error code signal can be found, the error can be corrected, more error codes are avoided, and the accuracy of the technical scheme of the application is further improved.

A second aspect of the embodiment of the present application provides an error code detection method, including:

And acquiring a first equalization result, wherein the first equalization result is obtained by equalizing a plurality of continuous signals in the signal set based on a first equalization mode, and the plurality of signals comprise target signals. And acquiring a second equalization result, wherein the second equalization result is obtained by equalizing the continuous multiple signals based on a second equalization mode. And if the first equalization result is different from the second equalization result, determining that the target signal is the initial EOB error signal.

In a possible implementation manner of the second aspect, the continuous plurality of signals includes a target signal and a previous signal of the target signal; or the target signal and the latter signal of the target signal.

A third aspect of an embodiment of the present application provides an error code detection apparatus, including:

An obtaining unit, configured to perform the obtaining operation in the foregoing first aspect and any implementation manner of the first aspect. A processing unit, configured to perform operations other than the acquiring operations in the foregoing first aspect and any implementation manner of the first aspect.

The beneficial effects shown in this aspect are similar to those in the first aspect and any implementation manner of the first aspect, and are not repeated here.

A fourth aspect of the present application provides an error detection apparatus, including:

An obtaining unit, configured to perform the obtaining operation in the foregoing second aspect and any implementation manner of the second aspect. A processing unit, configured to perform operations other than the acquiring operation in any implementation manner of the second aspect and the second aspect.

The beneficial effects shown in this aspect are similar to those in the second aspect and any implementation manner of the second aspect, and are not described herein.

A fifth aspect of the application provides a communication device comprising a processor and a memory, the processor storing instructions which, when executed on the processor, implement the method of any one of the possible implementations of the first aspect and the second aspect or any one of the possible implementations of the second aspect and the second aspect.

A sixth aspect of the present application provides a chip comprising a processing unit and a power supply circuit for powering the processing unit, the processing unit being configured to implement the method shown in any one of the foregoing first aspect and any one of the foregoing possible implementation manners of the second aspect.

A seventh aspect of the present application provides a computer readable storage medium having instructions stored thereon which, when executed on a processor, implement the method of any one of the possible implementations of the first aspect and the second aspect or any one of the possible implementations of the second aspect and the second aspect.

An eighth aspect of the application provides a computer program product which, when executed on a processor, implements any one of the possible implementations of the first aspect and the second aspect or the method shown in any one of the possible implementations of the second aspect and the second aspect.

The advantages of the fifth to eighth aspects are similar to those of the first aspect and any one of the possible implementation manners of the first aspect or the method of the second aspect and any one of the possible implementation manners of the second aspect, and are not repeated here.

Drawings

Fig. 1 is an effect schematic diagram of a precoding scheme;

FIG. 2 is a schematic diagram of a system architecture according to an embodiment of the present application;

fig. 3 is a schematic flow chart of an error code detection method according to an embodiment of the present application;

FIG. 4a is a signal processing block diagram of an error detection method according to an embodiment of the present application;

FIG. 4b is a signal processing block diagram of an error detection method according to an embodiment of the present application;

fig. 5 is a schematic flow chart of another error code detection method according to an embodiment of the present application;

FIG. 6 is another signal processing block diagram of an error detection method according to an embodiment of the present application;

FIG. 7 is a block diagram illustrating another signal processing method for error detection according to an embodiment of the present application;

FIG. 8 is a block diagram illustrating another signal processing method for error detection according to an embodiment of the present application;

FIG. 9 is a block diagram of another signal processing method for error detection according to an embodiment of the present application;

FIG. 10 is a block diagram illustrating another signal processing method for error detection according to an embodiment of the present application;

FIG. 11 is a schematic diagram of a simulation result of an error detection method according to an embodiment of the present application;

Fig. 12 is a schematic structural diagram of an error code detection device according to an embodiment of the present application;

fig. 13 is a schematic structural diagram of a communication device according to an embodiment of the present application.

Detailed Description

Embodiments of the present application are described below with reference to the accompanying drawings. As one of ordinary skill in the art can know, with the development of technology and the appearance of new scenes, the technical scheme provided by the embodiment of the application is also applicable to similar technical problems.

The terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and are merely illustrative of the manner in which embodiments of the application have been described in connection with the description of the objects having the same attributes. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. In addition, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and the representation may have three relationships, for example, a and/or B may represent: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural.

The intersymbol interference (inert-symbol interference, ISI) includes front-end intersymbol interference and back-end intersymbol interference, the feedforward equalizer (feed forward equalizer, FFE) is capable of canceling the front-end intersymbol interference and part of the back-end intersymbol interference, and the decision feedback equalizer (decision feedback equalizer, DFE) is capable of canceling the remaining back-end intersymbol interference. However, with the rapid development of high-speed wired serial communication links, the transmission rate is faster and faster, and the intersymbol interference of the channel is greater and greater, so that the equalization coefficient of the DFE is greater and larger. Accordingly, the probability of error transfer is also increasing. To solve the problem of error propagation of larger coefficient DFE, the signal may be precoded (precoding), including 1/(1+d) encoding at the transmitting end and 1/(1+d) decoding of the DFE-passed signal at the receiving end.

After precoding processing, burst errors resulting from successive DFE error transfers can be eliminated, but at the cost of adding a new error after the original error.

Referring to fig. 1, fig. 1 is a schematic diagram illustrating an effect of a precoding scheme. The precoding scheme refers to a scheme of dfe+ precodingd.

As shown in a diagram a of fig. 1, when the continuous error length of the signal after DFE processing is 1 (i.e., no error transfer occurs), the signal is precoded to become two error signals. As shown in the b diagram of fig. 1, when the continuous error length of the signal after DFE processing is greater than 1 (i.e., error transfer occurs), the signal is precoded again and then becomes two error signals, and the number of errors is reduced. In general, the first of a segment of consecutive burst errors is referred to as a burst start bit, SOB, error signal, and the error signal added after precoding is referred to as a burst end bit, EOB, error signal.

The error code detection method provided by the embodiment of the application detects SOB and EOB on the basis of DFE+ precoding and corrects the SOB and EOB so as to further reduce the error code rate and improve the transmission efficiency.

Next, referring to fig. 2, fig. 2 is a schematic diagram of a system architecture according to an embodiment of the present application.

The scenario to which the embodiments of the present application are applied may include all high-speed wired serial links, and communication devices acting on the receiving end are deployed in a serial interface chip (i.e., serDes chip). In some alternative embodiments, the error detection method provided by the implementation of the present application may be applied to a serial/deserializer (SerDes) chip at the receiving end. Such as shown in fig. 2, any of communication device a and communication device B, are interconnected via a high-speed serial link via a serializer/deserializer.

Note that the communication device a may be a transmitting device, and may be decoupled from the serializer/deserializer as shown in fig. 2, or coupled to the serializer/deserializer, which is not limited herein. The high-speed serial link used in the error code detection method may be a link between chips or a link between a chip and an optical module, or may be other types of high-speed serial links, for example, a link between an optical module and a board, which is not limited herein.

The following describes in detail the error code detection method provided by the embodiment of the present application, taking the serial interface chip coupled in the communication device and taking the communication device as an execution body as an example.

It will be appreciated that in detecting the SOB error signal and the EOB error signal, the SOB error signal is typically determined based on the EOB error signal. For ease of illustration, embodiments of the application are also described in this order.

First, a process of detecting an EOB error signal will be described. Referring to fig. 3, fig. 3 is a flowchart of an error code detection method according to an embodiment of the application, which includes the following steps:

301. and acquiring a first equalization result, wherein the first equalization result is obtained by equalizing a plurality of continuous signals in the signal set based on a first equalization mode, and the plurality of signals comprise target signals.

The first equalization mode may be a normal adaptive DFE equalization mode, or a joint equalization mode, or other modes capable of equalizing signals, which is not limited herein. The continuous plurality of signals includes a target signal and a previous signal to the target signal; or the target signal and the latter signal of the target signal, in particular not limited herein.

And processing the continuous multiple signals in a first equalization mode to obtain a first equalization result, wherein the equalization result can also be called a decision result. The decision result is to determine the level value corresponding to the signal as the standard level value closest to the signal. Taking the standard level value of PAM-4 as { -3, -1, 3} as an example, if the level value of the current signal is 2.5, the level value of the signal is decided to be 3 closest to 2.5.

302. And acquiring a second equalization result, wherein the second equalization result is obtained by equalizing the continuous multiple signals based on a second equalization mode.

The second equalization mode is different from the first equalization mode, and may be a normal adaptive DFE equalization mode, a joint equalization mode, or other modes capable of equalizing signals, which is not limited herein.

303. If the first equalization result is different from the second equalization result, determining that the target signal is an initial EOB error signal.

If the first equalization result and the second equalization result are different, then the target signal may be considered to be an EOB error signal, i.e., the target signal is determined to be an initial EOB error signal. As to whether the initial EOB error signal is actually the EOB error signal, it can be further confirmed by combining the determination of the SOB error signal, which will be described below.

It should be noted that, in the embodiment of the present application, the sequence of step 301 and step 302 is not limited, and step 301 may be performed first, step 302 may be performed first, or step 301 and step 302 may be performed simultaneously, which is not limited herein.

In the embodiment of the application, the possible error code signals are determined as the initial EOB error code signals from the signal set by combining the equalization results of different equalization modes on the continuous multiple signals, so that the EOB error code signals can be screened as much as possible. Meanwhile, the continuous multiple signals are balanced, and compared with a mode of judging only a single signal, the balanced result is more accurate. In addition, a plurality of continuous signals which are balanced by using different equalization modes are possible, the realization mode and the application scene of the technical scheme of the application are enriched, different requirements can be met, and the flexibility of the technical scheme is improved.

The above procedure is further described by taking as an example a DFE equalization mode in which the first equalization mode is normally adaptive, and the second equalization mode is a joint equalization mode, and assuming that a signal acquired by the communication device is a PAM-4 signal and a standard level value is (-3, -1, 3), a plurality of signals are consecutive as a target signal and a signal preceding the target signal.

Referring to fig. 4a, fig. 4a is a signal processing block diagram of an error code detection method according to an embodiment of the application.

As shown in fig. 4a, assuming equalization compensation of continuous-time linear equalizer (CTLE) and FFE, the residual ISI only leaves first-order ISI (post-1 ISI). That is, the FFE equalized signal FFEo _ut,FFEo_ut has first-order ISI, denoted by y n in fig. 4 a. Then there are:

y[n]＝a[n]+h[1]a[n-1]+w[n]

Wherein a [ n ] represents a signal after precoding of a target signal x [ n ] sent by a sending end, a [ n-1] represents a signal after precoding of a previous signal x [ n-1] of the target signal, h [1] represents post-1ISI, and w [ n ] represents Gaussian white noise.

In the signal processing block diagram shown in fig. 4a, the upper dotted line box indicates a processing circuit for first-order DFE (1-tap DFE) equalization, and the lower dotted line box indicates a processing circuit for Joint Decoding (JD) equalization, which will be described below.

As shown in the processing circuit of the first-order DFE equalization, the signal FFEo _ut is subjected to a conventional first-order DFE equalization to eliminate post-1ISI, and then the estimated result b n of the transmitted signal a n is obtained after decision, that is, the Slicero _ut signal in fig. 4 a.

In the figure, the post-1 coefficient c of the DFE is adaptively and dynamically adjusted to an optimal value by a least mean square (LEAST MEAN square, LMS) algorithm, and after a certain time, the coefficient c converges to be near the value h [1] of the post-1ISI, namely, c is approximately equal to h [1]. Thus, the input signal of the slewer-4 module can be expressed as:

y[n]-cb[n-1]＝a[n]+h[1]a[n-1]+w[n]-cb[n-1]

≈a[n]+c(a[n-1]-b[n-1])+w[n]

When the previous signal symbol is determined to be correct, i.e., a [ n-1] =b [ n-1], y [ n ] -cb [ n-1] =a [ n ] +w [ n ].

Through the decision of the decision device, the correct estimation result of an can be obtained with larger probability.

When the previous signal symbol is determined to be erroneous, i.e., a [ n-1] noteqb [ n-1], the error signal is represented by e [ n ] =a [ n-1] -b [ n-1], then there are:

y[n]-cb[n-1]＝a[n]+ce[n]+w[n]

at this time, the false estimation result of an is obtained with a larger probability through the judgment of the judgment device.

Because of the feedback mechanism of the DFE, the error signal e n always alternates positive and negative when successive burst errors are generated, so that when we add b n and b n-1, a result different from a n+a n-1 will only occur at SoB and EoB. Can be expressed by the following formula:

As shown in FIG. 4a, the FFE output signal (i.e., FFEo _ut) is also subjected to a joint decoding equalization process where an + a-1 is directly determined, as opposed to a determination of an n by the DFE.

According to FIG. 4a, the output signals of FFEs (i.e., FFEo _ut) are first delay-superimposed, i.e

y[n]+(1-c)y[n-1]

＝a[n]+h[1]a[n-1]+w[n]+(1-c)(a[n-1]+h[1]a[n-2]+w[n-1])

＝a[n]+a[n-1]+c(1-c)a[n-2]+w[n]+(1-c)w[n-1]

The a-2-dependent portion is subtracted from the delayed superimposed signal, where the decision result of the DFE is utilizedThus:

If 7 level decision is directly made on the signal, the estimation result of the signal a [ n ] +a [ n-1] can be obtained. The reason for the 7-level decision device is that, assuming that both a n and a n-1 are PAM-4 signals, there are four level values (-3, -1, 3). Then a n + a n-1 has 7 possible level results (-6, -4, -2,0,2,4,6).

Since precoding codes are performed at the transmitting end, there is a [ n ] = (x [ n ] -a [ n-1 ]) mod4. After obtaining the estimated value of a [ n ] +a [ n-1], the estimated result of x [ n ] can be obtained by performing map & mod4 operation (i.e. decoding operation) once again, namely:

thus, JDo _ut in FIG. 4a is the result of the recovery of the sender signal x [ n ].

And comparing the estimated results of the two equalization modes to a [ n ] +a [ n-1], and judging whether the signal x [ n ] corresponding to the a [ n ] is an initial EoB error code signal. Specifically, when the results obtained by the two equalization methods are the same, the current symbol (i.e., the target signal x [ n ]) is determined to be not an EoB error signal, eoBD signal =0. When the results of the two equalization methods are different, the current symbol is determined to be a possible EoB error signal, i.e., an initial EoB error signal.

Alternatively, in the following description, eoBD signal = -2 when the joint decoding symbol level is smaller than the DFE equalization result symbol level, and EoBD signal =2 when the joint decoding symbol level is greater than the DFE equalization result symbol level is set. EoBD signal are used for compensating the level value in the reverse error transmission, and will be described below, which will not be repeated here.

Note that the value of EoBD signal may be opposite to the above definition, that is, eoBD signal =2 may be set when the joint decoding symbol level is smaller than the DFE equalization result symbol level, and EoBD signal = -2 when the joint decoding symbol level is larger than the DFE equalization result symbol level. The specific examples are not limited herein. If the latter setting is adopted, the compensated level value needs to be correspondingly adjusted when the reverse error code transmission is carried out.

By calculating the examples shown in table 1 below, we can find that the result of normal DFE equalization is different from the result of joint decoding at symbol 7, and thus can determine that the signal corresponding to symbol 7 is the initial EOB error signal. The specific calculation results are shown in table 1 below.

TABLE 1

It should be noted that the embodiment shown in fig. 4a is merely an example of determining the initial EOB error signal based on two different equalization manners, and in practical application, the processing block may also take other structures, which is not limited herein.

Illustratively, as shown in fig. 4b, on the basis of the processing block diagram shown in fig. 4a, a MOD4 block is added before the comparator, and the MOD4 block is used to perform the decoding operation. In this case, input to the comparator is the output signals of the MOD4 block and the Map & MOD4 block.

It should be noted that PAM-4 is taken as an example in the above description, and in practical application, it may be widely applied to other types of signals, such as PAM-2, or PAM-6, etc., and is not limited herein. For example, assuming that PAM-2 signals with standard level values (-1, +1) are processed, the Slicer-4 module in FIG. 4a and FIG. 4b needs to be modified to be a Slicer-2 module, and the Slicer-7 module needs to be modified to be a Slicer-3 module. This is because it is assumed that both a [ n ] and a [ n-1] are PAM-2 signals, and that there are two level values (-1, 1). Then a [ n ] + a [ n-1] has 3 possible level results (-2,0,2). Similarly, assuming PAM-6 signals with standard level values (+ -1, + -3, + -5) are processed, the Slicer-4 module in FIG. 4a, FIG. 4b needs to be modified to be a Slicer-6 module, and the Slicer-7 module needs to be modified to be a Slicer-11 module.

The above describes the process of determining the initial EOB error signal based on two different equalization approaches, and in practical applications, other approaches and determination of the initial EOB error signal may be used.

In some alternative embodiments, the communication device may obtain the decision result and the decision error of the target signal in the signal set. If the judgment result is the extremum corresponding to the signal set and the judgment error absolute value is larger than the error threshold, the target signal is determined to be the initial EOB error signal.

Wherein, the extremum refers to the limit level value corresponding to the signal set, if the judgment result of the target signal is realized by judging the single signal, the limit level value refers to the limit level value of the single signal, for example, the single limit level value corresponding to the PAM-4 signal with standard level values (+ -1, + -3) is + -3; if the decision result of the target signal is achieved by deciding on a plurality of continuous signals, the limit level value refers to the limit level values of the plurality of signals, for example, the limit level values of two signals corresponding to PAM-4 signals having standard level values (±1, ±3) are ±6.

The decision result of the target signal may be a result obtained according to a DFE equalization manner (Slicero _ut shown in fig. 4 a), or may be a decision result obtained based on other decision manners, for example, a result obtained according to a joint coding equalization manner (JDo _ut shown in fig. 4 a), which is not limited herein.

The error threshold is set in relation to the channel coefficient, and in general, the larger the channel coefficient is, the larger the threshold is. The decision error is larger than the error threshold, which means that the decision error exceeds the error allowable range, and the probability of the signal being an error code signal is larger. Since the decision result is to determine the level value corresponding to the signal as the standard level value closest thereto. Therefore, after the error code is transferred to the limit level value, the positive direction or negative direction offset caused by the error code transfer is performed, and the judgment result is not affected, that is, the extreme level is the place where the EOB error code signal is most likely to occur. Meanwhile, the EOB error code signals can be more accurately identified by combining the judgment errors.

In some alternative embodiments, the communication device may also determine the initial EOB error signal by. Taking PAM-4 as an example:

Assuming that the equalization compensation by FFE is performed, the residual ISI only leaves first-order ISI (post-1 ISI). The signals input to FFE are denoted by y [ n ], then there are:

y[n]＝a[n]+h[1]a[n-1]+w[n]

And carrying out equalization treatment on y [ n ] through conventional 1-Tap DFE to obtain the following components:

y[n]-cb[n-1]＝a[n]+h[1]a[n-1]+w[n]-cb[n-1]

≈a[n]+c(a[n-1]-b[n-1])+w[n]

The decision result b [ n ] =sler { y [ n ] -cb [ n-1] } of a [ n ] is obtained through a decision device.

The decision error (Slicing Error) is: slicing error [ n ] = y [ n ] -cb [ n-1] -b [ n ].

A first threshold (thershold ₁) and a second threshold (thershold ₂) are set and compared with slicing error [ n ] to complete the first stage determination. Wherein. The first threshold is greater than the second threshold, and the magnitude of the threshold is related to the channel parameter, and the thresholds of different channels may be the same or different, which is not limited herein.

When slicing error [ n ] is not less than thershold ₁, the nth symbol is judged as an initial EoB error code signal.

When slicing error [ n ] is less than or equal to thershold ₂, the nth symbol is judged to be a non-initial EoB error code signal.

When thershold ₂＜slicing error[n]＜thershold₁ is applied, a second stage decision is needed to determine whether the nth symbol is the initial EOB error signal.

Specifically, for the signal y [ n+1] received at the next time and its conventional equalization result b [ n+1], the following calculation can be performed:

the decision result b' n of the other pair a n can be obtained through a decision device:

The definition signal S [ n ] is as follows:

in thershold ₂＜slicing error[n]＜thershold₁, calculating S [ n-1] and S [ n ], when S [ n-1] =0 and S [ n ] =1, determining the nth symbol as an initial EoB error signal; otherwise, the signal is a non-initial EoB error signal.

Alternatively, the definition of the signal S [ n ] may be modified as follows:

Then, in the case of thershold ₂＜slicing error[n]＜thershold₁, S [ n-1] and S [ n ] are calculated, when S [ n-1] =1 and S [ n ] =0, the nth symbol is determined as the initial EoB error signal; otherwise, the signal is a non-initial EoB error signal.

In general, in the thershold ₂＜slicing error[n]＜thershold₁ case, if b [ n-1] noteqb '[ n-1] is satisfied, and b [ n ] =b' [ n ], the nth symbol can be determined to be the initial EOB error signal.

Next, a process of detecting the SOB error signal will be described. Referring to fig. 5, fig. 5 is a flowchart of an error code detection method according to an embodiment of the application, which includes the following steps:

501. A signal set is obtained, the signal set including an initial end of burst bit EOB error signal.

The computing device can obtain a set of signals including an initial EOB error signal. The initial EOB error signal may be determined based on the manner described above.

502. And carrying out reverse error code transmission by taking the initial EOB error code signal as a starting point, determining the initial SOB error code signal from the signal set, and taking the initial SOB error code signal and a signal between the initial SOB error code signal and the initial EOB error code signal in the signal set as a signal to be detected.

And carrying out reverse error code transmission by taking the initial SOB error code signal as a starting point so as to offset errors caused by forward error code transmission, and determining the initial SOB error code signal according to the level value after the direction error code transmission. Specifically, the initial EOB error signal is used as a starting point to perform reverse error transmission, and when an abnormal level value occurs, the next signal of the signal corresponding to the abnormal level value is determined to be the initial SOB error signal. The abnormal level value is a level value (or a level value greater or less than a level extremum) which does not occur during normal signal transmission. Illustratively, taking PAM-4 signals with standard values (-3, -1, 3) as an example, each signal may have a level value of one of these 4 possible, with a level extremum of + -3. In this case, a level value greater than +3 or less than-3 is an abnormal level value. Assuming that the signal No. 5 is an initial EOB error signal, the signal No. 5 is used as a starting point to perform reverse error transmission, and an abnormal level value-5 appears when the signal No. 1 is transmitted, so that the next signal of the signal No. 1 (i.e. the signal No. 2) can be determined to be the initial SOB error signal.

The signal set comprises a signal to be detected, wherein the signal to be detected comprises an initial SOB error code signal and a signal from the initial SOB error code signal to the initial EOB error code signal. That is, from the initial SOB error signal to the signal before the initial EOB error signal, the signal is to be measured. For example, assuming that there are 7 signals with sequence numbers 1 to 7, the signal No. 7 is an initial EOB error signal, after the transmission of the reverse error, it is determined that the signal No. 2 is an initial SOB error signal, and then the signals No. 2 to 6 are signals to be tested.

503. And respectively calculating the accumulated error from each signal to be detected to the initial EOB error signal, wherein the accumulated error is determined according to the error from each signal to be detected to any two adjacent signals in the initial EOB error signal.

The accumulated error includes a reverse compensation error for compensating the error signal and a decision error indicating an error before and after the signal decision.

Illustratively, the cumulative error of the signal No. 2 to the initial EOB error signal (signal No. 7) is the sum of the errors of any two adjacent signals from the signal No. 2 to the signal No. 7; the accumulated error of the No. 3 signal to the No. 7 signal is the sum of the errors of any two adjacent signals from the No. 3 signal to the No. 7 signal.

504. And determining whether the target SOB error signal exists or not from the signal to be detected according to the accumulated error.

If the target signal to be detected with the smallest accumulated error and smaller than the accumulated error threshold exists in the signal to be detected, the target signal to be detected can be determined to be the target SOB error signal. If the accumulated error corresponding to any one of the signals to be detected is not smaller than the accumulated error threshold, the target SOB error signal does not exist in the signal set. The accumulated error threshold is the error corresponding to the initial EOB error signal.

In some alternative embodiments, in the case that it is determined that the target EOB error signal exists in the signal to be tested, then the initial EOB error signal may be determined to be the correct EOB error signal, and the target EOB error signal and the initial SOB error signal may be corrected.

In some alternative embodiments, if the accumulated error corresponding to any one of the signals to be measured is not less than the accumulated error threshold, which means that the error corresponding to the initial EOB error signal is the smallest error value, since one signal cannot be the EOB error signal and the SOB error at the same time, it can be determined that the target SOB error signal does not exist in the signals to be measured. Based on this, it is explained that the initial EOB error signal is a false decision, and the initial EOB error signal is actually a non-error signal.

In general, the embodiment of the application carries out reverse error transmission on the initial EOB error signals, after the initial SOB error signals are determined, the accumulated errors from each signal to be detected to the initial EOB error signals are calculated respectively, and the signal with the accumulated errors meeting the condition is determined as the target SOB error signal from the signals to be detected. The accumulated error of each signal to be detected is determined according to the error of any two adjacent signals in the initial EOB signal of the signal to be detected, that is, the technical scheme of the application is based on the sequence accumulated error, the determined SOB error code signal enriches the determination basis, reduces the error judgment probability and reduces the error rate.

The process of determining the target SOB error signal is further described below with reference to the accompanying schematic diagrams. Referring to fig. 6 to fig. 10, fig. 6 to fig. 10 are signal processing block diagrams of an error code detection method according to an embodiment of the application. Fig. 6 to 10 are illustrations of the case where the signal is PAM-4 signal and the standard level values are (-3, -1, 3), and the ISI is considered to be first-order ISI.

With the output of the signal processing block diagram shown in fig. 4a as the input to the signal processing block diagram shown in fig. 6, after the initial EOB error signal is detected, a decision error sequence may be calculated from the sler _in and sler _out signals and stored in a shift register, as shown in fig. 6. SoB _init detection is done according to slicers _out and EoBD signal, and reverse compensation errors are generated according to EoBD signal. And calculating the accumulated error of the short sequence, judging whether a target SOB error code signal exists according to the short sequence number with the minimum sequence accumulated error, and correcting. The SoB _init performs reverse error code transmission.

As shown in fig. 7, the decision error sequence module calculates and saves the decision error by using a shift register, and the decision error at the nth time is represented by S [ n ]:

S[n]＝silcer_in[n]-silcer_out[n]

The number N of the shift registers can be selected according to the requirement, and when the channel error code transmission probability is larger, N should be selected to be larger so as to obtain better performance; when the channel error transfer probability is small, N may be chosen smaller to save power consumption. The register holds from left to right S _1:N n= { S N, S N … …, S N-N } for a total of N instances of decision error values, which are then used to calculate the accumulated error.

As shown in fig. 8, the SoBinit detection module first uses N shift registers to buffer the sler _out signal, and detects whether an abnormal level value (i.e., +5 or-5 level) exists by passing the bit error in reverse. If so, the reverse transfer distance corresponding to the first +5 or-5 level is denoted as i ^*; if not, let i ^*＝N.SoB_init be represented as:

SoB_init＝EOB-i*+1

For example, in table 1, the results shown in table 2 below were obtained after the SoB _init detection, and after 6 symbols were passed in reverse, the-5 level was detected. I.e., an outlier is detected at symbol 1, the initial EOB error signal may be determined to be the signal corresponding to the next symbol of symbol 1 (i.e., symbol 2). So i ^*＝6,SoB_init＝EOB-i^* +1=7-6+1=2. This illustrates that the true SoB error signal is between symbol 2 and symbol 6.

TABLE 2

Symbol number n	1	2	3	4	5	6	7	8	9
										A [ n ] level	-3	-3	-3	-1	1	-1	3	-1	3
B [ n ] level	-3	-3	-1	-3	3	-3	3	-1	3
										Eobd signal	0	0	0	0	0	0	2	0	0
b[n]-a[n]	0	0	2	-2	2	-2	0	0	0
										Spill detection	-5	-1	-3	-1	1	-1

As shown in fig. 9, the reverse compensation error generation module generates a corresponding compensation signal e ₀[n],e₁[n],e₂ n according to EoBD Signal and stores the compensation signal in 3 registers.

e₀[n]＝ES

e₁[n]＝c×ES

e₂[n]＝(1-c)×ES

As shown in fig. 10, the sequence accumulated error module needs to calculate a soft decision accumulated error from the reverse compensation error e ₀[n],e₁[n],e₂ n and the decision error sequence S ₁:_N n. A total of i ^* accumulated errors need to be calculated, respectively:

wherein M _j [ n-i ] is a symbol after reverse transfer compensation, and satisfies:

It should be noted that M _j [ n-i ] is used only as a theoretical derivation intermediate variable, which is not required for practical implementation. By substituting M _j [ n-i ] into ε _j [ n ], it can be calculated

For j.gtoreq.3, there are:

Note that as shown in fig. 10, the signal e ₂＝e₀+e₁.

And then select the short sequence j ^*＝armmin_jεj n with the smallest accumulated error, so that sob=eob-j ^*, where SoB refers to the symbol number corresponding to the signal.

When j ^* is more than or equal to 1, correcting the corresponding SoB signal: JD _out[SoB]＝[JD_out[SoB]+(-1)^j*-1 sgn (ES) ] Mod4.

When j ^* is not less than 0, i.e. the first short sequence has the smallest soft-decision accumulated error, then there is sob=eob. Then the initial EOB error signal is considered to be a false positive and no EOB error signal is present in the signal set.

Note that in the embodiment shown in fig. 6, correction is performed on the signal corresponding to JD _out, and in practical application, JD _out may be replaced by slider _out, which is not limited herein.

Illustratively, it is assumed that the results shown in Table 3 below are obtained by performing corresponding short-sequence cumulative error calculations on the examples in Table 1 and Table 2. As shown in table 3, since eob=7 and epsilon ₄ [7] is the smallest, there is j ^* =4 and sob=7-4=3. That is, the signal corresponding to symbol 3 is determined to be the target SOB error signal. Then JD _out [3] can be corrected to obtain the correct symbol x [3]:

JD_out[3]＝[1-1]mod4＝0＝x[3]

TABLE 3 Table 3

Fig. 11 shows simulation results of bit error rates based on the embodiments shown in fig. 3 to 10. The simulation model considers only the channel model of first order ISIh (1) and gaussian white noise. Wherein the horizontal axis represents different channel ISI values, denoted by alpha (maximum 1). The vertical axis indicates the bit error rate (symbol error rate, SER) of PAM-4 symbols.

As shown in fig. 11, DFE indicates that only DFE is applied for equalization, dfe+ PreC indicates the result of DFE and Precoding, dfe+ PreC + EoBD indicates the result of applying EoBD after DFE and Precoding, and mlse+precoding indicates the result of applying MLSE equalization and then applying Precoding. The results of the embodiment shown in fig. 3 to 10 are denoted SoBD SSE, and simulation results show that the embodiment shown in fig. 3 to 10 can effectively reduce the bit error rate compared to EoBD. When the Alpha value is larger, the bit error rate of MLSE+precoding can be approximated. Meanwhile, the implementation complexity and power consumption of the embodiments shown in fig. 3 to 10 are much smaller than mlse+precoding. That is, the error code detection method provided by the embodiment of the application reduces complexity and power consumption under the condition of greatly improving detection accuracy.

The following describes related devices provided in the embodiments of the present application.

Referring to fig. 12, fig. 12 is a schematic diagram of an error detection apparatus according to an embodiment of the application.

As shown in fig. 12, the error detection apparatus 1200 includes:

An acquisition unit 1201 is configured to perform the acquisition operation performed by the communication apparatus in the embodiments shown in fig. 2 to 8 described above.

The processing unit 1202 is configured to perform operations other than the acquisition operations performed by the communication device in the embodiments shown in fig. 2 to 8.

In some alternative embodiments, the acquiring unit 1201 is configured to acquire a signal set, where the signal set includes an initial EOB error signal.

The processing unit 1202 is configured to perform inverse error transmission with the initial EOB error signal as a starting point, determine an initial SOB error signal from the signal set, and determine a signal between the initial SOB error signal and the initial SOB error signal to the initial EOB error signal in the signal set as a signal to be detected. And respectively calculating the accumulated error from each signal to be detected to the initial EOB error signal, wherein the accumulated error is determined according to the error from each signal to be detected to any two adjacent signals in the initial EOB error signal. And determining whether the target SOB error signal exists or not from the signal to be detected according to the accumulated error.

In some optional embodiments, the processing unit 1202 is specifically configured to determine that the target signal to be measured is the target SOB error signal if there is a target signal to be measured with a smallest accumulated error and less than an accumulated error threshold value, and the accumulated error threshold value is an error corresponding to the initial EOB error signal.

In some alternative embodiments, the accumulated error includes a reverse compensation error for compensating the error signal and a decision error indicating the error before and after the signal decision.

In some optional embodiments, the processing unit 1202 is specifically configured to perform reverse error transmission with the initial EOB error signal as a starting point, and determine that a signal corresponding to the abnormal level value is the initial SOB error signal when the abnormal level value occurs.

In some optional embodiments, the obtaining unit 1201 is further configured to obtain a first equalization result, where the first equalization result is obtained by equalizing a plurality of signals in a signal set, where the plurality of signals includes the target signal, based on the first equalization method. And acquiring a second equalization result, wherein the second equalization result is obtained by equalizing the continuous multiple signals based on a second equalization mode.

The processing unit 1202 is further configured to determine that the target signal is the initial EOB error signal if the first equalization result is different from the second equalization result.

In some alternative embodiments, the continuous plurality of signals comprises: a target signal and a signal preceding the target signal; or the target signal and the latter signal of the target signal.

In some alternative embodiments, the obtaining unit 1201 is further configured to obtain a decision result and a decision error of the target signal in the signal set.

The processing unit 1202 is further configured to determine that the target signal is an initial EOB error signal if the decision result is an extremum corresponding to the signal set and the absolute value of the decision error is greater than the error threshold.

In some optional embodiments, the acquiring unit 1201 is further configured to acquire a decision error and a first decision result of the target signal in the signal set.

The processing unit 1202 is further configured to confirm that the target signal is an initial EOB error signal if the decision error is greater than or equal to the first threshold; if the decision error is less than or equal to the second threshold, confirming that the target signal is not the initial EOB error signal; if the decision error is greater than the second threshold and less than the first threshold, a second stage decision is made to confirm whether the target signal is the initial error signal. And determining a second judgment result of the target signal according to the input signal corresponding to the next signal of the target signal and the equalization result. And acquiring a third judgment result and a fourth judgment result of a signal before the target signal, wherein the third judgment result and the first judgment result are based on the same judgment mode, and the second judgment result and the fourth judgment result are based on the same judgment mode. Under the condition that the judgment error is larger than the second threshold value and smaller than the first threshold value, if the first judgment result is the same as the second judgment result and the third judgment result is different from the fourth judgment result, confirming that the target signal is an initial EOB error signal; otherwise, the target signal is confirmed to be a non-initial EOB error signal.

In some alternative embodiments, the processing unit 1202 is further configured to correct the target SOB error signal and the initial EOB error signal if it is determined that the target SOB error signal is included in the signal under test.

In some optional embodiments, the processing unit 1202 is specifically configured to determine that the target SOB error signal does not exist in the signal to be detected if the accumulated error corresponding to any one of the signals to be detected is not less than the accumulated error threshold;

If the target SOB error code signal does not exist in the signal to be detected, the initial EOB error code signal is determined to be a non-error code signal.

The error detection apparatus 1200 may perform the operations performed by the communication device in the embodiments shown in fig. 2 to 11, which are not described herein.

Next, referring to fig. 13, fig. 13 is a schematic structural diagram of a communication device according to an embodiment of the present application. The communication device 1300 includes: a processor 1301, and a memory 1302, the memory 1302 having one or more applications or data stored therein.

Wherein the memory 1302 may be volatile storage or persistent storage. The program stored in the memory 1302 may include one or more modules, each of which may be used to perform a series of operations performed by the communications device 1300. Still further, the processor 1301 may be in communication with the memory 1302, executing a series of instruction operations in the memory 1302 on the communication apparatus 1300. Processor 1301 may be a central processing unit (central processing units, CPU) or may be a single-core processor, but may be other types of processors, such as a dual-core processor, and is not limited in this regard.

The communications device 1300 may also include one or more communications interfaces 1303, one or more operating systems, such as Windows Server ^TM,Mac OS X^TM,Unix^TM,Linux^TM,FreeBSD^TM, etc.

The communications device 1300 may perform the operations performed by the communications device in the embodiments shown in fig. 2 to 11, which are not described herein.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.

In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium, including instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a read-only memory (ROM), a random access memory (random access memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

Claims

1. An error code detection method, comprising:

Acquiring a signal set, wherein the signal set comprises an initial burst end bit EOB error signal;

The initial EOB error code signal is used as a starting point to carry out reverse error code transmission, an initial burst start bit SOB error code signal is determined from the signal set, and the initial SOB error code signal and a signal between the initial SOB error code signal and the initial EOB error code signal in the signal set are signals to be detected;

respectively calculating the accumulated error from each signal to be detected to the initial EOB error code signal, wherein the accumulated error is determined according to the error from each signal to be detected to any two adjacent signals in the initial EOB error code signal;

And determining whether a target SOB error code signal exists or not from the signal to be detected according to the accumulated error.

2. The method of claim 1, wherein said determining whether a target SOB error signal exists from the signal under test based on the accumulated error comprises:

if a target signal to be detected with the smallest accumulated error and smaller than an accumulated error threshold exists in the signal to be detected, determining that the target signal to be detected is the target SOB error signal, wherein the accumulated error threshold is an error corresponding to the initial EOB error signal.

3. A method according to claim 1 or 2, characterized in that the accumulated error comprises a reverse compensation error for compensating the error signal and a decision error indicating the error before and after the signal decision.

4. A method according to any one of claims 1 to 3, wherein said determining an initial SOB error signal from said signal set by reverse error transfer starting from said initial EOB error signal comprises:

And carrying out reverse error code transmission by taking the initial EOB error code signal as a starting point, and determining the next signal of the signal corresponding to the abnormal level value as the initial SOB error code signal when the abnormal level value appears.

5. The method according to any one of claims 1 to 4, further comprising:

acquiring a first equalization result, wherein the first equalization result is obtained by equalizing a plurality of continuous signals in the signal set based on a first equalization mode, and the plurality of signals comprise target signals;

Acquiring a second equalization result, wherein the second equalization result is obtained by equalizing the continuous multiple signals based on a second equalization mode;

and if the first equalization result is different from the second equalization result, determining that the target signal is the initial EOB error signal.

6. The method of claim 5, wherein the continuous plurality of signals comprises:

The target signal and a signal preceding the target signal; or alternatively

The target signal and a signal subsequent to the target signal.

7. The method according to any one of claims 1 to 4, further comprising:

acquiring a judgment result and a judgment error of a target signal in the signal set;

and if the judgment result is an extremum corresponding to the signal set and the absolute value of the judgment error is greater than an error threshold, determining the target signal as the initial EOB error code signal.

8. The method according to any one of claims 1 to 7, further comprising:

and if the signal to be detected comprises the target SOB error code signal, correcting the target SOB error code signal and the initial EOB error code signal.

9. The method according to any one of claims 1,3 to 7, wherein determining whether a target SOB error signal exists from the signal under test according to the accumulated error comprises:

If the accumulated error corresponding to any one of the signals to be detected is not smaller than the accumulated error threshold, determining that the target SOB error signal does not exist in the signals to be detected;

And if the target SOB error code signal does not exist in the signal to be detected, determining that the initial EOB error code signal is a non-error code signal.

10. An error code detection method, characterized in that the method further comprises:

And determining whether the target signal is the initial EOB error signal according to the first equalization result and the second equalization result.

11. The method of claim 10, wherein the continuous plurality of signals comprises:

The target signal and a signal preceding the target signal; or alternatively

The target signal and a signal subsequent to the target signal.

12. An error code detection apparatus, comprising:

An acquisition unit for performing the acquisition operation in the method of any one of claims 1 to 9;

a processing unit for performing operations other than the acquisition operations in the method of any one of claims 1 to 9.

13. An error code detection apparatus, comprising:

an acquisition unit for performing the acquisition operation in the method of claim 10 or 11;

A processing unit configured to perform operations other than the acquiring operations in the method according to claim 10 or 11.

14. A communication device, comprising: a processor and a memory;

the processor has stored instructions which, when run on the processor, implement the method of any one of claims 1 to 11.

15. A chip, comprising: a processing unit and a power supply circuit;

The power supply circuit powers the processing unit for performing the method of any one of claims 1 to 11.

16. A computer readable storage medium storing instructions which, when run on a processor, implement the method of any one of claims 1 to 11.

17. A computer program product, characterized in that the method of any of claims 1 to 11 is implemented when the computer program product is executed on a processor.