CN118069070A - Write-back method and device for reducing soft error rate of memory - Google Patents
Write-back method and device for reducing soft error rate of memory Download PDFInfo
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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Abstract
The invention discloses a write-back method and a device for reducing the soft error rate of a memory, which are characterized in that whether a read/write command request is initiated by a memory controller or not and whether a periodic read/write timer meets the set periodic read/write time is detected, two error detection and correction circuits are adopted to respectively carry out read/write operation and periodic read/write operation on a memory block in a memory array according to the detection result control, so that the data is ensured to be executed for at least one time in the specified time, the stability of the data is greatly improved, the error data in the memory array can be corrected in time, and the correctness of the data in a frequent reading or long-term idle state is ensured. The method of the invention can correct the error data in the storage array in time while ensuring the access instantaneity, and reduce the error accumulation number of the data in the space environment, thereby greatly reducing the soft error rate of the memory.
Description
Technical Field
The invention belongs to the technical field of memories, and particularly relates to a write-back method and device for reducing soft error rate of a memory.
Background
When the memory works in severe environments such as electromagnetism, outer space and the like, data stored in the memory can be overturned, so that the electronic system in which the memory is positioned is abnormal in function, such as data errors, procedure errors and the like. In this case, many methods for protecting the original data from being damaged are proposed by design engineers, and it is common to introduce Error DETECTING AND Correction (EDAC) circuits to write back the data during design.
The existing periodic read/write-back technology can regularly refresh data through an EDAC circuit, so that the correctness of the data is ensured. Under this technique, the memory will automatically correct errors and write back the data in a set time. If the set period is too short, the technology not only can compete with the read-write operation of the chip more frequently, but also can carry out excessive operation on correct data, so that the circuit power consumption is overlarge; if the set period is too long, there are multiple data that have flipped during the period and are out of the range of the number of bits that the EDAC circuit has correct, which can lead to data errors.
The prior art cannot meet the flexible application of an aerospace chip in various scenes in a space environment. If the chip is frequently reading data, the periodic read/write-back technique will compete with the read operation, and if the write-back operation is preferentially selected, the read speed will be slow; if the read operation is preferred, this results in the chip not writing back in the cycle, and possibly reading erroneous data. And when the chip stores data for a long time and does not read, the read-back writing technology cannot maintain the accuracy of the data.
Disclosure of Invention
Aiming at the technical problems in the prior art, the invention provides a write-back method for reducing the soft error rate of a memory.
In order to solve the problems, the technical scheme of the invention is as follows:
in one aspect, the present invention provides a write-back method for reducing a soft error rate of a memory, including:
detecting whether a current memory controller initiates a read/write command request or not, and detecting whether a current cycle read/write-back timer meets a set cycle read/write-back time or not;
judging whether the current memory array is executing periodic read/write back operation or not according to whether the current periodic read/write back timer meets the set periodic read/write back time;
If the current memory array is executing periodic read/write operation, and at the same time, the memory controller sends a read/write command request, and when the memory block corresponding to the selected address in the read/write command request and the memory block selected by the periodic read/write operation are the same memory block, for the periodic read/write operation being executed by the current memory array, the second error detection and correction circuit is controlled to suspend the memory block selected by the periodic read/write operation, and the next memory block in the memory array is selected to perform periodic read/write operation; for a read/write command request initiated by a memory controller, the memory array performs a read/write operation in the read/write command request initiated by the memory controller, wherein the read/write command request initiated by the memory controller includes a read command request and a write command request, and the read operation corresponding to the read command request is performed by the first error detection and correction circuit;
If the current memory array is executing periodic read/write operation, at the same time, the memory controller sends a read/write command request, and when the memory block corresponding to the selected address in the read/write command request and the memory block selected by the periodic read/write operation are different memory blocks, the memory controller initiates the read/write command request to the memory controller, and the memory array executes the read/write operation in the read/write command request initiated by the memory controller; for the periodic read/write operation being executed by the current memory array, if the periodic read/write operation has not executed the memory block corresponding to the selected address in the read/write command request, the second error detection and correction circuit skips the memory block corresponding to the selected address in the read/write command request, and sequentially decodes, detects and corrects the data of other memory blocks in the memory array; if the periodic read/write operation has been performed on the memory block corresponding to the selected address in the read/write command request, the second error detection and correction circuit continues to perform the periodic read/write operation.
Further, the memory array performs read/write operations in read/write command requests initiated by the memory controller, the method comprising:
Judging whether a read/write command request initiated by the memory controller is a read command request or a write command request;
if the memory controller initiates the write command request, the memory array performs a write operation corresponding to the write command request initiated by the memory controller, including: after encoding the data into a check code, writing the data and the check code into a corresponding storage block in the storage array according to a selected address in a write command request;
If the memory controller initiates the read command request, the memory array performs a read operation corresponding to the read command request initiated by the memory controller, including: the method comprises the steps that a read memory controller initiates all data in a memory block corresponding to a selected address in a read command request, a first error detection and correction circuit decodes, detects and corrects the data, and if the data is correct, the data is correctly output; if the data has errors and can be corrected, reporting the data to a memory controller, correcting the data, writing the corrected correct data back to the original address, and outputting the corrected correct data; if the data has errors and cannot be corrected, reporting the data errors to a memory controller.
In one aspect, a write-back device for reducing a soft error rate of a memory is provided, including:
A memory array including a plurality of memory blocks for storing data;
a periodic read/write back timer for periodically transmitting periodic read/write back commands;
The judging device is used for detecting whether the current memory controller initiates a read/write command request, detecting whether the current periodic read/write timer meets the set periodic read/write time and whether the current memory array is executing periodic read/write operation, and feeding back the detection result to the memory controller;
the memory controller is used for initiating a read/write command request, and simultaneously controlling the memory array to execute periodic read/write operation and controlling the memory array to execute the read/write operation in the read/write command request initiated by the memory controller according to the detection result of the determiner;
the first error detection and correction circuit is used for executing the read operation corresponding to the read command request initiated by the memory controller under the control of the memory controller;
and the second error detection and correction circuit is used for executing periodic read/write operation on the memory blocks in the memory array under the memory controller when the periodic read/write timer meets the set periodic read/write time.
Compared with the prior art, the invention has the following technical effects:
According to the invention, whether a read/write command request is initiated by a memory controller and whether a periodic read/write timer meets a set periodic read/write time is detected, two Error DETECTING AND Correction (EDAC) circuits are used for respectively performing read/write operation and periodic read/write operation on memory blocks in a memory array according to detection result control, and proper write operation is selected for writing back error data. The invention can ensure that the data is executed for at least one time in the set time, greatly improves the stability of the data, can correct the error data in the storage array in time, and ensures the correctness of the data in the frequently read or long-term idle state. The method of the invention can correct the error data in the storage array in time while ensuring the access instantaneity, and reduce the error accumulation number of the data in the space environment, thereby greatly reducing the soft error rate of the memory.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a write-back device for reducing soft error rate of a memory according to an embodiment;
FIG. 2 is a flow chart of a read/write operation according to an embodiment of the present application;
FIG. 3 is a flow chart of a periodic read/write-back operation according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the spirit of the present disclosure will be clearly described in the following drawings and detailed description, and any person skilled in the art, after having appreciated the embodiments of the present disclosure, may make alterations and modifications by the techniques taught by the present disclosure without departing from the spirit and scope of the present disclosure. The exemplary embodiments of the present invention and the descriptions thereof are intended to illustrate the present invention, but not to limit the present invention.
In one embodiment, a write-back method for reducing a soft error rate of a memory is provided, including:
detecting whether a current memory controller initiates a read/write command request or not, and detecting whether a current cycle read/write-back timer meets a set cycle read/write-back time or not;
judging whether the current memory array is executing periodic read/write back operation or not according to whether the current periodic read/write back timer meets the set periodic read/write back time;
If the current memory array is executing periodic read/write operation, and at the same time, the memory controller sends a read/write command request, and when the memory block corresponding to the selected address in the read/write command request and the memory block selected by the periodic read/write operation are the same memory block, for the periodic read/write operation being executed by the current memory array, the second error detection and correction circuit is controlled to suspend the memory block selected by the periodic read/write operation, and the next memory block in the memory array is selected to perform periodic read/write operation; for a read/write command request initiated by a memory controller, the memory array performs a read/write operation in the read/write command request initiated by the memory controller, wherein the read/write command request initiated by the memory controller includes a read command request and a write command request, and the read operation corresponding to the read command request is performed by the first error detection and correction circuit;
If the current memory array is executing periodic read/write operation, at the same time, the memory controller sends a read/write command request, and when the memory block corresponding to the selected address in the read/write command request and the memory block selected by the periodic read/write operation are different memory blocks, the memory controller initiates the read/write command request to the memory controller, and the memory array executes the read/write operation in the read/write command request initiated by the memory controller; for the periodic read/write operation being executed by the current memory array, if the periodic read/write operation has not executed the memory block corresponding to the selected address in the read/write command request, the second error detection and correction circuit skips the memory block corresponding to the selected address in the read/write command request, and sequentially decodes, detects and corrects the data of other memory blocks in the memory array; if the periodic read/write operation has been performed on the memory block corresponding to the selected address in the read/write command request, the second error detection and correction circuit continues to perform the periodic read/write operation. If the memory array has N total memory blocks, if the current memory array is executing periodic read/write operation, the periodic read/write operation is performed on a block-by-block basis from the first memory block to the N memory block; in this case, the memory controller sends a read/write command request, where the memory block corresponding to the selected address in the read/write command request is the xth block, for example, the memory block number < X where the periodic read/write operation is being performed, i.e., the "periodic read/write operation" does not yet perform the periodic read/write operation of the memory block corresponding to the selected address in the read/write command request. If the number of the memory block being executed by the periodic read/write operation is greater than X, the "periodic read/write operation" has already been executed by the memory block corresponding to the selected address in the read/write command request.
The flow of memory controller initiated read/write command requests, in which the memory array performs read/write operations, is shown in FIG. 2, includes:
when the memory controller sends a write command request, the memory array executes a write operation corresponding to the write command request initiated by the memory controller, and the write operation flow is as follows:
(1.1) a write operation begins;
(1.2) encoding the data into a check code;
(1.3) writing the data and the check code into a storage block, wherein the storage block stores the data;
the storage block is a storage block corresponding to a selected address in the write command request.
(1.4) The write operation ends.
When the memory controller sends a read command request, the memory array starts to execute a read operation corresponding to the read command request initiated by the memory controller, and the flow of the read operation is as follows:
(2.1) starting a read operation;
(2.2) reading all data (including data in the selected address and check code) in the memory block corresponding to the selected address in the read command request initiated by the memory controller;
(2.3) decoding data and judging errors;
the first error detecting and correcting circuit completes data decoding and error judgment.
(2.4) If the data has no error, outputting the correct data, and ending the reading operation;
if the data has errors, the first error detection and correction circuit judges whether the error bit number exceeds the correction bit number, if the data has errors and can be corrected, the data is corrected, corrected correct data is output, and the reading operation is finished; and simultaneously reporting the memory controller, wherein the memory controller sends a write command request, the memory array executes write operation corresponding to the write command request initiated by the memory controller, and the corrected correct data is written back to the original address in the memory array, wherein the write operation flow is described in detail in the foregoing and is not repeated here. If the number of data errors exceeds the number of correction bits, the data is erroneous and uncorrectable, and the data errors are reported to the memory controller.
The periodic read/write timer sets a period T, and sends periodic read/write commands every other period T, and the flow of the periodic read/write operations performed by the memory array is shown in fig. 3, and includes:
(3.1) periodic read/write back operations begin;
(3.2) selecting the Y-th data in the X-th memory block in the memory array, wherein x=0, y=0 represents the first data in the first memory block;
(3.3) the second error detection and correction circuit performs an error correction and detection procedure on the data:
(3.3.1) reading the data and the check code;
(3.3.2) data decoding and error determination;
(3.3.3) if the data is error-free, not processed; if the data has errors, the second error detection and correction circuit judges whether the error bit number exceeds the correction bit number, if the data has errors and can be corrected, the data is corrected and reported to the memory controller, the memory controller sends a write command request, the memory array executes the write operation corresponding to the write command request initiated by the memory controller, and the corrected correct data is written back to the original address in the memory array, wherein the write operation flow is described in detail above and is not repeated here. If the number of data errors exceeds the number of correction bits, the data is erroneous and uncorrectable, and the data errors are reported to the memory controller.
(3.4) Judging whether Y is smaller than the number of data stored in the X-th memory block, if not, turning to the step (3.5), if so, that is, if Y is smaller than the number of data stored in the xth storage block, updating Y, and making y=y+1, reading the next data in the xth storage block, and returning to the step (3.3);
(3.5) judging whether X is smaller than the number of storage blocks in the storage array, if not, ending the cycle write-back operation, and starting the timing of the next cycle T; if yes, that is, X is smaller than the number of the storage blocks in the storage array, updating X, enabling X=X+1 and Y=0, reading data in the next storage block in the storage array, and returning to the step (3.3). Typically, in the memory technology field, the first memory block or data is numbered "0", e.g., the first 8 bits of data are "000,001,010,011,100,101,110,111;" binary "corresponds to" 0,1,2,3,4,5,6,7; "decimal", respectively. Thus, when the first data in the next memory block in the memory array is read, let x=x+1, y=0.
The invention ensures that data is refreshed at least once in a specified time through periodic read/write back operation. When the data is read out or stored, the method can correct and refresh the data in time, thereby improving the stability of the data, further reducing the soft error rate of the memory, and simultaneously taking into account the timeliness of the access of the external memory controller.
Meanwhile, the invention also detects whether the current memory controller initiates a read/write command request, detects whether the current periodic read/write timer meets the set periodic read/write time, judges whether the read/write command request initiated by the memory controller collides with the periodic read/write command sent by the periodic read/write timer, and sets a scheme for resolving the conflict, wherein the scheme comprises that the current memory array is executing periodic read/write operation, and at the same time, the memory controller sends the read/write command request, and the memory block corresponding to the selected address in the read/write command request and the memory block selected by the periodic read/write operation are the same memory block. When collision occurs, the periodic read/write command avoids the storage block selected by the read/write command request, so that the instantaneity of external read/write operation is ensured; and before the data is output in the read operation, an Error DETECTING AND Correction (EDAC) process is executed to ensure the accuracy of the data read.
Considering that by detecting whether the current memory controller initiates a read/write command request, whether the current periodic read/write timer meets the set periodic read/write time or not, and the situation that the read/write command request initiated by the memory controller and the periodic read/write command issued by the periodic read/write timer do not conflict exists, the invention further designs the processing flow under various situations that no conflict exists, and specifically comprises the following steps:
if the current memory controller does not initiate a read/write command request and the periodic read/write timer does not meet the set periodic read/write time, the data of the memory array is in a hold state.
If the current read/write command request initiated by the memory controller is a write command request and the periodic read/write back timer does not meet the set periodic read/write back time, the memory array performs a write operation corresponding to the write command request initiated by the memory controller, including: after the data is encoded into the check code, the data and the check code are written into the corresponding storage blocks in the storage array according to the selected address in the write command request.
If the current read/write command request initiated by the memory controller is a read command request and the periodic read/write back timer does not meet the set periodic read/write back time, the memory array performs a read operation corresponding to the read command request initiated by the memory controller, including: the method comprises the steps that a read memory controller initiates all data in a memory block corresponding to a selected address in a read command request, a first error detection and correction circuit decodes, detects and corrects the data, and if the data is correct, the data is correctly output; if the data has errors and can be corrected, reporting the data to a memory controller, correcting the data, writing the corrected correct data back to the original address, and outputting the corrected correct data; if the data has errors and cannot be corrected, reporting the data errors to a memory controller. The processing procedure of reporting the memory controller, correcting the data and writing the corrected correct data back to the original address is as follows: and reporting the write command request to the memory controller, wherein the memory controller sends the write command request, the memory array executes the write operation corresponding to the write command request initiated by the memory controller, and the corrected correct data is written back to the original address in the memory array, wherein the write operation flow is described in detail above and is not repeated here.
If the current memory controller does not initiate a read/write command request and the periodic read/write timer meets the set periodic read/write time, the memory array executes periodic read/write operation, the data of each address are sequentially read out from the memory blocks of the memory array according to the set order, the second error detection and correction unit decodes, detects and corrects the selected data, and if the data is correct, the data is not processed; if the data has errors and can be corrected, reporting the data to a memory controller, correcting the data and writing the corrected correct data back to the original address; if the data has errors and cannot be corrected, reporting the data errors to a memory controller. The processing procedure of reporting the memory controller, correcting the data and writing the corrected correct data back to the original address is as follows: and reporting the write command request to the memory controller, wherein the memory controller sends the write command request, the memory array executes the write operation corresponding to the write command request initiated by the memory controller, and the corrected correct data is written back to the original address in the memory array, wherein the write operation flow is described in detail above and is not repeated here.
Referring to fig. 1, there is provided a write-back apparatus for reducing a soft error rate of a memory, including:
A memory array including a plurality of memory blocks for storing data;
a periodic read/write back timer for periodically transmitting periodic read/write back commands;
The judging device is used for detecting whether the current memory controller initiates a read/write command request, detecting whether the current periodic read/write timer meets the set periodic read/write time and whether the current memory array is executing periodic read/write operation, and feeding back the detection result to the memory controller;
And a memory controller for initiating a read/write command request, and simultaneously controlling the memory array to perform periodic read/write operations and controlling the memory array to perform read/write operations in the read/write command request initiated by the memory controller according to a detection result of the determiner, comprising: if the current memory array is executing periodic read/write operation, and at the same time, the memory controller sends a read/write command request, and when the memory block corresponding to the selected address in the read/write command request and the memory block selected by the periodic read/write operation are the same memory block, for the periodic read/write operation being executed by the current memory array, the second error detection and correction circuit is controlled to suspend the memory block selected by the periodic read/write operation, and the next memory block in the memory array is selected to perform periodic read/write operation; for a read/write command request initiated by a memory controller, the memory array performs a read/write operation in the read/write command request initiated by the memory controller, wherein the read/write command request initiated by the memory controller includes a read command request and a write command request, and the read operation corresponding to the read command request is performed by the first error detection and correction circuit;
If the current memory array is executing periodic read/write operation, at the same time, the memory controller sends a read/write command request, and when the memory block corresponding to the selected address in the read/write command request and the memory block selected by the periodic read/write operation are different memory blocks, the memory controller initiates the read/write command request to the memory controller, and the memory array executes the read/write operation in the read/write command request initiated by the memory controller; for the periodic read/write operation being executed by the current memory array, if the periodic read/write operation has not executed the memory block corresponding to the selected address in the read/write command request, the second error detection and correction circuit skips the memory block corresponding to the selected address in the read/write command request, and sequentially decodes, detects and corrects the data of other memory blocks in the memory array; if the periodic read/write operation has been performed on the memory block corresponding to the selected address in the read/write command request, the second error detection and correction circuit continues to perform the periodic read/write operation.
A first error detection and correction circuit, EDAC1, for performing a read operation under control of the memory controller corresponding to a read command request initiated by the memory controller;
The second error detection and correction circuit, EDAC2, is configured to perform a periodic read/write back operation on a memory block in the memory array under the memory controller when the periodic read/write back timer satisfies a set periodic read/write back time.
The read/write operation flow and the periodic read/write operation flow in the write-back device for reducing the soft error rate of the memory are the same as those of the method in the foregoing embodiments, and the flowcharts are shown in fig. 2 and 3, respectively.
The write-back device for reducing the soft error rate of the memory also considers that by detecting whether the current memory controller initiates the read/write command request, whether the current periodic read/write timer meets the set periodic read/write time is detected, and the condition that the read/write command request initiated by the memory controller does not conflict with the periodic read/write command issued by the periodic read/write timer exists, so that the processing flow under various conditions that no conflict exists is further designed, and the specific design scheme is the same as the method flow in the previous embodiment and is not repeated here.
The invention can ensure that the data is refreshed at least once in a set time. When the data is read out or stored, the method can correct and refresh the data in time, thereby improving the stability of the data, further reducing the soft error rate of the memory, and simultaneously taking into account the timeliness of the access of the external memory controller.
The invention is not a matter of the known technology.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A write-back method for reducing a soft error rate of a memory, comprising:
detecting whether a current memory controller initiates a read/write command request or not, and detecting whether a current cycle read/write-back timer meets a set cycle read/write-back time or not;
judging whether the current memory array is executing periodic read/write back operation or not according to whether the current periodic read/write back timer meets the set periodic read/write back time;
If the current memory array is executing periodic read/write operation, and at the same time, the memory controller sends a read/write command request, and when the memory block corresponding to the selected address in the read/write command request and the memory block selected by the periodic read/write operation are the same memory block, for the periodic read/write operation being executed by the current memory array, the second error detection and correction circuit is controlled to suspend the memory block selected by the periodic read/write operation, and the next memory block in the memory array is selected to perform periodic read/write operation; for a read/write command request initiated by a memory controller, the memory array performs a read/write operation in the read/write command request initiated by the memory controller, wherein the read/write command request initiated by the memory controller includes a read command request and a write command request, and the read operation corresponding to the read command request is performed by the first error detection and correction circuit;
If the current memory array is executing periodic read/write operation, at the same time, the memory controller sends a read/write command request, and when the memory block corresponding to the selected address in the read/write command request and the memory block selected by the periodic read/write operation are different memory blocks, the memory controller initiates the read/write command request to the memory controller, and the memory array executes the read/write operation in the read/write command request initiated by the memory controller; for the periodic read/write operation being executed by the current memory array, if the periodic read/write operation has not executed the memory block corresponding to the selected address in the read/write command request, the second error detection and correction circuit skips the memory block corresponding to the selected address in the read/write command request, and sequentially decodes, detects and corrects the data of other memory blocks in the memory array; if the periodic read/write operation has been performed on the memory block corresponding to the selected address in the read/write command request, the second error detection and correction circuit continues to perform the periodic read/write operation.
2. The method of claim 1, wherein the memory array performs read/write operations in read/write command requests initiated by the memory controller, the method comprising:
Judging whether a read/write command request initiated by the memory controller is a read command request or a write command request;
if the memory controller initiates the write command request, the memory array performs a write operation corresponding to the write command request initiated by the memory controller, including: after encoding the data into a check code, writing the data and the check code into a corresponding storage block in the storage array according to a selected address in a write command request;
If the memory controller initiates the read command request, the memory array performs a read operation corresponding to the read command request initiated by the memory controller, including: the method comprises the steps that a read memory controller initiates all data in a memory block corresponding to a selected address in a read command request, a first error detection and correction circuit decodes, detects and corrects the data, and if the data is correct, the data is correctly output; if the data has errors and can be corrected, reporting the data to a memory controller, correcting the data, writing the corrected correct data back to the original address, and outputting the corrected correct data; if the data has errors and cannot be corrected, reporting the data errors to a memory controller.
3. The write-back method for reducing a soft error rate of a memory according to claim 1 or 2, further comprising: if the current memory controller does not initiate a read/write command request and the periodic read/write timer does not meet the set periodic read/write time, the data of the memory array is in a hold state.
4. The write-back method for reducing a soft error rate of a memory according to claim 1, further comprising: if the current read/write command request initiated by the memory controller is a write command request and the periodic read/write back timer does not meet the set periodic read/write back time, the memory array performs a write operation corresponding to the write command request initiated by the memory controller, including: after the data is encoded into the check code, the data and the check code are written into the corresponding storage blocks in the storage array according to the selected address in the write command request.
5. The write-back method for reducing a soft error rate of a memory according to claim 1, further comprising: if the current read/write command request initiated by the memory controller is a read command request and the periodic read/write back timer does not meet the set periodic read/write back time, the memory array performs a read operation corresponding to the read command request initiated by the memory controller, including: the method comprises the steps that a read memory controller initiates all data in a memory block corresponding to a selected address in a read command request, a first error detection and correction circuit decodes, detects and corrects the data, and if the data is correct, the data is correctly output; if the data has errors and can be corrected, reporting the data to a memory controller, correcting the data, writing the corrected correct data back to the original address, and outputting the corrected correct data; if the data has errors and cannot be corrected, reporting the data errors to a memory controller.
6. The write-back method for reducing a soft error rate of a memory according to claim 1, further comprising: if the current memory controller does not initiate a read/write command request and the periodic read/write timer meets the set periodic read/write time, the memory array executes periodic read/write operation, the data of each address are sequentially read out from the memory blocks of the memory array according to the set order, the second error detection and correction unit decodes, detects and corrects the selected data, and if the data is correct, the data is not processed; if the data has errors and can be corrected, reporting the data to a memory controller, correcting the data and writing the corrected correct data back to the original address; if the data has errors and cannot be corrected, reporting the data errors to a memory controller.
7. A write-back apparatus for reducing a soft error rate of a memory, comprising:
A memory array including a plurality of memory blocks for storing data;
a periodic read/write back timer for periodically transmitting periodic read/write back commands;
The judging device is used for detecting whether the current memory controller initiates a read/write command request, detecting whether the current periodic read/write timer meets the set periodic read/write time and whether the current memory array is executing periodic read/write operation, and feeding back the detection result to the memory controller;
And a memory controller for initiating a read/write command request, and simultaneously controlling the memory array to perform periodic read/write operations and controlling the memory array to perform read/write operations in the read/write command request initiated by the memory controller according to a detection result of the determiner, comprising: if the current memory array is executing periodic read/write operation, and at the same time, the memory controller sends a read/write command request, and when the memory block corresponding to the selected address in the read/write command request and the memory block selected by the periodic read/write operation are the same memory block, for the periodic read/write operation being executed by the current memory array, the second error detection and correction circuit is controlled to suspend the memory block selected by the periodic read/write operation, and the next memory block in the memory array is selected to perform periodic read/write operation; for a read/write command request initiated by a memory controller, the memory array performs a read/write operation in the read/write command request initiated by the memory controller, wherein the read/write command request initiated by the memory controller includes a read command request and a write command request, and the read operation corresponding to the read command request is performed by the first error detection and correction circuit;
If the current memory array is executing periodic read/write operation, at the same time, the memory controller sends a read/write command request, and when the memory block corresponding to the selected address in the read/write command request and the memory block selected by the periodic read/write operation are different memory blocks, the memory controller initiates the read/write command request to the memory controller, and the memory array executes the read/write operation in the read/write command request initiated by the memory controller; for the periodic read/write operation being executed by the current memory array, if the periodic read/write operation has not executed the memory block corresponding to the selected address in the read/write command request, the second error detection and correction circuit skips the memory block corresponding to the selected address in the read/write command request, and sequentially decodes, detects and corrects the data of other memory blocks in the memory array; if the periodic read/write operation has been performed on the memory block corresponding to the selected address in the read/write command request, the second error detection and correction circuit continues to perform the periodic read/write operation;
the first error detection and correction circuit is used for executing the read operation corresponding to the read command request initiated by the memory controller under the control of the memory controller;
and the second error detection and correction circuit is used for executing periodic read/write operation on the memory blocks in the memory array under the memory controller when the periodic read/write timer meets the set periodic read/write time.
8. The write-back apparatus for reducing a soft error rate of a memory of claim 7, wherein the memory array performs read/write operations in read/write command requests initiated by the memory controller, the method comprising:
Judging whether a read/write command request initiated by the memory controller is a read command request or a write command request;
if the memory controller initiates the write command request, the memory array performs a write operation corresponding to the write command request initiated by the memory controller, including: after encoding the data into a check code, writing the data and the check code into a corresponding storage block in the storage array according to a selected address in a write command request;
If the memory controller initiates the read command request, the memory array performs a read operation corresponding to the read command request initiated by the memory controller, including: the method comprises the steps that a read memory controller initiates all data in a memory block corresponding to a selected address in a read command request, a first error detection and correction circuit decodes, detects and corrects the data, and if the data is correct, the data is correctly output; if the data has errors and can be corrected, reporting the data to a memory controller, correcting the data, writing the corrected correct data back to the original address, and outputting the corrected correct data; if the data has errors and cannot be corrected, reporting the data errors to a memory controller.
9. The apparatus for reducing soft error rate of memory according to claim 8, wherein if the detection result of the decision maker is: when the current memory controller does not initiate a read/write command request and the periodic read/write back timer does not meet the set periodic read/write back time, the data of the memory array is in a hold state.
10. The apparatus for reducing soft error rate of memory according to claim 8, wherein if the detection result of the decision maker is: when the current read/write command request initiated by the memory controller is a write command request and the periodic read/write back timer does not meet the set periodic read/write back time, the memory array executes a write operation corresponding to the write command request initiated by the memory controller, including: after encoding the data into a check code, writing the data and the check code into a corresponding storage block in the storage array according to a selected address in a write command request;
If the detection result of the decision device is: when the current read/write command request initiated by the memory controller is a read command request and the periodic read/write back timer does not meet the set periodic read/write back time, the memory array performs a read operation corresponding to the read command request initiated by the memory controller, including: the method comprises the steps that a read memory controller initiates all data in a memory block corresponding to a selected address in a read command request, a first error detection and correction circuit decodes, detects and corrects the data, and if the data is correct, the data is correctly output; if the data has errors and can be corrected, reporting the data to a memory controller, correcting the data, writing the corrected correct data back to the original address, and outputting the corrected correct data; if the data has errors and cannot be corrected, reporting the data errors to a memory controller;
If the detection result of the decision device is: the current memory controller does not initiate a read/write command request and the periodic read/write timer meets the set periodic read/write time, the memory array executes periodic read/write operation, data of each address are sequentially read out from a memory block of the memory array according to a set order, the selected data are decoded, detected and corrected by the second error detection and correction unit, and if the data are correct, the data are not processed; if the data has errors and can be corrected, reporting the data to a memory controller, correcting the data and writing the corrected correct data back to the original address; if the data has errors and cannot be corrected, reporting the data errors to a memory controller.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070288707A1 (en) * | 2006-06-08 | 2007-12-13 | International Business Machines Corporation | Systems and methods for providing data modification operations in memory subsystems |
| CN103700396A (en) * | 2013-12-03 | 2014-04-02 | 中国航天科技集团公司第九研究院第七七一研究所 | SRAM (static random access memory)-oriented anti-SEU (single-event upset) error accumulation controller and method |
| CN104575589A (en) * | 2014-12-27 | 2015-04-29 | 中国电子科技集团公司第三十八研究所 | Radiation-resistant SRAM self-refresh circuit with high utilizable ratio, and self-refresh method of radiation-resistant SRAM self-refresh circuit |
| US20180033469A1 (en) * | 2015-05-20 | 2018-02-01 | Hitachi, Ltd. | Memory device |
| CN111694691A (en) * | 2020-06-10 | 2020-09-22 | 西安微电子技术研究所 | SRAM circuit with automatic write-back function after error correction and detection and write-back method |
-
2024
- 2024-04-17 CN CN202410463400.XA patent/CN118069070B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070288707A1 (en) * | 2006-06-08 | 2007-12-13 | International Business Machines Corporation | Systems and methods for providing data modification operations in memory subsystems |
| CN103700396A (en) * | 2013-12-03 | 2014-04-02 | 中国航天科技集团公司第九研究院第七七一研究所 | SRAM (static random access memory)-oriented anti-SEU (single-event upset) error accumulation controller and method |
| CN104575589A (en) * | 2014-12-27 | 2015-04-29 | 中国电子科技集团公司第三十八研究所 | Radiation-resistant SRAM self-refresh circuit with high utilizable ratio, and self-refresh method of radiation-resistant SRAM self-refresh circuit |
| US20180033469A1 (en) * | 2015-05-20 | 2018-02-01 | Hitachi, Ltd. | Memory device |
| CN111694691A (en) * | 2020-06-10 | 2020-09-22 | 西安微电子技术研究所 | SRAM circuit with automatic write-back function after error correction and detection and write-back method |
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