CN118060206B - Chip sorting method, device, equipment and storage medium - Google Patents
Chip sorting method, device, equipment and storage medium Download PDFInfo
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- CN118060206B CN118060206B CN202410435484.6A CN202410435484A CN118060206B CN 118060206 B CN118060206 B CN 118060206B CN 202410435484 A CN202410435484 A CN 202410435484A CN 118060206 B CN118060206 B CN 118060206B
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B07—SEPARATING SOLIDS FROM SOLIDS; SORTING
- B07C—POSTAL SORTING; SORTING INDIVIDUAL ARTICLES, OR BULK MATERIAL FIT TO BE SORTED PIECE-MEAL, e.g. BY PICKING
- B07C5/00—Sorting according to a characteristic or feature of the articles or material being sorted, e.g. by control effected by devices which detect or measure such characteristic or feature; Sorting by manually actuated devices, e.g. switches
- B07C5/34—Sorting according to other particular properties
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B07—SEPARATING SOLIDS FROM SOLIDS; SORTING
- B07C—POSTAL SORTING; SORTING INDIVIDUAL ARTICLES, OR BULK MATERIAL FIT TO BE SORTED PIECE-MEAL, e.g. BY PICKING
- B07C5/00—Sorting according to a characteristic or feature of the articles or material being sorted, e.g. by control effected by devices which detect or measure such characteristic or feature; Sorting by manually actuated devices, e.g. switches
- B07C5/36—Sorting apparatus characterised by the means used for distribution
- B07C5/361—Processing or control devices therefor, e.g. escort memory
- B07C5/362—Separating or distributor mechanisms
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The application relates to the technical field of chip testing, and provides a chip sorting method, a device, equipment and a storage medium. The method comprises the following steps: in the same time period, performing radiation control on a target chip based on a radiation control curve, performing temperature control on the target chip based on a temperature control curve, and acquiring test values of all parameters of the target chip in real time through a preset parameter detection device in the process of performing radiation control and temperature control on the target chip simultaneously to obtain test parameter information; determining a target interfered factor of the target chip based on standard parameter information and the test parameter information; and judging whether the target chip is qualified or not based on the target interfered factor. The method can improve the reliability of chip sorting.
Description
Technical Field
The present application relates to the field of chip testing technologies, and in particular, to a chip sorting method, apparatus, device, and storage medium.
Background
With the continuous development of electronic products, chips are increasingly widely applied in the modern technological field, and as core devices of the electronic products, the chip sorting is an essential link in the chip production process, but in the prior art, the performance of the chips is usually tested by adopting a static test method, namely, the performance of the chips is tested in a stable test environment, and the chips are sorted according to test results, so that the method for sorting the chips, namely, screening qualified chips, has the problem of low reliability.
Disclosure of Invention
The application provides a chip sorting method, a device, equipment and a storage medium, which are used for solving the problems set forth in the background technology.
In a first aspect, the present application provides a chip sorting method, including:
acquiring a target test text of a target chip; the test text comprises a radiation control curve, a temperature control curve and standard parameter information, wherein the standard parameter information comprises standard values of all performance parameters of the target chip, and the duration corresponding to the radiation control curve is the same as the duration corresponding to the temperature control curve;
in the same time period, performing radiation control on the target chip based on the radiation control curve, performing temperature control on the target chip based on the temperature control curve, and acquiring test values of all parameters of the target chip in real time through a preset parameter detection device in the process of performing radiation control and temperature control on the target chip simultaneously to obtain test parameter information;
Determining a target interfered factor of the target chip based on the standard parameter information and the test parameter information;
and judging whether the target chip is qualified or not based on the target interfered factor.
In a second aspect, the present application provides a chip sorting apparatus comprising:
the acquisition module is used for acquiring a target test text of the target chip; the test text comprises a radiation control curve, a temperature control curve and standard parameter information, wherein the standard parameter information comprises standard values of all performance parameters of the target chip, and the duration corresponding to the radiation control curve is the same as the duration corresponding to the temperature control curve;
The control module is used for carrying out radiation control on the target chip based on the radiation control curve and carrying out temperature control on the target chip based on the temperature control curve in the same time period, and acquiring test values of all parameters of the target chip in real time through a preset parameter detection device in the process of carrying out radiation control and temperature control on the target chip at the same time to obtain test parameter information;
The determining module is used for determining a target interfered factor of the target chip based on the standard parameter information and the test parameter information;
And the judging module is used for judging whether the target chip is qualified or not based on the target interfered factor.
In a third aspect, the present application provides a terminal device comprising a processor, a memory and a computer program stored on the memory and executable by the processor, wherein the computer program, when executed by the processor, implements the chip sorting method as described above.
In a fourth aspect, the present application provides a computer readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the chip sorting method as described above.
The application provides a chip sorting method, a chip sorting device, chip sorting equipment and a storage medium. Wherein the method comprises the following steps: acquiring a target test text of a target chip; the test text comprises a radiation control curve, a temperature control curve and standard parameter information, wherein the standard parameter information comprises standard values of all performance parameters of the target chip, and the duration corresponding to the radiation control curve is the same as the duration corresponding to the temperature control curve; in the same time period, performing radiation control on the target chip based on the radiation control curve, performing temperature control on the target chip based on the temperature control curve, and acquiring test values of all parameters of the target chip in real time through a preset parameter detection device in the process of performing radiation control and temperature control on the target chip simultaneously to obtain test parameter information; determining a target interfered factor of the target chip based on the standard parameter information and the test parameter information; and judging whether the target chip is qualified or not based on the target interfered factor. The method is favorable for accurately judging whether the target chip accords with the use environment of the electronic product, namely, whether the use performance of the target chip is stable under the condition of temperature and radiation intensity change, is favorable for improving the reliability of a chip sorting method, and ensures that the target chip can be normally used in the electronic product when being judged to be a qualified product.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a chip sorting method according to an embodiment of the present application;
Fig. 2 is a schematic block diagram of a chip sorting apparatus according to an embodiment of the present application;
fig. 3 is a schematic block diagram of a structure of a terminal device according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The flow diagrams depicted in the figures are merely illustrative and not necessarily all of the elements and operations/steps are included or performed in the order described. For example, some operations/steps may be further divided, combined, or partially combined, so that the order of actual execution may be changed according to actual situations.
It is also to be understood that the terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
With the continuous development of electronic products, chips are increasingly widely applied in the modern technological field, and as core devices of the electronic products, the chip sorting is an essential link in the chip production process, but in the prior art, the performance of the chips is usually tested by adopting a static test method, namely, the performance of the chips is tested in a stable test environment, and the chips are sorted according to test results, so that the method for sorting the chips, namely, screening qualified chips, has the problem of low reliability. To this end, the present application provides a chip sorting method, apparatus, device and storage medium to solve the above-mentioned problems.
Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
Referring to fig. 1, fig. 1 is a flow chart of a chip sorting method according to an embodiment of the application, and as shown in fig. 1, the chip sorting method according to an embodiment of the application includes steps S100 to S400.
Step S100, obtaining a target test text of a target chip; the test text comprises a radiation control curve, a temperature control curve and standard parameter information, wherein the standard parameter information comprises standard values of all performance parameters of the target chip, and the duration corresponding to the radiation control curve is the same as the duration corresponding to the temperature control curve. Wherein the performance parameters include voltage, current, power consumption, resistance, clock frequency, delay time, timing relationship, and the like.
And step 200, performing radiation control on the target chip based on the radiation control curve in the same time period, performing temperature control on the target chip based on the temperature control curve, and acquiring test values of all parameters of the target chip in real time through a preset parameter detection device in the process of performing radiation control and temperature control on the target chip simultaneously to obtain test parameter information.
And step S300, determining a target interfered factor of the target chip based on the standard parameter information and the test parameter information.
And step 400, judging whether the target chip is qualified or not based on the target interfered factor.
In this embodiment, as described in step S100 above, a target test text of a target chip is acquired, specifically, first, a model of the target chip is acquired, and then the target test text is matched in a preset database based on the model.
As described in step S200, after the target test text is obtained, in the same period of time, radiation control is performed on the target chip based on the radiation control curve, temperature control is performed on the target chip based on the temperature control curve, and in the process of performing radiation control and temperature control on the target chip simultaneously, test values of each parameter of the target chip are obtained in real time through a preset parameter detection device, so as to obtain test parameter information. Specifically, when the target chip is sorted, the target chip is fixed on a test circuit board, then, in the same time period, a preset radiation adjusting device is controlled to adjust the radiation intensity of the target chip based on the radiation control curve, a preset temperature adjusting device is controlled to adjust the temperature of the target chip based on the temperature control curve, and in the process of simultaneously carrying out radiation control and temperature control on the target chip, the test value of each parameter of the target chip is obtained in real time through a preset parameter detecting device, so that test parameter information is obtained. It can be understood that the radiation control curve and the temperature control curve each comprise an ascending stage, a descending stage and a stable stage, and the radiation control curve and the temperature control curve are provided with a plurality of different stages, so that the influence of radiation change and temperature change on each performance parameter of a target chip can be accurately detected, and the reliability of chip sorting can be improved.
After obtaining the test parameter information, the target interfered factor of the target chip is determined based on the standard parameter information and the test parameter information as described in step S300. Specifically, first, an initial interfered factor of each performance parameter of the target chip is determined based on the standard parameter information and the test parameter information, and then, the largest initial interfered factor among the initial interfered factors is determined as a target interfered factor.
After the target interfered factor is obtained, whether the target chip is qualified is determined based on the target interfered factor as described in step S400. Specifically, firstly, comparing the target interfered factor with a preset interfered factor, and then, if the target interfered factor is not greater than the preset interfered factor, determining that the target chip is qualified.
It can be understood that, during the operation of the electronic product, the current of the circuit in the electronic product may generate a varying magnetic field, and meanwhile, a voltage difference exists between the circuits, which may cause the electronic product to generate electromagnetic radiation, thereby affecting the service performance of the chip. According to the method provided by the embodiment, the radiation control is performed on the target chip based on the radiation control curve, the temperature control is performed on the target chip based on the temperature control curve, and the test value of each parameter of the target chip is obtained in real time through the preset parameter detection device in the process of performing the radiation control and the temperature control on the target chip simultaneously, so that the test parameter information is obtained, whether the target chip accords with the use environment of an electronic product or not is facilitated to be accurately judged, namely, whether the use performance of the target chip is stable or not under the condition of temperature and radiation intensity change is facilitated to be improved, and the reliability of a chip sorting method is facilitated to be improved, so that the method can be normally used in the electronic product when the target chip is judged to be a qualified product.
In some embodiments, the obtaining the model of the target chip includes the following steps:
scanning the graphic code on the target chip by adopting a preset code scanning device to obtain an identification function and an identification form of the target chip;
Drawing a function curve of the identification function in a preset plane rectangular coordinate system, and mapping the identification table into the plane rectangular coordinate system based on a preset table mapping rule;
Determining a plurality of target cells in the identification table based on the function curve; wherein the function curve is contained in the region composed of each target cell;
and based on the positions of the target cells in the identification table, sequentially arranging the characters corresponding to the target cells to obtain the model.
Specifically, firstly, a preset code scanning device is adopted to scan the graphic codes on the target chip, so as to obtain the identification function and the identification table of the target chip. The graphic code can be a bar code or a two-dimensional code.
And then, after the identification function and the identification table are obtained, drawing a function curve of the identification function in a preset plane rectangular coordinate system, and mapping the identification table into the plane rectangular coordinate system based on a preset table mapping rule. For example, the rows of the table are parallel to the horizontal axis of the planar rectangular coordinate system, the columns of the table are parallel to the vertical axis of the planar rectangular coordinate system, and the lower right corner of the table is placed at the origin position of the planar rectangular coordinate system to map the identification table to the planar rectangular coordinate system.
Further, after the identification table is mapped into the planar rectangular coordinate system, a plurality of target cells are determined in the identification table based on the function curve.
Finally, after obtaining a plurality of target cells, sequentially arranging characters corresponding to the target cells based on the positions of the target cells in the identification table to obtain the model.
According to the method provided by the embodiment, the model of the target chip is obtained through the identification function and the identification table, and the model of the target chip can be effectively hidden, so that potential safety hazards existing after the model of the target chip is stolen by unauthorized personnel can be prevented.
In some embodiments, the preset database includes a plurality of test texts, and the matching the target test text in the preset database based on the model includes the following steps:
acquiring a preset decoding table; wherein the decoding table comprises character columns and digital columns;
Aiming at each character of the model, acquiring a hash value corresponding to the character based on a preset hash algorithm;
for each hash value, respectively carrying out decoding processing on each character of the hash value by utilizing the decoding table, and determining the hash value as a target hash value when decoding of each character of the hash value fails;
calculating products among the digits of the target hash values for the target hash values;
Sequentially arranging the target hash values based on products corresponding to the target hash values to obtain decryption passwords;
And respectively carrying out decryption processing on each test text based on the decryption passwords, and taking the test text successfully decrypted as the target test text.
Specifically, first, a preset decoding table is acquired in a preset database.
Then, after the decoding table is acquired, for each character of the model, acquiring a hash value corresponding to the character based on a preset hash algorithm.
And after obtaining the hash value corresponding to each character of the model, respectively decoding each character of the hash value by utilizing the decoding table for each hash value, and determining the hash value as a target hash value when decoding of each character of the hash value fails.
Further, after the target hash values are obtained, products among the digits of the target hash values are calculated for the respective target hash values.
Further, after obtaining the products corresponding to the target hash values, the target hash values are sequentially arranged based on the products corresponding to the target hash values, so as to obtain the decryption password.
And finally, after the decryption password is obtained, respectively carrying out decryption processing on each test text based on the decryption password, and taking the test text successfully decrypted as the target test text.
According to the method provided by the embodiment, on one hand, the encryption password is set for the target test text, so that the safety of the target test text is improved, and on the other hand, the decryption password is generated through the decoding table, the model and the hash algorithm, so that the difficulty in cracking the encryption password arranged on the target test text is improved, the safety of the target test text is further improved, and therefore the reliability of the chip sorting method is further improved.
In some embodiments, the determining the target interfered factor of the target chip based on the standard parameter information and the test parameter information includes the steps of:
calculating a first standard deviation among all test values corresponding to the performance parameters aiming at all the performance parameters of the target chip;
Aiming at each performance parameter of the target chip, based on a test time sequence corresponding to each test value of the performance parameter, sequentially arranging each test value of the performance parameter to obtain a test value sequence corresponding to the performance parameter, sequentially calculating first absolute values of differences between two adjacent test values in the test value sequence, and calculating second standard deviations between the first absolute values;
For each performance parameter of the target chip, calculating a second absolute value of a difference between a standard value corresponding to the performance parameter and each test value corresponding to the performance parameter, and determining the largest second absolute value in each second absolute value as a target absolute value;
Aiming at each performance parameter of the target chip, adding the first standard deviation, the second standard deviation and the target absolute value corresponding to the performance parameter to obtain an initial interfered factor corresponding to the performance parameter;
And determining the largest initial interfered factor as a target interfered factor in the initial interfered factors.
Specifically, first, for each performance parameter of the target chip, a first standard deviation between each test value corresponding to the performance parameter is calculated. It will be appreciated that the first standard deviation can reflect the stability of the performance parameter, the smaller the first standard deviation, the more stable the performance parameter.
And then, aiming at each performance parameter of the target chip, based on a test time sequence corresponding to each test value of the performance parameter, sequentially arranging each test value of the performance parameter to obtain a test value sequence corresponding to the performance parameter, sequentially calculating a first absolute value of a difference between two adjacent test values in the test value sequence, and calculating a second standard deviation between each first absolute value. It is understood that the second standard deviation can reflect the stability of the performance parameter variation trend, and the smaller the second standard deviation is, the more stable the performance parameter variation trend is.
Further, for each performance parameter of the target chip, a second absolute value of a difference between a standard value corresponding to the performance parameter and each test value corresponding to the performance parameter is calculated, and a largest second absolute value among the second absolute values is determined as a target absolute value.
Further, for each performance parameter of the target chip, adding the first standard deviation, the second standard deviation and the target absolute value corresponding to the performance parameter to obtain an initial interfered factor corresponding to the performance parameter.
And finally, determining the largest initial interfered factor as a target interfered factor in the initial interfered factors.
According to the method provided by the implementation, on one hand, for each performance parameter, the initial interfered factor corresponding to the performance parameter is obtained based on the first standard deviation, the second standard deviation and the target absolute value corresponding to the performance parameter, the initial interfered factor of the performance parameter is obtained based on the measurement of multiple factors, the reliability of the initial interfered factor is improved, on the other hand, the largest initial interfered factor is determined as the target interfered factor in each initial interfered factor, the reliability of the target interfered factor is improved, and the reliability of the chip sorting method is further improved.
Referring to fig. 2, fig. 2 is a schematic block diagram of a chip sorting apparatus 100 according to an embodiment of the present application, and as shown in fig. 2, the chip sorting apparatus 100 includes:
An obtaining module 110, configured to obtain a target test text of a target chip; the test text comprises a radiation control curve, a temperature control curve and standard parameter information, wherein the standard parameter information comprises standard values of all performance parameters of the target chip, and the duration corresponding to the radiation control curve is the same as the duration corresponding to the temperature control curve.
The control module 120 is configured to perform radiation control on the target chip based on the radiation control curve and perform temperature control on the target chip based on the temperature control curve in a same time period, and obtain test values of each parameter of the target chip in real time through a preset parameter detection device in a process of performing radiation control and temperature control on the target chip simultaneously, so as to obtain test parameter information.
A determining module 130, configured to determine a target interfered factor of the target chip based on the standard parameter information and the test parameter information.
And the judging module 140 is used for judging whether the target chip is qualified or not based on the target interfered factor.
It should be noted that, for convenience and brevity of description, the specific working process of the above-described apparatus and each module may refer to the corresponding process in the foregoing chip sorting method embodiment, which is not described herein again.
The chip sorting apparatus 100 provided in the above-described embodiment may be implemented in the form of a computer program that can be run on the terminal device 200 as shown in fig. 3.
Referring to fig. 3, fig. 3 is a schematic block diagram of a structure of a terminal device 200 according to an embodiment of the present application, where the terminal device 200 includes a processor 201 and a memory 202, and the processor 201 and the memory 202 are connected through a system bus 203, and the memory 202 may include a nonvolatile storage medium and an internal memory.
The non-volatile storage medium may store a computer program. The computer program comprises program instructions that, when executed by the processor 201, cause the processor 201 to perform any of the chip sorting methods described above.
The processor 201 is used to provide computing and control capabilities supporting the operation of the overall terminal device 200.
The internal memory provides an environment for the execution of a computer program in a non-volatile storage medium that, when executed by the processor 201, causes the processor 201 to perform any of the chip sorting methods described above.
It will be appreciated by those skilled in the art that the structure shown in fig. 3 is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation of the terminal device 200 related to the present application, and that a specific terminal device 200 may include more or less components than those shown in the drawings, or may combine some components, or have a different arrangement of components.
It should be appreciated that the Processor 201 may be a central processing unit (Central Processing Unit, CPU), and the Processor 201 may also be other general purpose processors, digital signal processors (DIGITAL SIGNAL processors, DSPs), application SPECIFIC INTEGRATED Circuits (ASICs), field-Programmable gate arrays (Field-Programmable GATE ARRAY, FPGA) or other Programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Wherein the general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
In some embodiments, the processor 201 is configured to execute a computer program stored in the memory to implement the following steps:
acquiring a target test text of a target chip; the test text comprises a radiation control curve, a temperature control curve and standard parameter information, wherein the standard parameter information comprises standard values of all performance parameters of the target chip, and the duration corresponding to the radiation control curve is the same as the duration corresponding to the temperature control curve;
in the same time period, performing radiation control on the target chip based on the radiation control curve, performing temperature control on the target chip based on the temperature control curve, and acquiring test values of all parameters of the target chip in real time through a preset parameter detection device in the process of performing radiation control and temperature control on the target chip simultaneously to obtain test parameter information;
Determining a target interfered factor of the target chip based on the standard parameter information and the test parameter information;
and judging whether the target chip is qualified or not based on the target interfered factor.
It should be noted that, for convenience and brevity of description, the specific working process of the terminal device 200 described above may refer to the corresponding process of the chip sorting method, and will not be described herein.
Embodiments of the present application also provide a computer-readable storage medium storing a computer program that, when executed by one or more processors, causes the one or more processors to implement a chip sorting method as provided by the embodiments of the present application.
The computer readable storage medium may be an internal storage unit of the terminal device 200 of the foregoing embodiment, for example, a hard disk or a memory of the terminal device 200. The computer readable storage medium may also be an external storage device of the terminal device 200, such as a plug-in hard disk, a smart memory card (SMART MEDIA CARD, SMC), a Secure Digital (SD) card, a flash memory card (FLASH CARD), or the like, which the terminal device 200 is equipped with.
While the application has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made and equivalents will be apparent to those skilled in the art without departing from the scope of the application. Therefore, the protection scope of the application is subject to the protection scope of the claims.
Claims (7)
1. A chip sorting method, comprising:
acquiring a target test text of a target chip; the test text comprises a radiation control curve, a temperature control curve and standard parameter information, wherein the standard parameter information comprises standard values of all performance parameters of the target chip, and the duration corresponding to the radiation control curve is the same as the duration corresponding to the temperature control curve;
in the same time period, performing radiation control on the target chip based on the radiation control curve, performing temperature control on the target chip based on the temperature control curve, and acquiring test values of all parameters of the target chip in real time through a preset parameter detection device in the process of performing radiation control and temperature control on the target chip simultaneously to obtain test parameter information;
Determining a target interfered factor of the target chip based on the standard parameter information and the test parameter information; comprising the following steps: calculating a first standard deviation among all test values corresponding to the performance parameters aiming at all the performance parameters of the target chip; aiming at each performance parameter of the target chip, based on a test time sequence corresponding to each test value of the performance parameter, sequentially arranging each test value of the performance parameter to obtain a test value sequence corresponding to the performance parameter, sequentially calculating first absolute values of differences between two adjacent test values in the test value sequence, and calculating second standard deviations between the first absolute values; for each performance parameter of the target chip, calculating a second absolute value of a difference between a standard value corresponding to the performance parameter and each test value corresponding to the performance parameter, and determining the largest second absolute value in each second absolute value as a target absolute value; aiming at each performance parameter of the target chip, adding the first standard deviation, the second standard deviation and the target absolute value corresponding to the performance parameter to obtain an initial interfered factor corresponding to the performance parameter; determining the largest initial interfered factor as a target interfered factor in the initial interfered factors;
judging whether the target chip is qualified or not based on the target interfered factor; comprising the following steps: comparing the target interfered factor with a preset interfered factor; and if the target interfered factor is not greater than the preset interfered factor, determining that the target chip is qualified.
2. The chip sorting method according to claim 1, wherein the obtaining the test text of the target chip includes:
obtaining the model of a target chip;
and matching the target test text in a preset database based on the model.
3. The chip sorting method according to claim 2, wherein the obtaining the model number of the target chip includes:
scanning the graphic code on the target chip by adopting a preset code scanning device to obtain an identification function and an identification form of the target chip;
Drawing a function curve of the identification function in a preset plane rectangular coordinate system, and mapping the identification table into the plane rectangular coordinate system based on a preset table mapping rule;
Determining a plurality of target cells in the identification table based on the function curve; wherein the function curve is contained in the region composed of each target cell;
and based on the positions of the target cells in the identification table, sequentially arranging the characters corresponding to the target cells to obtain the model.
4. The chip sorting method according to claim 2, wherein the preset database includes a plurality of test texts, the matching the target test text in the preset database based on the model number includes:
acquiring a preset decoding table; wherein the decoding table comprises character columns and digital columns;
Aiming at each character of the model, acquiring a hash value corresponding to the character based on a preset hash algorithm;
for each hash value, respectively carrying out decoding processing on each character of the hash value by utilizing the decoding table, and determining the hash value as a target hash value when decoding of each character of the hash value fails;
calculating products among the digits of the target hash values for the target hash values;
Sequentially arranging the target hash values based on products corresponding to the target hash values to obtain decryption passwords;
And respectively carrying out decryption processing on each test text based on the decryption passwords, and taking the test text successfully decrypted as the target test text.
5. A chip sorting apparatus, comprising:
the acquisition module is used for acquiring a target test text of the target chip; the test text comprises a radiation control curve, a temperature control curve and standard parameter information, wherein the standard parameter information comprises standard values of all performance parameters of the target chip, and the duration corresponding to the radiation control curve is the same as the duration corresponding to the temperature control curve;
The control module is used for carrying out radiation control on the target chip based on the radiation control curve and carrying out temperature control on the target chip based on the temperature control curve in the same time period, and acquiring test values of all parameters of the target chip in real time through a preset parameter detection device in the process of carrying out radiation control and temperature control on the target chip at the same time to obtain test parameter information;
the determining module is used for determining a target interfered factor of the target chip based on the standard parameter information and the test parameter information; comprising the following steps: calculating a first standard deviation among all test values corresponding to the performance parameters aiming at all the performance parameters of the target chip; aiming at each performance parameter of the target chip, based on a test time sequence corresponding to each test value of the performance parameter, sequentially arranging each test value of the performance parameter to obtain a test value sequence corresponding to the performance parameter, sequentially calculating first absolute values of differences between two adjacent test values in the test value sequence, and calculating second standard deviations between the first absolute values; for each performance parameter of the target chip, calculating a second absolute value of a difference between a standard value corresponding to the performance parameter and each test value corresponding to the performance parameter, and determining the largest second absolute value in each second absolute value as a target absolute value; aiming at each performance parameter of the target chip, adding the first standard deviation, the second standard deviation and the target absolute value corresponding to the performance parameter to obtain an initial interfered factor corresponding to the performance parameter; determining the largest initial interfered factor as a target interfered factor in the initial interfered factors;
The judging module is used for judging whether the target chip is qualified or not based on the target interfered factor; comprising the following steps: comparing the target interfered factor with a preset interfered factor; and if the target interfered factor is not greater than the preset interfered factor, determining that the target chip is qualified.
6. A terminal device comprising a processor, a memory and a computer program stored on the memory and executable by the processor, wherein the computer program when executed by the processor implements the chip sorting method according to any one of claims 1 to 4.
7. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program, wherein the computer program, when executed by a processor, implements the chip sorting method according to any of claims 1 to 4.
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| CN112444718A (en) * | 2019-08-29 | 2021-03-05 | 上海原动力通信科技有限公司 | Chip aging monitoring method, device and system |
| CN112824916A (en) * | 2019-11-20 | 2021-05-21 | 圣邦微电子（北京）股份有限公司 | High-temperature testing device and method for integrated chip |
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| CN114201350A (en) * | 2021-12-29 | 2022-03-18 | 上海赛美特软件科技有限公司 | Wafer chip testing method and device, electronic equipment and storage medium |
| CN117074923B (en) * | 2023-10-11 | 2023-12-12 | 蓝芯存储技术(赣州)有限公司 | Chip burn-in test method, device, equipment and storage medium |
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| CN112444718A (en) * | 2019-08-29 | 2021-03-05 | 上海原动力通信科技有限公司 | Chip aging monitoring method, device and system |
| CN112824916A (en) * | 2019-11-20 | 2021-05-21 | 圣邦微电子（北京）股份有限公司 | High-temperature testing device and method for integrated chip |
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