CN118057964A - Memory device and control method thereof - Google Patents

Abstract

A memory device includes: a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines; and a charge control circuit coupled to the memory cell array. The plurality of memory cells includes selected memory cells connected between a word line and a selected bit line and unselected memory cells connected between the word line and unselected bit line. The charge control circuit is configured to provide a precharge voltage to the unselected bit lines, the precharge voltage being between-3 volts and-5 volts.

Description

Memory device and control method thereof

Technical Field

The present disclosure relates to a memory device and a control method of the memory device.

Background

A read operation of a memory cell may require multiple steps or operations to precharge, charge share, or discharge the corresponding bit line before a read voltage is applied via the word line to read out the result. Due to the variety of materials of Phase Change Memories (PCM), the accuracy of read operations can become challenging.

Disclosure of Invention

In one aspect, a memory device is disclosed. The memory device includes a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, and a charge control circuit coupled to the memory cell array. The plurality of memory cells includes selected memory cells connected between a word line and a selected bit line, and unselected memory cells connected between the word line and unselected bit lines. The charge control circuit is configured to provide a precharge voltage to the unselected bit lines, the precharge voltage being between-3 volts and-5 volts.

In some implementations, the charge control circuit is configured to provide a first voltage to the selected bit line and the unselected bit line, and to control: the method includes precharging the unselected bit lines to the precharge voltage, charge sharing the unselected bit lines with the selected bit lines to reach a reference voltage, and discharging the selected bit lines to a second voltage.

In some embodiments, the first voltage is 0 volts. In some embodiments, the reference voltage is between-1.5 volts and-2.5 volts. In some embodiments, the second voltage is between-2 volts and-4 volts.

In some embodiments, the charge control circuit further includes a voltage comparator coupled to the memory cell array and configured to compare a reference voltage of the unselected bit line with a selected bit line voltage of the selected bit line and generate a comparison output signal.

In some embodiments, the voltage comparator is configured to determine that the selected memory cell is in a set state when the selected bit line voltage of the selected bit line is higher than the reference voltage of the unselected bit line; and determining that the selected memory cell is in a reset state when the selected bit line voltage of the selected bit line is lower than the reference voltage of the unselected bit line.

In some embodiments, the charge control circuit further includes a first local control gate coupled to the unselected bit line and configured to control the precharging of the unselected bit line to the precharge voltage; a second local control gate coupled between the selected bit line and the unselected bit line and configured to control charge sharing of the unselected bit line with the selected bit line to reach the reference voltage; and a third local control gate coupled to the selected bit line and configured to control discharging the selected bit line to the second voltage.

In some implementations, each memory cell includes a Phase Change Memory (PCM) cell. In some implementations, the PCM cell includes a PCM element and a selector in series with the PCM element.

In another aspect, a system is disclosed. The system includes a memory device and a memory controller coupled to the memory device and configured to control the memory device. The memory device includes a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, and a charge control circuit coupled to the memory cell array. The plurality of memory cells includes selected memory cells connected between a word line and a selected bit line, and unselected memory cells connected between the word line and unselected bit lines. The charge control circuit is configured to provide a precharge voltage to the unselected bit lines, the precharge voltage being between-3 volts and-5 volts.

In yet another aspect, a method for operating a memory device is disclosed. The memory device includes a selected memory cell connected between a word line and a selected bit line, and an unselected memory cell connected between the word line and an unselected bit line. The method includes setting the selected bit line and the unselected bit line to a first voltage; precharging the unselected bit lines to a precharge voltage, wherein the precharge voltage is between-3 volts and-5 volts; charging sharing is carried out on the unselected bit lines and the selected bit lines so as to reach a reference voltage; discharging the selected bit line to a second voltage; and applying a read voltage via the word line to obtain a read result.

In some embodiments, the first voltage is 0 volts. In some embodiments, the reference voltage is between-1.5 volts and-2.5 volts. In some embodiments, the second voltage is between-2 volts and-4 volts.

In some implementations, the unselected bit lines and the selected bit line are electrically connected to achieve the same voltage level.

In some implementations, the unselected bit lines and the selected bit line are disconnected and the second voltage is provided to the selected bit line. In some implementations, the unselected bit lines are maintained at the reference voltage.

In some implementations, the voltage on the selected bit line is pulled up above the reference voltage or maintained at the second voltage.

In some implementations, the voltage on the selected bit line is compared to the reference voltage and a comparison result is output as the read result.

In some implementations, the selected memory cell is determined to be in a set state when the voltage on the selected bit line is higher than the reference voltage; and determining that the selected memory cell is in a reset state when the voltage on the selected bit line is below the reference voltage.

Drawings

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate various aspects of the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the pertinent art to make and use the disclosure.

Fig. 1 illustrates a block diagram of an exemplary system having a memory device, in accordance with aspects of the present disclosure.

Fig. 2 illustrates a schematic diagram of an exemplary memory device including peripheral circuitry, in accordance with some aspects of the present disclosure.

FIG. 3 illustrates a schematic diagram of an exemplary memory device including a Phase Change Memory (PCM) cell, in accordance with aspects of the present disclosure.

Fig. 4 illustrates a block diagram of an exemplary memory device including a memory cell array and peripheral circuitry, in accordance with aspects of the present disclosure.

Fig. 5 illustrates a block diagram of an exemplary memory device including a charge control circuit, in accordance with aspects of the present disclosure.

Fig. 6A-6B illustrate a time sequence of read operations of an exemplary memory device according to some aspects of the present disclosure.

Fig. 7 illustrates a flow chart of an exemplary method of operating a memory device in accordance with aspects of the present disclosure.

The present disclosure will be described with reference to the accompanying drawings.

Detailed Description

While specific configurations and arrangements are discussed, it should be understood that this discussion is for illustrative purposes only. Accordingly, other configurations and arrangements may be used without departing from the scope of this disclosure. Moreover, the present disclosure may be employed in a variety of other applications. The functional and structural features described in the present disclosure may be combined, adjusted, and modified with each other in a manner not specifically shown in the drawings so that they are within the scope of the present disclosure.

Generally, terms should be understood at least in part by use in the context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, at least in part, depending on the context. Similarly, the terms "a," "an," or "the" may also be understood to convey a singular usage or a plural usage, depending at least in part on the context. Furthermore, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, but rather may permit the existence of other factors that are not necessarily explicitly stated, which again depends at least in part on context. In addition, the terms "coupled," "coupled to," or "coupled between … …" may be understood to not necessarily mean "physically joined or attached," i.e., directly attached, but may be interpreted as indirectly connected through intervening components.

Phase Change Memory (PCM) cells are non-volatile memory devices that use phase change materials to store data. PCM may take advantage of resistivity differences between amorphous and crystalline phases in phase change materials (e.g., chalcogenide alloys) based on heating and quenching the phase change material in an electrothermal manner. The phase change material in a PCM cell may be located between two electrodes and a current may be applied to cause the material (or a portion thereof blocking the current path) to repeatedly switch between the two phases to store data. The "set" state is a low resistance state of the PCM cell that can be obtained by creating a crystalline region in the chalcogenide material. Crystallization occurs when the chalcogenide material is heated at a crystallization temperature for a sufficient period of time. In contrast, the "reset" state is a high resistance state of the PCM cell, which can be obtained by creating amorphous regions in the chalcogenide material. Amorphous forms may be produced when a chalcogenide material is heated above its melting point and then rapidly quenched to cause the formation of an amorphous form. The "set" state may be referred to as an "on" state, and the "reset" state may be referred to as an "off" state.

A read operation of a memory cell may require multiple steps or operations to precharge, charge share, or discharge the corresponding bit line before a read voltage is applied via the word line to read out the result. Specifically, in order to obtain a result of determining whether the memory cell is in a "set" ("1") state or a "reset" ("0") state, a charge sharing process is required to bring the selected bit line and the unselected bit line to the same voltage level as the reference voltage before a read voltage is applied to the memory cell via the word line. The charge sharing process may include several precharge sharing, charge sharing, and discharging steps, which are controlled by applying several control signals to turn on and off several control gates and applying a specific charge or discharge bias voltage to the bit line.

Then, the selected bit line is set to a floating state, and a read voltage is applied to the word line. When the selector of the PCM cell is turned on, the floating bit line is charged by the word line. When the voltage difference between the word line and the bit line is higher than the reference voltage, the PCM cell is read as "1"; and when the voltage difference between the word line and the bit line is lower than the reference voltage, the PCM cell is read as "0". However, in some implementations, because of the diversity of PCM cells, the read voltage provided by the word line may be insufficient to charge the bit line to a voltage level above the reference voltage, and erroneous read results of the PCM cells may occur.

To address one or more of the foregoing problems, the present disclosure provides a low precharge voltage to unselected bit lines during a precharge operation, and thus, a reference voltage of a PCM cell may be changed during a read operation to improve the accuracy of the read operation.

Fig. 1 illustrates a block diagram of an exemplary system 100 having a memory device, in accordance with aspects of the present disclosure. The system 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual Reality (VR) device, augmented Reality (AR) device, or any other electronic device having a memory device located therein. As shown in FIG. 1, system 100 may include a host 108 and a storage system 102, storage system 102 having one or more storage devices 104 and a memory controller 106. Host 108 may be a processor (e.g., a Central Processing Unit (CPU)) or a system on a chip (SoC) (e.g., an Application Processor (AP)) of an electronic device. In some implementations, host 108 may be configured to send or receive data to or from storage device 104. In some implementations, the host may be user logic or a user interface so that a user may give instructions to the host and send instructions to the storage device or storage array.

The memory device 104 may be any memory device disclosed in this disclosure. As disclosed in detail below, according to some embodiments, the memory device 104 is, for example, a Phase Change Random Access Memory (PCRAM), a Dynamic Random Access Memory (DRAM), or a NAND flash memory device, and may include a clock input, a command bus, a data bus, control logic, an address register, a row decoder/word line driver, a memory cell array having memory cells, a voltage generator, a page buffer/sense amplifier, a column decoder/bit line driver, and a data input/output (I/O).

According to some embodiments, memory controller 106 is coupled to storage device 104 and host 108 and is configured to control storage device 104. Memory controller 106 may manage data stored in storage device 104 and communicate with host 108. In some implementations, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, compact Flash (CF) card, universal Serial Bus (USB) flash drive, or other medium used in electronic devices such as personal computers, digital cameras, mobile phones, and the like. In some implementations, the memory controller 106 is designed to operate in a high duty cycle environment, such as a Solid State Drive (SSD) or embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays. The memory controller 106 may be configured to control operations of the memory device 104, such as read, erase, and write operations. The memory controller 106 may also be configured to manage various functions related to data stored in the memory device 104 or to be stored in the memory device 104 including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, and the like. In some implementations, the memory controller 106 is further configured to process Error Correction Codes (ECCs) related to data read from the memory device 104 or written to the memory device 104. Any other suitable function may also be performed by the memory controller 106, such as formatting the memory device 104. The memory controller 106 may communicate with external devices (e.g., host 108) according to a particular communication protocol. For example, the memory controller 106 may communicate with external devices via at least one of various interface protocols (e.g., USB protocol, MMC protocol, peripheral Component Interconnect (PCI) protocol, PCI-E protocol, advanced Technology Attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small Computer Small Interface (SCSI) protocol, enhanced Small Disk Interface (ESDI) protocol, integrated Drive Electronics (IDE) protocol, firewire protocol, etc.). In addition, the memory controller 106 may also be configured to control the operation of the memory device 104 to perform methods according to some embodiments of the present disclosure. For example, in some implementations, the memory controller 106 can determine whether the read voltage is above or below the threshold voltage of the selected memory cell. In some implementations, the memory controller 106 can determine that the state of the selected memory cell is a "set" state in response to the read voltage being above the threshold voltage of the selected memory cell, or a "reset" state in response to the read voltage being below the threshold voltage of the selected memory cell. It is noted that, according to some embodiments of the present disclosure, one or more of these operations of the memory device 104 may also be performed in part or in whole by the control logic.

Fig. 2 shows a schematic circuit diagram of an exemplary memory device 200 including peripheral circuitry in accordance with some aspects of the present disclosure. Memory device 200 may be an example of memory device 104 in fig. 1. The memory device 200 may include a memory cell array 201 and peripheral circuitry 202 coupled to the memory cell array 201. The memory cell array 201 may include word lines (e.g., selected word lines 214), bit lines (e.g., selected bit lines 216 and unselected bit lines 218), and memory cells (e.g., selected memory cells 208 and unselected memory cells 210) formed between the word lines and the bit lines. In some embodiments, each memory cell (e.g., selected memory cell 208 and unselected memory cell 210) may include a PCM element (not shown) in series with a selector (not shown). In some embodiments, the memory cell (e.g., 208 or 210) may also be a DRAM cell including a pair of transistors and a capacitor. To read a selected memory cell (e.g., selected memory cell 208), a selected word line voltage (e.g., selected word line voltage Vwl 1) may be applied to a selected word line (e.g., selected word line 214), and a selected bit line voltage (e.g., selected bit line voltage Vbl 1) may be applied to a selected bit line (e.g., selected bit line 216). The other unselected word lines will remain at the unselected word line voltage (e.g., vwl 0), and the other unselected bit lines will remain at the unselected bit line voltage (e.g., vbl 0). In some implementations, before applying the selected word line voltage (e.g., selected word line voltage Vwl 1) to the selected word line (e.g., selected word line 214), the unselected bit line voltage (e.g., vbl 0) of the unselected bit line (e.g., unselected bit line 218) is configured to be set to the reference voltage by a series of voltages during the precharge sharing, charge sharing, and discharge processes. In some implementations, the selected bit line voltage (e.g., vbl 1) of the selected bit line (e.g., selected bit line 216) is configured to be set to a series of voltages during the precharge sharing, charge sharing, and discharge processes prior to the selected word line voltage (e.g., selected word line voltage Vwl 1) being applied to the selected word line (e.g., selected word line 214). These precharge sharing, charge sharing, and discharge sharing processes will be discussed later.

Fig. 3 shows a side view of a cross section of a memory device 300 having a PCM element in series with a selector. Memory device 300 includes one or more parallel bit lines 304 (i.e., corresponding to bit lines 216 in fig. 2) over substrate 302 and one or more parallel word lines 316 (i.e., corresponding to word lines 214 in fig. 2) over bit lines 304. Memory device 300 also includes one or more PCM cells 301 (i.e., corresponding to memory cell 208 in fig. 2), each disposed at an intersection of a corresponding pair of bit line 304 and word line 316. Adjacent PCM cells 301 are separated by insulating structures 322. Each PCM cell 301 includes a selector 308 and a PCM element 312 above the selector 308. Each PCM cell 301 also includes three electrodes 306, 310, and 314, respectively, vertically interposed between a corresponding bit line 304, a selector 308, a PCM element 312, and a corresponding word line 316.

It is noted that PCM element 312 may take advantage of resistivity differences between amorphous and crystalline phases in phase change materials (e.g., chalcogenide alloys) based on the heating and quenching of the phase change material in an electrothermal manner. The phase change element may be located between two electrodes and a current may be applied to cause the material (or a portion thereof blocking the current path) to repeatedly switch between the two phases to store data.

The selector 308 may include an Ovonic Threshold Switch (OTS) selector having an OTS material, such as zinc telluride (ZnTe), that exhibits field-dependent volatile resistance switching behavior (known as the "OTS" phenomenon) when an external bias voltage (Va) above a threshold voltage (Vth) is applied. At lower voltages (|va| < Vth), the high resistance of the OTS selector in its off state keeps the off state current (Ioff) low. At higher voltages (|va| > Vth), the OTS selector experiences OTS phenomena and switches to an on state with low resistance; therefore, the current (Ion) through the OTS selector in the on state increases. This volatile on state is maintained as long as a high voltage is supplied.

Fig. 4 illustrates a block diagram of an exemplary memory device 400 (e.g., corresponding to 104 in fig. 1) including a memory cell array 401 (e.g., corresponding to 201 in fig. 2) and peripheral circuitry, in accordance with some aspects of the present disclosure. In some embodiments, the memory cells of memory cell array 401 include PCM cells 301.

As shown in fig. 4, a page buffer/sense amplifier 404 may be coupled to the memory cell array 401 and configured to read data from the memory cell array 401 and program (write) data to the memory cell array 401 according to control signals from control logic 412. In one example, page buffer/sense amplifier 404 may store a page of programming data (write data) to be programmed into a page of memory cell array 201 (e.g., in fig. 2). In another example, the page buffer/sense amplifier 404 may perform a program verify operation to ensure that data has been properly programmed into the memory cells 208 coupled to the selected word line 214. In yet another example, the page buffer/sense amplifier 404 may also sense a low power signal representing the data bit stored in the memory cell 208 from the selected bit line 216 in a read operation and amplify the small voltage swing to an identifiable logic level.

The column decoder/bit line driver may be coupled to the memory cell array 401 and the control logic 412 and configured to control and select one or more memory cells (e.g., the selected memory cell 208) and bit lines (e.g., the selected bit line 216) through the control logic 412. The column decoder/bit line driver 406 may also be configured to drive the selected bit lines 216. The column decoder/bit line driver 406 may also be configured to drive the selected bit lines 216 using the bit line voltages generated from the voltage generator 410.

The data I/O416 may be coupled to the page buffer/sense amplifier 404 and/or the column decoder/bit line driver 406 and configured to direct (route) data input from the data bus 423 to the selected memory cells 208 of the memory cell array 201 and to direct (route) data output from the selected memory cells to the data bus 423.

The row decoder/wordline driver 408 may be coupled to the control logic 412 and the memory cell array 401 and configured to be controlled by the control logic 412 and to select one or more memory cells (e.g., the selected memory cell 208) and the selected wordline (e.g., the selected wordline 214) of the memory cell array 201. The row decoder/wordline driver 408 may also be configured to drive the selected wordline 214. The row decoder/wordline driver 408 may be further configured to drive the selected wordline 214 using the wordline voltage generated from the voltage generator 410.

The voltage generator 410 may be coupled to the control logic 412 and configured to be controlled by the control logic 412 according to control signals from the control logic 412 and generate a word line voltage (e.g., read voltage, program voltage, pass voltage, local voltage, verify voltage, etc.), a bit line voltage, and a source line voltage to be provided to the memory cell array 401.

Control logic 412 may be coupled to each of the peripheral circuits described above and configured to control the operation of each peripheral circuit. The control logic 412 is configured to receive clock signals, command signals, address signals, and data signals from a host (e.g., 108 in fig. 1). The command signals are received via a command bus 421. The data signal is received via data bus 423. In some implementations, the control logic 412 may be implemented by a microprocessor, microcontroller (also known as a microcontroller unit (MCU)), digital Signal Processor (DSP), application Specific Integrated Circuit (ASIC), field Programmable Gate Array (FPGA), programmable Logic Device (PLD), state machine, gating logic, discrete hardware circuitry, and other suitable hardware, firmware, and/or software configured to perform the various functions described. In some implementations, the control logic 412 is coupled to the word line drivers 408 and is configured to direct the read voltage into the selected memory cell via the word line drivers 408.

The address register 414 may be coupled to the control logic 412 or included in the control logic 412. The address register 414 may include a status register, a command register, and an address register to store status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit.

Fig. 5 illustrates a block diagram of a memory device (e.g., corresponding to 400 in fig. 4) including a charge control circuit 500, in accordance with some aspects of the present disclosure. As shown in fig. 4, once control logic 412 determines that the command signal is a read command, it triggers a read operation. The read operation includes a series of precharge sharing, charge sharing, and discharge processes prior to applying a read voltage to a selected word line. According to some embodiments of the present disclosure, these precharge sharing, charge sharing, and discharge processes are performed by the charge control circuit 500. The charge control circuit 500 may include a voltage comparator 501 (e.g., corresponding to or included in the page buffer/sense amplifier 404) coupled to the memory cell array (e.g., corresponding to the memory cell array 201 or 401), an unselected bit line 511 (e.g., corresponding to the unselected bit line 218) connected to a first input terminal 503 of the voltage comparator 501, and a selected bit line 513 (e.g., corresponding to the selected bit line 216) connected to a second input terminal 505 of the voltage comparator 501. In some implementations, the voltage comparator 501 is configured to determine that a selected memory cell (e.g., selected memory cell 208) is in a "set" state if the selected bit line voltage Vbl1 of the selected bit line 513 (e.g., selected bit line 216) is higher than the reference voltage held by the unselected bit line 511 (e.g., corresponding to unselected bit line 218); and determining that the selected memory cell is in a "reset" state if the selected bit line voltage of the selected bit line is below the reference voltage.

In some embodiments, the selected bit line 513 and the unselected bit lines may be initially set to the first voltage at the beginning of the read operation. In some embodiments, the first voltage may be a ground voltage. In some embodiments, the first voltage may be 0 volts.

The first local control gate 521 is coupled to the unselected bit line 511 (e.g., corresponding to the unselected bit line 218), and is configured to control whether the unselected bit line 511 is precharged to a precharge voltage (e.g., negative voltage Vn 1) during a precharge sharing process. In some embodiments, the negative voltage Vn1 can be between-3 volts and-3 volts. In some embodiments, the negative voltage Vn1 can be-3.6 volts. In some embodiments, the negative voltage Vn1 can be-4 volts. In some embodiments, the negative voltage Vn1 can be-4.5 volts. In some embodiments, the negative voltage Vn1 can be-5 volts.

The second local control gate 523 is coupled between the selected bit line 513 and the unselected bit line 511, and is configured to control whether the selected bit line 513 and the unselected bit line 511 are brought to the same voltage level (e.g., 1/2 of the negative voltage Vn 1) during the charge sharing process. This voltage level (e.g., 1/2 of the negative voltage Vn 1) after the charge sharing process can be a reference voltage that can be used to determine whether the selected memory cell is in a "set" state or a "reset" state by comparing the selected bit line voltage Vbl1 to the reference voltage maintained by the unselected bit line 511. For example, if the selected memory cell is in a "set" state, the selected bit line voltage will be pulled up above the reference voltage after the read voltage is applied across the selected word line. Conversely, if the selected memory cell is in the "reset" state, the selected bit line voltage will remain below the reference voltage after the read voltage is applied across the selected word line. In some embodiments, the reference voltage may be between-1.5 volts and-2.5 volts. In some embodiments, the reference voltage may be-1.8 volts. In some embodiments, the reference voltage may be-2 volts. In some embodiments, the reference voltage may be-2.25 volts. In some embodiments, the reference voltage may be-2.5 volts.

The third local control gate 525 is coupled to the selected bit line 513 and is configured to control whether the selected bit line 513 is discharged to a second voltage (e.g., a negative voltage Vn 2) during a discharging process. In some embodiments, the negative voltage Vn2 can be between-2 volts to-4 volts, for example-2.5 volts. It is noted that the charge control circuit 500 according to some embodiments of the present disclosure is merely an example of implementing a desired function or mechanism; any other control logic gate combinations that achieve the same or similar functionality are possible in view of the above teachings.

Fig. 6A-6B illustrate a time sequence of read operations of an exemplary memory device according to some aspects of the present disclosure. Specifically, fig. 6A shows a "set" state readout sequence, and fig. 6B shows a "reset" state readout sequence. Fig. 7 illustrates a flow chart of an exemplary method 700 of operating a memory device in accordance with aspects of the present disclosure. To better describe the present disclosure, the time series in FIGS. 6A-6B will be discussed with method 700 in FIG. 7. It is to be understood that the operations illustrated in method 700 are not exhaustive and that other operations may be performed before, after, or between any of the operations illustrated. Further, some of the operations may be performed simultaneously or in a different order than shown in fig. 6A-6B and fig. 7.

As shown in fig. 6A and in operation 702 in fig. 7, step 1 is an initial state in which when the word line voltage (Vwl) is not provided to the memory cell and both the selected bit line voltage (Vbl 0) and the unselected bit line voltage (Vbl 0) are set to a first voltage, e.g., ground voltage or 0 volts, the current (Icell) on the memory cell (e.g., selected memory cell 208) is 0mA. The selected bit line (e.g., 216 in fig. 2) and the unselected bit line (e.g., 218 in fig. 2) are selected and set to an initial state. In some embodiments, the first voltage of the initial state may be a ground voltage or 0 volts.

As shown in fig. 6A and in operation 704 in fig. 7, step 2 is a precharge sharing process in which an unselected bit line (e.g., unselected bit line 218) is precharged to a precharge voltage Vn1. During the precharge sharing process, the first local control gate (e.g., 521 in fig. 5) is set to an "on" state to precharge the unselected bit lines to a precharge voltage (e.g., negative voltage Vn 1). The precharge share process is used to pull one of the bit lines to a certain voltage (e.g., a negative voltage) so that after a subsequent charge share process, both bit lines will be placed at the same voltage level (e.g., half the previous negative voltage). In some embodiments, the precharge voltage, for example, vn1, may be between-3 volts and-5 volts. In some embodiments, the precharge voltage may be-3.6 volts. In some embodiments, the precharge voltage may be-4 volts. In some embodiments, the precharge voltage may be-4.5 volts. In some embodiments, the precharge voltage may be-5 volts.

As shown in fig. 6A and in operation 706 in fig. 7, step 3 is a charge sharing process in which the selected bit line is electrically connected with the unselected bit lines such that the selected bit line and the unselected bit line reach the same voltage level, i.e., the reference voltage. During the charge sharing process, the first local control gate is set to an "off" state to suspend precharging the unselected bit lines, and at the same time the second local control gate (e.g., 523 in fig. 5) is set to an "on" state so that the selected bit line and the unselected bit line reach the same voltage level, i.e., the reference voltage. In some embodiments, the reference voltage may be between-1.5 volts and-2.5 volts. In some embodiments, the reference voltage may be-1.8 volts. In some embodiments, the reference voltage may be-2 volts. In some embodiments, the reference voltage may be-2.25 volts. In some embodiments, the reference voltage may be-2.5 volts.

As shown in fig. 6A and operation 708 in fig. 7, step 4 is a discharging process in which the selected bit line is discharged to the second voltage Vn2. The second local control gate is set to an "off" state to terminate charge sharing of the selected bit line and the unselected bit lines, while the third local control gate (e.g., 525 in fig. 5) is set to an "on" state to discharge the selected bit line to a second voltage (e.g., negative voltage Vn 2), and then the third local control gate is set to an "off" state to terminate discharge of the selected bit line. In some embodiments, the negative voltage Vn2 can be between-2 volts to-4 volts, for example-2.5 volts. After the third local control gate is set to the "off" state, the selected bit line is in a floating state.

As shown in fig. 6A and operation 710 in fig. 7, step 5 is a read process in which a read voltage, e.g., a word line voltage (Vwl), is provided to the memory cell. Since the memory cell is in the "set" state, the current across the memory cell increases and the selected bit line voltage is pulled up above the reference voltage held by the unselected bit lines. The voltage comparator 501 (corresponding to or included in the sense amplifier 404) can thus determine that the memory cell is in the "set" state by the sense flag changing from 0 (Vbl 0> Vbl 1) to 1 (Vbl 0< Vbl 1). After the selected bit line is discharged to a negative voltage and the unselected bit lines are held at the reference voltage, a read voltage is applied via the corresponding word line and a read result is obtained. If the selected memory cell (e.g., selected memory cell 208 in FIG. 2) on the selected bit line (e.g., selected bit line 216 in FIG. 2) is in a "set" state, the voltage on the selected bit line will be pulled up above the reference voltage because the read voltage is above the set threshold voltage of the selected memory cell, while the unselected bit lines will remain at the reference voltage. The read data (e.g., read voltage or read current) of the memory cell in the "set" state may be obtained.

In contrast, as shown in FIG. 6B, if the memory cell is in the "reset" state, the current across the memory cell remains the same and the selected bit line voltage is not pulled up above the reference voltage. The voltage comparator 501 (corresponding to or included in the sense amplifier 404) can thus determine that the memory cell is in a "reset" state by the sense flag not changing from 0 to 1. If the selected memory cell on the selected bit line is in the "reset" state, the voltage on the selected bit line will not be pulled up above the reference voltage because the read voltage is below the reset threshold voltage of the selected memory cell. The read data (e.g., the read voltage or the read current) of the memory cell in the "reset" state may be obtained.

Step 6 is a restore process in which both the selected bit line and the unselected bit line are reset to an initial state, i.e., ground or 0 volts. After reading out the read result, the selected bit line and the unselected bit line are reset to the initial state during the recovery process, completing the read operation.

The foregoing description of the specific embodiments may be readily modified and/or adapted for various applications. Therefore, based on the teachings and guidance provided herein, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims (21)

1. A memory device, comprising:

A memory cell array comprising a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, wherein the plurality of memory cells comprises:

a selected memory cell connected between the word line and the selected bit line; and

Unselected memory cells connected between the word line and unselected bit line; and

A charge control circuit coupled to the array of memory cells and configured to provide a precharge voltage to the unselected bit lines, wherein the precharge voltage is between-3 volts and-5 volts.

2. The memory device of claim 1, wherein the charge control circuit is configured to provide a first voltage to the selected bit line and the unselected bit line, and to control: the method includes precharging the unselected bit lines to the precharge voltage, charge sharing the unselected bit lines with the selected bit lines to reach a reference voltage, and discharging the selected bit lines to a second voltage.

3. The memory device of claim 2, wherein the first voltage is 0 volts.

4. The memory device of claim 2, wherein the reference voltage is between-1.5 volts and-2.5 volts.

5. The memory device of claim 2, wherein the second voltage is between-2 volts and-4 volts.

6. The memory device of any of claims 2-5, wherein the charge control circuit further comprises:

a voltage comparator coupled to the array of memory cells and configured to compare the reference voltage of the unselected bit line with a selected bit line voltage of the selected bit line and generate a comparison output signal.

7. The memory device of claim 6, wherein the voltage comparator is configured to: determining that the selected memory cell is in a set state when the selected bit line voltage of the selected bit line is higher than the reference voltage of the unselected bit line; and determining that the selected memory cell is in a reset state when the selected bit line voltage of the selected bit line is lower than the reference voltage of the unselected bit line.

8. The memory device of any one of claims 2-7, wherein the charge control circuit further comprises:

A first local control gate coupled to the unselected bit line and configured to control the precharging of the unselected bit line to the precharge voltage;

A second local control gate coupled between the selected bit line and the unselected bit line and configured to control charge sharing of the unselected bit line with the selected bit line to reach the reference voltage; and

A third local control gate is coupled to the selected bit line and configured to control discharging the selected bit line to the second voltage.

9. The memory device of any of claims 1-8, wherein each memory cell comprises a Phase Change Memory (PCM) cell.

10. The memory device of claim 9, wherein the PCM cell comprises a PCM element and a selector in series with the PCM element.

11. A system, comprising:

a memory device, the memory device comprising:

A memory cell array comprising a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, wherein the plurality of memory cells comprises:

a selected memory cell connected between the word line and the selected bit line; and

Unselected memory cells connected between the word line and unselected bit line; and

A charge control circuit coupled to the array of memory cells and configured to provide a precharge voltage to the unselected bit lines, wherein the precharge voltage is between-3 volts and-5 volts; and

A memory controller coupled to the memory device and configured to control the memory device.

12. A method for operating a memory device including selected memory cells connected between a word line and a selected bit line and unselected memory cells connected between the word line and unselected bit lines, the method comprising:

setting the selected bit line and the unselected bit line to a first voltage;

Precharging the unselected bit lines to a precharge voltage, wherein the precharge voltage is between-3 volts and-5 volts;

Charging sharing is carried out on the unselected bit lines and the selected bit lines so as to reach a reference voltage;

discharging the selected bit line to a second voltage; and

A read voltage is applied via the word line to obtain a read result.

13. The method of claim 12, wherein the first voltage is 0 volts.

14. The method of any of claims 12-13, wherein the reference voltage is between-1.5 volts and-2.5 volts.

15. The method of any of claims 12-14, wherein the second voltage is between-2 volts and-4 volts.

16. The method of claim 12, wherein charge sharing the unselected bit lines and the selected bit line to reach the reference voltage comprises:

The unselected bit lines are electrically connected to the selected bit line to reach the same voltage level.

17. The method of claim 16, wherein discharging the selected bit line to the second voltage comprises:

Disconnecting the unselected bit lines and the selected bit lines; and

The second voltage is provided to the selected bit line.

18. The method of claim 17, further comprising:

The unselected bit lines are maintained at the reference voltage.

19. The method of claim 12, wherein applying the read voltage via the word line to obtain the read result comprises:

Pulling up the voltage on the selected bit line above the reference voltage; or alternatively

The voltage on the selected bit line is maintained at the second voltage.

20. The method of claim 19, further comprising:

Comparing the voltage on the selected bit line with the reference voltage; and

And calculating a comparison result as the reading result.

21. The method of claim 12, wherein applying the read voltage via the word line to obtain the read result comprises:

determining that the selected memory cell is in a set state when the voltage on the selected bit line is higher than the reference voltage; and

When the voltage on the selected bit line is lower than the reference voltage, the selected memory cell is determined to be in a reset state.