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CN118054784A - Phase-locked loop, noise elimination method, chip and electronic equipment - Google Patents

Phase-locked loop, noise elimination method, chip and electronic equipment Download PDF

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Publication number
CN118054784A
CN118054784A CN202211439530.7A CN202211439530A CN118054784A CN 118054784 A CN118054784 A CN 118054784A CN 202211439530 A CN202211439530 A CN 202211439530A CN 118054784 A CN118054784 A CN 118054784A
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CN
China
Prior art keywords
delay circuit
signal
clock signal
delay
circuit
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Pending
Application number
CN202211439530.7A
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Chinese (zh)
Inventor
陶婷婷
毛懿鸿
田洪亮
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to CN202211439530.7A priority Critical patent/CN118054784A/en
Priority to PCT/CN2023/104081 priority patent/WO2024103766A1/en
Publication of CN118054784A publication Critical patent/CN118054784A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)

Abstract

The application provides a phase-locked loop, a noise elimination method, a chip and an electronic device, wherein a first reference clock signal and a first feedback clock signal are respectively sent to a first delay circuit and a second delay circuit through a first signal switching circuit, the first reference clock signal delayed by the first delay circuit and the second delay circuit is provided as a second reference clock signal to a time-to-digital converter through the second signal switching circuit, and the first feedback clock signal delayed by the first delay circuit and the second delay circuit is provided as a second feedback clock signal to the time-to-digital converter, so that the frequencies of flicker noise generated on the first delay circuit and the second delay circuit are shifted, and the shifted flicker noise is filtered through a subsequent low-pass filter, thereby achieving the purpose of eliminating the flicker noise.

Description

Phase-locked loop, noise elimination method, chip and electronic equipment
Technical Field
The present application relates to the field of noise cancellation, and in particular, to a phase locked loop, a noise cancellation method, a chip, and an electronic device.
Background
In wireless communication systems, frequency synthesizers based on a phase locked loop (phase locked loop, PLL) architecture are widely employed to provide local oscillator signals. In data transmission systems, a phase locked loop architecture is also commonly employed to provide the sampling clock. The quality of the clock signal output based on the phase-locked loop structure directly affects the quality of the communication signal or affects the transmission quality of the data.
In all-digital phase-locked loops (ADPLL) and analog phase-locked loops (analog phase locked loop, APLL), a frequency multiplier is typically used to boost the frequency of the reference clock, thereby enhancing the output phase noise performance of the phase-locked loop. To obtain finer output frequencies, fractional division techniques are generally used, and the instantaneous division value of the divider is adjusted by a modulator (sigma-delta, SDM) to obtain the fractional division. However, the application of SDM generates large quantization noise, and also causes a problem of fractional spurs (fractional spurs) in the output signal.
To address the two problems with SDM, a DTC (digital to time converter, digital time converter) circuit is typically used on either the reference clock path or the feedback clock path, and the delay of the DTC circuit is controlled by adjusting the input codeword of the DTC.
The DTC is a programmable delay circuit, and the phase of the clock path must be capable of bidirectional variation for the purposes of spurious cancellation and quantization noise cancellation in the PLL. It is common practice to put the DTC input control codeword (offset) at the center point first, and the output phase of the DTC may be dithered to both sides along with the input codeword at the center position. Thus, the maximum delay of the DTC is to cover a phase jitter range of more than 2 times. However, to accomplish a wide range of delay variations, both the device noise and power consumption of the DTC circuit increase with increasing delay. Thus, the DTC circuit itself also contributes more low frequency phase noise, affecting the PLL output clock quality.
In view of this, there is a need to propose a phase locked loop that can achieve a large delay range and reduce flicker noise (flicker) generated by internal devices.
Disclosure of Invention
The application provides a phase-locked loop, a noise elimination method, a chip and electronic equipment, which can realize a larger delay range and reduce flicker noise generated by internal devices.
In a first aspect, the present application provides a phase locked loop comprising a digital to time converter and a time to digital converter; wherein; the digital time converter includes: a first delay circuit, a second delay circuit, a first signal switching circuit, and a second signal switching circuit; the first signal switching circuit is used for acquiring a first reference clock signal and a first feedback clock signal and selectively transmitting the first reference clock signal and the first feedback clock signal to the first delay circuit and the second delay circuit respectively; the first delay circuit is used for performing first delay processing on the received signal, and the second delay circuit is used for performing second delay processing on the received signal; and the second signal switching circuit is used for providing the first reference clock signal delayed by the first delay circuit and the first reference clock signal delayed by the second delay circuit as a second reference clock signal to the time-to-digital converter and providing the first feedback clock signal delayed by the first delay circuit and the first feedback clock signal delayed by the second delay circuit as a second feedback clock signal to the time-to-digital converter.
The first reference clock signal and the first feedback clock signal are respectively sent to the first delay circuit and the second delay circuit in the first signal switching circuit, the first reference clock signal delayed by the first delay circuit and the second delay circuit is used as the second reference clock signal to be provided to the time-to-digital converter by the second signal switching circuit, the first feedback clock signal delayed by the first delay circuit and the second delay circuit is used as the second feedback clock signal to be provided to the time-to-digital converter, so that the frequencies of flicker noise generated on the first delay circuit and the second delay circuit are shifted, and the shifted flicker noise is filtered by a subsequent low-pass filter, so that the purpose of eliminating the flicker noise is achieved.
As a possible implementation manner, the phase-locked loop further includes: a controller; a controller for: and acquiring a target signal, and controlling the first signal switching circuit and the second signal switching circuit based on the target signal, wherein the frequency of the target signal is the same as that of the first reference clock signal. The first signal switching circuit may selectively adjust output paths of the first reference clock signal and the first feedback clock signal according to a level change of the target signal, and may also selectively supply the first reference clock signal delayed by the first delay circuit/the second delay circuit as the second reference clock signal to the time-to-digital converter and selectively supply the first reference clock signal delayed by the first delay circuit/the second delay circuit as the second reference clock signal to the time-to-digital converter according to the level change of the target signal.
As a possible implementation, the controller is specifically configured to: when the target signal is at a first level, controlling the first signal switching circuit to input a first reference clock signal into the first delay circuit and to input a first feedback clock signal into the second delay circuit; controlling the second signal switching circuit to provide the first reference clock signal delayed by the first delay circuit as a second reference clock signal to the time-to-digital converter, and providing the first feedback clock signal delayed by the second delay circuit as a second feedback clock signal to the time-to-digital converter; when the target signal is at a second level, controlling the first signal switching circuit to input a first reference clock signal into the second delay circuit and to input a first feedback clock signal into the first delay circuit; the second signal switching circuit is controlled to provide the first reference clock signal delayed by the second delay circuit as a second reference clock signal to the time-to-digital converter, and the first feedback clock signal delayed by the first delay circuit as a second feedback clock signal to the time-to-digital converter.
The controller may control the first signal switching circuit to receive the first reference clock signal and the first feedback clock signal at two different ports, respectively, and input the received first reference clock signal to the first delay circuit and the first feedback clock signal to the second delay circuit when the target signal is at the first level. In addition, since the time-to-digital converter generally calculates a time difference between the first input signal and the second input signal when calculating the delay difference, the controller also needs to control the second signal switching circuit to input the first reference clock signal delayed by the first delay circuit as the second reference clock signal to the first input terminal of the time-to-digital converter and input the first feedback clock signal delayed by the second delay circuit as the second feedback clock signal to the second input terminal of the time-to-digital converter, so that the time-to-digital converter calculates the time difference between the second reference clock signal and the second feedback clock signal.
Therefore, the flicker noise generated in the first delay circuit and the second delay circuit is originally low-frequency noise, the flicker noise frequency spectrums generated in the first delay circuit and the second delay circuit can be shifted to the high frequency corresponding to the first reference clock signal through continuous alternating control of the controller, and in the subsequent low-pass filter, the flicker noise with the frequency spectrums shifted to the high frequency can be effectively filtered.
As one possible implementation manner, the first signal switching circuit specifically includes: the first control switch, the second control switch, the third control switch and the fourth control switch, the second signal switching circuit specifically includes: a fifth control switch, a sixth control switch, a seventh control switch, and an eighth control switch; one end of the first control switch and one end of the second control switch receive a first reference clock signal, and one end of the third control switch and one end of the fourth control switch receive a first feedback clock signal; the other end of the first control switch is connected with the first delay circuit, the other end of the second control switch is connected with the second delay circuit, the other end of the third control switch is connected with the first delay circuit, and the other end of the fourth control switch is connected with the second delay circuit; one end of a fifth control switch is connected with the output end of the first delay circuit, the other end of the fifth control switch is connected with the first input end of the time-to-digital converter, one end of the sixth control switch is connected with the output end of the first delay circuit, the other end of the sixth control switch is connected with the second input end of the time-to-digital converter, one end of the seventh control switch is connected with the output end of the second delay circuit, the other end of the seventh control switch is connected with the first input end of the time-to-digital converter, one end of the eighth control switch is connected with the output end of the second delay circuit, and the other end of the eighth control switch is connected with the second input end of the time-to-digital converter.
The first signal switching circuit and the second signal switching circuit may also be switching circuit structures such as butterfly switching circuits, as long as other switching structures of the basic function that can alternate between successive cycles can be used in other embodiments, as will be appreciated by those skilled in the art.
As a possible implementation manner, the phase-locked loop further includes: a delay control circuit for: selectively utilizing the first control signal or the second control signal to control the first delay circuit so as to adjust the delay time length of the first delay circuit for the received signal, wherein the polarity of the first control signal is opposite to that of the second control signal; the second delay circuit is selectively controlled by a third control signal or a fourth control signal to adjust the delay time of the second delay circuit for the received signal, wherein the polarity of the third control signal is opposite to that of the fourth control signal.
In order to keep the delay relation between the input and the output of the digital-to-time converter unchanged, when the target signal is at a first level, the first feedback clock signal is input into the second delay circuit as the controller controls the first signal switching circuit to input the first reference clock signal into the first delay circuit. Therefore, the first control signal is used for controlling the delay time length of the first delay circuit, and the third control signal is used for controlling the delay time length of the second delay circuit.
And when the target signal is at the second level, the controller controls the first signal switching circuit to input the first feedback clock signal into the first delay circuit, and the first reference clock signal is input into the second delay circuit. The delay time length of the first delay circuit is controlled by the second control signal, and the delay time length of the second delay circuit is controlled by the fourth control signal. Since the polarities of the first control signal and the second control signal, and the polarities of the third control signal and the fourth control signal are opposite, the delay relation of the digital-to-time converter is unchanged when the second reference clock signal and the second feedback clock signal are calculated by the digital-to-time converter.
As a possible implementation manner, the phase-locked loop further includes: a controller; a controller for: when the target signal is at a first level, controlling the delay time length of the first delay circuit by using a first control signal, and controlling the delay time length of the second delay circuit by using a third control signal; when the target signal is at the second level, the delay time length of the first delay circuit is controlled by the second control signal, and the delay time length of the second delay circuit is controlled by the fourth control signal.
As a possible implementation manner, the first delay circuit or the second delay circuit includes a first driving unit, a second driving unit, a resistor and an adjustable capacitor; the first end of the first driving unit is connected with the first end of the resistor, the second end of the resistor is connected with the first end of the second driving unit and the first end of the adjustable capacitor, the second end of the adjustable capacitor is grounded, the second end of the first driving unit is the input end of the delay circuit, and the second end of the second driving unit is the output end of the delay circuit.
As a possible implementation manner, the first delay circuit or the second delay circuit includes: and a plurality of delay units, each of the plurality of delay units being connected in series.
Since flicker noise is also typically present in a time-to-digital converter, as a possible implementation, the time-to-digital converter is used to: determining a delay difference between the second reference clock signal and the second feedback clock signal, and converting the delay difference between the second reference clock signal and the second feedback clock signal into a digital signal; the phase-locked loop also comprises an output control circuit for adjusting the sign of the digital signal output by the time-to-digital converter; a controller, further configured to: when the target signal is at the second level, the output control circuit is controlled to perform symbol inversion processing on the digital signal output from the time-to-digital converter. As can be seen from the above embodiment, in the working process of the phase-locked loop provided by the present application, the delay signal in the digital signal that is finally output is unchanged, and the flicker noise in the digital signal is periodically turned over in polarity with the frequency of the target signal, so that the flicker noise generated in the digital-to-time converter and the time-to-digital converter can be moved to the vicinity of the high-frequency signal period of the target signal, and the high-frequency noise is filtered by using the low-pass characteristic in the following process, so that the purpose of eliminating the flicker noise can be achieved.
As a possible implementation manner, the phase-locked loop further includes: digital loop filter, digitally controlled oscillator and feedback divider. The delay circuits in the digital time converter circuit are used for respectively carrying out signal delay processing on the reference clock signal and the feedback clock signal, and the signals corresponding to the reference clock signal and the feedback clock signal after delay processing are input to the time digital converter, so that the memory effect of the digital time converter is eliminated, and the problem of sensitivity of the digital time converter to power supply noise is solved.
In a second aspect, the present application provides a noise cancellation method applied to the phase-locked loop of the first aspect, the method comprising:
Acquiring a first reference clock signal and a first feedback clock signal, and selectively transmitting the first reference clock signal and the first feedback clock signal to a first delay circuit and a second delay circuit respectively;
The first reference clock signal delayed by the first delay circuit and the first reference clock signal delayed by the second delay circuit are provided as second reference clock signals to the time-to-digital converter, and the first feedback clock signal delayed by the first delay circuit and the first feedback clock signal delayed by the second delay circuit are provided as reference second feedback clock signals to the time-to-digital converter.
In a third aspect, the present application provides a chip comprising: the phase locked loop provided in the first aspect.
In a fourth aspect, the present application provides an electronic device comprising: the circuit board and the chip provided in the third aspect are arranged on the circuit board.
These and other aspects of the application will be more readily apparent from the following description of the embodiments.
Drawings
FIG. 1 is a schematic diagram of a phase locked loop;
FIG. 2 is a schematic diagram of a phase locked loop;
FIG. 3A is a control diagram of a controller;
FIG. 3B is a second control diagram of a controller;
fig. 4 is a schematic diagram of a phase locked loop;
fig. 5 is a schematic diagram of a phase locked loop;
FIG. 6 is a schematic diagram of a delay circuit;
FIG. 7 is a schematic diagram of a delay circuit;
fig. 8 is a schematic diagram of a phase locked loop;
fig. 9 is a schematic diagram of a phase locked loop;
Fig. 10 is a flowchart of a noise canceling method.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus a repetitive description thereof will be omitted. The words expressing the positions and directions described in the present application are described by taking the drawings as an example, but can be changed according to the needs, and all the changes are included in the protection scope of the present application. The drawings of the present application are merely schematic representations of relative positional relationships and are not intended to represent true proportions.
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings. The specific method of operation in the method embodiment may also be applied to the device embodiment or the system embodiment. In the description of the present application, "at least one" means one or more, wherein a plurality means two or more. In view of this, the term "plurality" may also be understood as "at least two" in embodiments of the present application. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/", unless otherwise specified, generally indicates that the associated object is an "or" relationship. In addition, it should be understood that in the description of the present application, the words "first," "second," and the like are used merely for distinguishing between the descriptions and not for indicating or implying any relative importance or order.
Frequency synthesizers based on phase locked loop structures are widely used in communication systems to provide local oscillation signals. In data transmission systems, it is also common to provide a sampling clock based on a phase locked loop structure. The quality of the communication signal is directly influenced or the transmission quality of the data is influenced based on the quality of the clock signal output by the phase-locked loop structure.
In digital phase-locked loops and analog phase-locked loops, a frequency multiplier is generally used to boost the frequency of a reference clock, thereby enhancing the output phase noise performance of the phase-locked loop. In order to obtain a more accurate output frequency, a fractional frequency division technology is generally adopted, and an instantaneous frequency division value of a frequency multiplier is adjusted through a sigma-delta modulator, so that the fractional frequency division is obtained. The application of SDM, however, produces large quantization noise and also causes fractional spurious problems in the output signal.
To solve the above problem caused by SDM, it is common to add a digital-to-time converter circuit to control the delay of the DTC circuit by inputting a random codeword, thereby eliminating the fractional spir. Or the DTC is controlled in conjunction with the fractional error codeword in the fractional divider (fractional divider) on the feedback loop so that the phase of the reference clock path follows the phase of the feedback clock, thereby eliminating quantization noise of the fractional divider. However, in the prior art, the delay coverage of the DTC circuit is larger, and the device noise and the power consumption of the DTC circuit both increase along with the increase of the delay, however, if the change of the delay is completed in a large range, the device noise and the power consumption of the DTC circuit both increase along with the increase of the delay. Thus, the DTC circuit itself also contributes more low frequency noise, which is difficult to cancel, thus affecting the PLL output clock quality.
In view of this, the phase-locked loop of the present application can not only realize a larger delay range, but also eliminate flicker noise of the digital time converter.
Referring to fig. 1, fig. 1 is a schematic diagram of a phase locked loop; the phase locked loop 100 includes: a digital-to-time converter 101 and a time-to-digital converter 102; the digital time converter 101 includes: a first delay circuit 1011, a second delay circuit 1012, a first signal switching circuit 1013, and a second signal switching circuit 1014.
The first signal switching circuit 1013 is configured to acquire a first reference clock signal and a first feedback clock signal, and selectively send the first reference clock signal and the first feedback clock signal to the first delay circuit 1011 and the second delay circuit 1012, respectively, where the first delay circuit 1011 is configured to perform a first delay process on the received signal, and the second delay circuit 1012 is configured to perform a second delay process on the received signal.
The second signal switching circuit 1014 is configured to supply the first reference clock signal delayed by the first delay circuit 1011 and the first reference clock signal delayed by the second delay circuit 1012 as the second reference clock signal to the time-to-digital converter 102, and to supply the first feedback clock signal delayed by the first delay circuit 1011 and the first feedback clock signal delayed by the second delay circuit 1012 as the second feedback clock signal to the time-to-digital converter 102.
The first delay circuit 1011 and the second delay circuit 1012 are configured to delay the first reference clock signal (fref_in shown in fig. 1) to obtain the second reference clock signal (fref_out shown in fig. 1), and the first delay circuit 1011 and the second delay circuit 1012 are also configured to delay the first feedback clock signal (fdiv_in shown in fig. 1) to obtain the second feedback clock signal (fdiv_out shown in fig. 1).
The time-to-digital converter 102 is configured to detect a time difference between the second reference clock signal and the second feedback clock signal, and convert the time difference between the second reference clock signal and the second feedback clock signal into a digital signal for output.
Referring to fig. 2, fig. 2 is a schematic diagram of a second phase-locked loop, and the phase-locked loop 100 further includes: the controller 103 is configured to acquire a target signal, and control the first signal switching circuit 1013 and the second signal switching circuit 1014 based on the target signal, wherein the frequency of the target signal is the same as the frequency of the first reference clock signal. For example, the target signal may be a square wave signal of the same frequency as the first reference clock signal, and the amplitude of the square wave may include a first level, a second level, and so on.
The first signal switching circuit may selectively adjust output paths of the first reference clock signal and the first feedback clock signal according to a level change of the target signal, and may also selectively supply the first reference clock signal delayed by the first delay circuit 1011/the second delay circuit 1012 as the second reference clock signal to the time-to-digital converter 102 and selectively supply the first reference clock signal delayed by the first delay circuit 1011/the second delay circuit 1012 as the second reference clock signal to the time-to-digital converter 102 according to a level change of the target signal.
As an alternative embodiment, referring to fig. 3A, fig. 3A is a control schematic diagram of a controller, where the controller 103 is configured to control the first signal switching circuit 1013 to input the first reference clock signal to the first delay circuit 1011 and the first feedback clock signal to the second delay circuit 1012 when the target signal is at the first level; the second signal switching circuit 1014 is controlled to supply the first reference clock signal delayed by the first delay circuit 1011 as a second reference clock signal to the time-to-digital converter 102, and to supply the first feedback clock signal delayed by the second delay circuit 1012 as a second feedback clock signal to the time-to-digital converter 102.
The controller 103 may control the first signal switching circuit 1013 to receive the first reference clock signal and the first feedback clock signal at two different ports, respectively, and input the received first reference clock signal to the first delay circuit 1011 and the first feedback clock signal to the second delay circuit 1012 when the target signal is at the first level. In addition, since the time-to-digital converter 102 generally calculates the time difference between the first input signal and the second input signal when calculating the delay difference, the controller 103 also needs to control the second signal switching circuit 1014 to input the first reference clock signal delayed by the first delay circuit 1011 as the second reference clock signal to the first input of the time-to-digital converter 102 and to input the first feedback clock signal delayed by the second delay circuit 1012 as the second feedback clock signal to the second input of the time-to-digital converter 102, thereby causing the time-to-digital converter 102 to calculate the time difference between the second reference clock signal and the second feedback clock signal.
Referring to fig. 3B, fig. 3B is a second control schematic diagram of a controller, where the controller 103 is configured to control the first signal switching circuit 1013 to input the first reference clock signal to the second delay circuit 1012 and the first feedback clock signal to the first delay circuit 1011 when the target signal is at the second level; the second signal switching circuit 1014 is controlled to supply the first reference clock signal delayed by the second delay circuit 1012 to the time-to-digital converter 102 as a second reference clock signal, and to supply the first feedback clock signal delayed by the first delay circuit 1011 to the time-to-digital converter 102 as a second feedback clock signal.
When the target signal is at the first level, the controller 103 may control the first signal switching circuit 1013 to input the received first reference clock signal to the second delay circuit 1012 and the first feedback clock signal to the first delay circuit 1011. Since the delay processing is performed by the second delay circuit 1012 on the first reference clock signal and the delay processing is performed by the first delay circuit 1011 on the first feedback clock signal, the controller 103 also needs to control the second signal switching circuit 1014 to input the first feedback clock signal delayed by the first delay circuit 1011 as the second feedback clock signal to the second input terminal of the time-to-digital converter 102, and to input the first reference clock signal delayed by the second delay circuit 1012 as the second reference clock signal to the first input terminal of the time-to-digital converter 102, so that the time-to-digital converter 102 still calculates the time difference between the second reference clock signal and the second feedback clock signal.
In this way, the flicker noise generated in the first delay circuit 1011 and the second delay circuit 1012 is low-frequency noise, and the flicker noise spectrum generated in the first delay circuit 1011 and the second delay circuit 1012 is shifted to the high frequency corresponding to the first reference clock signal by the continuous alternating control (chopping characteristic) of the controller 103, and the flicker noise whose spectrum is shifted to the high frequency can be effectively filtered in the subsequent low-pass filter.
In addition, the frequency of the target signal may be different from the frequency of the first reference clock signal, or the frequency of the target signal may be half of the frequency of the first reference clock signal, or the like, which is not limited herein.
As a possible implementation manner, referring to fig. 4, fig. 4 is a schematic diagram of a phase-locked loop. The first signal switching circuit 1013 specifically includes: the first control switch 401, the second control switch 402, the third control switch 403, and the fourth control switch 404, the second signal switching circuit 1014 specifically includes: a fifth control switch 405, a sixth control switch 406, a seventh control switch 407, and an eighth control switch 408; one end of the first control switch 401 and one end of the second control switch 402 receive the first reference clock signal, and one end of the third control switch 403 and one end of the fourth control switch 404 receive the first feedback clock signal.
The other end of the first control switch 401 is connected to the first delay circuit 1011, the other end of the second control switch 402 is connected to the second delay circuit 1012, the other end of the third control switch 403 is connected to the first delay circuit 1011, and the other end of the fourth control switch 404 is connected to the second delay circuit 1012; one end of a fifth control switch 405 is connected to the output end of the first delay circuit 1011, the other end of the fifth control switch 405 is connected to the first input end of the time-to-digital converter 102, one end of a sixth control switch 406 is connected to the output end of the first delay circuit 1011, the other end of the sixth control switch 406 is connected to the second input end of the time-to-digital converter 102, one end of a seventh control switch 407 is connected to the output end of the second delay circuit 1012, the other end of the seventh control switch 407 is connected to the first input end of the time-to-digital converter 102, one end of an eighth control switch 408 is connected to the output end of the second delay circuit 1012, and the other end of the eighth control switch 408 is connected to the second input end of the time-to-digital converter 102.
Alternatively, the first signal switching circuit 1013 and the second signal switching circuit 1014 may be switch circuit structures such as butterfly switch circuits, and other switch structures having basic functions that alternate between successive cycles may be used in other embodiments, as will be appreciated by those skilled in the art.
As an alternative embodiment, referring to fig. 5, fig. 5 is a schematic diagram of a phase locked loop. The phase-locked loop 100 further comprises: delay control circuit 104 for: selectively controlling the first delay circuit 1011 with a first control signal or a second control signal to adjust a delay time of the first delay circuit 1011 with respect to a received signal, the first control signal having a polarity opposite to that of the second control signal; the second delay circuit 1012 is selectively controlled with a third control signal or a fourth control signal to adjust a delay time length of the second delay circuit 1012 for a received signal, the third control signal being opposite in polarity to the fourth control signal.
A controller 103 for: when the target signal is at the first level, the delay period of the first delay circuit 1011 is controlled with the first control signal, and the delay period of the second delay circuit 1012 is controlled with the third control signal.
When the target signal is at the second level, the delay period of the first delay circuit 1011 is controlled with the second control signal, and the delay period of the second delay circuit 1012 is controlled with the fourth control signal.
In order to keep the delay relationship between the input and output of the digital-to-time converter 101 unchanged, when the target signal is at the first level, the first feedback clock signal is input to the second delay circuit 1012 because the controller 103 controls the first signal switching circuit 1013 to input the first reference clock signal to the first delay circuit 1011. Accordingly, the delay period of the first delay circuit 1011 is controlled using the first control signal, and the delay period of the second delay circuit 1012 is controlled using the third control signal.
And when the target signal is at the second level, the controller 103 controls the first signal switching circuit 1013 to input the first feedback clock signal to the first delay circuit 1011 and the first reference clock signal to the second delay circuit 1012. The delay time length of the first delay circuit 1011 is controlled by a second control signal, and the delay time length of the second delay circuit 1012 is controlled by a fourth control signal. Since the polarities of the first control signal and the second control signal are opposite, and the polarities of the third control signal and the fourth control signal are opposite, the digital-to-time converter 101 delay relationship is unchanged when the second reference clock signal and the second feedback clock signal are calculated by the time-to-digital converter 102.
For example, the first signal switching circuit 1013, the second signal switching circuit 1014, and the delay control circuit 104 may be simultaneously controlled by the sel signal through the controller 103 (i.e., the target signal), where the sel signal may be a square wave signal of the same frequency as the first reference clock signal), and the square wave may have a magnitude of (-1, 1), so that the first reference clock signal and the first feedback clock signal are alternately input in the frequency of the first reference clock signal, and the second reference clock signal and the second feedback clock signal are alternately output in the frequency of the first reference clock signal, and since the delay control circuit 104 controls the first delay circuit 1011 and the second delay circuit 1012 by using control signals of opposite polarities, the delay relationship of the entire digital-to-time converter is unchanged.
When sel=1, the first reference clock signal is delayed by the first delay circuit 1011 and provided as the second reference clock signal to the time-to-digital converter 102, and the first feedback clock signal is delayed by the second delay circuit 1012 and provided as the second feedback clock signal to the time-to-digital converter 102. The delay control circuit 104 transmits the first control signal D First one to the first delay circuit 1011 and the third control signal D Third step to the second delay circuit 1012 according to the sel signal.
The total delay of the reference clock signal is: t Reference signal total ＝T Reference input +noise2 First one +D First one *T0, wherein T 0 is the delay precision of the first delay circuit 1011 or the second delay circuit 1012, T Reference input is the input delay of the reference clock signal, noise 2 First one is the flicker noise generated by the signal on the first delay circuit 1011, and the total delay of the feedback clock signal is: t Feedback signal total ＝T Feedback input +noise2 Second one +D Third step *T0. Where T Feedback input is the input delay of the feedback clock signal and noise 2 Second one is the flicker noise of the signal on the second delay circuit 1012. Thus, the delay difference between the total delay of the reference clock signal and the total delay of the feedback clock signal is ：T Total output of ＝T Total input difference +noise2 First one -noise2 Second one +(D First one -D Third step )*T0,, where T Total input difference is the input delay difference of T Reference input and T Feedback input .
At sel= -1, the first reference clock signal is delayed by the second delay circuit 1012 and provided as a second reference clock signal to the time-to-digital converter 102, and the first feedback clock signal is delayed by the first delay circuit 1011 and provided as a second feedback clock signal to the time-to-digital converter 102. The delay control circuit 104 transmits the second control signal D Second one to the first delay circuit 1011 and the fourth control signal D Fourth step to the second delay circuit 1012 according to the sel signal.
The total delay of the reference input signal is: t Reference signal total ＝T Reference input +noise2 Second one +D Second one *T0, the total delay of the feedback input signal is: t Feedback signal total ＝T Feedback input +noise2 First one +D Fourth step *T0. Where T Feedback input is the input delay of the feedback clock signal and noise 2 Second one is the flicker noise of the signal on the second delay circuit 1012. Thus, the delay difference between the total delay of the reference input signal and the total delay of the feedback input signal is ：T Total output of ＝T Total input difference -noise2 First one +noise2 Second one +(D Second one -D Fourth step )*T0,, where T Total input difference is the input delay difference of T Reference input and T Feedback input .
As can be seen from the above embodiments, in the operation process of the phase-locked loop 100 provided by the embodiment of the present application, the difference between the two delay signals of the first delay circuit 1011 and the second delay circuit 1012 is kept unchanged all the time due to the D First one ＝-D Second one ,D Third step ＝D Fourth step . And because the sel signal is periodically inverted, the difference (noise 2 First one -noise2 Second one /noise2 Second one -noise2 First one ) between the flicker noise in the delay difference of the first delay circuit 1011 and the second delay circuit 1012 periodically inverts the polarity at the frequency of the sel signal (i.e. the frequency of the reference clock signal), so that the flicker noise can be moved to the vicinity of the high-frequency signal period of the sel signal, and then the high-frequency noise can be filtered by using a low-pass filter, thereby achieving the purpose of eliminating the flicker noise.
Alternatively, the first delay circuit 1011 and the second delay circuit 1012 may be mutually coupled circuits, and ,D First one ＝A/2*T0+Din,D Second one ＝-A/2*T0-Din,D Third step ＝A/2*T0-Din,D Fourth step ＝-A/2*T0+Din,A is the maximum delay value of the first delay circuit 1011 or the second delay circuit 1012, and D in is within the [ -a/2*T 0,A/2*T0 ] interval. At sel=1, the total delay of the reference clock signal is: t Reference signal total ＝T Reference input +noise2 First one +(A/2*T0+Din)*T0, the total delay of the feedback clock signal is: t Feedback signal total ＝T Feedback input +noise2 Second one +(A/2*T0-Din)*T0. Thus, the delay difference between the total delay of the reference input signal and the total delay of the feedback input signal is: t Total output of ＝T Total input difference +noise2 First one -noise2 Second one +2*T0*Din.
At sel= -1, the total delay of the reference clock signal is: t Reference signal total ＝T Reference input +noise2 Second one -(A/2*T0+Din)*T0, the total delay of the feedback clock signal is: t Feedback signal total ＝T Feedback input +noise2 First one -(A/2*T0-Din)*T0. Thus, the delay difference between the total delay of the reference input signal and the total delay of the feedback input signal is: t Total output of ＝T Total input difference -noise2 First one +noise2 Second one +2*T0*Din.
In addition, when the delay of any one of the first delay circuit 1011 and the second delay circuit 1012 is zero (the zero delay circuit is regarded as the signal line to be turned on), the whole digital time converter 101 can be regarded as a single delay circuit structure, so the scheme provided by the embodiment of the application can be applied to the digital time converter 101 with a single delay circuit structure, and the purpose of eliminating the flicker noise of the digital time converter can be achieved.
Referring to fig. 6, fig. 6 is a schematic diagram of a delay circuit, in which a plurality of delay units may be included, and in an exemplary embodiment, any one of the delay circuits may include a plurality of delay units (delay units … and delay units n), where the plurality of delay units in the delay circuit are connected in series, and the delay precision of each delay unit determines the delay duration range of the delay circuit together, which will be understood by those skilled in the art, and will not be described herein in detail.
Referring to fig. 7, fig. 7 is a schematic diagram of a second delay circuit, and as a possible implementation, the first delay circuit 1011 or the second delay circuit 1012 includes a first driving unit 701, a second driving unit 702, a resistor 703 and an adjustable capacitor 704.
The first end of the first driving unit 701 is connected to the first end of the resistor 703, the second end of the resistor 703 is connected to the first end of the second driving unit 702 and the first end of the adjustable capacitor 704, the second end of the adjustable capacitor 704 is grounded, the second end of the first driving unit 701 is an input end of the delay circuit, and the second end of the second driving unit 702 is an output end of the delay circuit.
The reference clock signal or the feedback clock signal can be delay controlled by using the capacitance values of the first driving unit 701, the second driving unit 702, the resistor 703 and the adjustable capacitor 704, and the delay range of the reference clock signal or the feedback clock signal can be determined by the capacitance value adjustment range of the adjustable capacitor 704.
As flicker noise will also occur in the time-to-digital converter 102, referring to fig. 8, fig. 8 is a schematic diagram of a phase-locked loop, and the time-to-digital converter 102 is specifically configured to determine a delay difference between the second reference clock signal and the second feedback clock signal, and convert the delay difference between the second reference clock signal and the second feedback clock signal into a digital signal Code Output of for outputting.
The phase-locked loop further comprises an output control circuit 106 for adjusting the sign of the digital signal output by the time-to-digital converter 102; the controller 103 is further configured to: when the target signal is at the second level, the output control circuit 106 is controlled to perform the sign inverting process on the digital signal output from the time-to-digital converter 102.
Illustratively, the first signal switching circuit 1013, the second signal switching circuit 1014, the delay control circuit 104, and the output control circuit 106 may all be controlled by the sel signal at the same time.
When sel=1, the first reference clock signal is delayed by the first delay circuit 1011 and provided as the second reference clock signal to the time-to-digital converter 102, and the first feedback clock signal is delayed by the second delay circuit 1012 and provided as the second feedback clock signal to the time-to-digital converter 102. The delay control circuit 104 sends a first control signal D First one to the first delay circuit 1011 and a third control signal D Third step to the second delay circuit 1012 according to the sel signal, and the time-to-digital converter 102 is configured to determine a delay difference between the second reference clock signal and the second feedback clock signal, and convert the delay difference into a digital Code Output of to output.
The output of the time-to-digital converter 102 is ：Code Output of ＝gain*[T Reference input -T Feedback input +noise2 First one -noise2 Second one +(D First one -D Third step )*T0+noise2 tdc First one -noise2 tdc Second one ],, where noise 2 tdc First one is a flicker noise equivalently input to the first input terminal of the time-to-digital converter 102, noise 2 tdc Second one is a flicker noise equivalently input to the second input terminal of the time-to-digital converter 102, and gain is a gain value equivalent to the digital code converted by the time-to-digital converter 102 from the delay difference between the second reference clock signal and the second feedback clock signal.
At sel= -1, the first reference clock signal is delayed by the second delay circuit 1012 and provided as a second reference clock signal to the time-to-digital converter 102, and the first feedback clock signal is delayed by the first delay circuit 1011 and provided as a second feedback clock signal to the time-to-digital converter 102. The delay control circuit 104 transmits the second control signal D Second one to the first delay circuit 1011 and the fourth control signal D Fourth step to the second delay circuit 1012 according to the sel signal. The time-to-digital converter 102 is configured to determine a delay difference between the second reference clock signal and the second feedback clock signal, and the output control circuit 106 performs a sign inversion process on the digital Code Output of of the time-to-digital converter 102.
The output of the time-to-digital converter 102 is ：Code Output of ＝gain*[T Feedback input -T Reference input +noise2 First one -noise2 Second one +(D Fourth step -D Second one )*T0+noise2 tdc First one -noise2 tdc Second one ], and since the output control circuit 106 performs the sign-inverting process on the digital Code Output of of the time-to-digital converter 102, the output control circuit performs the sign-inverting process on the digital Code ,Code Output of ＝-gain*[T Feedback input -T Reference input +noise2 First one -noise2 Second one +(D Fourth step -D Second one )*T0+noise2 tdc First one -noise2 tdc Second one ]→→Code Output of ＝gain*[T Reference input -T Feedback input -noise2 First one +noise2 Second one +(D Second one -D Fourth step )*T0+noise2 tdc Second one -noise2 tdc First one ].
As can be seen from the above embodiment, in the working process of the phase-locked loop provided by the embodiment of the present application, the delay signal in the Code Output of that is finally output is unchanged (the polarity of the flicker noise in the T Reference input -T Feedback input +(D First one -D Third step )*T0),Code Output of is periodically inverted (noise2 First one -noise2 Second one +noise2 tdc First one -noise2 tdc Second one /noise2 Second one -noise2 First one +noise2 tdc Second one -noise2 tdc First one ) by the frequency of the sel signal (i.e. the target frequency), so that the flicker noise generated in the digital-to-time converter 101 and the time-to-digital converter 102 can be moved to the vicinity of the high-frequency signal period of the sel signal, and the high-frequency noise is filtered by using the low-pass characteristic in the following process, so that the purpose of eliminating the flicker noise can be achieved.
Based on the same concept, referring to fig. 9, fig. 9 is a schematic diagram of a phase-locked loop, taking an all-digital phase-locked loop system (ALL DIGITAL PHASE locked loop) as an example, a digital time converter 901, a time-to-digital converter 902, a digital loop filter (digital loop filter, DLPF) 903, a feedback divider (feedback divider, NDIV) 904, a digitally controlled oscillator (DIGITALLY CONTROLLED OSCILLATOR, DCO) 905, and a delta-sigma modulator (SIGMA DELTA modulator, SDM) 906. The delay circuits in the digital time converter 901 are used for respectively carrying out signal delay processing on the reference clock signal and the feedback clock signal, the signals after the delay processing corresponding to the reference clock signal and the feedback clock signal are input to the time digital converter 902, after the delay difference is calculated by the time digital converter 902, a control signal is generated based on the delay difference to control the digital control oscillator 905, so that the memory effect of the digital time converter 901 is eliminated, the problem of sensitivity of the digital time converter 901 to power supply noise is reduced, and the frequency change is realized. The digital loop filter 903 may be a low-pass filter, so that the low-pass characteristic filters out high-frequency noise, and flicker noise generated by the digital-to-time converter 901 and the time-to-digital converter 902.
By using the phase-locked loop provided by the embodiment of the application, the first reference clock signal and the first feedback clock signal are respectively sent to the first delay circuit and the second delay circuit through the first signal switching circuit, the first reference clock signal delayed by the first delay circuit and the second delay circuit is provided as the second reference clock signal to the time-to-digital converter through the second signal switching circuit, and the first feedback clock signal delayed by the first delay circuit and the second delay circuit is provided as the second feedback clock signal to the time-to-digital converter, so that the frequencies of flicker noise generated on the first delay circuit and the second delay circuit are shifted, and the shifted flicker noise is filtered through a subsequent low-pass filter, thereby achieving the purpose of eliminating the flicker noise. In addition, in the working process of the phase-locked loop provided by the embodiment of the application, the flicker noise in the delay difference of the time-to-digital converter can be moved to the vicinity of the period of the high-frequency signal, and the low-pass characteristic is used for filtering the high-frequency noise and filtering the flicker noise generated by the time-to-digital converter.
Based on the above-mentioned digital-to-time converter circuit embodiment, the embodiment of the present application further provides a noise cancellation method applied to the phase-locked loop described in the above-mentioned embodiment, referring to fig. 10, fig. 10 is a flowchart of a noise cancellation method applied to the phase-locked loop 100 shown in fig. 1, where the method includes:
Step S1001: a first reference clock signal and a first feedback clock signal are acquired and selectively transmitted to the first delay circuit and the second delay circuit, respectively.
Step S1002: the first reference clock signal delayed by the first delay circuit and the first reference clock signal delayed by the second delay circuit are provided as second reference clock signals to the time-to-digital converter, and the first feedback clock signal delayed by the first delay circuit and the first feedback clock signal delayed by the second delay circuit are provided as reference second feedback clock signals to the time-to-digital converter.
Based on the same conception, the application also provides a chip, comprising the phase-locked loop in any one of the possible designs.
Based on the same conception, the application also provides electronic equipment, which comprises: the circuit board and the chips in any of the above possible designs are disposed on the circuit board.
Embodiments of the present application also provide a computer-readable storage medium storing computer instructions that, when executed by a digital-to-time converter circuit, cause the noise cancellation method shown in fig. 10 to be performed.
Embodiments of the present application also provide a computer program product comprising computer instructions which, when executed by a digital-to-time converter circuit, cause the noise cancellation method shown in fig. 10 to be performed.
That is, aspects of the signal delay processing method provided by the present application may also be implemented in the form of a program product comprising program code for causing a computer device to carry out the steps of the signal delay processing method described above in the present specification when the program code is run on the computer device or on a circuit product.
Furthermore, although the operations of the methods of the present application are depicted in the drawings in a particular order, this is not required or suggested that these operations must be performed in this particular order or that all of the illustrated operations must be performed in order to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (13)

1. A phase locked loop, comprising: a digital-to-time converter and a time-to-digital converter; wherein;
The digital-to-time converter includes: a first delay circuit, a second delay circuit, a first signal switching circuit, and a second signal switching circuit;
The first signal switching circuit is used for acquiring a first reference clock signal and a first feedback clock signal and selectively transmitting the first reference clock signal and the first feedback clock signal to the first delay circuit and the second delay circuit respectively;
The first delay circuit is used for performing first delay processing on the received signal, and the second delay circuit is used for performing second delay processing on the received signal;
The second signal switching circuit is configured to supply the first reference clock signal delayed by the first delay circuit and the first reference clock signal delayed by the second delay circuit as a second reference clock signal to the time-to-digital converter, and supply the first feedback clock signal delayed by the first delay circuit and the first feedback clock signal delayed by the second delay circuit as a second feedback clock signal to the time-to-digital converter.
2. The phase locked loop of claim 1, wherein the phase locked loop further comprises: a controller;
The controller is used for: and acquiring a target signal, and controlling the first signal switching circuit and the second signal switching circuit based on the target signal, wherein the frequency of the target signal is the same as the frequency of the first reference clock signal.
3. Phase locked loop according to claim 2, characterized in that the controller is in particular adapted to:
When the target signal is at a first level, controlling the first signal switching circuit to input the first reference clock signal into the first delay circuit and to input the first feedback clock signal into the second delay circuit; controlling the second signal switching circuit to provide the first reference clock signal delayed by the first delay circuit as a second reference clock signal to the time-to-digital converter, and providing the first feedback clock signal delayed by the second delay circuit as a second feedback clock signal to the time-to-digital converter;
when the target signal is at a second level, controlling the first signal switching circuit to input the first reference clock signal into the second delay circuit and to input the first feedback clock signal into the first delay circuit; and controlling the second signal switching circuit to provide the first reference clock signal delayed by the second delay circuit as a second reference clock signal to the time-to-digital converter, and providing the first feedback clock signal delayed by the first delay circuit as a second feedback clock signal to the time-to-digital converter.
4. A phase locked loop as claimed in any one of claims 1 to 3, wherein said first signal switching circuit comprises in particular: the first control switch, the second control switch, the third control switch and the fourth control switch, the second signal switching circuit specifically includes: a fifth control switch, a sixth control switch, a seventh control switch, and an eighth control switch; one end of the first control switch and one end of the second control switch receive a first reference clock signal, and one end of the third control switch and one end of the fourth control switch receive a first feedback clock signal;
The other end of the first control switch is connected with the first delay circuit, the other end of the second control switch is connected with the second delay circuit, the other end of the third control switch is connected with the first delay circuit, and the other end of the fourth control switch is connected with the second delay circuit;
One end of the fifth control switch is connected with the output end of the first delay circuit, the other end of the fifth control switch is connected with the first input end of the time-to-digital converter, one end of the sixth control switch is connected with the output end of the first delay circuit, the other end of the sixth control switch is connected with the second input end of the time-to-digital converter, one end of the seventh control switch is connected with the output end of the second delay circuit, the other end of the seventh control switch is connected with the first input end of the time-to-digital converter, one end of the eighth control switch is connected with the output end of the second delay circuit, and the other end of the eighth control switch is connected with the second input end of the time-to-digital converter.
5. The phase locked loop of any one of claims 1-4, wherein the phase locked loop further comprises:
A delay control circuit for: selectively controlling the first delay circuit with a first control signal or a second control signal to adjust a delay time length of the first delay circuit for a received signal, wherein the first control signal and the second control signal are opposite in polarity;
The second delay circuit is selectively controlled by a third control signal or a fourth control signal to adjust the delay time length of the second delay circuit for the received signal, wherein the third control signal and the fourth control signal are opposite in polarity.
6. The phase locked loop of claim 5, further comprising: a controller;
the controller is used for: when the target signal is at a first level, controlling the delay time length of the first delay circuit by the first control signal, and controlling the delay time length of the second delay circuit by the third control signal;
When the target signal is at a second level, the delay time length of the first delay circuit is controlled by the second control signal, and the delay time length of the second delay circuit is controlled by the fourth control signal.
7. The phase locked loop of any one of claims 1-6, wherein the first delay circuit or the second delay circuit comprises a first drive unit, a second drive unit, a resistor, and an adjustable capacitor;
The first end of the first driving unit is connected with the first end of the resistor, the second end of the resistor is connected with the first end of the second driving unit and the first end of the adjustable capacitor, the second end of the adjustable capacitor is grounded, the second end of the first driving unit is an input end of the delay circuit, and the second end of the second driving unit is an output end of the delay circuit.
8. The phase locked loop of any one of claims 1-7, wherein the first delay circuit or the second delay circuit comprises: and a plurality of delay units, each of the plurality of delay units being connected in series between the delay units.
9. A phase locked loop as claimed in claim 2 or 6, wherein the time to digital converter is arranged to:
Determining a delay difference between the second reference clock signal and the second feedback clock signal and converting the delay difference between the second reference clock signal and the second feedback clock signal into a digital signal;
The phase-locked loop also comprises an output control circuit for adjusting the sign of the digital signal output by the time-to-digital converter;
The controller is further configured to: and when the target signal is at a second level, controlling the output control circuit to perform sign inversion processing on the digital signal output by the time-to-digital converter.
10. A phase locked loop as claimed in any one of claims 1 to 9, wherein said phase locked loop further comprises: digital loop filter, digitally controlled oscillator and feedback divider.
11. A method of noise cancellation applied to a phase locked loop as claimed in any one of claims 1 to 10, the method comprising:
Acquiring a first reference clock signal and a first feedback clock signal, and selectively transmitting the first reference clock signal and the first feedback clock signal to the first delay circuit and the second delay circuit respectively;
The first reference clock signal delayed by the first delay circuit and the first reference clock signal delayed by the second delay circuit are provided as second reference clock signals to the time-to-digital converter, and the first feedback clock signal delayed by the first delay circuit and the first feedback clock signal delayed by the second delay circuit are provided as reference second feedback clock signals to the time-to-digital converter.
12. A chip, comprising: a phase locked loop as claimed in any one of claims 1 to 10.
13. An electronic device, comprising: a circuit board and a chip as claimed in claim 12, said chip being disposed on said circuit board.
CN202211439530.7A 2022-11-17 2022-11-17 Phase-locked loop, noise elimination method, chip and electronic equipment Pending CN118054784A (en)

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