CN118053883A - CMOS image sensor manufacturing method - Google Patents

Abstract

The present invention discloses a method for manufacturing a CMOS image sensor, the method comprising: providing a silicon substrate; forming a first dielectric layer on the silicon substrate, comprising first forming a first silicon oxide layer with a thickness of h, and then depositing a second dielectric layer; wherein the density of the first silicon oxide layer with a thickness of h0 in contact with the surface of the silicon substrate is higher than the density of the silicon oxide layer formed by a CVD process; wherein h0≤h; etching the first dielectric layer to form a gate sidewall; and performing ion implantation to form a surface doping layer of a photosensitive diode region in the surface area of the silicon substrate. The scheme of the present invention can effectively suppress the generation of white pixels in a CMOS image sensor.

Description

CMOS Image Sensor Manufacturing Method

Technical Field

The present invention relates to the field of semiconductor process technology, and in particular to a method for manufacturing a CMOS image sensor.

Background technique

Complementary Metal Oxide Semiconductor (CMOS) image sensor (CIS) is an optical sensor whose function is to convert light signals into electrical signals and convert them into digital signals through readout circuits. It is widely used in the field of vision and is a core component of camera modules. In order to obtain better shooting effects, the performance requirements for CIS devices are getting higher and higher. The number of white pixels (WP) directly affects the imaging quality of CIS and is one of the important indicators for evaluating the performance of CIS devices. Therefore, how to improve the diode manufacturing process to effectively suppress the generation of white pixels is an important research topic in the industry.

Summary of the invention

The embodiment of the present invention provides a method for manufacturing a CMOS image sensor, so as to effectively suppress the generation of white pixels of the CMOS image sensor.

The embodiment of the present invention provides the following technical solutions:

A method for manufacturing a CMOS image sensor, the method comprising:

providing a silicon substrate;

Forming a first dielectric layer on a silicon substrate, comprising first forming a first silicon oxide layer with a thickness of h, and then depositing a second dielectric layer; wherein the density of the first silicon oxide layer with a thickness of h0 in contact with the surface of the silicon substrate is higher than the density of the silicon oxide layer formed by a CVD process; wherein h0≤h;

Etching the first dielectric layer to form gate sidewalls;

Ion implantation is performed to form a surface doping layer in a photodiode region on the surface of the silicon substrate.

Optionally, forming a first silicon oxide layer with a thickness of h comprises:

A first silicon oxide layer having a thickness of h is formed by at least one of HTO and ALD.

Optionally, forming a first silicon oxide layer with a thickness of h comprises:

Firstly, an ALD method is used to form a first silicon oxide layer with a thickness of h1, and then an HTO method is used to form a first silicon oxide layer with a thickness of h2; or,

First, a first silicon oxide layer with a thickness of h1 is formed by using the HTO method, and then a first silicon oxide layer with a thickness of h2 is formed by using the ALD method; h1+h2=h.

Optionally, forming a first silicon oxide layer with a thickness of h includes: first forming a second silicon oxide layer with a thickness of h3, and then forming a third silicon oxide layer with a thickness of h4 through a CVD process; h3+h4=h; wherein the density of the second silicon oxide layer is higher than the density of the third silicon oxide layer.

Optionally, forming the second silicon oxide layer with a thickness of h3 includes: forming the second silicon oxide layer with a thickness of h3 by adopting at least one of a HTO method or an ALD method.

Optionally, h is 30A to 1000A.

Optionally, etching the first dielectric layer to form a gate sidewall includes:

Remove the second dielectric layer by dry etching to form the gate sidewall;

A portion of the first silicon oxide layer is removed by wet etching, and after etching, a fourth silicon oxide layer with a thickness of h' is retained on the surface of the silicon substrate outside the side wall, where h'<h.

Optionally, h’ is 30-300A.

Optionally, the performing ion implantation includes: performing ion implantation using boron as an ion source.

Optionally, a gate dielectric layer and a gate conductive material layer are formed on the silicon substrate.

Optionally, the second dielectric layer includes at least one of silicon oxide, silicon nitride or silicon oxynitride.

Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

The CMOS image sensor manufacturing method provided by the embodiment of the present invention forms a dielectric layer by depositing a more dense material on a semiconductor substrate through an improved sidewall deposition method. The dielectric layer formed by this solution has a higher density of silicon oxide remaining on the surface of the semiconductor substrate after sidewall etching than the density of silicon oxide formed by a CVD process. When performing Post-pin ion implantation, since it is implanted based on a dense dielectric layer, the precipitation of boron ions after Post-pin ion implantation can be effectively suppressed, thereby effectively improving the white pixel performance of the CIS device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a flow chart of a method for manufacturing a CMOS image sensor according to an embodiment of the present invention;

2 to 6 are schematic structural diagrams corresponding to the steps of the method for manufacturing a CMOS image sensor provided by an embodiment of the present invention.

Detailed ways

In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

The reason for the generation of white pixels is the existence of dark current, which is manifested as the pixel unit still being able to output a high-brightness signal under light-shielding conditions. Theoretically, CIS will not generate current without light, but in the manufacturing process it will inevitably be affected by various factors such as changes in raw materials, process fluctuations, metal contamination, etc., resulting in the pixel itself generating charges when no light is irradiated on the pixel unit. As the charges continue to increase and gather together, dark current is formed. For a pixel unit, when its dark current exceeds the photocurrent generated by capturing photons, the pixel will be defaulted to a white pixel by the control circuit.

The main source of dark current is the leakage current of the device itself, and the leakage paths mainly include leakage of the photodiode and substrate, damage to the surface of the photodiode, leakage of the preset transistor and substrate, and leakage of shallow trench isolation caused by breakdown of the gate oxide layer of the preset transistor. Metal impurity contamination in the chip is an important factor in generating dark current. The main reason is that metal impurities in the transistor will reduce the reverse breakdown current of the diode, thereby causing the dark current to rise.

For CIS devices, the increase in dark current is mainly attributed to defects (such as lattice damage, segregation defects, etc.) generated during the process of the photodiode (PD) of the pixel unit and contamination by metals (such as molybdenum (Mo), nickel (Ni), etc.). Under normal circumstances, when no light energy is absorbed, the dark current of the CIS device is very small; but after being contaminated by metal impurities, since metal ions carry charges, if they pass through the photodiode during the migration process, a large amount of charges will fill the well that should be filled by photons, causing the dark current of the pixel to increase. When the dark current exceeds the state of the normal chip after absorbing light energy, it will cause it to appear as a bright spot in a completely dark field, that is, a white pixel. This situation will greatly affect the performance of the CIS device and the quality of imaging.

For photodiodes, ion implantation is the main factor affecting their dark current. Ion implantation (Implant, IMP) is a method of semiconductor doping, which is to ionize impurities into ions and focus them into ion beams, accelerate them in an electric field to obtain extremely high kinetic energy, and then inject them into silicon to achieve doping. In the process flow of the pixel unit of the CIS device, ion implantation is divided into Pre-pin and Post-pin. Among them, Pre-pin ion implantation refers to the P-type doping layer on the surface of the semiconductor substrate before the gate sidewall (spacer) is formed; Post-pin ion implantation refers to the ion implantation of the surface area of the semiconductor substrate after the gate sidewall is formed, and its purpose is to form a P-type doping layer on the surface of the photodiode area on the surface area of the semiconductor substrate. The ion dose of Pre-pin implantation is much lower than that of Post-pin. In some embodiments, Pre-pin can be omitted.

The spacer process mainly includes: spacer deposition (Spacer Dep) and spacer etching (Spacer Etch), including dry etching (dryetch) and wet etching (wetetch). Among them, spacer deposition is to deposit a layer of oxide dielectric layer on the semiconductor substrate; spacer etching refers to forming gate spacers by exposure and etching, including forming a patterned photoresist layer on the surface of the dielectric layer, using it as a mask to etch the dielectric layer, and then removing the patterned photoresist layer and the dielectric layer.

At present, the ion sources available for PIN photodiode ion implantation mainly include boron (B) and boron difluoride (BF2). Among them:

Boron difluoride has a small diffusion coefficient and will hardly be segregated to the surface during annealing, nor will it affect the isolation of the photodiode and NMOS tube area. However, the charge-to-mass ratio (also known as specific charge, which refers to the ratio of the charge amount and mass of a charged body) of the boron difluoride ion group is similar to the charge-to-mass ratio of molybdenum (Mo) ions in the metal components of the machine. The deflection magnetic field cannot effectively filter out this metal impurity during injection. After the molybdenum ion is injected, a deep energy level will be introduced into the silicon (Si) band gap, causing the dark current to increase and produce white pixels.

Boron ion implantation can effectively avoid molybdenum contamination. However, boron ions diffuse at a high rate in silicon and tend to concentrate on the surface of the silicon wafer during annealing, forming precipitation defects, which causes the white pixel performance to deteriorate again.

In view of the high requirements of white pixel performance for the pixel unit of high-performance CIS devices, it is necessary to continuously improve the process conditions of PIN photodiode ion implantation. Among them, metal contamination must be avoided, so boron can be mainly considered as the ion source of post-pin ion implantation.

In addition, when performing Post-pin ion implantation, the thickness of the residual oxide (ROX) on the surface of the semiconductor substrate after the sidewall etching and the quality of the oxide must also be considered. If the residual oxide is too thick, too few ions will be injected during the Post-pin ion implantation; if the residual oxide is too thin, the ions will be implanted too deeply during the Post-pin ion implantation, which will seriously affect the full well capacity (FWC) of the pixel. In addition, the quality of the residual oxide itself will also affect the quality of the photodiode. If the density of the residual oxide is small, it will aggravate the precipitation of boron ions after the Post-pin ion implantation, causing metal contamination, and causing the performance of white pixels to deteriorate again.

Based on the above analysis, an embodiment of the present invention provides a method for manufacturing a CMOS image sensor, which uses a more dense material to deposit a dielectric layer on a semiconductor substrate through an improved sidewall deposition method. The dielectric layer formed based on this solution has a higher density of silicon oxide remaining on the surface of the semiconductor substrate after sidewall etching than the density of silicon oxide formed by a CVD process. When performing Post-pin ion implantation, since it is based on a dense dielectric layer, the precipitation of boron ions after Post-pin ion implantation can be effectively suppressed, effectively improving the white pixel performance of the CIS device.

As shown in FIG. 1 , it is a flow chart of a method for manufacturing a CMOS image sensor according to an embodiment of the present invention, which comprises the following steps:

Step 101, providing a silicon substrate.

In this embodiment, a photodiode region is formed inside the silicon substrate. In addition, a gate dielectric layer and a gate conductive material layer are formed on the silicon substrate.

Step 102, forming a first dielectric layer on a silicon substrate, including first forming a first silicon oxide layer with a thickness of h, and then forming a second dielectric layer; wherein the density of the first silicon oxide layer with a thickness of h0 in contact with the surface of the silicon substrate is higher than the density of the silicon oxide layer formed by a CVD (Chemical Vapor Deposition) process; wherein h0≤h. Specifically, the silicon oxide layer can be formed by a CVD process using TEOS and O ₃ as precursors; or, by a CVD process, SiH 4 and O ₂ react to form the silicon oxide layer; or, by a CVD process, SiCl ₄ , CO ₂ and H ₂ react to form the silicon oxide layer.

That is, the first dielectric layer includes a first silicon oxide layer in contact with the surface of the silicon substrate, and a second dielectric layer located on the first oxide layer, and the density of the entire first silicon oxide layer or a silicon oxide layer of a certain thickness in contact with the surface of the silicon substrate is higher than the density of the silicon oxide layer formed by CVD. In specific applications, the thickness h of the first silicon oxide layer can be determined according to actual needs, for example, it can be 30A to 1000A.

The first silicon oxide layer of thickness h can be formed by one or more methods such as HTO (High Temperature Oxide) method or ALD (Atomic Layer Deposition) method, as illustrated below. For example:

(1) In a non-limiting embodiment, a first silicon oxide layer having a thickness of h is formed by an ALD method or a HTO method;

(2) In another non-limiting embodiment, an ALD method may be used to first form a first silicon oxide layer with a thickness of h1, and then an HTO method may be used to form a first silicon oxide layer with a thickness of h2;

(3) In another non-limiting embodiment, a first silicon oxide layer with a thickness of h1 may be formed by using a HTO method, and then a first silicon oxide layer with a thickness of h2 may be formed by using an ALD method.

The above h1 and h2 satisfy: h1+h2=h, which means that different processes can be used to form the first silicon oxide layer, and the density of the first silicon oxide layer with a thickness of h1 and the first silicon oxide layer with a thickness of h2 are both higher than the existing O3TEOS, but the formation processes of the two first silicon oxide layers are different.

(4) In another non-limiting embodiment, a second silicon oxide layer with a thickness of h3 may be formed first, and then a third silicon oxide layer with a thickness of h4 may be formed by a CVD process; h3+h4=h; wherein the density of the second silicon oxide layer is higher than the density of the third silicon oxide layer.

In a specific application, any of the above-mentioned processes for forming the first silicon oxide layer (1) to (3) can be used to form the second silicon oxide layer with a thickness of h3, which is not limited in this embodiment of the present invention.

In addition, the above h3 and h4 satisfy: h3+h4=h, that is, two silicon oxide layers with different densities can be formed by the same or different processes.

Of course, there are many other variations on the specific implementation method of forming the first silicon oxide layer of thickness h, which will not be listed one by one here. It is only necessary to ensure that the silicon oxide layer of a certain thickness (i.e., the h0 mentioned above) in contact with the surface of the silicon substrate has a higher density (density is higher than that of the silicon oxide layer formed by the CVD process).

In the embodiment of the present invention, the second dielectric layer may include at least one of silicon oxide, silicon nitride or silicon oxynitride, and the deposition process may adopt a deposition process in the prior art, such as CVD or ALD, etc., which is not limited in the embodiment of the present invention. In addition, the thickness of the second dielectric layer is not limited and can be determined according to actual needs.

Step 103: etching the first dielectric layer to form gate sidewalls.

First, the second dielectric layer is removed by dry etching to form a gate sidewall; then, a portion of the first silicon oxide layer is removed by wet etching, and after etching, a fourth silicon oxide layer with a thickness of h' is retained on the surface of the silicon substrate outside the sidewall, where h'<h.

The thickness h' of the fourth silicon oxide layer can be determined according to actual needs, for example, it can be 30-300 Å.

Since when forming and depositing the first dielectric layer, no matter which deposition process described above is used, the density of the first silicon oxide layer of a certain thickness (i.e., the thickness h0 mentioned above) in contact with the surface of the silicon substrate is higher than the density of the silicon oxide layer formed by the CVD process with TEOS and _O3 as precursors, therefore, whether the thickness h' of the fourth silicon oxide layer retained on the surface of the silicon substrate after etching is greater than, equal to or less than the above h0, it can ensure that the silicon oxide layer in contact with the surface of the silicon substrate after etching has a higher density.

Step 104 , performing ion implantation to form a surface doping layer of a photodiode region on the surface of the silicon substrate.

In the embodiment of the present invention, boron can be preferably used as the ion source for post-pin ion implantation. Although the diffusion rate of boron ions in silicon is relatively high, the silicon oxide layer in contact with the surface of the silicon substrate after etching has a higher density, thus effectively preventing the precipitation of boron ions after ion implantation.

The structures corresponding to the steps of the method for manufacturing a CMOS image sensor provided by an embodiment of the present invention are further described below in conjunction with FIG. 2 to FIG. 6 .

First, as shown in FIG. 2 , a silicon substrate 1 is provided, on which a gate dielectric layer 2 and a gate conductive material layer 3 are sequentially formed.

3, a first dielectric layer 4 is formed on the silicon substrate, including first forming a first silicon oxide layer 4 with a thickness of h, and then depositing a second dielectric layer 5. The formation process of the first dielectric layer 4 and the second dielectric layer 5 can refer to the above description.

Then, referring to FIG. 4 , the second dielectric layer is removed by dry etching to form a gate sidewall 6;

Then, referring to FIG5 , a portion of the first silicon oxide layer is removed by wet etching. After etching, a fourth silicon oxide layer 7 with a thickness of h’ is retained on the surface of the silicon substrate outside the gate sidewall 6, where h’<h.

Finally, referring to FIG. 6 , ion implantation is performed to form a surface doping layer 8 in the photodiode region on the surface of the silicon substrate.

The CMOS image sensor manufacturing method provided by the embodiment of the present invention forms a dielectric layer on a silicon substrate through an improved process, specifically, first forms a first silicon oxide layer with a thickness of h, and then deposits a second dielectric layer; wherein the density of the first silicon oxide layer with a thickness of h0 in contact with the surface of the silicon substrate is higher than the density of the silicon oxide layer formed by the CVD process. The dielectric layer formed based on this scheme, after the sidewall etching, has a higher density of the silicon oxide layer remaining on the surface of the semiconductor substrate than the existing silicon oxide layer formed by the CVD process. When performing Post-pin ion implantation, since it is based on the dielectric layer with higher density, the precipitation of boron ions after Post-pin ion implantation can be effectively suppressed, and the white pixel performance of the CIS device can be effectively improved.

It should be understood that the term "and/or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and/or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character "/" in this article indicates that the associated objects before and after are in an "or" relationship.

The first, second, etc. descriptions appearing in the embodiments of the present application are only used for illustration and distinction of the description objects. There is no order, nor do they indicate any special limitation on the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims (11)

1. A method of fabricating a CMOS image sensor, the method comprising:

Providing a silicon substrate;

Forming a first dielectric layer on a silicon substrate, wherein the first dielectric layer comprises a first silicon oxide layer with h thickness, and then depositing a second dielectric layer; wherein the density of the h0 thickness of the first silicon oxide layer in contact with the surface of the silicon substrate is higher than that of a silicon oxide layer formed by a CVD process; wherein h0 is less than or equal to h;

Etching the first dielectric layer to form a grid side wall;

And performing ion implantation to form a doped layer on the surface of the photodiode region in the surface area of the silicon substrate.

2. The method of claim 1, wherein forming the first silicon oxide layer having an h thickness comprises:

The first silicon oxide layer is formed to a thickness h using at least one of HTO or ALD.

3. The method of claim 1, wherein forming the first silicon oxide layer having an h thickness comprises:

Forming a first silicon oxide layer with h1 thickness by adopting an ALD method, and then forming a first silicon oxide layer with h2 thickness by adopting an HTO method; or alternatively

Firstly, forming a first silicon oxide layer with h1 thickness by adopting an HTO method, and then forming a first silicon oxide layer with h2 thickness by adopting an ALD method; h1+h2=h.

4. The method of claim 1, wherein forming the first silicon oxide layer having an h thickness comprises:

Forming a second silicon oxide layer with h3 thickness, and then forming a third silicon oxide layer with h4 thickness through a CVD (chemical vapor deposition) process; h3+h4=h; wherein the density of the second silicon oxide layer is higher than that of the third silicon oxide layer.

5. The method of claim 4, wherein forming the h3 thickness of the second silicon dioxide layer comprises:

The second silicon dioxide layer of h3 thickness is formed using at least one of HTO or ALD.

6. The method of claim 1, wherein h is from 30A to 1000A.

7. The method of claim 1, wherein etching the first dielectric layer to form a gate sidewall comprises:

Removing the second dielectric layer by dry etching to form the grid side wall;

And removing part of the first silicon oxide layer by wet etching, and reserving a fourth silicon oxide layer with h 'thickness on the surface of the silicon substrate outside the side wall after etching, wherein h' < h.

8. The method of claim 7, wherein h' is 30-300A.

9. The method of any one of claims 1 to 8, wherein the performing ion implantation comprises:

ion implantation is performed using boron as the ion source.

10. The method of any one of claims 1 to 8, wherein a gate dielectric layer and a gate conductive material layer are formed on the silicon substrate.

11. The method of any of claims 1 to 8, wherein the second dielectric layer comprises at least one of silicon oxide, silicon nitride, or silicon oxynitride.